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DESCRIPTION: flip-flop cell data sheets Truth Table: AT


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ATL35 CMOS Gate Array
DESCRIPTION: flip-flop
cell data sheets
Truth Table:
ATL55Cells
Q(T+1) Q(T)
VDD! VDD!
VDD!
VSS! VDD!
VDD!
VSS! VSS!
VSS! VDD!
VSS!
VSS!
VDD!
VDD!
VSS!
VSS!
($Revision: 1.35
15:28:51 1997
ATL35 CMOS Gate Array
DESCRIPTION: flip-flop
cell data sheets
SITES: Core Ring LOADS: D=2.0 CLK=1.0
TIMING TABLE
Path -CLK Path Rise Slope -0.01381 Setup -0.15715
(NomProc,25degC,Nom trf)
Rise -0.48736 Hold -0.11602 Fall Slope -0.01280 Fall -0.47135
Typical Case Path Delays rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:28:51 1997
DFFBCPX ATL35 CMOS Gate Array
cell data sheets
DESCRIPTION: flip-flop with asynchronous clear preset with complementary outputs
ATL55Cells
Truth Table: Q(T+1) QB(T+1) Q(T) QB(T)
DFFBCPX
VDD!
VDD!
P146 N108
VDD! VDD!
VSS!
N112 P111 N106
VDD! VSS! VDD! VSS! VDD!
N147
VDD! VDD! VSS!
P107
N102 N103
VSS! VDD!
P123 N105 N119
P141
N131
VDD! VSS!
N116
P113 N109 P110
VSS!
P114 P115 N117 N118
VDD!
P150 N152
VDD! VSS!
VDD!
VDD!
N100 N101
VSS!
P129 N125
P136
N132
VSS!
VDD! VSS! VSS! VSS!
N104
VSS!
($Revision: 1.35
15:28:51 1997
DFFBCPX ATL35 CMOS Gate Array
cell data sheets
DESCRIPTION: flip-flop with asynchronous clear preset with complementary outputs
SITES: Core Ring LOADS: D=2.0 CLK=1.0 C=2.0 P=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.01383 0.01387 0.01375 0.01387 0.01388 0.01377 Setup -0.15571
(NomProc,25degC,Nom trf)
Rise -0.70801 0.71565 0.83887 0.45052 0.47469 0.67391 Hold -0.08959 Fall Slope -0.01274 0.01263 0.00000 0.01269 0.01265 0.00000 Fall -0.82269 0.56415 0.00000 0.41638 0.42910 0.00000
DFFBCPX Typical Case Path Delays rise fall rise fall rise fall rise fall rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:28:51 1997
DFFBSRX ATL35 CMOS Gate Array
cell data sheets
DESCRIPTION: flip-flop with asynchronous reset with complementary outputs
ATL55Cells
Truth Table: Q(T+1) QB(T+1) Q(T) QB(T)
DFFBSRX
VDD!
VDD!
VDD!
VSS! VDD! VDD! VDD!
P100
VSS!
VSS!
VDD! VDD!
VSS!
VSS! VDD!
VSS! VDD! VDD!
VSS!
VSS! VSS! VDD! VDD!
P116 N113
VSS!
P126
VSS!
N125
VSS!
VSS!
VDD!
VSS!
($Revision: 1.35
15:30:02 1997
DFFBSRX ATL35 CMOS Gate Array
cell data sheets
DESCRIPTION: flip-flop with asynchronous reset with complementary outputs
SITES: Core Ring LOADS: D=2.0 CLK=1.0 R=2.0 S=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.02768 0.02770 0.02776 0.00000 0.00000 0.02753 Setup -0.26648
(NomProc,25degC,Nom trf)
Rise -0.69860 0.54628 0.33395 0.00000 0.00000 0.29532 Hold -0.16129 Fall Slope -0.02526 0.02532 0.02534 0.02527 0.02525 0.02541 Fall -0.71156 0.62387 0.50513 0.78850 0.44907 0.41692
DFFBSRX Typical Case Path Delays rise fall rise fall rise fall rise fall rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:30:02 1997
DFFC ATL35 CMOS Gate Array
DESCRIPTION: flip-flop with asynchronous clear
cell data sheets
Truth Table:
ATL55Cells
DFFC
Q(T+1) Q(T)
VDD! VDD! VDD! VDD!
VDD! VSS!
VDD!
VSS! VDD!
VDD!
VDD! VSS!
VSS!
VSS!
VSS!
VDD!
VDD!
VSS!
VSS!
($Revision: 1.35
15:30:02 1997
DFFC ATL35 CMOS Gate Array
DESCRIPTION: flip-flop with asynchronous clear
cell data sheets
SITES: Core Ring LOADS: D=2.0 CLK=1.0 C=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.01398 0.00000 Setup -0.15688
(NomProc,25degC,Nom trf)
Rise -0.57280 0.00000 Hold -0.06739 Fall Slope -0.01278 0.01265 Fall -0.46474 0.44156
DFFC Typical Case Path Delays rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:30:02 1997
DFFR ATL35 CMOS Gate Array
DESCRIPTION: flip-flop with asynchronous reset
cell data sheets
Truth Table:
ATL55Cells
DFFR
Q(T+1) Q(T)
VDD!
VDD!
VDD! VDD!
P180
VDD!
VSS!
P149 N152 N155
P154 N112
N182
VDD! VSS!
P122
P175 N174
VSS! VDD!
P125
P124 P131 VDD! P110 N139
VSS!
VSS!
VDD!
P162 N166 N164
VSS!
P163
VSS! VDD! VDD!
P136
P114 N101 N104
VSS!
VSS!
($Revision: 1.35
15:30:02 1997
DFFR ATL35 CMOS Gate Array
DESCRIPTION: flip-flop with asynchronous reset
cell data sheets
SITES: Core Ring LOADS: D=2.0 CLK=1.0 R=1.0
TIMING TABLE
Path -CLK Path Rise Slope -0.01404 0.00000 Setup -0.15609
(NomProc,25degC,Nom trf)
Rise -0.57881 0.00000 Hold -0.06790 Fall Slope -0.01277 0.01274 Fall -0.47395 0.49542
DFFR Typical Case Path Delays rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:30:02 1997
DFFRQ ATL35 CMOS Gate Array
DESCRIPTION: Quad flip-flop with reset
cell data sheets
ATL55Cells
DFFRQ
Truth Table: Q(T+1) Q(T)
VDD!
VSS!
VDD! VDD! VDD!
P180
VDD!
N155 P124 VDD! VSS! P131 P110
VDD! VDD!
P149 P154 N152
N182
VDD! VSS!
N112 P125
P122
VDD! VDD!
P175 N174
VSS!
VSS! P162 P163 N166 N164
VSS!
N139
VSS!
P252 N253
VSS! VDD!
P114 N104
VSS! VDD!
P136 N101
VSS!
P256 N257
VSS! VDD! VDD! VDD!
P272
VDD!
N275 P263 VSS! N279 VDD! P260 P265 N274
VSS!
N281
P269 P261 N273
N282
VDD! VSS!
N276 P262 N280 P267
P264 N278
VSS! VDD! VDD!
P270 N283
VSS!
P268 P266 N277 N301
VSS! VDD!
VDD! VDD!
P303
VDD!
N326 P312 VSS! N322 VDD! P315 P310 N327
VSS!
N320
P306 P314 N328
N319
VDD! VSS!
N325 P313 N321 P308
P311 N323
VSS! VDD! VDD!
P305 N318
VSS!
P307 P309 N324 N316
VSS! VDD!
VDD! VDD!
P388
VDD!
N365 P379 VSS! N369 VDD! P376 P381 N364
VSS!
N371
P385 P377 N363
N372
VDD! VSS!
N366 P378 N370 P383
P380 N368
VSS! VDD! VDD!
P386 N373
VSS!
P384 P382 N367 N375
VSS!
($Revision: 1.35
15:30:02 1997
DFFRQ ATL35 CMOS Gate Array
DESCRIPTION: Quad flip-flop with reset
cell data sheets
SITES: Core Ring LOADS: D0=2.0 D1=2.0 D2=2.0 D3=2.0 CLK=2.0 R=1.0
TIMING TABLE
Path -CLK Path Rise Slope -0.01401 0.01401 0.01401 0.01401 0.00000 0.00000 0.00000 0.00000 Setup -0.10562 0.10562 0.10562 0.10562
(NomProc,25degC,Nom trf)
Rise -0.69141 0.69141 0.69141 0.69141 0.00000 0.00000 0.00000 0.00000 Hold -0.20645 0.20645 0.20645 0.20645 Fall Slope -0.01277 0.01277 0.01277 0.01277 0.01267 0.01267 0.01267 0.01267 Fall -0.55449 0.55449 0.55449 0.55449 0.74735 0.74735 0.74735 0.74735
DFFRQ Typical Case Path Delays rise fall rise fall rise fall rise fall rise fall rise fall rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:30:02 1997
DFFS ATL35 CMOS Gate Array
DESCRIPTION: flip-flop with asynchronous
cell data sheets
Truth Table:
ATL55Cells
DFFS
Q(T+1) Q(T)
VDD!
P114
VDD! VDD!
P100
N120
P117 N118 N121 P122 VDD! P123 P124 N125
VSS! VSS! VSS!
N113
VDD! VSS!
P119
P116 N115
VSS!
VDD!
N106
VSS!
N101
VSS!
VSS!
N126
VDD!
VDD!
P110
P111 N109 N112
VSS!
VSS!
($Revision: 1.35
15:30:02 1997
DFFS ATL35 CMOS Gate Array
DESCRIPTION: flip-flop with asynchronous
cell data sheets
SITES: Core Ring LOADS: D=2.0 CLK=1.0 S=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.01382 0.01378 Setup -0.15688
(NomProc,25degC,Nom trf)
Rise -0.48223 0.34701 Hold -0.11597 Fall Slope -0.01308 0.00000 Fall -0.54857 0.00000
DFFS Typical Case Path Delays rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:30:02 1997
DFFSR ATL35 CMOS Gate Array
DESCRIPTION: flip-flop with asynchronous reset
cell data sheets
Truth Table:
ATL55Cells
DFFSR
Q(T+1) Q(T)
VDD!
VDD!
VDD! VDD!
VDD! VSS!
VSS!
VSS!
VDD!
VSS!
VSS! VDD!
VSS!
VSS!
VSS!
VDD! VDD!
VSS! VSS! VSS!
VSS!
VSS!
($Revision: 1.35
15:31:04 1997
DFFSR ATL35 CMOS Gate Array
DESCRIPTION: flip-flop with asynchronous reset
cell data sheets
SITES: Core Ring LOADS: D=2.0 CLK=1.0 R=2.0 S=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.01382 0.01385 0.01376 Setup -0.15612
(NomProc,25degC,Nom trf)
Rise -0.67800 0.43997 0.50411 Hold -0.15914 Fall Slope -0.01259 0.01261 0.00000 Fall -0.59294 0.31693 0.00000
DFFSR Typical Case Path Delays rise fall rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:31:04 1997
ATL35 CMOS Gate Array
DESCRIPTION: scan flip-flop
cell data sheets
Truth Table:
ATL55Cells
Q(T+1) Q(T)
VDD!
VDD!
VDD!
VDD!
N101
VSS!
VSS! VDD!
VSS! VDD!
P111
N105
VDD!
N110
VDD! VSS!
P122 N120
P103
VSS!
VSS!
VDD! VSS!
VSS! VDD! VDD!
P127 N128
VSS!
VSS!
VSS!
($Revision: 1.35
15:32:08 1997
ATL35 CMOS Gate Array
DESCRIPTION: scan flip-flop
cell data sheets
SITES: Core Ring LOADS: D=2.0 TI=2.0 CLK=1.0 TE=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.00917 Setup -0.40039 0.48338 0.51739
(NomProc,25degC,Nom trf)
Rise -0.51123 Hold -0.00000 0.00692 0.01972 Fall Slope -0.00844 Fall -0.56385
Typical Case Path Delays rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:32:08 1997
DSSBCPY ATL35 CMOS Gate Array
DESCRIPTION: scan flip-flop with clear preset
cell data sheets
ATL55Cells
Truth Table:
Q(T+1) QB(T+1) Q(T) QB(T)
DSSBCPY
VDD!
VDD!
P106
VDD!
VDD!
VDD! VDD! VSS!
VSS! VDD!
P243 N246
VDD! VSS!
N117
P224
N222
VSS!
VSS! VDD! VDD!
N124
VDD!
P231 N233 VDD!
VSS!
VSS! VDD!
P114
N108
VSS! VDD! VDD!
VSS!
P248 N247
VDD! VSS!
VSS! VSS!
P252 N256
VSS!
VSS!
($Revision: 1.35
15:32:08 1997
DSSBCPY ATL35 CMOS Gate Array
DESCRIPTION: scan flip-flop with clear preset
cell data sheets
SITES: Core Ring LOADS: D=2.0 TI=2.0 CLK=1.0 TE=2.0 C=2.0 P=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.01384 0.01383 0.01382 0.00000 0.00000 0.01388 Setup -0.50944 0.46345 0.61939
(NomProc,25degC,Nom trf)
Rise -0.83469 0.49469 0.37091 0.00000 0.00000 0.34923 Hold -0.00000 0.00000 0.00000 Fall Slope -0.01273 0.01273 0.01289 0.01277 0.01267 0.01274 Fall -0.72735 0.72751 0.46890 1.05516 0.53949 0.41808
DSSBCPY Typical Case Path Delays rise fall rise fall rise fall rise fall rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:32:08 1997
DSSBR ATL35 CMOS Gate Array
DESCRIPTION: scan flip-flop with reset
cell data sheets
Truth Table:
ATL55Cells
Q(T+1) QB(T+1) Q(T) QB(T)
DSSBR
VDD!
P306
VDD! VDD! VDD!
N286
P279 N280
VSS!
N250
P274 P273
N231
P240 N212 N244 P234 VDD! P252 P257 N263
VSS! VSS! VSS!
N302
VDD! VSS!
P214
P284 N294
VDD!
P311 N315
VSS! VDD!
P215 N241 VDD! P203
N269
VSS!
N265
VSS!
P223 N198
VSS!
P289 P283
P338 N343 N256
VDD! VSS!
N297
VSS! VDD!
VDD!
P344 N335
P200
P222 N237 N229
VSS! VSS!
VSS!
($Revision: 1.35
15:32:08 1997
DSSBR ATL35 CMOS Gate Array
DESCRIPTION: scan flip-flop with reset
cell data sheets
SITES: Core Ring LOADS: D=2.0 TI=2.0 CLK=1.0 TE=2.0 R=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.01377 0.01380 0.01379 0.00000 Setup -0.50277 0.50116 0.61597
(NomProc,25degC,Nom trf)
Rise -0.64500 0.50883 0.26490 0.00000 Hold -0.00000 0.00000 0.02002 Fall Slope -0.01275 0.01271 0.00000 0.01259 Fall -0.73294 0.51787 0.00000 0.45991
DSSBR Typical Case Path Delays rise fall rise fall rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:32:08 1997
DSSBS ATL35 CMOS Gate Array
DESCRIPTION: scan flip-flop with
cell data sheets
ATL55Cells
Truth Table:
Q(T+1) QB(T+1) Q(T) QB(T)
DSSBS
VDD!
VDD!
P158
P114
VDD! VDD! VDD!
VDD!
N155
VSS!
N135
P128 N131
VSS!
P100
N106
N120
P117 N118 N121 P122 VDD!
VSS! VDD!
N113
VDD! VSS!
P119
P116 N115
P134 N139
N101
VDD! VSS!
VSS! VSS!
P124 N125 N126
P123
VSS! VDD!
P140
VDD!
P162 N173
VDD! VSS!
P146
VDD!
VDD!
P110
P169 P111 N170 N112
VSS!
N147
VSS!
N109
VSS!
VSS!
($Revision: 1.35
15:32:08 1997
DSSBS ATL35 CMOS Gate Array
DESCRIPTION: scan flip-flop with
cell data sheets
SITES: Core Ring LOADS: D=2.0 TI=2.0 CLK=1.0 TE=2.0 S=1.0
TIMING TABLE
Path -CLK Path Rise Slope -0.01386 0.01382 0.00000 0.01374 Setup -0.40049 0.40317 0.61901
(NomProc,25degC,Nom trf)
Rise -0.75651 0.47091 0.00000 0.55723 Hold -0.00000 0.00000 0.00000 Fall Slope -0.01263 0.01263 0.01260 0.00000 Fall -0.61367 0.57066 0.31946 0.00000
DSSBS Typical Case Path Delays rise fall rise fall rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:32:08 1997
DSSR ATL35 CMOS Gate Array
DESCRIPTION: scan flip-flop with reset
cell data sheets
ATL55Cells
Truth Table:
Q(T+1) Q(T)
DSSR
VDD! VDD!
VDD!
VDD!
N286
P279 N280
VSS!
N250
P274 P273
N231
P240 N212 N244 P234 VDD! P252 P257 N263
VSS! VSS! VSS!
P306
P214
N302
VDD! VSS!
P284 N294
VDD!
P215 N241 VDD! P203
N269
VSS!
N265
VSS!
P311 N315
VSS!
P223 N198
VSS!
P289 P283
N297
VSS! VDD!
N256
VDD!
P200
P222 N237 N229
VSS!
VSS!
($Revision: 1.35
15:32:08 1997
DSSR ATL35 CMOS Gate Array
DESCRIPTION: scan flip-flop with reset
cell data sheets
SITES: Core Ring LOADS: D=2.0 TI=2.0 CLK=1.0 TE=2.0 R=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.01375 0.00000 Setup -0.50277 0.50550 0.61609
(NomProc,25degC,Nom trf)
Rise -0.51780 0.00000 Hold -0.00000 0.00000 0.01998 Fall Slope -0.01271 0.01268 Fall -0.51882 0.45610
DSSR Typical Case Path Delays rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:32:08 1997
DSSS ATL35 CMOS Gate Array
DESCRIPTION: scan flip-flop with
cell data sheets
ATL55Cells
Truth Table:
Q(T+1) Q(T)
DSSS
VDD!
VDD!
P158
P114
VDD! VDD! VDD!
VDD!
N135
N155 VSS! P128 N131
P100
N106 N101
N120
P117
VSS!
N113
P119 N121
N118 P122 VDD!
VSS! VDD! VDD!
P134
P116 N115
VSS!
VSS!
VDD! VSS!
N139
VSS! VDD! VDD!
P124
P123
P140
VDD!
N125 N126
VSS!
P146
N147
VSS!
P110 N109
VSS!
P111 N112
VSS!
($Revision: 1.35
15:33:06 1997
DSSS ATL35 CMOS Gate Array
DESCRIPTION: scan flip-flop with
cell data sheets
SITES: Core Ring LOADS: D=2.0 TI=2.0 CLK=1.0 TE=2.0 S=1.0
TIMING TABLE
Path -CLK Path Rise Slope -0.01378 0.01381 Setup -0.40040 0.40308 0.61892
(NomProc,25degC,Nom trf)
Rise -0.47286 0.50812 Hold -0.00000 0.00000 0.00000 Fall Slope -0.01263 0.00000 Fall -0.56643 0.00000
DSSS Typical Case Path Delays rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:33:06 1997
DSSSR ATL35 CMOS Gate Array
DESCRIPTION: scan flip-flop with reset
cell data sheets
ATL55Cells
DSSSR
Truth Table:
Q(T+1) Q(T)
VDD!
P136
VDD!
P134
VSS!
N140
VDD! VDD! VDD!
N115
N132
VDD! VDD!
VSS! VDD!
VSS! VDD! VDD!
P119 N108
P123 N126 P120
VSS!
VDD! VDD! VSS!
VSS! VDD!
VSS!
VDD!
VSS!
VSS!
P124
N113
VDD!
VDD!
VSS!
VSS!
VSS!
($Revision: 1.35
15:33:06 1997
DSSSR ATL35 CMOS Gate Array
DESCRIPTION: scan flip-flop with reset
cell data sheets
SITES: Core Ring LOADS: D=2.0 TI=2.0 CLK=1.0 TE=2.0 R=1.0 S=1.0
TIMING TABLE
Path -CLK Path Rise Slope -0.01382 0.01385 0.01383 Setup -0.50328 0.50614 0.61699
(NomProc,25degC,Nom trf)
Rise -0.60140 0.47723 0.79112 Hold -0.00000 0.00000 0.01944 Fall Slope -0.01270 0.01264 0.00000 Fall -0.58152 0.34695 0.00000
DSSSR Typical Case Path Delays rise fall rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:33:06 1997
ATL35 CMOS Gate Array
DESCRIPTION: flip-flop
cell data sheets
Truth Table:
ATL55Cells
Q(T+1) Q(T) Q(T) Q(T)BAR
VDD!
I130 I133
VDD! VDD! VDD! VSS!
VDD!
I120 I115 I114 VDD! I118 I121
VSS! VSS! VSS!
I126 I127
I129 I132
VSS! VDD!
I131 I134
VSS!
I124
VSS!
P109
I112 I113 VDD!
VSS!
VDD!
I128 I139
I116 I122 I123 I117
I135 I137
VSS!
($Revision: 1.35
15:34:55 1997
ATL35 CMOS Gate Array
DESCRIPTION: flip-flop
cell data sheets
SITES: Core Ring LOADS: J=2.0 K=1.0 CLK=1.0
TIMING TABLE
Path -CLK Path Rise Slope -0.01382 Setup -0.19992 0.72418
(NomProc,25degC,Nom trf)
Rise -0.49373 Hold -0.09626 0.01134 Fall Slope -0.01282 Fall -0.47539
Typical Case Path Delays rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:34:55 1997
JKFBCPX ATL35 CMOS Gate Array
cell data sheets
DESCRIPTION: Clear preset flip-flop with asynchronous clear preset complementary outputs
ATL55Cells
Truth Table:
Q(T+1) QB(T+1) Q(T) QB(T) Q(T) QB(T) QB(T) Q(T)
JKFBCPX
VDD! VDD! VDD! VDD! VDD! VDD!
VDD!
P189 N188
P155
P146
VSS! VDD!
N156 N153
VDD!
VDD!
P158
P105 N103
P167
VSS!
VSS!
N157 N160
VSS! VDD! VDD!
VSS! VDD!
VDD!
VDD!
VDD! VSS!
P175
P198 N200
VDD!
P172
P184
VSS!
N100
VSS! VDD!
N168
N171
N183
P199 N197
VSS!
VSS!
VSS! VSS!
VSS! VDD! VDD!
P117 N115
P124 N119
VSS!
VSS!
($Revision: 1.35
15:34:55 1997
JKFBCPX ATL35 CMOS Gate Array
cell data sheets
DESCRIPTION: Clear preset flip-flop with asynchronous clear preset complementary outputs
SITES: Core Ring LOADS: J=1.0 K=1.0 CLK=1.0 C=2.0 P=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.01388 0.01391 0.01400 0.01385 0.01398 0.01376 Setup -0.95451 0.55668
(NomProc,25degC,Nom trf)
Rise -0.90109 0.59587 0.88927 0.33084 0.56499 0.71335 Hold -0.01156 0.01159 Fall Slope -0.01266 0.01265 0.00000 0.01270 0.01270 0.00000 Fall -0.78615 0.58593 0.00000 0.29485 0.41048 0.00000
JKFBCPX Typical Case Path Delays rise fall rise fall rise fall rise fall rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:34:55 1997
JKFC ATL35 CMOS Gate Array
DESCRIPTION: flip-flop with asynchronous clear
cell data sheets
ATL55Cells
Truth Table: Q(T+1) Q(T) Q(T) Q(T)BAR
JKFC
VDD!
I130 I133
VDD! VDD! VDD! VDD! VSS!
VDD!
I119 I115 I114 VDD! I118 I121
VSS! VSS! VSS!
I120 I124 I125
VSS!
I126 I127
I129 I132
VSS! VDD! VDD!
I131 I134
VSS!
P109
I112 I113 VDD!
VSS!
VDD!
I128 I139
I116 I122 I123 I117
I135 I137 I138
VSS!
I136
($Revision: 1.35
15:35:51 1997
JKFC ATL35 CMOS Gate Array
DESCRIPTION: flip-flop with asynchronous clear
cell data sheets
SITES: Core Ring LOADS: J=2.0 K=1.0 CLK=1.0 C=2.0
TIMING TABLE
Path -CLK Path Rise Slope -0.01407 0.00000 Setup -0.29859 0.72386
(NomProc,25degC,Nom trf)
Rise -0.57077 0.00000 Hold -0.19325 0.01068 Fall Slope -0.01278 0.01266 Fall -0.46681 0.44030
JKFC Typical Case Path Delays rise fall rise fall
Delay (ns)
Number unit loads
($Revision: 1.35
15:35:51 1997

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