Memory ATL35 0.35µ Compiled Gate Level SRAMs Compiled Gate Level
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ATL35 Memory SRAMs-1.2-04/99
Memory ATL35 0.35µ Compiled Gate Level SRAMs
Compiled Gate Level SRAM Loading Common Single Port SRAM Sizes: Table. Common Port SRAM Sizes: Table. PRAM4X4 PRAM4X4R1W1 PRAM48X4 PRAM64X4 Single Port Operation Best Case Process Typical Case Process Worst Case Process. Port Operation Best Case Process Typical Case Process 9-10 Worst Case Process. 9-11
ATL35 Memory SRAMs-1.2-04/99
Compiled Gate Level SRAMs
Atmel offers variety compiled personalization RAMs ATL35 series gate arrays. These static asynchronous SRAMs utilize personalization layers occupy standard gate array sites. SRAMs come either port single port architectures. port SRAMs have sets address inputs, read address write address. output SRAM word which pointed read address. When (Write Enable) input goes low, word written address specified write address. single port SRAMs have address inputs which controls both write read operations. output SRAM always word which pointed address inputs. When input goes low, word written address specified address input. Both single port port SRAMs have enables their outputs. outputs stay high while output enable signal high. SRAMs compiled depths ranging from words words. following tables give size information some common SRAM sizes. Note that site count listed tables includes unusable sites immediately around SRAM. Contact Atmel exact size SRAM listed.
SRAM Loading
Single Port SRAM Inputs Port SRAM Inputs LOADS (unit loads): A0=4.0 A1=4.0 A2=4.0 A3=4.0 A4=4.0 LOADS (unit loads): A0=4.0 A1=4.0 A2=4.0 A3=4.0 A4=4.0 B0=4.0 N=4.0 WE=4.0 DIN=4.0 B1=4.0 B2=4.0 B3=4.0 B4=4.0 AN=4.0 BWE=4.0 DIN=4.0
Common Single Port SRAM Sizes
SRAM Width (bits)
sites PRAM4X8 sites PRAM8X8 sites PRAM12X8 sites PRAM16X8 1302 sites PRAM24X8 1694 sites PRAM32X8
sites PRAM4X12 sites PRAM8X12 sites PRAM12X12 1170 sites PRAM16X12 1674 sites PRAM24X12 2178 sites PRAM32X12
sites PRAM4X16 sites PRAM8X16 1122 sites PRAM12X16 1430 sites PRAM16X16 2046 sites PRAM24X16 2662 sites PRAM32X16
sites PRAM4X24 1110 sites PRAM8X24 1530 sites PRAM12X24 1950 sites PRAM16X24 2790 sites PRAM24X24 3630 sites PRAM32X24
sites PRAM4X32 1406 sites PRAM8X32 1938 sites PRAM12X32 2470 sites PRAM16X32 3534sites PRAM24X32 4598 sites PRAM32X32
Depth (words)
ATL35 Memory SRAMs
ATL35 Memory SRAMs-1.2-04/99
Common Port SRAM Sizes
SRAM Width (bits)
sites PRAM4X8R1W1
sites PRAM4X12R1W1 sites PRAM8X12R1W1 1007 sites PRAM12X12R1W1 1273 sites PRAM16X12R1W1 1805 sites PRAM24X12R1W1 2337 sites PRAM32X12R1W1
sites PRAM4X16R1W1 sites PRAM8X16R1W1 1219 sites PRAM12X16R1W1 1541 sites PRAM16X16R1W1 2185 sites PRAM24X16R1W1 2829 sites PRAM32X16R1W1
sites PRAM4X24R1W1 1209 sites PRAM8X24R1W1 1643 sites PRAM12X24R1W1 2077 sites PRAM16X24R1W1 2945 sites PRAM24X24R1W1 3813 sites PRAM32X24R1W1
sites PRAM4X32R1W1 1521 sites PRAM8X32R1W1 2067 sites PRAM12X32R1W1 2613 sites PRAM16X32R1W1 3705 sites PRAM24X32R1W1 4797 sites PRAM32X32R1W1
DEPTH (words)
sites PRAM8X8R1W1
sites PRAM12X8R1W1
1005 sites PRAM16X8R1W1
1425 sites PRAM24X8R1W1
1845 sites PRAM32X8R1W1
Below symbols single port SRAMs (PRAM4X4 PRAM4X4R1W1). Note that unused address inputs must tied SRAM will function properly (i.e. ADDR4 tied
SRAMs smaller than words, ADDR3 SRAMs smaller than words, ADDR2 SRAMs smaller than words, ADDR1 word SRAM). This also true port memories.
PRAM4X4
PRAM4X4R1W1
DIN0 DIN1 DIN2 DIN3
DOUT0 DOUT1 DOUT2 DOUT3
BDIN0 BDIN1 BDIN2 BDIN3
ADOUT0 ADOUT1 ADOUT2 ADOUT3
ATL35 Memory SRAMs-1.2-04/99
PRAM48X4
SRAMs multiplexed create deeper SRAM. example build single port SRAM shown below.
BUF2 BUF2 BUF2 BUF2 BUF2 INV2
A5BAR INV2
DIN0 DIN1 DIN2 DIN3 NAN2H DOUT3 DOUT0 DOUT1 DOUT2 DOUT3 NAN2H DOUT1 NAN2H DOUT0
PRAM32X4
NAN2H DOUT2
INV2 DIN0 INV2 DIN1 INV2 DIN2 INV2 DIN3
A5BAR
DIN0 DIN1 DIN2 DIN3
DOUT0 DOUT1 DOUT2 DOUT3
PRAM16X4
VSS!
ORR2
A5BAR
ORR2
following pages contain SRAM write read timing which gathered from running Spice simulations. write timing determined measuring propagation delay from ADDR, pins memory latch large (32x36) small (2x2) SRAM. times given were measured from input pins when actual data memory changed. This done initializing SRAM specific state such that only input under analysis changed, memory would changed. delays were measured memory rising falling. longest path memory latch
large SRAM represents maximum delay shortest path memory latch small SRAM represents minimum delay. setup hold timing were derived from these delays. equations used given with specifications. read timing determined measuring propagation delay through SRAMs. These Spice simulations were with best, typical, worst temperature process conditions. Four unit loads were applied SRAM outputs Spice simulations.
ATL35 Memory SRAMs
ATL35 Memory SRAMs-1.2-04/99
PRAM64X4
SRAMs also connected with latched inputs create synchronous SRAM. example build single port synchronous SRAM shown below. Note: necessary initialize flop forcing reset beginning simulation.
INV2 DIN<3:0> BUF2 DDR<4:0>
D<3:0> AL<0> AL<1> AL<4:0> AL<2> AL<3> AL<4> DIN0 DIN1 DIN2 DIN3 NAN2H DOUT0 DOUT1 DOUT2 DOUT3 NAN2H DOUT NAN2H DOUT
PRAM32X4
NAN2H
DOUT
INV2 ADDR<5>
AL5B
INV2
WE_A
DOUT
DEC4N VSS!
WE_B WE_A AL<0> AL<1> AL<2> AL<3> AL<4> AL5B WE_B
DIN0 DIN1 DIN2 DIN3
DOUT0 DOUT1 DOUT2 DOUT3
NAN2
DLY2 INV1
PRAM32X4
ATL35 Memory SRAMs-1.2-04/99
Single Port Operation 0.35µ Best Case Process
Compiled Personalization SRAMs
Conditions
Best Case Process, Temperature -55°C Voltage Volts Output Loading Unit Loads .030pf) Input Rise/Fall Time
Write Cycle Timing ADDRSU DATASU DATAHOLD WEMINPWL WEMINPWH ADDRHOLD
Write Cycle Propagation Delay*
Minimum (PRAM2x2) Maximum (PRAM32x36) 0.71 0.87 1.01 0.31
ADDR
ADDR (MAX) WRITE (MIN) WRITE (MAX) ADDR (MIN) (MAX) WRITE (MIN) WRITE (MAX) (MIN) WRITE (MAX) ADDRSU DATAHOLD
MEMLATCH ADDR
1.01 0.35 0.66 0.71 0.44 0.27 0.31 0.21 0.10 0.71 0.08 0.63 0.87 0.66 0.63 1.29
0.21 0.35 0.44 0.08
ADDRSU ADDRHOLD DATASU DATAHOLD WEMINPWL WEMINPWH
Read Timing*
Minimum (PRAM2x2) PDA-D PD0-D 0.49 0.14 Maximum (PRAM32x36) 1.25 0.71
PDA-D PD0-D DOUT time nanoseconds
ATL35 Memory SRAMs
ATL35 Memory SRAMs-1.2-04/99
Single Port Operation 0.35µ Typical Case Process
Compiled Personalization SRAMs
Conditions
Typical Case Process, Temperature 25°C Voltage Volts Output Loading Unit Loads .030pf) Input Rise/Fall Time
Write Cycle Timing ADDRSU DATASU DATAHOLD WEMINPWL WEMINPWH ADDRHOLD
Write Cycle Propagation Delay*
Minimum (PRAM2x2) Maximum (PRAM32x36) 1.32 1.73 2.04 0.59
ADDR
ADDR (MAX) WRITE (MIN) WRITE (MAX) ADDR (MIN) (MAX) WRITE (MIN) WRITE (MAX) (MIN) WRITE (MAX) ADDRSU DATAHOLD
MEMLATCH ADDR
2.04 0.72 1.35 1.32 0.82 0.50 0.59 0.29 0.30 1.32 0.15 1.17 1.73 1.32 1.17 2.49
0.30 0.72 0.82 0.15
ADDRSU ADDRHOLD DATASU DATAHOLD WEMINPWL WEMINPWH
Read Timing*
PDA-D PD0-D DOUT time nanoseconds
PDA-D PD0-D
Minimum (PRAM2x2) 0.88 0.20
Maximum (PRAM32x36) 2.47 1.18
ATL35 Memory SRAMs-1.2-04/99
Single Port Operation 0.35µ Worst Case Process
Compiled Personalization SRAMs
Conditions
Worst Case Process, Temperature 125°C Voltage Volts Output Loading Unit Loads .030pf) Input Rise/Fall Time
Write Cycle Timing WEMINPWL ADDRSU DATASU DATAHOLD WEMINPWH ADDRHOLD
Write Cycle Propagation Delay*
Minimum (PRAM2x2) Maximum (PRAM32x36) 2.91 3.85 4.63 1.13
ADDR
ADDR (MAX) WRITE (MIN) WRITE (MAX) ADDR (MIN) (MAX) WRITE (MIN) WRITE (MAX) (MIN) WRITE (MAX) ADDRSU DATAHOLD
MEMLATCH ADDR
4.63 1.61 3.02 2.91 1.90 1.01 1.13 0.77 0.36 2.91 0.51 2.40 3.85 3.02 2.40 5.42
0.77 1.61 1.90 0.51
ADDRSU ADDRHOLD DATASU DATAHOLD WEMINPWL WEMINPWH
Read Timing*
PDA-D PD0-D DOUT time nanoseconds
PDA-D PD0-D
Minimum (PRAM2x2) 2.00 0.60
Maximum (PRAM32x36) 5.58 2.34
ATL35 Memory SRAMs
ATL35 Memory SRAMs-1.2-04/99
Port Operation 0.35µ Best Case Process
Compiled Personalization PRAMR1W1
Conditions
Best Case Process, Temperature -55°C Voltage Volts Output Loading Unit Loads .030pf) Input Rise/Fall Time
Write Cycle Timing WEMINPWL ADDRSU DATASU BDIN DATAHOLD WEMINPWH ADDRHOLD
Write Cycle Propagation Delay*
Minimum Maximum (PRAM2x2R1W1) (PRAM32x36R1W1)
BDIN
ADDR
ADDR (MAX) WRITE (MIN) WRITE (MAX) ADDR (MIN) (MAX) WRITE (MIN) WRITE (MAX) (MIN) WRITE (MAX) ADDRSU DATAHOLD
MEMLATCH ADDR
1.14 0.35 0.79 0.71 0.55 0.16 0.31 0.21 0.10 0.71 0.08 0.63 0.88 0.79 0.63 1.42
0.21 0.35 0.55 0.08
0.71 0.88 1.14 0.31
ADDRSU ADDRHOLD DATASU DATAHOLD WEMINPWL WEMINPWH
Read Timing*
PDA-D PD0-D ADOUT time nanoseconds
PDA-D PD0-D
Minimum (PRAM2x2R1W1) 0.48 0.14
Maximum (PRAM32x36R1W1) 1.28 0.71
ATL35 Memory SRAMs-1.2-04/99
Port Operation 0.35µ Typical Case Process
Compiled Personalization PRAMR1W1
Conditions
Typical Case Process, Temperature 25°C Voltage Volts Output Loading Unit Loads .030pf) Input Rise/Fall Time
Write Cycle Timing WEMINPWL ADDRSU DATASU BDIN DATAHOLD WEMINPWH ADDRHOLD
Write Cycle Propagation Delay*
Minimum Maximum (PRAM2x2R1W1) (PRAM32x36R1W1)
BDIN
ADDR MEMLATCH
ADDR
2.28 0.71 1.57 1.32 1.06 0.26 0.59 0.29 0.30 1.32 0.15 1.17 1.70 1.57 1.17 2.74
0.29 0.71 1.06 0.15
1.32 1.70 2.28 0.59
ADDRSU ADDRHOLD DATASU DATAHOLD WEMINPWL WEMINPWH
ADDR (MAX) WRITE (MIN) WRITE (MAX) ADDR (MIN) (MAX) WRITE (MIN) WRITE (MAX) (MIN) WRITE (MAX) ADDRSU DATAHOLD
Read Timing*
PDA-D PD0-D ADOUT time nanoseconds
PDA-D PD0-D
Minimum (PRAM2x2R1W1) 0.92 0.19
Maximum (PRAM32x36R1W1) 2.53 1.18
9-10
ATL35 Memory SRAMs
ATL35 Memory SRAMs-1.2-04/99
Port Operation 0.35µ Worst Case Process
Compiled Personalization PRAMR1W1
Conditions
Worst Case Process, Temperature 125°C Voltage Volts Output Loading Unit Loads .030pf) Input Rise/Fall Time
Write Cycle Timing ADDRSU DATASU BDIN Write Cycle Propagation Delay
Minimum Maximum (PRAM2x2R1W1) (PRAM32x36R1W1)
WEMINPWL
WEMINPWH ADDRHOLD DATAHOLD
BDIN
ADDR
ADDR (MAX) WRITE (MIN) WRITE (MAX) ADDR (MIN) (MAX) WRITE (MIN) WRITE (MAX) (MIN) WRITE (MAX) ADDRSU DATAHOLD
MEMLATCH ADDR
0.75 1.61 2.50 0.51
2.91 3.85 5.23 1.13
ADDRSU ADDRHOLD DATASU DATAHOLD WEMINPWL WEMINPWH
5.23 1.61 3.62 2.91 2.50 0.41 1.13 0.75 0.38 2.91 0.51 2.40 3.85 3.62 2.40 6.02
Read Timing
PDA-D PD0-D ADOUT time nanoseconds
PDA-D PD0-D
Minimum (PRAM2x2R1W1) 2.10 0.49
Maximum (PRAM32x36R1W1) 5.71 2.34
9-11
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