HomePHYSingle-Chip 1/10 Mbps Home Networking DISTINCTIVE CHARACTE
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Am79C901
HomePHYSingle-Chip 1/10 Mbps Home Networking
DISTINCTIVE CHARACTERISTICS
Fully integrated Mbps HomePNA Physical Layer (PHY) defined Home Phoneline Networking Alliance (HomePNA) specification Optimized home networking applications over existing telephone wire Media Independent Interface (MII)-compatible connecting external Media Access Controller (MAC) In-band control features: Adjustable power speed levels bits reserved in-band messaging piggybacked Ethernet packet Register programmable features: Power control Speed control Performance registers Optional control Squelch algorithm Major frame timing parameters programmable: ISBI, ISBI, pulse width, inter-symbol time any1Homelink detection: Indicates that valid home networking node been detected Detects network failure allows upper layer protocol take corrective action Fully integrated Mbps Ethernet transceiver Comprehensive Auto-Negotiation implementation IEEE 802.3u-compliant Full-duplex operation supported port with independent Transmit (TX) Receive (RX) channels Optimized 10BASE-T applications Compliant with HomePNA specification General Purpose Serial Interface (GPSI)/Serial Peripheral Interface (SPI) Extensive programmable internal/external loopback capabilities Extensive status support IEEE 1149.1-compliant JTAG Boundary Scan test access port interface Very power consumption +3.3 power supply along with tolerant I/Os enable broad system compatibility XTAL1 supports only XTAL2 supports only Available low-cost 68-pin PLCC package
GENERAL DESCRIPTION
Am79C901 HomePHY single-chip device that contains both physical layer (PHY) Mbps data networking over existing residential telephone wiring based specification published HomePNA physical layer supporting IEEE 802.3 standard 10BASE-T. HomePHY targeted embedded applications both GPSI MII-compatible interfaces. integrated HomePNA transceiver physical layer device that enables data networking speeds Mbps over existing residential phone wiring regardless topology without disrupting telephone (POTS) service. integrated Ethernet transceiver physical layer device suppor ting IEEE 802.3 standard 10BASE-T. provides layer functions required support Mbps data transfer speeds. compliant IEEE 1149.1 JTAG test interface board level testing provided. Am79C901 also provides on-chip drivers collision, link integrity, speed, activity, power output. Am79C901 fabricated advanced power CMOS process provide operating current power sensitive applications. Am79C901 available low-cost 68-pin PLCC package.
Publication# 22304 Rev: Amendment/0 Issue Date: April 1999
Refer Website (www.amd.com) latest information.
BLOCK DIAGRAM
POWER
SPEED
LINK
TCLK
1Mbps HomePNA Interface JTAG Port Control Link Control
PHY_SEL PHY_AD ISOLATE MII/GPSI GM_MODE RXDAT, RXCLK, RXCRS, CLS, TXDAT, TXCLK, TXEN RXD[3:0], TXD[3:0], CRS, COL, RX_DV, TX_EN, TX_CLK, RX_CLK, RX_ER MDC, MDIO SCLK, SDI, SDO,
Transmit State Machine
Drive Control HRTXRXP/N
Data Interface Receive State Machine Analog Front
DATA
MII/GPSI Interface
DATA
Control Registers 10BASE-T CONTROL CONTROL Link Control
Transmit State Machine
Data Interface Receive State Machine
CONTROL
Clock Reference
Control Registers
XTAL1
XTAL2
XCLK/XTAL
22304A-1
Am79C901
TABLE CONTENTS
DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION. BLOCK DIAGRAM RELATED PRODUCTS. CONNECTION DIAGRAM 068). DESIGNATIONS 068). Listed Number Listed Group Listed Driver Type ORDERING INFORMATION Standard Products DESCRIPTIONS Configuration Pins Board Interface GPSI Interface Interface (Slave Mode Only) Interface IEEE 1149.1 (JTAG) Test Access Port Interface Ethernet Network Interfaces HomePNA Network Interface Clock Interface Power Supply Scan Test Interface BASIC FUNCTIONS. Network Interfaces Data Interfaces Reset H_RESET S_RESET. DETAILED FUNCTIONS GPSI Interface Serial Peripheral Interface (SPI-Slave) Mode MII-Compatible Interface HomePNA MII-Compliant Interface 10BASE-T Mbps HomePNA PHY. HomePNA Medium Interface. HomePNA Symbol Waveform Time Interval Unit. Collisions Signal. Access Values. Silence Interval (AID symbol Data Symbols. Mode Interface Mbps HomePNA Loopback any1Home Link Detection 10BASE-T Twisted Pair Transmit Function Twisted Pair Receive Function Twisted Pair Interface Status Collision Detect Function Jabber Function Reverse Polarity Detect Auto-Negotiation Soft Reset Function 10BASE-T Loopback Support IEEE 1149.1 (JTAG) Test Access Port Interface Boundary Scan Circuit
Am79C901
Finite State Machine Supported Instructions Instruction Register Decoding Logic Boundary Scan Register Other Data Registers Boundary Scan Cells USER ACCESSIBLE REGISTERS Mbps HomePNA Management Registers (HPRs) HPR0: HomePNA Control Register (Register HPR1: HomePNA Status Register (Register HPR2 HPR3: HomePNA Registers (Registers HPR4: HomePNA Auto-Negotiation Advertisement Register (Register HPR5: HomePNA Auto-Negotiation Link Partner Ability Register (Register HPR6: HomePNA Auto-Negotiation Expansion Register (Register HPR7: HomePNA Auto-Negotiation Next Page Register (Register Reserved Registers: HPR8 HPR15 HPR16: HomePNA Control Register (Register HPR17: HomePNA Status/Control Register (Register HPR18 HPR19: HomePNA TxCOMM Registers (Registers HPR20 HPR21: HomePNA RxCOMM Registers (Registers HPR22: HomePNA Register (Register 22). HPR23: HomePNA Noise Control Register (Register HPR24: HomePNA Noise Control Register (Register HPR25: HomePNA Noise Statistics Register (Register HPR26: HomePNA Event Status Register (Register HPR27: HomePNA Control Register (Register HPR28: HomePNA ISBI Control Register (Register HPR29: HomePNA Control Register (Register HPR30: HomePNA Drive Level Control Register (Register HPR31: HomePNA Analog Control Register (Register
10BASE-T Management Registers (TBRs)
TBR0: 10BASE-T Control Register (Register TBR1: 10BASE-T Status Register (Register TBR2 TBR3: 10BASE-T Identifier Register (Registers TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register Reserved Registers (Registers 8-15, 20-23, 25-31) TBR16: 10BASE-T Status Enable Register (Register TBR17: 10BASE-T Control/Status Register (Register TBR19: 10BASE-T Management Extension Register (Register TBR24: 10BASE-T Summary Status Register (Register ABSOLUTE MAXIMUM RATINGS OPERATING RANGES CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES SWITCHING WAVEFORMS Switching Waveforms SWITCHING TEST CIRCUITS CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES GPSI 10BASE-T Transmit Timing (GPSI) 10BASE-T Receive Timing (GPSI) 10BASE-T Transmit Clock Timing (GPSI) 10BASE-T Receive Clock Timing (GPSI) Mbps HomePNA Transmit Timing (GPSI) Mbps HomePNA Receive Timing (GPSI) Mbps HomePNA Clock Timing (GPSI) 10BASE-T Transmit Timing (MII).
Am79C901
10BASE-T Receive Timing (MII) 10BASE-T Transmit Clock Timing (MII). 10BASE-T Receive Clock Timing (MII) Mbps HomePNA Transmit Timing (MII) Mbps HomePNA Receive Timing (MII) Mbps HomePNA Clock Timing (MII) MDC/MDIO 10BASE-T Mbps HomePNA Analog JTAG External Clock (XTAL1) Reset PHYSICAL DIMENSIONS INDEX. .INDEX-1 LIST FIGURES Figure Idle State. Figure RXPKT RXCRS Asserted. Figure RXPKT RXCRS Cleared. Figure TXPKT TXEN Asserted. Figure TXPKT RXCLK Active. Figure TXPKT TXEN Cleared Figure TXPKT Asserted Figure RXPKT Asserted Figure Operation Interface. Figure Read Operation Figure Aborted Operation Interface. Figure First Operation Following Abort Figure Normal Operation Figure Start Transmission Figure Transmission Figure HomePNA Framing. Figure Symbol Transmit Timing Figure Symbol Receive Timing Figure Transmit Data Symbol Timing Figure Receive Symbol Timing Figure Coding Tree Figure 10BASE-T Transmit Receive Data Paths Figure Normal Tri-State Outputs Figure Mbps Transmit Timing (GPSI) Figure Mbps Receive Start Packet Timing (GPSI) Figure Mbps Receive Packet Timing (GPSI) Figure Mbps Transmit Receive Clock Timing (GPSI) Figure Mbps HomePNA Transmit Timing (GPSI) Figure Mbps HomePNA Receive Timing (GPSI). Figure Mbps HomePNA Clock Timing (GPSI). Figure Mbps Transmit Timing (MII) Figure Mbps Receive Start Packet Timing (MII) Figure Mbps Receive Packet Timing (MII) Figure Mbps Transmit Receive Clock Timing (MII) Figure Mbps HomePNA Transmit Timing (MII) Figure Mbps HomePNA Receive Timing (MII) Figure Mbps HomePNA Clock Timing (MII) Figure Management Timing Figure Timing. Figure Mbps Transmit (TX±) Timing Diagram Figure Mbps Receive (RX±) Timing Diagram Figure HomePNA Waveform Figure JTAG (IEEE 1149.1) Test Signal Timing Figure Clock Timing
Am79C901
LIST TABLES Table Clock Source Selection. Table GPSI Timing Table Codes. Table MII-Compatible Timing Table Control Frame Format. Table HomePNA Pulse Parameters. Table Access Symbol Pulse Positions Encoding Table Blanking Interval Speed Settings Table Master Station Control Word Functions Table Auto-Negotiation Capabilities Table Default Configuration Table IEEE 1149.1 Supported Instruction Summary Table Mode Operation. Table Device Register Table Boundary Scan Ring Order Table Mbps HomePNA Management Registers (HPRs) Table HPR0: HomePNA Control Register (Register Table HPR1: HomePNA Status Register (Register Table HPR2: HomePNA Register (Register Table HPR3: HomePNA Register (Register Table HPR4: HomePNA Auto-Negotiation Advertisement Register (Register Table HPR5: HomePNA Auto-Negotiation Link Partner Ability Register Base Page Format (Register Table HPR5: HomePNA Auto-Negotiation Link Partner Ability Register Next Page Format (Register Table HPR6: HomePNA Auto-Negotiation Expansion Register (Register Table HPR7: HomePNA Auto-Negotiation Next Page Register (Register Table HPR16: HomePNA Control Register (Register Table HPR17: HomePNA Status/Control Register (Register 17). Table HPR18 HPR19: HomePNA TxCOMM Registers (Registers Table HPR20 HPR21: HomePNA RxCOMM Registers (Registers 21). Table HPR22: HomePNA Register (Register Table HPR23: HomePNA Noise Control Register (Register Table HPR24: HomePNA Noise Control Register (Register 24). Table HPR25: HomePNA Noise Statistics Register (Register Table HPR26: HomePNA Event Status Register (Register Table HPR27: HomePNA Control Register (Register Table HPR28: HomePNA ISBI Control Register (Register Table HPR29: HomePNA Control Register (Register 29). Table HPR30: HomePNA Drive Level Control Register (Register Table HPR31: HomePNA Analog Control Register (Register Table 10BASE-T Management Registers (TBRs) Table TBR0: 10BASE-T Control Register (Register Table TBR1: 10BASE-T Status Register (Register Table TBR2: 10BASE-T Identifier Register (Register Table TBR3: 10BASE-T Identifier Register (Register Table TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register Table TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register Base Page Format Table TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register Next Page Format Table TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register Table TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register Table TBR16: 10BASE-T Status Enable Register (Register Table TBR17: 10BASE-T Control/Status Register (Register Table TBR19: 10BASE-T Management Extension Register (Register Table TBR24: 10BASE-T Summary Status Register (Register
Am79C901
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Am79C901
CONNECTION DIAGRAM 068)
LED_ACTIVITY
LED_POWER
LED_SPEED
MDC/SCLK
MDIO/SDO
LED_LINK
LED_COL
ISOLATE
MII/GPSI
PHY_AD
RXD1 RXD0/RXDAT DVSS RX_DV DVDD RX_CLK/RXCLK AVDD PHY_SEL DVDD RX_ER DVSS GM_MODE TX_CLK/TXCLK TX_EN/TXEN TXD0/TXDAT TXD1/SDI
RXDVDD AVSS TXAVDD DVSS IREF AVDD HRTXRXP AVDD HRTXRXN AVSS AVSS AVDD
Am79C901 HomePHY
RESET
DVDD
DVSS
DVSS
RXD2
RXD3
CRS/RXCRS XCLK/XTAL XTAL2 XTAL1 DVDD DVDD COL/CLS TXD3/CS AVDD TXD2 DVSS DVSS
Note: pins reserved should left unconnected.
22304A-2
Am79C901
DESIGNATIONS 068) Listed Number
Name LED_LINK LED_COL LED_ACTIVITY DVDD LED_POWER LED_SPEED DVSS RXD3 RXD2 RXD1 RXD0/RXDAT DVSS RX_DV DVDD RX_CLK/RXCLK AVDD PHY_SEL DVDD RX_ER DVSS GM_MODE TX_CLK/TXCLK TX_EN/TXEN TXD0/TXDAT TXD1/SDI TXD2 TXD3/CS DVSS COL/CLS DVSS CRS/RXCRS DVDD DVDD Name XCLK/XTAL XTAL2 XTAL1 AVDD AVDD AVSS AVSS HRTXRXN AVDD HRTXRXP AVDD IREF Name DVSS AVDD TXAVSS DVDD RXNC RESET MII/GPSI PHY_AD ISOLATE MDIO/SDO DVSS MDC/SCLK Name
Note: pins reserved should left unconnected.
Am79C901
DESIGNATIONS 068) Listed Group
Name Configuration MII/GPSI GM_MODE ISOLATE PHY_SEL PHY_AD Board Interface RESET XCLK/XTAL XTAL1 XTAL2 IREF LED_COL LED_ACTIVITY LED_LINK LED_SPEED LED_POWER RESET Oscillator/Crystal Select Crystal Input XTAL/60 CLK) Crystal Output XTAL) Tied 12.1 resistor Collision Indication Activity Indication Link Valid Indication High Speed Indication High Power Indication XTAL Selects GPSI mode Selects MDC/MDIO GPSI data Isolates device register isolate set=1 Defines default Defines address Function Type Driver Type Number Pins
Mbps HomePNA Network Ports HRTXRXP/N Receive/Transmit Data
10BASE-T Network Ports Interface TX_CLK TXD[3:0] TX_EN RX_CLK RXD[3:0] RX_ER RX_DV MDIO Transmit Clock Transmit Data Transmit Enable Receive Clock Receive Data Receive Error Receive Data Valid Management Data Clock Management Data Input/Output Carrier Sense Collision OMII OMII OMII OMII OMII TSMII OMII OMII Serial Transmit Data Serial Receive Data
Am79C901
Number Pins
Name GPSI Interface TXCLK TXDAT TXEN RXCLK RXDAT RXCRS Interface SCLK Clock Data Data Chip Select
Function
Type
Driver Type
GPSI Transmit Clock GPSI Transmit Data GPSI Transmit Enable GPSI Receive Clock GPSI Receive Data Carrier Sense Collision
OMII OMII OMII OMII OMII
TSMII
IEEE 1149.1 (JTAG) Test Access Port Interface Power Supply DVDD AVDD DVSS AVSS Test Interface Test Enable Digital Power Analog Power Digital Ground Analog Ground Test Clock Test Mode Select Test Data Test Data
Am79C901
DESIGNATIONS Listed Driver Type
following table describes various types output drivers used Am79C901 PHY. values shown table apply signaling. sustained tri-state signal active-low signal that driven high clock period before left floating. differential output driver. characteristics those XTAL2 output described Characteristics section.
Driver Name OMII TSMII
Type Tri-State Tri-State Tri-State
(mA)
(mA)
Load (pF)
Note: reference only. specification actual limits.
Am79C901
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination elements below.
AM79C901
ALTERNATE PACKAGING OPTION Tape Reel TEMPERATURE RANGE Commercial +70° PACKAGE TYPE Plastic Leaded Chip Carrier 068)
SPEED OPTION applicable
DEVICE NUMBER/DESCRIPTION AM79C901 HomePHY Single-Chip 1/10 Mbps Home Networking
Valid Combinations AM79C901 JC\T
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am79C901
DESCRIPTIONS Configuration Pins MII/GPSI
MII/GPSI Input Selects between GPSI interface. This must connected either VSS. Changing state this prohibited.
status signals will driven onto interface. When HIGH, 10BASE-T data status signals will driven onto interface. This functions conjunction with ISOLATE pin. Mbps HomePNA HIGH 10BASE-T
HPR0 TBR0 PHY_SEL ISOLATE Interface Source
GM_MODE
GM_MODE Input This input selects between MDC/MDIO command control interface interface normally available GPSI mode. This must connected either VSS. Changing state this prohibited.
Data Interface GPSI GPSI Command Control Interface MDC/MDIO MDC/MDIO
Managed Mode Mbps HomePNA 10BASE-T Valid
External Control Mode Don't Care 10BASE-T Mbps HomePNA
GM_MODE
MII/GPSI
Note: GM_MODE overrides value MII/GPSI configuration pin.
PHY_AD
Address Input Sets Address field. PHYs have default address 0x00 (0000b) Mbps HomePNA 0x01 (0001b) 10BASE-T PHY. this set, address HomePNA 0x02 (00010b) 0x03 (00011b) 10BASE-T PHY.
Board Interface LED_COL
LED_COL Output This output designed directly drive LED. indicates that collision been detected currently active PHY. internal pulse stretching circuit will ensure that minimum output pulse approximately
LED_ACTIVITY
LED_ACTIVITY Output This output designed directly drive LED. ACTIVITY indicates that there receive transmit activity network currently active PHY. internal pulse stretching circuit will ensure that minimum output pulse approximately
ISOLATE
Isolate Input environment that utilizes command control interface, this must held HIGH. environment that does command control interface, this enables data interface when LOW, forces interface into high impedance state when held HIGH. This functions conjunction with PHY_SEL HPR0, TBR0,
LED_LINK
LED_LINK Output This output designed directly drive LED. LINK indicates that valid link been detected currently active PHY.
PHY_SEL
Select Input environment that utilizes command control interface, this must held LOW. environment that does command control interface, this selects which data status signals will driven onto interface. When LOW, HomePNA data
LED_SPEED
LED_SPEED Output This output designed directly drive LED. SPEED indicates that HomePNA currently high-speed mode. When operating 10BASE-T mode this output will held high.
Am79C901
LED_POWER
LED_POWER Output This output designed directly drive LED. POWER indicates that HomePNA currently high-power mode. When operating 10BASE-T mode this output will held high.
TXEN
Transmit Enable Input TXEN indicates when device presenting valid transmit data TXDAT pin. TXEN must asserted with first preamble remain asserted throughout duration packet until deasserted prior first TXCLK following final frame. TXEN transitions synchronous TXCLK.
RESET
RESET Input RESET active-low, asynchronous RESET signal. This signal must held minimum requires recovery after rising edge RESET.
Interface (Slave Mode Only) SCLK
Clock Input SCLK driven from controlling device timing reference transfer information signals. maximum clock frequency MHz.
GPSI Interface RXDAT
Receive Data Output RXDAT serial data received from selected port. Data RXDAT driven falling edge RXCLK.
Chip Select Input This used enable Am79C901 slave mode transfers. When this inactive (HIGH), device ignores SCLK inputs holds high-impedance.
RXCLK
Receive Data Clock Output RXCLK provides timing reference transfer receive data. RXCLK driven device operates maximum frequency MHz.
Serial Data Input This data line provides input data from master device Am79C901. data presented this latched rising edge SCLK.
RXCRS
Receive Carrier Sense Output RXCRS active during receive transmit activity HomePNA during receive (based TBR17, 10BASE-T PHY.
Serial Data Output This data line provides output data from Am79C901 master device. provide robust interface, this data driven rising edge SCLK.
Collision Output This signal asserted whenever collision detected transmit receive path selected port. This signal will also asserted within after negation TXEN signal support test. functionality controlled TBR17, HPR16,
Interface RX_CLK
Receive Clock Output RX_CLK clock input that provides timing reference transfer RX_DV, RXD[3:0], RX_ER signals from Am79C901 device. RX_CLK will provide nibble rate clock. operates maximum frequency MHz.
TXDAT
Transmit Data Input TXDAT serial data driven from MAC. Data TXDAT latched falling edge TXCLK.
RXD[3:0]
Receive Data Output RXD[3:0] nibble-wide receive data bus. Data RXD[3:0] driven falling edge RX_CLK. RXD[3:0] should ignored while RX_DV deasserted.
TXCLK
Receive Data Clock Output TXCLK provides timing reference transfer transmitted data. TXCLK driven device operates maximum frequency MHz.
Am79C901
RX_DV
Receive Data Valid Output RX_DV output used indicate that valid received data being presented RXD[3:0] pins RX_CLK synchronous receive data. RX_DV will asserted prior RX_CLK rising edge, when first nibble Start Frame Delimiter (SFD) driven RXD[3:0], will remain asserted until after rising edge RX_CLK, when last nibble driven RXD[3:0]. RX_DV will deasserted prior RX_CLK rising edge which follows this final nibble. RX_DV transitions driven falling edge RX_CLK.
TX_EN
Transmit Enable Input TX_EN indicates that device presenting valid transmit data TXD[3:0] bus. TX_EN must asserted with first nibble preamble remains asserted throughout duration packet until deasserted prior first TX_CLK following final nibble frame. TX_EN transitions latched falling edge TX_CLK.
Management Data Clock Input non-continuous clock input that provides timing reference bits MDIO pin. During management port operations, runs nominal frequency MHz.
Carrier Sense Output active during receive transmit activity HomePNA during receive (based TBR17, 10BASE-T PHY.
MDIO
Management Data Input/Output Input/Output MDIO bidirectional management port data pin. MDIO input during header portion management frame transfers during data portion write operations. MDIO output during data portion read operations. MDIO should externally pulled with resistor.
Collision Output This signal asserted whenever collision detected transmit receive path selected port. This signal will also asserted within after negation TXEN signal support test. functionality controlled TBR17, HPR16,
RX_ER
Receive Error Output RX_ER output 10BASE-T that indicates that transceiver device detected coding error receive data frame currently being transferred RXD[3:0] pins. RX_ER ignored while RX_DV deasserted. Special code groups generated while RX_DV deasserted ignored (e.g., idle T4). RX_ER transitions synchronous RX_CLK.
IEEE 1149.1 (JTAG) Test Access Port Interface
Test Clock Input clock input boundary scan test mode operation. operate frequency MHz. internal pull-up resistor.
Test Data Input test data input path Am79C901 PHY. internal pull-up resistor.
TX_CLK
Transmit Clock Output TX_CLK clock output that provides timing reference transfer TXD[3:0] TX_ER signals from Am79C901 device. TX_CLK provides nibble rate clock.
Test Data Output test data output path from Am79C901 PHY. tri-stated when JTAG port inactive.
TXD[3:0]
Transmit Data Input TXD[3:0] nibble-wide data bus. Valid data generated TXD[3:0] every rising edge TX_CLK while TX_EN asserted. While TX_EN deasserted, TXD[3:0] values ignored. TXD[3:0] transitions latched falling edge TX_CLK.
Test Mode Select Input serial input stream used define specific boundary scan test executed. internal pull-up resistor.
Am79C901
Ethernet Network Interfaces
Serial Transmit Data Output These pins carry transmit output data connected transmit side magnetics module.
XTAL1
Crystal Oscillator Input internal clock generator utilizes either 20-MHz crystal that attached pins XTAL1 XTAL2 60-MHz clock source connected XTAL1. This tolerant, clock source should from source.
Serial Receive Data Input These pins accept receive input data from magnetics module.
XTAL2
Crystal Oscillator Output internal clock generator utilizes 20-MHz crystal that attached pins XTAL1 XTAL2. XTAL mode, this should left unconnected.
IREF
Internal Current Reference Input This serves current reference integrated 1/10 PHY. must connected through 12.1 resistor (1%).
Power Supply DVDD
Digital Power Pins) +3.3 Power These pins power supply pins that used provide power digital portions design. DVDD pins must connected +3.3 supply.
HomePNA Network Interface HRTXRXP/HRTXRXN
Serial Receive Data Input/Output These pins accept receive input data from magnetics module carry transmit output data. 102-W resistor should placed between these pins.
AVDD
Analog Power Pins) +3.3 Power These pins power supply pins that used provide power analog portions design. AVDD pins must connected +3.3 supply.
Clock Interface XCLK/XTAL
External Clock/Crystal Select Input When HIGH, external 60-MHz clock source selected bypassing crystal circuit clock trippler. When LOW, 20-MHz crystal used instead. Table illustrates this works.
DVSS
Digital Ground Pins) Ground These pins ground connections digital portions design.
AVSS
Analog Ground Pins) Ground These pins ground connections analog portion design.
Table
Input XTAL1 XTAL1 Output XTAL2
Clock Source Selection
XCLK/XTAL Clock Source 20-MHz Crystal 60-MHz Oscillator/ External Source
Scan Test Interface
Test Enable Input test enable factory only. must connected normal operation.
Am79C901
BASIC FUNCTIONS Network Interfaces
Am79C901 contains integrated Mbps home networking 10BASE-T PHY. This device compliant with HomePNA specification IEEE 802.3 specification. integrated HomePNA transceiver physical layer device that enables data networking speeds Mbps over existing residential phone wiring regardless topology without disrupting telephone (POTS) service. integrated Ethernet transceiver physical layer device suppor ting IEEE 802.3 standard 10BASE-T. provides layer functions required support Mbps data transfer speeds. 10BASE-T suppor both half-duplex full-duplex operation.
H_RESET S_RESET. following description each type RESET operation. H_RESET Hardware Reset (H_RESET) reset operation that been initiated proper assertion RESET Am79C901 device. When minimum pulse width timing specified RESET description been satisfied, internal reset operation will performed. H_RESET will program registers their default value. S_RESET software reset (S_RESET), programming HPR0 will reset registers Mbps HomePNA (HPRs), programming TBR0 will reset TBR4, TBR7, TBR17, TBR24 10BASE-T PHY. These bits self-clearing.
Data Interfaces
Am79C901 both GPSI MII-compatible data interfaces. addition, special mode, GM_MODE, allows access MDC/MDIO command control interface while GPSI mode. more information, Descriptions Detailed Functions sections.
DETAILED FUNCTIONS GPSI Interface
seven signals that comprise GPSI TXCLK, TXEN, TXDAT, RXCLK, RXCRS, RXDAT, CLS. these, only TXEN TXDAT inputs PHY; other five outputs from PHY. These signals behave differently depending which operation currently happening PHY. operations follows: Idle activity either direction), RXPKT (receiving data), TXPKT (transmitting data). subsequent subsections analyze each GPSI-related state detail.
Reset
There different types RESET operations that perfor Am79C901 device,
TXCLK TXEN TXDAT RXCLK RXCRS RXDAT
22304A-3
Note: RXCLK TXCLK synchronized same phase. other signals inactive. clock signals toggle overall period 583.3ns (about MHz).
Figure
Idle State
Am79C901
TXCLK TXEN TXDAT RXCLK RXCRS RXDAT
22304A-4
Note: RXCLK becomes disabled soon RXCRS asserted.
Figure RXPKT RXCRS Asserted
TXCLK TXEN TXDAT RXCLK RXCRS RXDAT
22304A-5
Note: RXCLK TXCLK unrelated each other during this time. When symbol been received decoded, RXCLK toggles order shift three bits encoded symbol. middle portion this diagram shows preamble, followed beginning data. RXCRS will fall after last received symbol. Once RXCRS falls, RXCLK TXCLK toggled continuously cycles, after which returns Idle state.
Figure RXPKT RXCRS Cleared
Am79C901
TXCLK TXEN TXDAT RXCLK RXCRS RXDAT
22304A-6
Note: Once TXEN asserted, stops RXCLK, asserts RXCRS, toggles TXCLK.
Figure TXPKT TXEN Asserted
TXCLK TXEN TXDAT RXCLK RXCRS RXDAT
22304A-7
Note: TXCLK continues toggle until observed, shown first section above diagram. this point, TXCLK disabled (low) until header been transmitted wire until been detected). this time RXCLK starts toggling, thereby, shifting bits preamble back MAC. Sometime later, TXCLK restarts symbols sent onto wire analogous manner RXCLK during packet reception.
Figure TXPKT RXCLK Active
Am79C901
TXCLK TXEN TXDAT RXCLK RXCRS RXDAT
22304A-8
Note: Once TXEN cleared, last symbol gets encoded transmitted, looped-back data presented back MAC, RXCRS falls. Once RXCRS falls, TXCLK RXCLK toggle clocks, after which system returns Idle state.
Figure TXPKT TXEN Cleared
TXCLK TXEN TXDAT RXCLK RXCRS RXDAT
22304A-9
Note: will asserted some time after preamble have been clocked TXCLK RXCLK then clocked until RXCRS drops. TXEN drops about clocks after asserted. RXCRS dropped together after more than clocks (about µs). TXCLK RXCLK keep toggling approximately another clock cycles, when system returns Idle state.
Figure
TXPKT Asserted
Am79C901
TXCLK TXEN TXDAT RXCLK RXCRS RXDAT
22304A-10
Note: asserted after RXCRS been asserted. Once been asserted, TXCLK RXCLK until cycles after RXCRS cleared. take maximum approximately RXCRS clear.
Figure RXPKT Asserted
Table
Condition Idle (excluding time) Preamble (first bits frame) Data (throughout data phase) times following
GPSI Timing
Frequency
Period 583.3
233.3 233.3
opcode, followed 10-bit register address bits delimiter. operation write, data bits written into desired register. operation read, then these data bits ignored. will shift data bits representing contents register referenced address field read operations. commands must initiated with high-to-low transition pin. Only command sent cycle. assistance debugging access interface, error code driven onto SDO. there less than bits SCLK during time that asserted, error code field next command will indicate AAAA. When there incorrect opcode command AAAA will immediately driven until deasserts. there more than clock cycles while low, first assumed contain data, additional clock bits associated data ignored. this case, might generate AAAA under additional clock bits. Figure
avg.
Note: During interval, TXCLK RXCLK stop
Serial Peripheral Interface (SPI-Slave) Mode
When MII/GPSI device "SPI" mode. device acts slave peripheral this mode operation. Commands issued device asserting signal (active low), shifting 4-bit
SCLK
Codes Error Code
Address
Data Data
22304A-11
Figure
Operation Interface
Am79C901
Table Codes
Codes READ WRITE PHYADD AAAAA AAAAA Error Code READ WRITE 0000 Error/AAAA Error Detected 0000 Error/AAAA Error Detected Data D15.D0 Don't Care Address REGADD RRRRR RRRRR Don't Care D15.D0 Data
Start Frame SCLK
Read Command
Delimiter
First Data
Last Data
22304A-12
Figure
Read Operation
SCLK
Codes Error Code
Address
22304A-13
Figure
Aborted Operation Interface
SCLK
Codes
Address Error Code AAAA
Data Data
22304A-14
Figure
First Operation Following Abort
Am79C901
SCLK
Codes
Address Error Code
Data Data
22304A-15
Figure
Normal Operation
MII-Compatible Interface HomePNA
control data signals that utilized MIIcompatible interface Mbps HomePNA function manner that identical that defined 802.3u specification. signals RXCLK TXCLK function slightly different manner that they operate reduced data rate that these clock signals constant rate RLL25encoding scheme. Table
signals TXCLK RXCLK will toggle rate approximately during idle time. When TXEN signal asserted indicate beginning transmission, clock rate will enter preamble phase. Once been detected HomePNA begun transmission HomePNA header, clock enters data phase. When TXEN signal deasserted indicate ending transmission, TXCLK halted until RXDATA path detects packet. this time, clock rate increased data rate times then returns Idle state.
Table
Condition Idle (excluding time)
MII-Compatible Timing
Period 2333.34 933.33 933.33 Frequency 428.6 1.07 avg. 1.07
MII-Compliant Interface 10BASE-T
interface fully IEEE 802.3u-compliant when 10BASE-T selected. management interface specified Clause IEEE 802.3u standard provides simple wire, serial interface connect management entity managed purpose controlling gathering status information. lines Management Data Input/Output (MDIO) Management Data Clock (MDC). station management entity, which attached multiple entities, must have prior knowledge appropriate address each entity. management interface physically transports management information across MII. information encapsulated frame format specified Clause IEEE 802.3u standard shown Table
Preamble (first bits frame) Data (throughout data phase) times following
Note: During interval, TX_CLK RX_CLK stop
Figure Figure represent signal relationships when MII-compatible data interface utilized.
Table Control Frame Format
READ WRITE PHYADD AAAAA AAAAA REGADD RRRRR RRRRR DATA D15.D0 D15.D0 IDLE
Am79C901
operation field (OP) follows start field (ST). indicates whether operation read write operation. address (PHYADD) register address (REGADD) that were programmed follow this. turnaround field (TA) follows REGADD field. During read operation, field used determine responding properly read request. final field idle field, required allow drivers turn off. PHYADD field, which five bits wide, allows unique addresses. managed layer device that connected station management entity interface respond transactions addressed PHY's address. station management entity attached multiple PHYs required have prior knowledge appropriate address. more information, IEEE 802.3 specification descriptions.
Idle TX_CLK
Preamble
Data
TX_EN
RX_CLK
RX_DV
22304A-16
Figure Start Transmission
Am79C901
TX_CLK Times TX_EN
Idle
data
RX_CLK
RX_DV
data
data
enabled
22304A-17
Figure Transmission
Am79C901
Mbps HomePNA
integrated HomePNA transceiver physical layer device supporting HomePNA specification home phoneline networking. provides layer functions required support Mbps data transfer speeds over existing residential phone wiring. data bits encoded into relative time position pulse with respect previous one. waveform wire consists carrier sinusoid enclosed within exponential (bell shaped) envelope. waveform produced generating four square wave cycles passing them through external bandpass filter. HomePNA frame consists HomePNA header that replaces normal Ethernet 64-bit preamble delimiter. frame header prepended standard Ethernet packet starting with destination address ending with CRC. Only layer parameters modified from that standard Ethernet implementation. HomePNA layer designed operate with standard Ethernet layer controller implementing CSMA/CD protocol features. frame begins with characteristic SYNC interval that delineates beginning HomePNA frame followed Access (AID) which encodes bits bits control word. used detect collisions dynamically assigned, while control word carries speed power information. followed silence interval, then bits data reserved layer communication. These bits accessible internal registers future use. Data encoding consists symbol types: symbol data symbol. symbol always transmitted same speed encodes bits that determine pulse position (one four) relative previous pulse. These bits transmitted first. access symbol interval fixed.
data symbol interval variable. arriving stream blocked into from 3-bit 6-bit blocks according proprietary (RLL25) algorithm. bits each block then used encode data symbol. Each symbol consists Data Inter Symbol Blanking Interval (DISBI) then pulse possible positions. bits data block determine pulse position. Immediately after pulse symbol interval begins. During DISBI receiver ignores incoming pulses allow network reflections out. station programmed assume role master remotely command, control word, rest units network change their transmit speed power level. Many framing parameters programmable HomePNA will allow modifications transmission speed center frequency well noise reflection rejection algorithms. default speeds provided, Mbps high Mbps. HomePNA Medium Interface
Framing
HomePNA frame phone wire network consists header generated prepended IEEE 802.3 Ethernet data packet received from layer. Figure When transmitting phone wire pair, HomePNA first receives Ethernet frame from MAC. octets preamble delimiter stripped replaced with HomePNA header described below, then transmitted home network with each symbol being transmitted first. During receive operation, reverse process executed. When HomePNA frame received PHY, header stripped replaced with octets preamble delimiter IEEE 802.3 Ethernet frame specification then passed layer.
Am79C901
HomePNA Header SYNC interval blanking interval Fixed 14.93 tics Access Silence
PCOM
Ethernet Packet
Destination Source Length ETHERNET DATA 1500
blanking interval
blanking interval
blanking interval
blanking interval
blanking interval
Silence interval bits PCOM
Ethernet Packet
tics
tics pulse
potential pulse position tics ACCESS Symbol tics ACCESS Symbol tics ACCESS Symbol
Data symbols
tics SYNC Symbol
tics ACCESS Symbol
tics ACCESS Symbol
tics ACCESS Symbol
tics ACCESS Symbol
30.75 Mbps
ACCESS interval Fixed 120.39
Example Access 01110100 control word 0100 HomePNA Header 151.14 Mbps 116.6667 receiver blanking interval
Note: Using default configurations.
22304A-18
Figure HomePNA Framing
HomePNA Symbol Waveform HomePNA symbols composed transmitter silence interval pulse formed integer number cycles (TX_PULSE_CYCLES_P/ wave (CENTER_FREQUENCY TX_PULSE_WIDTH HPR29) that been filtered with external bandpass filter. Data encoded time interval from preceding pulse.
These symbols described following sections.
Symbol (SYNC interval)
SYNC Transmit Timing: SYNC interval (AID symbol delineates beginning HomePNA frame composed SYNC_START pulse, followed SYNC_END pulse, after fixed silence interval shown Figure Timing this (AID symbol starts (TIC beginning SYNC_START pulse. SYNC_END pulse starts 126. 129, this symbol ends next symbol begins, with symbol timing reference reset information bits coded SYNC (AID symbol interval). SYNC Receive Timing: soon SYNC_START pulse detected receiver disables (blanks) further detection until time after which detection reenabled next received pulse. receiver allows jitter establishing window around each legal pulse position. This asymmetrical window TICS wide side position wide other. SYNC_END pulse that arrives outside window legal considered noise event which used setting adaptive squelch level, aborts packet, sets receiver search SYNC_START pulse SYNC interval. transmitting station, COLLISION event asserted described Collisions section.
Table
HomePNA Pulse Parameters
Value Tolerance -Unit Cycles
Parameter CENTER_FREQUENCY CYCLES_PER_PULSE
Time Interval Unit HomePNA time intervals expressed Time Interval Clock (TIC) units. defined 7/60E6 seconds approximately 116.7
Access Intervals
HomePNA frame begins with Access (AID) interval which composed eight equally spaced subintervals termed symbols through shown Figure symbol TICs long. Transmit timing shown Figure receive timing Figure Timing starts beginning each symbol ends 129.
Am79C901
Transmitter
Symbol pulse pulse Symbol pulse shown position Symbol
SYNC_START TIC=0 SYNC_END TIC=126
TIC=129 TIC=0 AID_Position_0 TIC=66 AID_Position_1 TIC=86 AID_Position_2 TIC=106 AID_Position_3 TIC=126
TIC=129 TIC=0
22304A-19
Figure Symbol Transmit Timing
Receiver
slice threshold pulse Symbol pulse Symbol pulse shown position Symbol
Detected envelope
END_RCV_BLANK SYNC_START TIC=0 TIC=129 TIC=0 AID_Position_0 TIC=66 AID_Position_1 TIC=86 AID_Position_2 TIC=106 SYNC_END TIC=126 AID_Position_3 TIC=126 TIC=129 TIC=0 AID_GUARD_INTERVAL
22304A-20
Figure Symbol Receive Timing
SYNC interval followed symbols (symbols through Transmit timing shown Figure receive timing Figure Data encoded relative position each pulse with respect previous one. pulse occur one, only one, four possible positions within symbol yielding bits data coded symbol. decoded bits from symbols produce eight bits Access which used identify individual HomePNA stations detect collisions. encoded Symbol leftmost Table
Table
Pulse Position
Access Symbol Pulse Positions Encoding
TICs from Beginning Symbol Encoding
Am79C901
next symbols encode four bits control word information. encoded Symbol Control word messages described further Mode Interface section. Transmit Timing: transmitter encodes Access pulse position each interval. Each symbol interval must have only pulse. Pulse transmission must start only four possible positions (measured from beginning Access symbol) defined Table Receive Timing: receiver allows jitter establishing window around each legal pulse position. This asymmetrical window TICS wide side position wide other. pulse that arrives outside legal positions considered COLLISION event. Collisions Collision detected only during Access silent intervals (AID symbols through general during collision, transmitting station will read back value that does match own, recognize event collision, alert other stations with signal. Non-transmitting stations also detect some collisions interpreting received non-conforming pulses collisions. With transmitters colliding, each transmitter normally blanks receive input immediately after transmitting (and simultaneously receiving) pulse. Therefore, only when transmitting station receives pulses position earlier than position transmitted will recognize pulse transmitted another station signal collision. this reason, guaranteed collision detection possible only long spacing between successive possible pulse positions symbol TICs greater than roundtrip delay between colliding nodes. approximately propagation delay foot, maximum distance between HomePNA units must greater than feet collision detection purposes (1.5 roundtrip delay plus margin). following criteria must guarantee reliable collision detection: least HomePNA station colliding group must always detect collision when delay between beginning transmitted packet beginning received colliding packet between -1.5 +1.5 general, received pulse HomePNA station that does conform pulse position requirements symbols through shall indicate collision wire. When transmitting station senses collision, emits signal alert other stations collision. following conditions signify COLLISION event: HomePNA station receives that does match being sent. HomePNA station receives pulse outside AID_GUARD INTERVAL intervals HomePNA station receives pulse inside SILENT_INTERVAL (AID symbol cases, pulses received during blanking interval ignored. Passive stations (stations actively transmitting during collision) cannot reliably detect collisions. Therefore, once collision detected transmitting station, station must inform rest stations collision with pattern described below. Only transmitting station emits signal. Once collision detected, COLLISION signal interface asserted reset until deactivates TXEN signal. Signal pattern consists pulse every TICs continues until least intervals. After interval, pattern will continue until TXEN from deactivated. Access Values access values stations randomly picked each individual station from numbers described management section. During operation, each HomePNA station monitors HomePNA frames received wire. detects another HomePNA station using same AID, will select random AID. Silence Interval (AID symbol Access symbols followed fixed silence interval TICs. receive blanking interval same that symbols through pulses detected silence interval considered COLLISION event transmitting stations handled described Collisions section. Data Symbols Data symbols encode data much higher transmission rate, they allow collision detection.
Am79C901
Data Transmit Timing
data symbol interval begins with start transmission pulse shown Figure Transmit Symbol timing TICs) measured from this point (TIC Depending data code, next pulse begin PULSE_POSITION_N where Each position separated from previous TIC. PULSE_POSITION_0 occurs value defined Table which determines transmission speed.
When pulse begins transmission, previous symbol interval ends begins immediately. Table Blanking Interval Speed Settings
Nominal Data Rate Mbps Mbps PULSE_POSITION_0 Value TICs)
Speed Setting LOW_SPEED HIGH_SPEED
Transmitter
Pulse Symbol Data Blanking interval (DISBI) Pulse Symbol Pulse
START_TX_PULSE TIC=0
END_TX_PULSE time
PULSE_POSITION_0 time
Position
Position n=0-24
Position
Position
Position
22304A-21
Figure Transmit Data Symbol Timing
Data Receive Timing
incoming waveform formed from transmitted pulse along with distortions reflections that occur wiring network. receiver detects point which envelope received waveform crosses threshold. Figure Immediately after threshold crossing, receiver disables further detection period ISBI-3 TICs (HPR28, ISBI_SLOW ISBI_FAST) starting with detection pulse peak.
receiver then re-enabled pulse detection. Upon reception next pulse, receiver measures elapsed time from previous pulse. This value then placed nearest pulse position (one where pulse position PULSE_POSITION_0 each subsequent position spaced from previous defined Data Transmit Timing section. Data symbol intervals therefore variable depend encoded data.
Receiver
Symbol Data slice threshold Pulse Detected Envelope Pulse Symbol Pulse
END_DATA_BLANK Begin receive Blanking interval Position Position Position Position Position Position
22304A-22
Figure Receive Symbol Timing
Am79C901
Data Symbol RLL25 Encoding
RLL25 code version TM32 that developed HomePNA PHY. produces highest rate given value ISBI size. manner similar length limited disk coding, RLL25 encodes data bits groups varying sizes, specifically: bits. Pulse positions assigned encoded groups manner, which causes more data bits encoded positions that farther apart. This keeps both average minimum rates higher. Data symbol RLL25 codes data traversing tree illustrated Figure Assuming that successive data bits encoded labeled D,., etc., encoding process begins root node proceeds follows: first (bit one, next three bits select which eight positions transmitted. encoding process then continues root node. zero one, next three bits select which eight positions 9-16 transmitted. encoding process then continues root node.
zero, zero, one, next three bits select which eight positions 17-24 transmitted. encoding process then continues root node. Finally, bits zeros, position transmitted. encoding process then continues root node. result, Symbol encodes 3-bit data pattern 000, positions encode 4-bit data pattern 1BCD, positions 9-16 encode 5-bit data pattern 01CDE, positions 17-24 encode 6-bit data pattern 001DEF. data encoded random, positions used will 4-bit patterns, will 5bit patterns, 12.5% will 6-bit patterns, 12.5% will 3-bit patterns. Mode Interface HomePNA managed from either interfaces (the managed parameters vary depending interface): Remote Control-Word management commands embedded HomePNA header wire network. Management messages from local management entity.
Data stream from controller Start: Examine next bits encoded Encoded sent
Awaiting coding transmission
Send symbol
These select position Send symbol 9-16
These select position Send symbol 17-24
These select position Send symbol
22304A-23
Figure
Coding Tree
Am79C901
Header Remote Control Word Commands
Stations configured either master stations slave stations. Only master exist given HomePNA segment network over which HomePNA header preserved. master station send commands embedded HomePNA header control word remotely various parameters remote slave stations. Stations identified follows: master station identified HomePNA wire network with FFh. slave identified with EFh. values reserved future use. Once command been transmitted, master station will revert slave AID, that subsequent control words interpreted slave stations commands. Master mode entered writing control register (HPR16, bits exited upon completion command sequence. valid master remote command consists three HomePNA frames with FFh. Since HomePNA header prepended packets received from MAC, well any1Home packets, packets from master station separated intervals during which other (slave) stations transmit their frames. remote master Control Word command will recognized executed HomePNA when receives three consecutive valid HomePNA frames with FFh. Valid commands follows: SET_POWER: Commands slave stations their transmit level prescribed level until another master command received. SET_SPEED: Commands slave stations their transmit speed prescribed value until another master command received. control word encoding possible values described Table Table
low-speed transmit mode. high-speed transmit mode. Reserved
Slave stations transmit following status messages HomePNA header control word outgoing frames: VERSION_STATUS: HomePNA version slave station. receiving station must revert this version interpret packet. POWER_STATUS: transmit power level transmitting slave station current frame. HomePNA units support both LOW_POWER HIGH_POWER modes operation. SPEED_STATUS: transmit speed slave station current frame. Receiving stations will adjust their receiver parameters correctly interpret this frame. slave control word encoding identical master control word format. Mbps HomePNA Loopback HomePNA capable supporting internal loopback only.
Internal Loopback
internal loopback, transmitted data returned receive data without transmitting data network. must programmed support full-duplex operation responsible comparing transmitted data that received. Internal loopback accomplished setting "enable loopback mode" HPR0, any1Home Link Detection While consuming minimal network resources, AMD's innovative any1Home Link Detection Packet provides means indicate MAC, thus upper layers system protocol, that valid network defined HomePNA) been detected. Link Detection Packet also capable detecting network failure allows upper layer protocol take corrective action. Thus, any1Home Packet provides link indication that requires compliance Microsoft PC97, PC98, HomePNA requirements.
Master Station Control Word Functions
Command Function version low-power transmit mode. high-power transmit mode.
10BASE-T
10BASE-T transceiver incorporates physical layer function, including both clock recovery (ENDEC) transceiver function. Data transmission over 10BASE-T medium requires integrated 10BASE-T MAU. transceiver meets electrical requirements 10BASE-T specified IEEE 802.3i. transmit signal filtered transceiver reduce harmonic content IEEE 802.3i. Since filtering
Am79C901
performed silicon, external filtering modules needed. 10BASE-T transceiver receives Mbps data from across million nibbles second (parallel), million bits second (serial) 10BASE-T. then Manchester encodes data before transmission network. 10BASE-T block consists following subblocks: Transmit Process Receive Process Interface Status Collision Detect Function Jabber Function Reverse Polarity Detect Refer Figure 10BASE-T block diagram. Twisted Pair Receive Function port differential twisted-pair receiver. When properly terminated, port will meet electrical requirements 10BASE-T receivers specified IEEE 802.3, Section 14.3.1.3. receiver internal filtering does require external filter modules common mode chokes. Signals appearing differential input pair routed internal decoder. receiver function meets propagation delays jitter requirements specified 10BASE-T standard. receiver squelch level drops half threshold value after unsquelch allow reception minimum amplitude signals mitigate carrier fade event worst case signal attenuation crosstalk noise conditions. Twisted Pair Interface Status Am79C901 device will power Link Fail state. Auto-Negotiation algorithm will apply allow enter Link Pass state. Link Pass state, receive activity which passes pulse width/amplitude requirements inputs will cause Control block assert Carrier Sense (CRS) signal interface. collision would cause Control block assert Carrier Sense (CRS) Collision (COL) signals MII. Link Fail state, this block would cause Control block deassert Carrier Sense (CRS) Collision (COL). jabber detect mode, this block would cause Control block assert signal allow Control block assert deassert indicate current state pair. there receive activity RX±, this block would cause Control block assert only MII. there activity, this block would cause Control block assert both MII.
22304A-24
Clock
Data
Clock
Data
Manchester Encoder
Manchester Decoder
Squelch Circuit
Driver
Driver
Collision Detect Function Simultaneous activity (presence valid data signals) from both internal encoder transmit function twisted pair pins constitutes collision, thereby causing Control block assert MII. Jabber Function Jabber function inhibits 10BASE-T twisted pair transmit function Am79C901 device circuits active excessive period (20-150 ms). This prevents port from disrupting network stuck-on faulty transmitter condition. maximum transmit time exceeded, data path through 10BASE-T transmitter circuitry disabled (although Link Test pulses will continue sent). Control block also asserts signal
Figure
10BASE-T Transmit Receive Data Paths
Twisted Pair Transmit Function Data transmission over 10BASE-T medium requires integrated 10BASE-T uses differential driver circuitry pins. differential twisted-pair driver. When properly terminated, will meet transmitter electrical requirements 10BASE-T transmitters specified IEEE 802.3, Section 14.3.1.2. load twisted pair cable that meets IEEE 802.3, Section 14.4.
Am79C901
sets Jabber Detect Register active PHY. Once internal transmit data stream from MENDEC stops, unjab time 250-750 will elapse before this block causes Control block deassert indication re-enable transmit circuitry. When jabber detected, this block will cause Control block assert signal allow Control block assert deassert signal indicate current state pair. there receive activity RX±, this block causes Control block assert only signal MII. there activity, this block will cause Control block assert both MII. Reverse Polarity Detect polarity 10BASE-T signals reception Normal Link Pulses (NLP) packets. Polarity locked, however, incoming packets only. first received when trying bring link will ignored, will polarity correct state. reception consecutive packets will cause polarity locked, based polarity Transmit Data (ETD). order change polarity once been locked, link must brought down back again. Auto-Negotiation object Auto-Negotiation function determine abilities devices sharing link. After exchanging abilities, Am79C901 device remote link partner device acknowledge each other make choice which advertised abilities support. Auto-Negotiation function facilitates ordered resolution between exchanged abilities. This exchange allows both devices either link take maximum advantage their respective shared abilities. Auto-Negotiation algorithm uses burst link pulses called Fast Link Pulses (FLPs). burst link pulses spaced between ignored standard 10BASE-T algorithm. burst conveys information about abilities sending device. receiver accept decode burst learn abilities sending device. link pulses transmitted conform standard 10BASE-T template. device perform Auto-Negotiation with reverse polarity link pulses. Am79C901 device uses Auto-Negotiation algorithm select type connection established according following priority: 10BASE-T full duplex, then 10BASE-T half-duplex. Table Auto-Negotiation algorithm initiated following events: Auto-Negotiation enable set, hardware reset, soft reset, transition link fail state (when Auto-Negotiation enable set), Auto-Negotiation restart set. result Auto-Negotiation process read from status register (Summary Status Register, TBR24). default, link partner must least 10BASE-T half-duplex capable. Am79C901 automatically negotiate with network yield highest performance possible without software support. Table
Network Speed Mbps Mbps
Auto-Negotiation Capabilities
Physical Network Type 10BASE-T, Full Duplex 10BASE-T, Half Duplex
Auto-Negotiation goes further providing messagebased communication scheme called Next Pages before connecting Link Partner. Soft Reset Function Control Register (TBR0) incorporates soft reset function (bit 15). read/write register self-clearing. Writing this causes soft reset. When read, register returns soft reset still being performed; otherwise, cleared Note that register polled verify that soft reset terminated. Under normal operating conditions, soft reset will finished clock cycles. Soft reset only resets 10BASE-T unit registers default values (some register bits retain their previous values). Soft reset does reset management interface. 10BASE-T Loopback 10BASE-T capable supporting different types loopback, referred internal external loopback.
Internal Loopback
internal loopback, transmitted data returned receive data without transmitted data appearing network. must programmed support full-duplex operation responsible comparing transmitted data that received. Internal loopback accomplished setting "enable loopback mode" TBR0,
External Loopback
External loopback accomplished exter shor ting plug. this environment, 10BASE-T left through mode (i.e., enable loopback mode TBR0 full duplex. transmitted data will then looped back shorting plug into receive circuitry driven onto receive data process verify.
Am79C901
Support
controller support five LEDs. outp LED_SPEED, LED_POWER allow direct connection supporting pull-up device. outputs stretched allow human recognize even short events that last only several microseconds. five outputs configured shown Table
provided further ease board-level testing. unused instruction codes reserved. Table summary supported instructions. Table IEEE 1149.1 Supported Instruction Summary
Selected Data Register Bypass Bypass
Instruction Instruction Description Name Code EXTEST 0000 0001 0010 0011 1111 External Test Code Inspection Sample Boundary Force TriState
Mode Test Normal Normal Normal
Table
Output LED_COL LED_ACTIVITY LED_LINK LED_SPEED LED_POWER
Default Configuration
Indication Collision Activity Link Speed Power Driver Mode Open Drain Active Open Drain Active Open Drain Active Open Drain Active Open Drain Active Pulse Stretch Enabled Enabled applicable applicable applicable
IDCODE SAMPLE TRI_ST BYPASS
Bypass Scan Normal
Instruction Register Decoding Logic After reset, IDCODE instruction always invoked. decoding logic gives signals control data flow data registers according current instruction. Boundary Scan Register Each Boundary Scan Register (BSR) cell stages. flip-flop latch used Serial Shift Stage Parallel Output Stage, respectively. There four possible operation modes cell shown Table Table
IEEE 1149.1 (JTAG) Test Access Port Interface
IEEE 1149.1-compatible boundary scan Test Access Port provided board-level continuity test diagnostics. digital input, output, input/output pins tested. following paragraphs summarize IEEE 1149.1-compatible test functions implemented controller. Refer IEEE 1149.1 Boundary Scan Architecture document details. Boundary Scan Circuit boundary scan test circuit requires four pins (TCK, TMS, TDI, TDO), defined Test Access Port (TAP). includes finite state machine (FSM), instruction register, data register array, power-on reset circuit. Internal pull-up resistors provided TDI, TCK, pins. Finite State Machine engine 16-state driven Test Clock (TCK) Test Mode Select (TMS) pins. independent power-on reset circuit provided ensure that TEST_LOGIC_RESET state power-up. Therefore, TRST provided. also reset when high five periods. Supported Instructions addition minimum IEEE 1149.1 requirements (BYPASS, EXTEST, SAMPLE instructions), additional instructions (IDCODE TRI_ST)
Mode Operation
Capture Shift Update System Function
Other Data Registers Other data registers following: Bypass register bit) Device register bits) (Table 14).
Table
Bits 31-28 Bits 27-12 Bits 11-1 Version
Device Register
Part Number (1001 0000 0001 0000) Manufacturer 11-bit manufacturer code 00000000001 accordance with JEDEC publication 106-A. Always logic
Am79C901
Boundary Scan Cells Boundary Scan, most chip input output latches linked together form scan chain. main purpose this board-level testing. Table force output pins, SAMPLE load cells EXTEST force output. Program output cells, control cells enable output, clear control cells float output. sample chip inputs outputs, SAMPLE command cell values shifted through pin. Check values input cells. Both input output pins have input-type cells.
RXD_OEN RXD0_RXDAT RXD0_RXDAT RXD1 RXD1 RXD2 RXD2 RXD3 RXD3 LED_SPEED LED_SPEED LED_SPEED LED_POWER LED_POWER LED_POWER LED_ACTIVITY LED_ACTIVITY LED_ACTIVITY LED_COL LED_COL LED_COL LED_LINK LED_LINK LED_LINK MDC_SCLK MDIO MDIO MDIO_OEN ISOLATE PHY_AD MODE_MII RESET_L
Table
Cell
Boundary Scan Ring Order
Cell Name XTAL_SEL_L CRS_COL_OEN TXD3_CSN TXD2 TXD1_SDI TXD0_TXDAT TX_EN TX_CLK_OEN TX_CLK TX_CLK GM_MODE RX_ER RX_ER PHY_SEL RX_CLK RX_CLK RX_DV_RXEN RX_DV_RXEN Cell Type1
Notes:
input cells, samples device inputs internal outputs; output cells, drives device outputs internal inputs; control cells, controls output enable.
Cell closest TDO. Boundary register bits long. Data path starts from cell cell TDO.
Am79C901
USER ACCESSIBLE REGISTERS
Am79C901 types user registers: Mbps HomePNA management registers (HPRs) 10BASE-T management registers (TBRs).
Mbps HomePNA Management Registers (HPRs)
registers HomePNA accessible interface. reserved registers should written reading them will return undetermined value. Table lists registers implemented HomePNA PHY.
Table
Register Address 8-15 Symbol HPR0 HPR1 HPR2 HPR3 HPR4 HPR5 HPR6 HPR7 HPR8-HPR15 HPR16 HPR17 HPR18 HPR19 HPR20 HPR21 HPR22 HPR23 HPR24 HPR25 HPR26 HPR27 HPR28 HPR29 HPR30 HPR31
Mbps HomePNA Management Registers (HPRs)
Name Control Register Status Register PHY_ID Register PHY_ID Register Auto-Negotiation Register Auto-Negotiation Register Auto-Negotiation Register Auto-Negotiation Register Reserved Control Register Status/Control Register TXCOMM Register TXCOMM Register RXCOMM Register RXCOMM Register Register Noise Control Register Noise Control Register Noise Statistics Register Event Status Register Control Register ISBI Control Register Control Register Drive Level Control Register Analog Control Register Basic/Extended Default Value After H_RESET 0400h 0841h 0000h 6B91h 0021h 0000h 0000h 0000h -0005h 000xh 0000h 0000h 0000h 0000h 0000h 03FFh F4xxh 03FFh 0000h 1440h 2C1Ch 0444h x549h C000h
Am79C901
HPR0: HomePNA Control Register (Register
Table
HPR0: HomePNA Control Register (Register
Read/ Write Default Value (hex)
Bits
Name RESET
Description
RESET
When read, reset process Normal operation Self Clearing after
Enable Loopback Mode Speed Selection Auto-Negotiation Enabled
Loopback mode enable Loopback mode disable Mbps Enabled Disabled Power down
Power Down
Normal operation (This mirrored Control
Isolate
Electrically isolates from MII/GPSI Normal operation Restart Auto-Negotiation
Restart Auto-Negotiation
Normal operation Self Clearing
Duplex Mode
Full-Duplex (for Loopback test only) Half-Duplex Enable test signal Disable test signal Write ignore read
Collision Test (Note Reserved
Notes: collision test, "enable loopback mode" must also ensure that collision traffic imposed network. Read/Write; Read only.
Am79C901
HPR1: HomePNA Status Register (Register
Table
HPR1: HomePNA Status Register (Register
Default Value (hex)
Bits 10:7 100BASE-T4
Name
Description able perform 100BASE-T4 able perform Full-Duplex 100BASE-X able perform Half-Duplex 100BASE-X able perform Mbps Full-Duplex able perform Mbps Half-Duplex Reads will produce undefined results will accept management frames with Preamble suppressed will accept management frames with Preamble suppressed Auto-Negotiation completed Auto-Negotiation completed Remote fault detected Normal operation able perform Auto-Negotiation able perform Auto-Negotiation Link
Read/Write
100BASE-X Full-Duplex 100BASE-X Half-Duplex Mbps Full-Duplex Mbps Half-Duplex Reserved Management Frame Preamble Suppression
Auto-Negotiation Complete
Remote Fault
Auto-Negotiation Ability
Link Status
Link down This will RESET (latched re-enabled Read).
Jabber Detect
Jabber condition detected Normal operation Extended Register capability Basic Register capability
Extended Capability
Am79C901
HPR2 HPR3: HomePNA Registers (Registers
Table
HPR2: HomePNA Register (Register
Read/ Write Default Value (hex) 0000
Bits 15:0
Name PHY_ID (31-16)
Description Most significant bytes PHY_ID (Bits 3-18)
Table
HPR3: HomePNA Register (Register
Read/ Write Default Value (hex)
Bits 15:10
Name PHY_ID (15-10) PHY_ID (9-4) PHY_ID (3-0)
Description IEEE Address (Bits 19-24) Manufacturer's Model Number Revision Number
Am79C901
HPR4: HomePNA Auto-Negotiation Advertisement Register (Register This register contains advertised ability Am79C901 device. purpose this register advertise technology ability link partner device. When this register modified, Restart Auto-Negotiation (Register must enabled guarantee change implemented.
Table
HPR4: HomePNA Auto-Negotiation Advertisement Register (Register
Default Value (hex)
Bits 12:11
Name Next Page Reserved Remote Fault Reserved PAUSE Reserved Full-Duplex 100BASE-TX Half-Duplex 100BASE-TX Full-Duplex 10BASE-T Half-Duplex 10BASE-T Selector Field
Description When set, device wishes engage next page exchange. cleared, device does wish engage next page exchange.
Read/Write
When set, remote fault inserted into base link code word during Auto-Negotiation process. When cleared, base link code work will have position remote fault cleared.
This should PAUSE capability advertised.
This advertises Full-Duplex capability. When set, Full-Duplex capability advertised. When cleared, Full-Duplex capability advertised. This advertises Half-Duplex capability Auto-Negotiation process. Setting this advertises Half-Duplex capability. Clearing this does advertise Half-Duplex capability. This advertises Full-Duplex capability. When set, Full-Duplex capability advertised. When cleared, Full-Duplex capability advertised. This advertises Half-Duplex capability Auto-Negotiation process. Setting this advertises Half-Duplex capability. Clearing this does advertise Half-Duplex capability. Am79C901 device IEEE 802.3 compliant device.
Am79C901
HPR5: HomePNA Auto-Negotiation Link Partner Ability Register (Register Auto-Negotiation Link Partner Ability Register Read Only. register contains advertised ability link partner. definitions represent received link code word. This register contains either base page link partner's next pages. values contained these registers only valid once AutoNegotiation successfully completed, indicated HPR1, Next Page exchange used, after Page Received (bit HPR6) been logic one.
Table
HPR5: HomePNA Auto-Negotiation Link Partner Ability Register Base Page Format (Register
Default Value (hex)
Bits 12:5
Name Next Page Acknowledge Remote Fault Technology Ability Selector Field
Description Link partner next page request Link partner acknowledgment Link partner remote fault request Link partner technology ability field Link partner selector field
Read/Write
Table
HPR5: HomePNA Auto-Negotiation Link Partner Ability Register Next Page Format (Register
Default Value (hex)
Bits 10:0
Name Next Page Acknowledge Message Page Acknowledge Toggle Message Field
Description Link partner next page request Link partner acknowledgment Link partner message page request Link partner comply with request Link partner cannot comply with request Link partner toggle Link partner's message code
Read/Write
Am79C901
HPR6: HomePNA Auto-Negotiation Expansion Register (Register Auto-Negotiation Expansion Register provides additional information that aids Auto-Negotiation process. Auto-Negotiation Expansion Register bits Read Only.
Table
HPR6: HomePNA Auto-Negotiation Expansion Register (Register
Default Value (hex)
Bits 15:5
Name Reserved Parallel Detection Fault Link Partner Next Page Able Next Page Able
Description
Read/Write
1=Parallel detection fault 0=No parallel detection fault Link partner next page able Link partner next page able Am79C901 device channel next page able Am79C901 device channel next page able page been received page been received Link partner Auto-Negotiation able Link partner Auto-Negotiation able
Page Received Link Partner AutoNegotiation Able
HPR7: HomePNA Auto-Negotiation Next Page Register (Register Auto-Negotiation Next Page Register contains next page link code word transmitted.
power-up default value 0x2001 represents message page with message code null.
Table
HPR7: HomePNA Auto-Negotiation Next Page Register (Register
Default Value (hex)
Bits 10:0
Name Next Page Reserved Message Page Acknowledge Toggle Message Field
Description Am79C901 device channel next page request
Read/Write
Am79C901 device channel message page request Am79C901 device channel comply with request Am79C901 device channel cannot comply with request Am79C901 device channel toggle Message code field
Reserved Registers: HPR8 HPR15 These registers should ignored when read should written time.
Am79C901
HPR16: HomePNA Control Register (Register Table HPR16: HomePNA Control Register (Register
Read/ Write Default Value (hex)
Bits 14:13
Name Remote Command Reserved
Description Ignore Remote Commands Normal operation Reads will produce undefined results. Should written Disables heartbeat which occurs after each transmission.
SQE_TEST Disable
heartbeat assertion occurs approximately after transmission duration Command power Normal operation Command high power Normal operation Command speed Normal operation Command high speed Normal operation Disable negotiation Normal operation Clear event counter
Command Power
Command High Power
Command Speed
Command High Speed
Disable Negotiation
Clear PHY-Event Counter
Normal operation **Self clearing after ~100
Disable Squelch adaptation
Disable Squelch adaptation Normal operation Power down
Power Down
Normal operation (This controlled HPR0,
Reserved High Speed
Reads will produce undefined results Device currently High speed Device currently speed Device currently High power Device currently power Reads will produce undefined results
High Power Reserved
Note: Writes bits will affect speed power node only.
Am79C901
HPR17: HomePNA Status/Control Register (Register HomePNA Status/Control Register provides information regarding global aspects operation PHY.
Table
HPR17: HomePNA Status/Control Register (Register
Default Value (hex)
Bits 15:13 11:7 Reserved
Name
Description Test control bits. Reads will produce undefined results. Should written any1Home Link packet disabled. any1Home Link packet enabled. Test control bits. Reads will produce undefined results. Should written 1=Last packet received, sent High Power 0=Last packet received, sent Power 1=Last packet received, sent High Speed 0=Last packet received, sent Speed 1=Last packet received, sent Version 0=Last packet received, sent Version Test control bits. Reads will produce undefined results. Should written
Read/Write
any1Home_ Disable Reserved Received_Power
Received_Speed
Received_Ver Reserved
Am79C901
HPR18 HPR19: HomePNA TxCOMM Registers (Registers Table HPR18 HPR19: HomePNA TxCOMM Registers (Registers
Default Value (hex) 0000
Bits 15:0
Name PHY_TX_COMM
Description 32-bit preamble transmitted HomePNA PHY. HPR18 contains high word HPR19 word.
Read/Write
32-bit transmitted data field used outof-band communication between management entities. protocol out-of-band management been defined. Accessing word causes send all-0 PCOMs until high word been accessed. Once accessed, next transmitted packet will cause this register's contents shifted
PCOM field transmitted packet. Upon transmission, this register will read back non-null transmitted PCOM will TxPCOM Ready Event Status Register (HPR26). access TxPCOM words will clear TxPCOM Ready ISTAT register.
HPR20 HPR21: HomePNA RxCOMM Registers (Registers Table HPR20 HPR21: HomePNA RxCOMM Registers (Registers
Default Value (hex) 0000
Bits 15:0
Name PHY_RX_COMM
Description 32-bit preamble received HomePNA PHY. HPR20 contains high word HPR21 word.
Read/Write
32-bit received data field used out-ofband communication between management entities. protocol out-of-band management been defined. Accessing word register sufficient ensure that subsequently received packets
will overwrite register contents. non-null received PCOM will RxPCOM Valid Event Status Register (HPR26). Accessing high word register clears this allows overwriting register subsequent received packets.
Am79C901
HPR22: HomePNA Register (Register Table HPR22: HomePNA Register (Register
Default Value (hex)
Bits 15:8 PHY_AID
Name
Description Access this PHY. PHY_Control Disable Negotiation set, then writes this will have effect. 8-bit counter that records number noise events detected. Overflows held FFh. cleared setting HPR16.
Read/Write
Noise Events
PHY's address used collision detection. Unless CONTROL register set, assured select unique address. Addresses
above reserved. Address defined indicate remote command.
HPR23: HomePNA Noise Control Register (Register Table HPR23: HomePNA Noise Control Register (Register
Read/ Write Default Value (hex)
Bits 15:8 Noise Floor Noise Ceiling
Name
Description minimum value NOISE measurement. maximum value NOISE measurement. exceeded, NOISE reset FLOOR.
HPR24: HomePNA Noise Control Register (Register
Table
Bits Name
HPR24: HomePNA Noise Control Register (Register
Description Sets attack characteristics NOISE algorithm. High nibble sets number noise events needed raise NOISE level immediately, while nibble number noise events needed raise level period. Reads will produce undefined results. Read/ Write Default Value
15:8
Noise Attack
Reserved
Am79C901
HPR25: HomePNA Noise Statistics Register (Register
Table
HPR25: HomePNA Noise Statistics Register (Register
Read/ Write Default Value (hex)
Bits
Name
Description This digital value SLICE_LVL_NOISE output. effectively measure noise level wire tracks noise counting number false triggers NOISE comparator window. When auto-adaptation enabled (bit PHY_Control Register false), this register updated with current NOISE count every When adaptation disabled, this register written used generate both SLICE_LVL_NOISE SLICE_LVL_DATA signals. This measurement peak level last valid (non-collision) received.
15:8
Noise Level
Peak Level
HPR26: HomePNA Event Status Register (Register
Table
HPR26: HomePNA Event Status Register (Register
Read/ Write Indicates valid RxPCOM. access RxCOM Register will clear this bit. Indicates valid TxPCOM. access TxCOM registers (Registers will clear this bit. Reads will produce undefined results. Should written Status cleared writing Status cleared writing valid remote command received. Status cleared writing remote command been sent. Status cleared writing Default Value (hex)
Bits 15:10 Reserved RxPCOM
Name
Description
TxPCOM
Reserved Packet Received Packet Transmitted Remote Command Received
Remote Command Sent
Am79C901
HPR27: HomePNA Control Register (Register HomePNA Control Register reports state each event source. written facilitate software-stimulated event testing.
Table
HPR27: HomePNA Control Register (Register
Read/ Write Default Value (hex)
Bits 15:8
Mnemonic AID_INTERVAL AID_ISBI
Description This value defines number TCLKs (116.6 separating symbols. This value defines number TCLKs (116.6 separating symbol
HPR28: HomePNA ISBI Control Register (Register Table HPR28: HomePNA ISBI Control Register (Register
Read/ Write Default Value (hex)
Bits 15:8 ISBI_SLOW
Name
Description This value defines number TCLKs (116.6 separating data pulses Symbol low-speed mode. This value defines number TCLKs (116.6 separating data pulses Symbol high-speed mode.
ISBI_FAST
HPR29: HomePNA Control Register (Register Table HPR29: HomePNA Control Register (Register
Read/ Write Default Value (hex)
Bits 15:8
Name TX_PULSE_WIDTH
Description This value defines duration transmit pulse cycles (16.7 ns). This will effectively determine transmit spectrum PHY. This value defines number pulses that will driven onto HRTXRX_N pin. This value defines number pulses that will driven onto HRTXRX_P pin.
TX_PULSE_CYCLES_N TX_PULSE_CYCLES_P
Am79C901
HPR30: HomePNA Drive Level Control Register (Register
Table
HPR30: HomePNA Drive Level Control Register (Register
Read/ Write Default Value (hex)
Bits 15:12 11:6 Reserved
Mnemonic
Description Reserved. Must written Read Defines drive level that will utilized High Power mode. Defines drive level that will utilized Power mode.
High Level Control Level Control
HPR31: HomePNA Analog Control Register (Register
Table
HPR31: HomePNA Analog Control Register (Register
Read/ Write Default Value (hex)
Bits
Mnemonic
Description Global output slope adjustment. These bits control number current sources enabled transmit. Each represents single current source. Thus 10101 enables three current sources does 11100. Reserved. Must written Link Status will held valid Normal operation Reserved. Must written
15:11
Level_Adjust
10:8
Reserved Force_Link_Valid Reserved
Am79C901
10BASE-T Management Registers (TBRs)
Am79C901 home networking device supports basic register extended register set. Both sets registers accessible through management interface interface. specified IEEE standard, basic register consists
Control Register (Register Status Register (Register extended register consists Registers (decimal). Table lists 10BASE-T registers implemented device. reserved registers should written reading them will return undetermined value.
Table
Register Address 8:15 20:23 25:31 Symbol TBR0 TBR1 TBR2 TBR3 TBR4 TBR5 TBR6 TBR7 TBR8-TBR15 TBR16 TBR17 TBR18 TBR19 TBR20-TBR23 TBR24 TBR25-TBR31
10BASE-T Management Registers (TBRs)
Name Basic/Extended Default Value After H_RESET 1500h 1xx9h 0000h 6B71h 0061h 0000h 0004h 2001h -0000h 0001h -0000h
Control Register Status Register PHY_ID[31:16] PHY_ID[15:0] Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Register Reserved Status Enable Register Control/Status Register Reserved Management Extension Register Reserved Summary Status Register Reserved
Am79C901
TBR0: 10BASE-T Control Register (Register Table TBR0: 10BASE-T Control Register (Register
Read/Write (Note Default Value (hex)
Bits
Name
Description When write, software reset,
Soft Reset (Note
normal operation. When read, reset process, reset done.
R/W,
Enable Loopback Mode Speed Selection (Note Auto-Negotiation Enable
Loopback mode enable Loopback mode disable Mbps (not available), Mbps enable Auto-Negotiation, disable Auto-Negotiation power down, normal operation electrically isolates from MII/GPSI normal operation restart Auto-Negotiation, normal operation Full-Duplex, Half-Duplex enable signal test, disable signal test Write ignore read
Power Down Isolate (Note Restart Auto-Negotiation Duplex Mode (Note Collision Test (Note Reserved
R/W,
Notes: Read/Write, Self Clearing, Read only. Soft Reset does reset block. Refer Soft Reset section details. Bits have effect Auto-Negotiation enabled (Bit ISOL chip Isolate Register this will set. "enable loopback mode" must also ensure that collision traffic imposed network.
Am79C901
TBR1: 10BASE-T Status Register (Register Status Register identifies physical AutoNegotiation capabilities local PHY. This register read only; write will have effect. Table
Table
TBR1: 10BASE-T Status Register (Register
Read/Write (Note Default Value (hex)
Bits 10:7 100BASE-T4
Name
Description 100BASE-T4 able, 100BASE-T4 able 100BASE-X full-duplex able, 100BASE-X full-duplex able 100BASE-X half-duplex able, 100BASE-X half-duplex able Mbps full-duplex able, Mbps full-duplex able Mbps half-duplex able, Mbps half-duplex able Ignore when read accept management (mgmt) frames with without preamble, only accept mgmt frames with preamble Auto-Negotiation completed, Auto-Negotiation completed remote fault detected, remote fault detected able auto-negotiate, able auto-negotiate link link down jabber condition detected, jabber condition detected extended register capabilities, basic register capabilities only
100BASE-X Full-Duplex 100BASE-X Half-Duplex Mbps Full-Duplex Mbps Half-Duplex Reserved Management Frame Preamble Suppression
Auto-Negotiation Complete Remote Fault Auto-Negotiation Ability Link Status Jabber Detect Extended Capability
(Note
(Note
Note: Latching High, Latching Low.
Am79C901
TBR2 TBR3: 10BASE-T Identifier Register (Registers Registers contain unique identifier, consisting bits organizationally unique IEEE identifier, 6-bit manufacturer's model number, 4-bit manufacturer's revision number. most significant identifier register least significant identifier register Register corresponds IEEE identifier register corresponds IEEE identifier. Register corresponds IEEE identifier register corresponds IEEE identifier. Register bits 9-4, contain manufacturer's model number bits contain manufacturer's revision number. These registers shown Table Table
Table
Bits 15:0 Name PHY_ID[31-16]
TBR2: 10BASE-T Identifier Register (Register
Description IEEE Address (bits 3-18); Register Identifier Read/ Write Default Value (hex) 0000
Table
Bits 15:10 Name PHY_ID[15-10] PHY_ID[9-4] PHY_ID[3-0]
TBR3: 10BASE-T Identifier Register (Register
Description IEEE Address (bits 19-24) Manufacturer's Model Number (bits 5-0) Revision Number (bits 3-0); Register Identifier Read/ Write Default Value (hex)
Am79C901
TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register This register contains advertised ability Am79C901 home networking device. purpose this register advertise technology ability link partner device. Table When this register modified, Restar AutoNegotiation (Register must enabled guarantee change implemented.
Table
TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register
Read/ Write When set, remote fault inserted into base link code word during Auto-Negotiation process. When cleared, base link code work will have position remote fault cleared. Default Value (hex)
Bits
Name Next Page Reserved
Description When set, device wishes engage next page exchange. cleared, device does wish engage next page exchange.
Remote Fault
12:11
Reserved PAUSE Reserved Full-Duplex 100BASE-TX This advertises Full-Duplex capability. When set, Full-Duplex capability advertised. When cleared, Full-Duplex capability advertised. This advertises Half-Duplex capability Auto-Negotiation process. Setting this advertises Half-Duplex capability. Clearing this does advertise Half-Duplex capability. This advertises Full-Duplex capability. When set, Full-Duplex capability advertised. When cleared, Full-Duplex capability advertised. This advertises Half-Duplex capability Auto-Negotiation process. Setting this advertises Half-Duplex capability. Clearing this does advertise Half-Duplex capability. 10BASE-T Am79C901 home networking device 802.3 compliant device. This should PAUSE capability advertised.
Half-Duplex 100BASE-TX
Full-Duplex 10BASE-T
Half-Duplex 10BASE-T
Selector Field
Am79C901
TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register Auto-Negotiation Link Partner Ability Register Read Only. register contains advertised ability link partner. definitions represent received link code word. This register contains either base page link partner's next pages. values contained these registers only valid once AutoNegotiation successfully completed, indicated TBR1, Next Page exchange used after Page Received (TBR6, been logic one. Table Table
Table
Bits 12:5
TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register Base Page Format
Name Next Page Acknowledge Remote Fault Description Link partner next page request Link partner acknowledgment Link partner remote fault request Read/ Write Default Value (hex)
Technology Ability Link partner technology ability field Selector Field Link partner selector field
Table
Bits 10:0
TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register Next Page Format
Name Next Page Acknowledge Message Page Acknowledge Toggle Message Field Description Link partner next page request Link partner acknowledgment Link partner message page request Link partner comply with request Link partner cannot comply with request Link partner toggle Link partner's message code Read/ Write Default Value (hex)
Am79C901
TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register Auto-Negotiation Expansion Register provides additional information which aids Auto-Negotiation process. Auto-Negotiation Expansion Register bits Read Only. Table
Table
Bits 15:5 Name Reserved
TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register
Description Read/ Write Default Value (hex)
Parallel Detection 1=Parallel detection fault Fault 0=No parallel detection fault Link Partner Next Page Able Next Page Able Link partner next page able Link partner next page able Am79C901 device channel next page able Am79C901 device channel next page able page been received page been received
Page Received
Link Partner ANEG Link partner Auto-Negotiation able Able Link partner Auto-Negotiation able
TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register Auto-Negotiation Next Page Register contains next page link code word transmitted.
power-up default value 2001h represents message page with message code null. Table
Table
Bits 10:0 Name Next Page Reserved Message Page Acknowledge Toggle Message Field
TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register
Description Am79C901 device channel next page request Read/ Write Am79C901 device channel message page request Am79C901 device channel comply with request Am79C901 device channel cannot comply with request Am79C901 device channel toggle Message code field Default Value (hex)
Reserved Registers (Registers 8-15, 20-23, 25-31) Am79C901 device contains reserved registers addresses 8-15, 20-23, 25-31. These registers should ignored when read should written time.
Am79C901
TBR16: 10BASE-T Status Enable Register (Register status bits indicate when there change Link Status, Duplex Mode, Auto-Negotiation status, Speed status. Register contains status enable bits. status always updated whether enable bits set. When status change occurs, system will need read this register clear status bits. Table
Table
Bits 15:14 Name Reserved
TBR16: 10BASE-T Status Enable Register (Register
Description Read/ Write When this set, setting bits 12:9 this register will cause condition that will bits accordingly. effect test register bits with forced interrupt condition. Bits only interrupt condition bits 12:9 set) occurs. Default Value (hex)
Status Test Enable (Note
Link Status Change Enable Duplex Mode Change Enable Auto-Negotiation Change Enable Speed Change Enable
Link Status change enable This interrupt masked Duplex Mode change enable This interrupt masked Auto-Negotiation change enable This interrupt masked Speed change enable This interrupt masked Global interrupt enable This interrupt masked
Global Enable Reserved Link Status Change
Link Status changed port change Link Status Duplex Mode changed port change Duplex mode Auto-Negotiation status changed port change Auto-Negotiation status Speed status changed port change Indicates change status above interrupts Indicates change Interrupt status
Duplex Mode Change
Auto-Negotiation Change
Speed Change
Global
Note: bits, except cleared read (COR). register must read twice been cleared.
Am79C901
TBR17: 10BASE-T Control/Status Register (Register This register used control configuration Mbps Am79C901 home networking device. Table
Table
TBR17: 10BASE-T Control/Status Register (Register
Default Value (hex)
Bits 15:14
Name Reserved Force Link Good Enable
Description
Read/Write
link status forced link state link status determined device Link pulses sent from 10BASE-T transmitter suppressed Link pulse enabled (normal operation) Disables heartbeat which occurs after each 10BASE-T transmission heartbeat assertion occurs approximately after transmission duration
Disable Link Pulse
SQE_TEST Disable
Reserved Jabber Detect Disable Reserved Receive Polarity Reversed Auto Receive Polarity Correction Disable Receive polarity 10BASE-T receiver reversed Receive polarity correct polarity correction circuit disabled 10BASE-T Self correcting polarity circuit enabled 10BASE-T receive squelch thresholds reduced allow reception frames which greater than meters Squelch thresholds standard distance meters outputs active Transmit valid data asserted when transmit receive medium active asserted when receive medium active disable jabber detect enable jabber detect
Extended Distance Enable
TX_DISABLE
TX_CRS_EN Reserved Isolated
10BASE-T isolated 10BASE-T enabled
Note: these loopback paths, data also transmitted pins (TX±).
Am79C901
TBR19: 10BASE-T Management Extension Register (Register Table contains Management Extension Register (Register bits.
Table
Bits 15:6
TBR19: 10BASE-T Management Extension Register (Register
Description Write ignore read last management frame invalid (opcode error, etc.) last management frame valid Address defaults 000X1. Read/Write Default Value (hex)
Name Reserved Mgmt Frame Format
Address
Value PHY_ADD (i.e., 00001 00011)
01/03
TBR24: 10BASE-T Summary Status Register (Register Summary Status register global register containing status information. This register Read Only represents most important data which single register access convey. mary Status register indicates following: Link Status, Full-Duplex Status, Auto-Negotiation Alert, Speed. Table
Table
Bits 15:4 Name Reserved Link Status Full-Duplex Auto-Negotiation Alert Speed
TBR24: 10BASE-T Summary Status Register (Register
Description Read/Write Default Value (hex)
Write Ignore Read Link Status Link Status down Operating Full-Duplex mode Operating Half-Duplex mode Auto-Negotiation status changed Auto-Negotiation status unchanged Operating Mbps Operating Mbps
Am79C901
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature -65°C +70°C Supply Voltage with respect -0.3 3.63
OPERATING RANGES
Commercial Devices Temperature (TA) .0°C +70°C Supply Voltages (VDD) inputs within range:
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability.
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES unless otherwise specified
Parameter Symbol Parameter Description Digital Voltage Input HIGH Voltage VIH5V Input HIGH voltage (5V) Input Voltage Output Voltage Test Conditions IOL1 IOL2 IOL3 IOH1 VOUT Output HIGH Voltage (Notes IOH2 (Note Output Voltage (peak) (Note Input Differential Squelch Assert VDIFF (peak) Input Differential De-Assert Voltage VDIFF (peak) Digital Current Output Leakage Current (Note Input Leakage Current (Note Input Current (Note Input HIGH Current (Note Power Supply Current Mbps) Mbps) (Static) Mbps mode RX±. Outputs driving load. 10BASE-T mode RX±. Outputs driving load. XCLK frequency 1.55 1.98 Units
DVDD
<VOUT <VDD <VIN <VDD VDD= Maximum Transmitting maximum packets minimum IPG. VDD= Maximum Transmitting maximum packets minimum IPG. VDD= Maximum VDD= Maximum
-200
transmitting. (Idle) Capacitance Capacitance CCLK Capacitance LPIN Inductance
(Note (Notes (Note
Am79C901
Notes:
does apply open-drain output pins. IOH2 applies other outputs. applies output bidirectional pins. Tests performed only. applies input pins except TDI, TCLK, pins. apply TDI, TCLK, pins. Parameter tested. Value determined characterization. CCLK applies only pin. VOUT reflects output levels prior transformer state.
Am79C901
SWITCHING WAVEFORMS Switching Waveforms
WAVEFORM
INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply
OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUITS
Sense Point
VTHRESHOLD
22304A-25
Figure Normal Tri-State Outputs
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED GPSI
10BASE-T Transmit Timing (GPSI)
Symbol tPWL Parameter Description TXDAT, TXEN setup time TXCLK edge TXDAT, TXEN hold time TXCLK edge Transmit latency (TXEN sampled HIGH data) RXCRS assert from TXEN sampled HIGH RXCRS de-assert from TXEN sampled TXEN de-assertion time between packets -360 -Unit
TXCLK TXEN RXCRS Packet TXDAT, TXEN Start Packet
22304A-26
Figure
Mbps Transmit Timing (GPSI)
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED)
10BASE-T Receive Timing (GPSI)
Symbol Parameter Description assert latency from RXCRS assert latency from Receive latency (SOP RXDAT valid) RXCLK edge RXDAT transition de-assert latency from RXCRS de-assert latency from Unit
RXCLK
Start Packet
RXCRS
RXDAT
22304A-27
Figure
Mbps Receive Start Packet Timing (GPSI)
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED)
10BASE-T Receive Timing (GPSI) (Continued)
RXCLK
Packet
RXCRS
22304A-28
Figure
Mbps Receive Packet Timing (GPSI)
10BASE-T Transmit Clock Timing (GPSI)
Symbol tPER tPWH tPWL TXCLK period TXCLK pulse width HIGH TXCLK pulse width Parameter Description 99.99 100.01 Unit
10BASE-T Receive Clock Timing (GPSI)
Symbol tPER tPWH tPWL RXCLK period RXCLK pulse width HIGH RXCLK pulse width Parameter Description 99.99 100.01 Unit
TXCLK, RXCLK
22304A-29
Figure
Mbps Transmit Receive Clock Timing (GPSI)
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED)
Mbps HomePNA Transmit Timing (GPSI)
Symbol Parameter Description TXDAT, TXEN setup time TXCLK edge TXDAT, TXEN hold time TXCLK edge TXEN active SYNC pulse TXEN active active -Max -500 Unit
TX_CLK TXDAT
TX_EN
SYNC
HRTXRXP/N±
PCOM
DATA
22304A-30
Figure
Mbps HomePNA Transmit Timing (GPSI)
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED)
Mbps HomePNA Receive Timing (GPSI)
Symbol Parameter Description RXCLK edge RXDAT transition SYNC pulse detected RXCRS clocked active Last DATA pulse crosses noise slice level RXCRS inactive RXCRS inactive inactive clocked into 15.98 -Max 16.10 Unit
RXCLK RXDAT SYNC HRTXRXP/N± DATA RXCRS
22304A-31
DATA
DATA
Figure
Mbps HomePNA Receive Timing (GPSI)
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED)
Mbps HomePNA Clock Timing (GPSI)
Symbol Parameter Description Clock Period Unit
Idle (excluding time) tPER tPWH tPWL TXCLK, RXCLK period TXCLK, RXCLK pulse width HIGH TXCLK, RXCLK pulse width 583.3 115.5 467.8
Preamble (first bits frame) tPER tPWH tPWL TXCLK, RXCLK period TXCLK, RXCLK pulse width HIGH TXCLK, RXCLK pulse width 233.3 115.5 117.8
Data (thoughtout data phase) tPER tPWH tPWL TXCLK, RXCLK period TXCLK, RXCLK pulse width HIGH TXCLK, RXCLK pulse width 233.3 115.5 117.8
times following falling edge) tPER tPWH tPWL TXCLK, RXCLK period TXCLK, RXCLK pulse width HIGH TXCLK, RXCLK pulse width 233.3 115.5 117.8
Note: During interval, RXCLK TXCLK stop
TXCLK, RXCLK
22304A-32
Figure
Mbps HomePNA Clock Timing (GPSI)
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED)
10BASE-T Transmit Timing (MII)
Symbol tPWL Parameter Description TXD, TX_EN setup time TXCLK edge TXD, TX_EN hold time TXCLK edge Transmit latency (TX_EN sampled HIGH data) assert from TX_EN sampled HIGH de-assert from TX_EN sampled TX_EN de-assertion time between packets 1200 -510 -Unit
TX_CLK TX_EN Packet TXD, TX_EN Start Packet
22304A-33
Figure Mbps Transmit Timing (MII)
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED)
10BASE-T Receive Timing (MII)
Symbol Parameter Description assert latency from assert latency from Receive latency (SOP RXD, RX_DV valid) RX_CLK edge RXD, RX_DV transition RX_DV de-assert latency de-assert latency from de-assert latency from 1275 Unit
RX_CLK
Start Packet
RXD, RX_DV
22304A-34
Figure
Mbps Receive Start Packet Timing (MII)
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED)
10BASE-T Receive Timing (MII) (Continued)
RX_CLK
Packet
RX_DV
22304A-35
Figure
Mbps Receive Packet Timing (MII)
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED)
10BASE-T Transmit Clock Timing (MII)
Symbol tPER tPWH tPWL TX_CLK period TX_CLK pulse width HIGH TX_CLK pulse width Parameter Description 399.6 400.4 Unit
10BASE-T Receive Clock Timing (MII)
Symbol tPER tPWH tPWL RX_CLK period RX_CLK pulse width HIGH RX_CLK pulse width Parameter Description 399.6 400.4 Unit
TX_CLK, RX_CLK
22304A-36
Figure
Mbps Transmit Receive Clock Timing (MII)
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED)
Mbps HomePNA Transmit Timing (MII)
Symbol Parameter Description TXD, TX_EN setup time TX_CLK edge TXD, TX_EN hold time TX_CLK edge TX_EN active SYNC pulse TX_EN active active -Max -500 Unit
TX_CLK
TX_EN HRTXRXP/N±
SYNC
PCOM
DATA
22304A-37
Figure
Mbps HomePNA Transmit Timing (MII)
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED)
Mbps HomePNA Receive Timing (MII)
Symbol Parameter Description RX_CLK edge RXD, RX_DV transitions SYNC pulse detected clocked active Last DATA pulse crosses noise slice level inactive inactive inactive clocked into 15.98 -Max 16.10 Unit
RX_CLK RXD, RX_DV SYNC HRTXRXP/N± DATA
22304A-38
DATA
DATA
Figure
Mbps HomePNA Receive Timing (MII)
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED)
Mbps HomePNA Clock Timing (MII)
Symbol Parameter Description Clock Period Unit
Idle (excluding time) tPER tPWH tPWL TX_CLK, RX_CLK period TX_CLK, RX_CLK pulse width HIGH TX_CLK, RX_CLK pulse width 2333.34 1165 1168
Preamble (first bits frame) tPER tPWH tPWL TX_CLK, RX_CLK period TX_CLK, RX_CLK pulse width HIGH TX_CLK, RX_CLK pulse width 933.33
Data (throughout data phase) tPER tPWH tPWL TX_CLK, RX_CLK period TX_CLK, RX_CLK pulse width HIGH TX_CLK, RX_CLK pulse width
times following falling edge) tPER tPWH tPWL TX_CLK, RX_CLK period TX_CLK, RX_CLK pulse width HIGH TX_CLK, RX_CLK pulse width 933.33
Note: During interval, RX_CLK TX_CLK stop
TX_CLK, RX_CLK
22304A-39
Figure
Mbps HomePNA Clock Timing (MII)
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED) MDC/MDIO
Symbol tPER tPWH tPWL period pulse width HIGH pulse width
Parameter Description
-300
Unit
MDIO output delay from edge MDIO input setup time edge MDIO input hold time from edge high impedance
MDIO
22304A-40
Figure Management Timing
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED)
Parameter Symbol tPWH tPWL tPZD
Parameter Name SCLK period SCLK pulse HIGH SCLK pulse setup SCLK hold SCLK setup SCLK hold SCLK SCLK valid
Unit
SCLK
22304A-41
Figure
Timing
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED) 10BASE-T
Symbol tTETD tPWKRD Parameter Description Transmit Transmit Data Pulse Width Maintain/Turn Threshold |VIN| |VTHS| (Note Test Conditions Unit
Note: pulses narrower than tPWDRD (min) will maintain internal Carrier Sense pulses wider than tPWKRD (max) will turn internal Carrier Sense off.
22304A-42
Figure
Mbps Transmit (TX±) Timing Diagram
VTSQ+ VTSQ100
22304A-43
Figure
Mbps Receive (RX±) Timing Diagram
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED) Mbps HomePNA Analog
Parameter Symbol tPWH tPWL tVMAXp tVMAXn
Parameter Name Pulse Width Pulse Width HIGH Pulse Width Maximum Voltage (positive)
Conditions
Typical
Units
Power High Power Power High Power
1.00 2.00 1.00 2.00
Maximum Voltage (negative)
Notes: registers default values 25°C. Measurements across HRTXTXP HRTXTXN, differentially measured, with resistive load.
22304A-44
Figure HomePNA Waveform
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONTINUED) JTAG
Parameter Symbol tPER tPWH tPWL Period HIGH Time Time TDI, Setup Time TDI, Hold Time Valid Delay Float Delay Parameter Name -Max Unit
Note: tested; parameter guaranteed design characterization.
TDI,
22304A-45
Figure
JTAG (IEEE 1149.1) Test Signal Timing
Am79C901
CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED (CONCLUDED) External Clock (XTAL1)
Symbol tPER tPWH tPWL Cycle time Cycle HIGH time Cycle time Parameter Description 16.665 TCYCLE TCYCLE 16.669 TCYCLE TCYCLE Unit
XTAL1
22304A-46
Figure External Clock Timing
Reset
Symbol Parameter Description RESET RESET 5000 -Unit
Am79C901
PHYSICAL DIMENSIONS* Plastic Leaded Chip Carrier (measured inches)
.985 .995 .950 .956 Lead Pocket .042 .048
.950 .985 .956 .995
.0085
.026 .032
.050 .005 BOTTOM VIEW
VIEW
.042 .056
.062 .083 .013 .018
Detail
Note .020
Seating Plane .800 .890 .930 Scale: None .013 .021 (.007) TOTAL
Note .025 .045
.026 .032 .066 .072
.023 .029
.007 .013 .090 .130 .165 .180
DETAIL
Seating Plane
16-038-SQ_AM PL68/PLH68 EP80 8.13.98
SIDE VIEW
Notes: Dimensions inches. Dimensions measured from outermost point. Dimensions include corner mold flash. Allowable corner mold flash 0.010 inch. Dimensions "A", "A1", "D2", "E2" measured points contact base plane. Lead spacing measured from center-line center-line shall within 0.005 inch. J-bend lead tips should located inside "pockets". Lead coplanarity shall within 0.004 inch measured from seating plane. Lead tweeze shall within 0.0045 inch each side measured from vertical flat plane. lead pocket rectangular shown) oval. corner lead pockets connected then 0.005-inch minimum lead spacing required.
*For reference only. ANSI standard Basic Space Centering.
Am79C901
contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks Copyright 1999 Advanced Micro Devices, Inc. rights reserved. AMD, logo, combinations thereof registered trademarks Advanced Micro Devices, Inc. AlertIT, any1Home, eIMR, eIMR+, GigaPHY, HIMIB, HomePHY, IMR2, MACE, Magic Packet, NetPHY, PCnet, PCnet-Home, QuEST, QuIET trademarks Advanced Micro Devices, Inc. RLL25 trademark Systems, Inc. Product names used this publication identification purposes only trademarks their respective companies.
Am79C90
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