NetPHYTM-1LP Power 10/100-TX/FX Ethernet Transceiver DISTINCTIVE

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NetPHYTM-1LP Power 10/100-TX/FX Ethernet Transceiver DISTINCTIVE

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Am79C874
NetPHYTM-1LP Power 10/100-TX/FX Ethernet Transceiver
DISTINCTIVE CHARACTERISTICS
10/100BASE-TX Ethernet PHY100BASE-FX fiber optic support Typical power consumption Sends/receives data reliably over cable lengths greater than meters mode supports 100BASE-X 10BASE-T 7-Wire (General Purpose Serial Interface (GPSI)) mode supports 10BASE-T only Three PowerWisemanagement modes (from typical) Power down: only management responds Typical power Unplugged: cable, receive clock Typical power Idle wire: wire signal, receiver power Typical power saves over Supports 1.25:1 transmit transformer Using 1.25:1 ratio saves transmit power consumption external filters chokes required Waveshaping external filter required 10BASE-T Full half-duplex operation with full-featured Auto-Negotiation function indicators: Link, activity, activity, Collision, Mbps, Mbps, Full Half Duplex Automatic Polarity Detection Built-in loopback test modes Single 3.3-V power supply with tolerance 80-pin TQFP package
GENERAL DESCRIPTION
Am79C874 NetPHY-1LP device provides physical (PHY) layer transceiver functions 10/100 Mbps Ethernet port. delivers dual benefits CMOS power consumption small package size. Operating consumes only Three power management modes provide options even lower power consumption levels. small 12x12 80-pin package conserves valuable board space adapter cards, switch uplinks, embedded Ethernet applications. NetPHY-1LP 10/100 Mbps Ethernet IEEE 802.3u compliant. receive transmit data reliably over meters. includes on-chip input filtering output waveshaping unshielded twisted pair operation without requiring external filters chokes. NetPHY-1LP device isolation transformers 1.25:1 isolation transformers. 1.25:1 isolation transformers provide lower transmit power consumption. PECL interface available 100BASE-FX applications. Interface Media Access Controller (MAC) layer established standard Media Independent Interface (MII) 5-bit symbol interface. Auto-Negotiation determines network speed full half-duplex operation. Automatic polarity correction performed during Auto-Negotiation during 10BASE-T signal reception. legacy 10BASE-T devices, 7-wire (GPSI) mode selected. Multiple pins provided front panel status feedback. option dual-color LEDs that flash show device 100BASE-TX 10BASE-T mode, Half Full Duplex, data being received. Individual LEDs indicate link detection, collision detection, data being transmitted. NetPHY-1LP device needs only external 25MHz crystal because uses dual-speed clock synthesizer generate other clock domains required. receiver adaptive equalizer/DC restoration circuit accurate clock/data recovery from 100BASE-TX signal.
Publication# 22235 Rev: Amendment/0 Issue Date: April 1999
Refer AMD's Website (www.amd.com) latest information.
BLOCK DIAGRAM
Framer Carrier Detect 4B/5B Data Interface Interface MDC/MDIO
Clock Recovery Link Monitor Signal Detect
TP_PMD MLT-3 Stream Cipher 10TX
100TX 100RX
10BASE-T
10RX
Transformer
Control/Status
Serial Management Interface Registers
Generator Test Control
AutoNegotiation
PHYAD[4:0]
XTL+ XTL-
TEST Drivers
22235B-1
Am79C874
CONNECTION DIAGRAM
TVCC2 TVCC1 TXTX+ TGND2 XTL+ XTLREFVCC IBREF REFGND FXTFXT+ TEST2 FXR+ FXREQGND RXTEST3/SDI+ RPTR
PCSBP ISODEF TGND1 REFCLK CLK25 TEST1/BURN_IN PWRDN PLLVCC PLLGND OGND1 OVDD1 PHYAD[4]/10RXDPHYAD[3]/10RXD+ PHYAD[2]/10TXD++ PHYAD[1]/10TXD+ GPIO[1]/TP125 EQVCC ADPVCC LEDDPX/LEDTXB LEDSPD[1]/LEDTXA/CLK25EN ANEGA TECH_SEL[0]/LINK_BT TECH_SEL[1]/SPDSEL TECH_SEL[2]/DPX CRVVCC CRVGND OGND2 OVDD2 LEDLNK/LED_10LNK/LED_PCSBP_SD LEDTX/LEDBTB LEDRX/LEDSEL LEDCOL/SCRAM_EN LEDSPD[0]/LEDBTA/FX_SEL INTR CRS/10CRS COL/10COL Am79C874
NetPHY-1LP
MDIO RXD[3] RXD[2] RXD[1] RXD[0]/10RXD VDD1 DGND1 RX_DV RX_CLK/10RXCLK RX_ER/RXD[4] TX_ER/TXD[4] TX_CLK/10TXCLK/PCSBP_CLK TX_EN/10TXEN DGND2 VDD2 TXD[0]/10TXD TXD[1] TXD[2] TXD[3]
22235B-2
Am79C874
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination elements below. AM79C874
ALTERNATE PACKAGING OPTION Trimmed formed tray
TEMPERATURE RANGE Commercial (0°C +70°C) PACKAGE TYPE 80-Pin Plastic Quad Flat Pack (PQT SPEED OPTION Applicable
DEVICE NUMBER/DESCRIPTION Am79C874 NetPHY-1LP Power 10/100-TX/FX Ethernet Transceiver
Valid Combinations AM79C874 VC\W
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am79C874
RELATED PRODUCTS
Part Controllers Am79C90
Description
CMOS Local Area Network Controller Ethernet (C-LANCETM)
Integrated Controllers Am79C940 Am79C961A Am79C965A Am79C970A Am79C971 Am79C972 Am79C973/ Am79C975 Am79C978 Media Access Controller Ethernet (MACETM) PCnetTM-ISA Full Duplex Single-Chip Ethernet Controller PCnetTM-32 Single-Chip 32-Bit Ethernet Controller Buses PCnetTM-PCI Full Duplex Single-Chip Ethernet Controller Local PCnetTM-FAST Single-Chip Full Duplex 10/100 Mbps Ethernet Controller Local PCnetTM-FAST+ Enhanced 10/100 Mbps Ethernet Controller with OnNow Support PCnetTM-FAST Single-Chip 10/100 Mbps Ethernet Controller with Integrated PCnetTM-Home Single-Chip 1/10 Mbps Home Networking Controller
Physical Layer Devices (Single-Port) Am79761 Am79C98 Am79C100 Am79C873 Physical Layer 10-Bit Transceiver Gigabit Ethernet (GigaPHYTM-SD) Twisted Pair Ethernet Transceiver (TPEX) Twisted Pair Ethernet Transceiver Plus (TPEX+) NetPHYTM-1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support
Physical Layer Devices (Multi-Port) Am79C875 Am79C988A Am79C989 NetPHYTM-4LP Power Quad10/100-TX/FX Ethernet Transceiver Quad Integrated Ethernet Transceiver (QuIETTM) Quad Ethernet Switching Transceiver (QuESTTM)
Integrated Repeater/Hub Devices Am79C981 Am79C982 Am79C983 Am79C984A Am79C985 Am79C987 Integrated Multiport Repeater Plus (IMR+) Basic Integrated Multiport Repeater (bIMR) Integrated Multiport Repeater (IMR2TM) Enhanced Integrated Multiport Repeater (eIMRTM) Enhanced Integrated Multiport Repeater Plus (eIMR+TM) Hardware Implemented Management Information Base (HIMIBTM)
Am79C874
TABLE CONTENTS
DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM CONNECTION DIAGRAM ORDERING INFORMATION Standard Products RELATED PRODUCTS DESIGNATIONS DESCRIPTIONS Media Connections MII/7-Wire (GPSI) Signals Miscellaneous Functions Port Pins Bias Power Ground FUNCTIONAL DESCRIPTION Modes Operation Mode 7-Wire (GPSI) Mode 100BASE-X Block Transmit Process Receive Process 4B/5B Encoder/Decoder Scrambler/Descrambler Link Monitor MLT-3. Adaptive Equalizer Baseline Wander Compensation Clock/Data Recovery Clock Synthesizer 10BASE-T Block Twisted Pair Transmit Process Twisted Pair Receive Process Twisted Pair Interface Status Collision Detect Function Jabber Function Reverse Polarity Detection Correction Auto-Negotiation Miscellaneous Functions. Auto-Negotiation Parallel Detection Far-End Fault (Heartbeat) Loopback Operation. Reset Port Configuration Power Savings Mechanisms Selectable Transformer Power Down. Unplugged Idle Wire CONTROL MANAGEMENT BLOCK (PCM BLOCK) Register Administration 100BASE-X Device Description Methodology Management Frame Handling REGISTER DESCRIPTIONS Serial Management Registers
Am79C874
Management Control Register (Register Management Status Register (Register Identifier Register (Register Identifier Register (Register Auto-Negotiation Advertisement Register (Register Auto-Negotiation Link Partner Ability Register Base Page Format (Register Auto-Negotiation Link Partner Ability Register Next Page Format (Register Auto-Negotiation Expansion Register (Register Auto-Negotiation Next Page Advertisement Register (Register Reserved Registers (Registers 8-15, 25-31) Miscellaneous Features Register (Register Interrupt Control/Status Register (Register Diagnostic Register (Register Power/Loopback Register (Register Mode Control Register (Register Disconnect Counter Register (Register Receive Error Counter Register (Register ABSOLUTE MAXIMUM RATINGS Operating Ranges CHARACTERISTICS SWITCHING CHARACTERISTICS System Clock Signal MLT-3 Signals. Management Signals Signals Mbps Transmit Timing Mbps Receive Timing Mbps Transmit Timing Mbps Receive Timing PHYSICAL DIMENSIONS PQT80
Am79C874
DESIGNATIONS
Listed Number
Name PCSBP ISODEF TGND1 REFCLK CLK25 TEST1/BURN_IN PWRDN PLLVCC PLLGND OGND1 OVDD1 PHYAD[4]/10RXDPHYAD[3]/10RXD+ PHYAD[2]/10TXD++ PHYAD[1]/10TXD+ PHYAD[0]/10TXDGPIO[0]/10TXD-/ 7Wire GPIO[1]/TP125
Name MDIO RXD[3]TEST3/SDI+ RXD[2] RXD[1] RXD[0]/10RXD VDD1 DGND1 RX_DV RX_CLK/10RXCLK RX_ER/RXD[4] TX_ER/TXD[4] TX_CLK/10TXCLK/ PCSBP_CLK TX_EN/10TXEN DGND2 VDD2 TXD[0]/10TXD TXD[1] TXD[2] TXD[3]
Name COL/10COL CRS/10CRS INTR LEDSPD[0]/ LEDBTA/FX_SEL LEDCOL/ SCRAM_EN LEDRX/LEDSEL LEDTX/LEDBTB LEDLNK/ LED_10LNK/ LED_PCSBP_SD OVDD2 OGND2 CRVGND CRVVCC TECH_SEL[2]/DPX TECH_SEL[1]/ SPDSEL TECH_SEL[0]/ LINK_BT ANEGA LEDSPD[1]/ LEDTXA/CLK25EN LEDDPX/LEDTXB ADPVCC EQVCC
Name RPTR TEST3/SDI+ RXRX+ EQGND FXRFXR+ TEST2 FXT+ FXTREFGND IBREF REFVCC XTLXTL+ TGND2 TXTVCC1 TVCC2
Am79C874
DESCRIPTIONS
following table describes terms used descriptions.
Term Input Analog Input Output Analog Output High Impedance Pull Pull Down Description Digital input Analog input Digital output from Analog output from Tri-state capable output from internal pull resistor. NC=HIGH internal pull down resistor. NC=LOW
MII/7-Wire (GPSI) Signals
RXD[3:0] Receive Data Output, High Impedance data synchronous with RX_CLK when RX_DV active. When 7-wire 10BASE-T interface operation enabled (GPIO[0]= HIGH), RXD[0] will serve serial data output. RX_DV Receive Data Valid Output, High Impedance
RX_DV asserted high when valid data present RXD[3:0] pins. 100BASE-TX mode, asserted with first nibble preamble de-asserted when last data nibble been received. 10BASE-T mode, asserted when Start-ofFrame delimiter (SFD) detected. RX_CLK/10RXCLK Receive Clock Output, High Impedance continuous clock which provides timing reference RX_DV, RX_ER, RXD[3:0] signals. 100BASE-TX/FX 10BASE-T. further reduce power consumption overall system, device provides optional mode enabled through Register which RX_CLK held inactive (low) when data received. When 7-wire 10BASE-T mode enabled, this will provide clock. RX_CLK high impedance when enabled RX_ER/RXD[4] Receive Error Output, High Impedance When RX_ER active high, indicates error been detected during frame reception. This becomes highest-order receive 5-bit code group bypass (PCSBP=HIGH) mode. This output ignored 10BASE-T operation. TX_ER/TXD[4] Transmit Error Input When TX_ER asserted, will cause 4B/5B encoding process substitute transmit error codegroup encoded data word. This becomes higher-order transmit 5bit code group bypass (PCSBP=HIGH) mode. This input ignored 10BASE-T operation. TX_CLK/10TXCLK/PCSBPCLK Transmit Clock Output, High Impedance free-running clock which provides timing reference TX_EN, TX_ER, TXD[3:0] signals. 100BASE-TX/FX 10BASE-T. When 7-wire 10BASE-T mode enabled, this will provide transmit clock 10BASE-T operation.
Media Connections
Transmitter Outputs Analog Output pins differential transmit output pair. pins transmit 10BASE-T MLT-3 signals depending state link port. Receiver Input Analog Input pins differential receive input pair. pins receive 10BASE-T MLT-3 signals depending state link port. FXT± Transmit Analog Output These pins connected 10/100BASE-TX mode. When FX_SEL (Pin pulled low, these pins become level transmit output 100BASE-FX. FXR± Receive Analog Input When FX_SEL (Pin pulled low, these pins become level receive input 100BASE-FX. These pins have internal pull-downs normal 100BASE-TX 10BASE-T mode, they left unconnected. TEST3/SDI+ Transceiver Signal Detect Analog Input This connected 10/100BASE-TX mode. When FX_SEL (Pin pulled low, this becomes Signal Detect input from Fiber-Optic transceiver. When signal quality good, SDI+ should driven high.
Am79C874
When working PCSBP mode, this will provide clock 100BASE-TX operation, clock 10BASE-T operation. TX_CLK high impedance when enabled. TX_EN/10TXEN Transmit Enable Input 10RXD± differential receive outputs MAC. 10TXD± differential transmit inputs from MAC. 10TXD++/10TXD- differential pre-emphasis transmit outputs from MAC. ISODEF Isolate Default Input, Pull Down
TX_EN asserted indicate that data present TXD[3:0]. When 7-wire 10BASE-T mode enabled, this transmit enable signal. TXD[3:1] Transmit Data Input
This used when multiple PHYs connected single MAC. When high, interface will high impedance. status this will latched into Register after reset. When this left unconnected, default condition output pins high impedance state. Isolate Input, Pull Down output pins will become high impedance when pulled high resistor. However, input pins will still respond data. This allows multiple PHYs attached same interface. same isolate condition also achieved asserting Register repeater mode, will tri-state pin. When this left unconnected, output pins high impedance state. REFCLK Clock Input Input, Pull Down This connects 25-MHz clock source. When crystal input used, this should tied ground resistor. XTL± Crystal Inputs Analog Input These pins should connected 25-MHz crystal. REFCLK (Pin should tied when crystal used clock source. CLK25 Clock Output, Pull Down When CLK25EN pulled resistor, CLK25 provides continuous clock MAC. TEST1/BURN_IN Test Enable Input, Pull Down When asserted, this forces NetPHY-1LP device into either manufacturing test mode Burn-in mode reliability assurance control. TEST2 Test Output Analog Output TEST2 used test mode output monitor pin.
will source TXD[3:1] PHY. data will synchronous with TX_CLK when TX_EN asserted. will clock data based rising edge TX_CLK. TXD[0]/10TXD Transmit Data[0]/10 Mbps Transmit Data Input will source TXD[0] PHY. data will synchronous with TX_CLK when TX_EN asserted. will clock data based rising edge TX_CLK. When 7-wire 10BASE-T mode enabled, this will transmit serial data. COL/10COL Collision Output, High Impedance asserted high when collision detected media. also used test function 10BASE-T mode. 10COL asserted HIGH when collision detected during 7-wire interface mode. CRS/10CRS Carrier Sense Output, High Impedance
asserted high when twisted pair media nonidle. This signal used both 10BASE-T 100BASE-X. 10CRS used carrier sense output 7wire interface mode.
Miscellaneous Functions
PCSBP Bypass Input, Pull Down
100BASE-TX well scrambler/descrambler will bypassed when PCSBP asserted high. TX_ER will become TXD[4] RX_ER will become RXD[4]. Mbps bypass mode, signals valid. signals that interface (i.e., DECPC 21143) located pins signals defined follows:
Am79C874
Reset LOW, GPIO[1] output. value Register will reflected GPIO[1] output pin. MDIO Management Data Input/Output Pull Down This bidirectional data interface used access management registers within NetPHY-1LP device. This internal pull-down, therefore, requires pull-up resistor specified IEEE 802.3 when interfaced with MAC. Management Data Clock Input This clock sourced used synchronize MDIO data. INTR Interrupt Output, High Impedance
Input, Pull
input forces NetPHY-1LP device known reset state. chip also reset through internal power-on-reset Register PWRDN Power Down Input, Pull Down
HIGH input will power down device's analog modules reset device's digital circuits. However, device will still respond MDC/MDIO data. same power-down state also achieved through Register PHYAD[4:0] Address Input/Output, Pull
These pins allow configurable addresses. PHYAD will also determine scramble seed, which helps reduce when there multiple ports switching same time (repeater/switch applications). Each should either pulled ground resistor (set zero) left unconnected order achieve desired address. bypass mode, PHYAD[4:0] GPIO[1:0] serves 10BASE-T serial input output. GPIO[0] General Purpose Input/Output, Pull this pulled ground resistor, rising edge reset, device will operate 10BASE-T 7-wire (GPSI) mode. this left unconnected during rising edge reset, device will operate standard mode. After reset operation completed, this function input output (dependent value GPIO[0] Register Register HIGH, GPIO[0] input. input value GPIO[0] will reflected Register GPIO[0] Data. Register LOW, GPIO[0] output. value Register will reflected GPIO[0] output pin. GPIO[1] General Purpose Input/Output, Pull Down
This used signal interrupt MAC. will forced high (normally high impedance) signal interrupt depending upon value INTR_LEVL bit, Register events which trigger interrupt programmed Interrupt Control Register (Register 17). TECH_SEL[2:0] Technology Select Input, Pull Technology Select pins, conjunction with ANEGA pin, speed duplex configurations device rising edge reset. These capabilities reflected Register Register Table lists possible configurations device. input listed LOW, should pulled ground resistor rising edge reset. input listed HIGH, left unconnected. Note limitations changing speed, duplex, enabling autonegotiation bits Register based upon configuration device. ANEGA Auto-Negotiation Ability Input, Pull When this pulled ground resistor, rising edge reset, Auto-Negotiation disabled. When this left unconnected, rising edge reset, Auto-Negotiation enabled. Note that this acts conjunction with Tech_Sel[2:0] rising edge reset. Refer Table determine desired configuration device. RPTR Repeater Mode Input When this asserted high resistor, repeater mode will enabled. repeater mode, becomes receive activity. test function disabled 10BASE-T mode. Repeater mode also enabled Register This should tied ground resistor Repeater mode
this pulled HIGH resistor, rising edge reset, device will enabled with 1.25:1 transmit ratio transformer. this left unconnected during rising edge reset, device will enabled with transmit ratio transformer. After reset operation completed, this function input output (dependent value GPIO[1] Register Register HIGH, GPIO[1] input. input value GPIO[1] will reflected Register GPIO[1] Data. Register
Am79C874
disabled. This requires pull-down resistor when used applications. LEDSPD[1]/LEDTXA/CLK25EN 100BASE-X
Input, Output
Port Pins
LEDSPD[0]/LEDBTA/FX_SEL Speed Output
output indicates 10BASE-T, high indicates 100BASE-TX. When this pulled resistor, CLK25 sources clock signal which MAC. LEDDPX/LEDTXB Duplex Output
Active indicates 100BASE-TX, active high indicates 10BASE-T. 100BASE-FX mode selected this pulled resistor. LEDCOL/SCRAM_EN Collision Input/Output
Active indicates Full Duplex, high indicates Half Duplex.
This will toggle between high when there collision half-duplex mode. inactive full-duplex mode. When this pulled resistor, reset will disable scrambler/descrambler function. LEDRX/LEDSEL Receive Input/Output, Pull This will toggle between high when data received. When this pulled resistor, reset will enable advanced function. LEDTX/LEDBTB Transmit Output This will toggle between high when data transmitted. LEDLNK/LED_10LNK/LED_PCBSP_SD Link Output This active when link established. When operating 10BASE-T 7-wire serial mode, this indicates Link Status (Active High). This also active high when link established 100BASE-TX operation. When bypass mode, this used indicate Signal Detect (Active High) symbol interface.
Bias
IBREF Reference Bias Resistor Analog
This should tied external 10.0 (1%) resistor which should connected analog ground.
Power Ground
PLLVCC, OVDD1, OVDD2, VDD1, VDD2, CRV_VCC, ADPVCC, EQVCC, REFVCC, TVCC1, TVCC2 Power Pins Power Each these pins connected power supply. PLLGND, OGND1, OGND2, DGND1, DGND2, CRVGND, EQGND, REFGND, TGND1, TGND2 Ground Pins Power These pins ground power pins follows: PLLGND ground PLLVCC; OGND ground OVDD; DGND ground VDD; CRVGND ground CRV_VCC ADPVCC; EQGND ground EQVCC; REFGND ground REFVCC; TGND ground TVCC.
Am79C874
FUNCTIONAL DESCRIPTION
NetPHY-1LP device integrates 100BASE-X PCS, PMA, functions 10BASE-T Manchester ENDEC transceiver functions single chip Ethernet Mbps Mbps operations. performs 4B/5B, MLT3, NRZI, Manchester encoding decoding, clock data recovery, stream cipher scrambling/descrambling, adaptive equalization, line transmission, carrier sense link integrity monitor, Auto-Negotiation, management functions. provides IEEE 802.3u compatible Media Independent Interface (MII) communicate with Ethernet Media Access Controller (MAC). Selection Mbps Mbps operation based settings internal Serial Management Interface registers determined on-chip Auto-Negotiation logic. device operate either full-duplex mode half-duplex mode either Mbps Mbps. NetPHY-1LP device communicates with repeater, switch, device through either Media Independent Interface (MII) Mbps 7-wire (GPSI) interface. NetPHY-1LP device consists following functional blocks: Mode 7-Wire (GPSI) Mode 100BASE-X Block including: Transmit Process Receive Process 4B/5B Encoder Decoder Scrambler Descrambler Link Monitor MLT-3 Adaptive Equalizer Baseline Wander Compensation Clock/Data Recovery Clock Synthesizer 10BASE-T Block including: Transmit Process Receive Process Interface Status Collision Detect Jabber Reverse Polarity Detection Correction Auto-Negotiation miscellaneous functions including: Auto-Negotiation
Parallel Detection Far-End Fault (Heartbeat) Loopback Operation Reset Port Configuration Power Savings Mechanisms including: Selectable Transformer Power Down Unplugged Idle Wire Control Management
Modes Operation
MII/GPSI interface provides data path connection between NetPHY-1LP transceiver Media Access Controller (MAC), repeater, switch. MDIO pins responsible communication between NetPHY-1LP transceiver station management entity (STA). When device operating Shared mode, interface interoperable with interfaces compatible Clause IEE802.3 specification. Mode purpose mode provide simple, easy implement connection between Reconciliation layer PHY. designed make differences between various media transparent sublayer. consists nibble wide receive data bus, nibble wide transmit data bus, control signals facilitate data transfers between Reconciliation layer. (transmit data) nibble bits) data that driven reconciliation sublayer synchronously with respect TX_CLK. each TX_CLK period which TX_EN asserted, TXD[3:0] accepted transmission PHY. TX_CLK (transmit clock) output reconciliation sublayer continuous clock that provides timing reference transfer TX_EN, TXD, TX_ER signals. TX_EN (transmit enable) input from reconciliation sublayer indicate nibbles being presented transmission physical medium. TX_ER (transmit coding error) transitions synchronously with respect TX_CLK. TX_ER asserted more clock periods, TX_EN asserted, will emit more symbols that part valid data delimiter somewhere frame being transmitted.
Am79C874
(receive data) nibble bits) data that sampled reconciliation sublayer synchronously with respect RX_CLK. each RX_CLK period which RX_DV asserted, RXD[3:0] transferred from reconciliation sublayer. RX_CLK (receive clock) output reconciliation sublayer continuous clock that provides timing reference transfer RX_DV, RXD, RX_ER signals. RX_DV (receive data valid) input from indicate presenting recovered decoded nibbles reconciliation sublayer. interpret receive frame correctly reconciliation sublayer, RX_DV must encompass frame starting later than Start-of-Frame delimiter excluding End-Stream delimiter. RX_ER (receive error) transitions synchronously with respect RX_CLK. RX_ER will asserted more clock periods indicate reconciliation sublayer that error detected somewhere frame being received PHY. (carrier sense) asserted when either transmit receive medium non-idle deasserted when transmit receive medium idle. 7-Wire (GPSI) Mode 7-Wire (GPSI) mode uses existing pins, data transferred only TXD[0] RXD[0]. This mode used General Purpose Serial Interface (GPSI) configuration 10BASE-T. GPIO[0] rising edge reset, then GPSI mode selected. this configuration, TX_CLK runs MHz. pins that relate 7-wire (GPSI) mode shown Table unused input pins this mode should tied ground through resistor. RPTR must connected GND.
Name CRS/10CRS RX_ER 7-Wire (GPSI) RENA (see note below) used
Note: ends one-half times after last data bit. effect dribbling bits every packet. MACs truncate packets eliminate dribbling bits. only noticeable effect that errors recorded framing errors.
TECH_SEL[2:0] select desired 10BASET operation. example, auto-negotiate between Full Duplex Half Duplex Mbps, ANEG=1 TECH[2:0]=101.
100BASE-X Block
functions performed device include encoding 4-bit data (4B/5B), decoding received code groups (5B/4B), generating carrier sense collision detect indications, serialization code groups transmission, de-serialization serial data upon reception, mapping transmit, receive, carrier sense, collision interface, recovery clock from incoming data stream. offers stream cipher scrambling descrambling capability 100BASETX applications. NetPHY-1LP transceiver receives 4-bit (nibble) wide data across million nibbles second. 100BASE-TX applications, encodes scrambles data, serializes transmits MLT-3 data stream media isolation transformer. 100BASE-FX applications, encodes serializes data transmits Pseudo-ECL (PECL) data stream fiber optic transmitter. receive data path Mbps, NetPHY-1LP transceiver receives MLT-3 data stream from network. 100BASE-TX, then recovers clock from data stream, de-serializes data stream, descrambles/decodes data stream (5B/4B) before presenting interface. 100BASE-FX operation, NetPHY-1LP receives PECL data stream from fiber optic transceiver decodes that data stream. 100BASE-X block consists following subblocks: Transmit Process Receive Process 4B/5B Encoder Decoder Scrambler/Descrambler Link Monitor Fault Generation Detection CodeGroup Generator MLT-3 encoder/decoder with Adaptive Equalization
Table
Pins That Relate Wire (GPSI) Mode
7-Wire (GPSI) TCLK used TENA used RCLK used CLSN
Name TX_CLK/10TXCLK TXD[0]/10TXD TXD[3:1] TX_EN/10TXEN TX_ER RX_CLK/10RXCLK RXD[0] /10RXD RXD[3:1] COL/10COL
Am79C874
Baseline Restoration Clock Recovery Transmit Process transmit process generates code-groups based transmit control data signals MII. This process also responsible frame encapsulation into Physical Layer Stream, generating collision signal based whether carrier received simultaneously during transmission generating Carrier Sense Collision signals MII. transmit process implemented compliance with transmit state diagram defined Clause IEEE 802.3u specification. NetPHY-1LP device transmit function converts synchronous 4-bit data nibbles from 125Mbps differential serial data stream. entire operation synchronous 25-MHz clock 125-MHz clock. Both clocks generated on-chip clock synthesizer that locked external 25-MHz clock source. 100BASE-FX mode, NetPHY-1LP device will bypass scrambler 4B/5B encoder. output data NRZI PECL signal. This PECL level signal will then drive Fiber transmitter. Receive Process receive path includes receiver with adaptive equalization restoration, MLT-3-to-NRZI conversion, data clock recovery 125-MHz, NRZI-toNRZ conversion, Serial-to-Parallel conversion, descrambling, decoding. receiver circuit starts with bias differential inputs, follows with low-pass filter filter high-frequency noise from transmission channel media. energy detect circuit also added determine whether there signal energy media. This useful power-saving mode. (See description Power Savings Mechanisms section). amplification ratio slicer thresholds on-chip bandgap reference. 100BASE-FX mode, signal will received through PECL receiver, directly passed clock recovery data/clock extraction. mode, scrambler/descrambler cipher will bypassed. 4B/5B Encoder/Decoder Mbps process NetPHY-1LP device uses 4B/5B encoding scheme defined IEEE 802.3, Section This scheme converts between data encoded data media pins. encoder converts data 4B/5B code. also inserts stream boundary delimiters (/J/K/ /T/R/) beginning data stream appropriate. decoder converts between encoded data media pins data MII. also detects stream boundary delimiters help determine start packets. code-group mapping defined Table 4B/5B encoding bypassed when Register "1", PCSBP (pin strapped high. Scrambler/Descrambler 4B/5B encoded data repetitive patterns which result peaks spectrum large enough keep system from meeting standards regulatory agencies such FCC. peaks radiated signal reduced significantly scrambling transmitted signal. Scramblers output random generator data signal. resulting signal fewer repetitive data patterns. After reset, scrambler seed each port will address value help improve performance device. scrambled data stream descrambled receiver adding output another random generator. receiver's random generator uses same function transmitter's random generator. 100BASE-TX mode, 5-bit transmit data streams scrambled defined TP-PMD Stream Cipher function order reduce radiated emissions twisted pair cable. scrambler encodes plain text stream using stream periodic sequence 2047 bits generated recursive linear function: X[n] X[n-11] X[n-9] (modulo scrambler reduces peak emissions randomly spreading signal energy over transmit frequency range, thus eliminating peaks single frequency. When Register "1," data scrambling function disabled 5-bit data stream clocked directly device's sublayer. Link Monitor Signal levels detected through squelch detection circuit. signal detect (SD) circuit following equalizer asserted high whenever peak detector senses post-equalized signal with peak-to-ground voltage level larger than This approximately percent normal signal voltage level. addition, energy level must sustained longer than order signal detect asserted. gets de-asserted approximately after energy level consistently less than from peak-to-ground. link signal forced during local loopback operation (i.e., when Register Loopback asserted) forced high when remote loopback
Am79C874
taking place (i.e., when Register EN_RPBK, set). 100BASE-TX mode, when signal invalid signal detected receive pair, link monitor will enter "link fail" state where only scrambled idle code will transmitted. When valid signal detected minimum period time, link monitor will then enter link pass state when transmit receive functions entered. 100BASE-FX mode, external fiber-optic receiver performs signal energy detection function communicates this information directly NetPHY-1LP device through SDI+ pin.
Table
(TXD[3:0]) 0000 0001 0010 0011 0100 0101 0111 1000 1001 1010 1011 1100 1101 1110 1111 Undefined 0101 0101 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Name
Code-Group Mapping
Interpretation Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data IDLE; used inter-Stream fill code Start-of-Stream Delimiter, Part always used pairs with Start-of-Stream Delimiter, Part always used pairs with End-of-Stream Delimiter, Part always used pairs with End-of-Stream Delimiter, Part always used pairs with Transmit Error; used force signaling errors Invalid Code Invalid Code Invalid Code Invalid Code Invalid Code Invalid Code Invalid Code Invalid Code Invalid Code Invalid Code 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 00111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001
Code-Group
Am79C874
MLT-3 This block responsible converting NRZI data stream from block MLT-3 encoded data stream. effect MLT-3 reduction energy copper media cable) critical frequency range MHz. receive section this block responsible equalizing amplifying received data stream link detection. adaptive equalizer compensates amplitude phase distortion cable. MLT-3 tri-level signal. transitions between transition logical value lack transition logical value benefit MLT-3 that reduces maximum frequency over data line. rate data Mbps. maximum frequency (using NRZI) half 62.5 MHz. MLT-3 reduces maximum frequency 31.25 MHz. data signal stream following MLT-3 rules illustrated Figure data stream 1010101. pins connected media either transformer 1.25:1 transformer. 1.25:1 ratio provides transmit power savings over ratio. Refer Figure Adaptive Equalizer NetPHY-1LP device designed accommodate maximum cable length meters CAT-5 cable. meters CAT-5 cable attenuation MHz. typical attenuation meter cable worst case attenuation around 24-26 defined TP-PMD. amplitude phase distortion from cable will cause intersymbol interference (ISI) which makes clock data recovery impossible. adaptive equalizer made closely matching inverse transfer function twist-pair cable. This variable equalizer that changes equalizer frequency response accordance cable length. cable length estimated based comparisons incoming signal strength against some known cable characteristics. equalizer monotonical frequency response, tunes itself automatically cable length compensate amplitude phase distortion incurred from cable. Baseline Wander Compensation 100BASE-TX data stream always balanced. transformer blocks component incoming signal, thus offset differential receive inputs wander. shift signal levels, coupled with non-zero rise fall times serial stream cause pulse-width distortion. This creates jitter possible increase error rates. Therefore, restoration circuit needed compensate attenuation component. NetPHY-1LP device implements patentpending restoration circuit. Unlike traditional implementation, does need feedback information from slicer clock recovery circuit. This only simplifies system/circuit design, also eliminates random/systematic offset receive path. 10BASE-T 100Base-FX modes, baseline wander correction circuit required therefore will bypassed.
MLT-3
22236B-3
Figure
MLT-3 Waveform
drivers convert NRZI serial output MLT-3 format. receivers convert received MLT-3 signals NRZI. transmit receive signals will compliant with IEEE 802.3u, Section required signals (MLT-3) described detail ANSI X3.263:1995 TP-PMD Revision (1995). NetPHY-1LP device provides on-chip filtering. External filters required either transmit receive signals.
Am79C874
Isolation Transformer with common-mode chokes 1.25:1 RJ45 Connector SDI+
(Note
(Note
(chassis ground)
(chassis ground)
Notes: 22236B-4 isolation transformers include common-mode chokes. Consult magnetics vendors appropriate termaination schemes. Consult recommended board layout. isolation transformer used 1.25:1 isolation transformer used.
Figure Clock/Data Recovery
Termination BASE-TX 10BASE-T APLL switches back lock with TX_CLK, thus providing continuously running RX_CLK. recovered data converted from NRZI-to-NRZ then 5-bit parallel format. 5-bit parallel data necessarily aligned 4B/5B code-group's symbol boundary. data presented receive data register output, gated 25-MHz RX_CLK. Clock Synthesizer NetPHY-1LP device includes on-chip clock synthesizer that generates clock 100BASE-TX clock 10BASE-T Auto-Negotiation operations. Only external crystal signal source required reference clock. After power-on reset, clock synthesizer defaulted generating clock output will stay active until 100BASE-X operation mode selected.
equalized MLT-3 signal passes through slicer circuit which then converts NRZI format. NetPHY1LP device uses analog phase-locked loop (APLL) extract clock information from incoming NRZI data. extracted clock used re-time data stream data boundaries. transmit clock locked 25-MHz clock input, while receive clock locked incoming data streams. When initial lock achieved, APLL switches lock data stream, extracts clock from that framing recover data. recovered clock also used generate RX_CLK. APLL requires external components operation high noise immunity jitter. provides fast phase align (lock) data transition data/clock acquisition time after power-on less than transitions. APLL maintain lock run-lengths data bits absence signal transitions. When valid data present, i.e., when de-asserted,
Am79C874
10BASE-T Block
NetPHY-1LP transceiver incor porates 10BASE-T physical layer functions, including clock recovery (ENDEC), MAUs, transceiver functions. NetPHY-1LP transceiver receives 10-Mbps data from MAC, switch, repeater across million nibbles second (parallel), million bits second (serial). then Manchester encodes data before transmission network. Refer Figure 10BASE-T transmit receive data paths.
directly standard transformer. External filtering modules needed Twisted Pair Receive Process 10BASE-T mode, signal first passes through third order Elliptical filter, which filters noise from cable, board, transformer. This eliminates need 10BASE-T external filter. Manchester decoder Serial-to-Parallel converter then follow generate 4-bit nibble mode. ports differential twisted-pair receivers. When properly terminated, each port meets electrical requirements 10BASE-T receivers specified IEEE 802.3, Section 14.3.1.3. Each receiver internal filtering does require external filter modules common mode chokes. Signals appearing differential input pair routed internal decoder. receiver function meets propagation delays jitter requirements specified 10BASE-T standard. receiver squelch level drops half threshold value after unsquelch allow reception minimum amplitude signals mitigate carrier fade event worst case signal attenuation crosstalk noise conditions. Twisted Pair Interface Status NetPHY-1LP transceiver will power Link Fail state. Auto-Negotiation algorithm will apply allow enter Link Pass state. link-pulse detection circuit constantly monitors pins presence valid link pulses. Link Pass state, receive activity which passes pulse width/amplitude requirements inputs cause Control block assert Carrier Sense (CRS) signal interface. Collision Detect Function Simultaneous activity (presence valid data signals) from both internal encoder transmit function twisted pair pins constitutes collision, thereby causing Control block assert MII. Collisions cause Control block assert Carrier Sense (CRS) Collision (COL) signals MII. Link Fail state, this block would cause Control block de-assert Carrier Sense (CRS) Collision (COL). Jabber Function Jabber function inhibits 10BASE-T twisted pair transmit function NetPHY-1LP transceiver device circuits active excessive period (20-150 ms). This prevents port from disrupting network stuck-on faulty transmitter condition. maximum transmit time exceeded, data path through 10BASE-T transmitter circuitry disabled (although Link Test pulses will continue
Clock
Data
Clock
Data
Manchester Encoder
Manchester Decoder
Loopback (Register
Squelch Circuit
Driver
Driver
22235B-5
Figure
10BASE-T Transmit /Receive Data Paths
Twisted Pair Transmit Process 10BASE-T mode, Manchester code will generated 10BASE-T core logic, which will then synthesized through output waveshaping driver. This will help reduce emission, eliminating need external filter. Data transmission over 10BASE-T medium requires integrated 10BASE-T uses differential driver circuitry pins. differential twisted-pair driver. When properly terminated, meets transmitter electrical requirements 10BASE-T transmitters specified IEEE 802.3, Section 14.3.1.2. load twisted pair cable that meets IEEE 802.3, Section 14.4. signal filtered chip reduce harmonic content Section 14.3.2.1 (10BASE-T). Since filtering performed silicon, connected
Am79C874
sent). Control block also asserts sets Jabber Detect Register Once internal transmit data stream from MENDEC stops, unjab time 250-750 will elapse before this block causes Control block de-assert indication re-enable transmit circuitry. When jabber detected, this block causes control block assert allows Control block assert de-assert indicate current state pair. there receive activity RX±, this block causes Control block assert only MII. there activity, this block causes Control block assert both MII. Jabber function disabled setting Register Reverse Polarity Detection Correction Proper 10BASE-T receiver operation requires that differential input signal correct polarity. That line connected input pin, line connected input pin. Improper setup external wiring cause polarity reversed. NetPHY-1LP receiver ability detect polarity incoming signal compensate Thus, proper signal will appear regardless polarity input signals. internal polarity detection correction circuitry during reception normal link pulses (NLP) packets. receiver detects polarity input signal first NLP. locks polarity correction circuitry after reception consecutive packets. state polarity correction circuitry locked long link established. NetPHY-1LP device will automatically choose mode operation advertising abilities comparing them with those received from link partner whenever Auto-Negotiation enabled. contents Register sent link partner during Auto-Negotiation, coded Fast Link Pulse (FLP). Register bits reflects state TECH[2:0] pins after reset. TECH[2:0]=111, then Register bits 8:5=1111. TECH[2:0]=001, then Register bits 8:5=0001.
Note: After reset, software change these bits from back from Therefore, hardware priority over software.
When Auto-Negotiation enabled, NetPHY-1LP device sends during following conditions: power link loss, restart command. same time, device monitors incoming data determine mode operation. When device receives burst FLPs from link partner with three identical link code words (ignoring acknowledge bit), stores these code words Register waits next three identical code words. Once device detects second code word, will configure itself highest technology that common both ends. technology priorities are: 100BASE-TX, full-duplex, 100BASE-TX, half-duplex, 10BASET, full-duplex, 10BASE-T half-duplex. Once Auto-Negotiation complete, Register bits 14:11 will reflect actual speed duplex that were chosen. Parallel Detection parallel detection circuit enabled soon either 10BASE-T idle 100BASE-TX idle detected. mode operation gets configured based technology incoming signal. NetPHY-1LP device also check 10BASE-T 100BASE-TX idle symbol. either detected, device automatically configures match detected operating speed half-duplex mode. This ability allows device communicate with legacy 10BASE-T 100BASE-TX systems.
Auto-Negotiation Miscellaneous Functions
Auto-Negotiation NetPHY-1LP device ability negotiate mode operation over twisted pair using AutoNegotiation mechanism defined Clause IEEE 802.3u specification. Auto-Negotiation enabled disabled hardware (ANEGA, software (MII Register control (see Table
Am79C874
Table
ANEGA Tech[2] Tech[1] Tech[0] (Hardwired Board) (Note (Note (Note (Note (Note (Note (Note (Note (Note
Speed Duplex Capabilities
Speed (Note Duplex (Note (Note (Note (Note (Note (Note (Note (Note (Note (Note ANEG-EN Capabilities/ANEG (Note (Note (Note (Note (Note (Note (Note (Note Capabilities 10HD 100HD 100HD Capabilities 10FD 100FD 100FD Capabilities, ANEG 10HD, ANEG 100HD, ANEG 100HD, 10HD, ANEG Capabilities, ANEG 10FD/HD, ANEG 100FD/HD, ANEG Capabilities, ANEG (Changeable Register
Notes: Register (speed duplex bits) must achieve link. advertised abilities Register cannot exceed abilities Register Auto-Negotiation should always remain enabled. When Auto-Negotiation enabled, these bits written will ignored PHY.
Far-End Fault Auto-Negotiation provides remote fault capability detecting asymmetric link failure. Since 100Base-FX systems Auto-Negotiation, alternative, in-band signaling scheme, Far-End Fault used signal remote fault conditions. Far-End Fault stream consecutive followed logic This pattern repeated three times. Far-End Fault will signaled under three conditions: when activity received from link partner, when clock recovery circuit detects signal error lock error, when management entity sets transmit (MII Register Far-End Fault mechanism defaults enable 100BASE-FX mode disable 100BASE-TX 10BASE-T modes, controlled software after reset. (Heartbeat) When test enabled, signal with time pulse will issued after each transmitting packet. enabled disabled Register
Loopback Operation local loopback remote loopback provided testing. They enabled writing either Register (LPBK) Register (EN_RPBK). local loopback routes transmitted data output NRZ-to-NRZI conversion module back receiving path's clock data recovery module connection bits symbol format. This loopback used check connections 5-bit symbol side operation analog phase locked loop. local loopback, output forced logic outputs tristated. remote loopback, incoming data passes through equalizer clock recovery, then loop back NRZI/ MLT3 conversion module driver. This loopback used check device's connection media side operation internal adaptive equalizer, phase-locked loop, digital wave shape synthesizer. During remote loopback, signal detect (SD) output forced logic zero.
Am79C874
Reset NetPHY-1LP device reset three following ways: During initial power (with internal power reset circuit). hardware reset. logic signal pulse width applied pin. software reset. Write Register polarity drivers (Active-LOW ActiveHIGH) rising edge RST. rising edge RST, becomes active-HIGH driver. HIGH rising edge RST, becomes active-LOW driver. Proper configuration requires external pull-up pulldown resistors. corresponding used, must terminated resistor. resistor value critical range corresponding used, terminating resistor must placed parallel with LED. suggested connection diagram simplifying board design shown Figure value series resistor (RL) should selected ensure sufficient illumination LED. dependent rating LED.
Port Configuration
NetPHY-1LP device several pins that used both device configuration drivers. These pins configuration device rising edge thereafter indicate state respective port. Table
Table
MODE Link 10BT Half Duplex 10BT Half Activity 10BT Full Duplex 10BT Full Activity 100BT Half Duplex 100BT Half Activity 100BT Full Duplex 100BT Full Activity LEDBTX/ LEDBTA (Pin Flash (Note
Selections
LEDBT/ LEDTXA (Pin Flash (Note LEDFDX/ LEDTXB (Pin Flash (Note
LEDTX/ LEDBTB (Pin Flash (Note
Notes: flashes activity. flashes activity.
LEDBTA Dual-Color LEDBTB 10Base-T Indicator LEDTXB LEDTXA
100Base-TX Indicator
22235B-6
Figure
Bi-Color Connection Diagram
Am79C874
Power Savings Mechanisms
power consumption device significantly reduced built-in power down features. Separate power supply lines also used power 10BASE-T circuitry 100BASE-TX circuitry. Therefore, modes operation turnedon turned-off independently. Whenever NetPHY-1LP device operate 100BASE-TX mode, 10BASE-T circuitry powered down, when 10BASE-T mode, 100BASE-TX circuitry powered down. NetPHY-1LP device offers following power management: Selectable Transformer, Power Down, Unplugged, Idle. Selectable Transformer outputs drive either transformer 1.25:1 transformer. latter used reduce transmit power further. current pins ratio transformer MLT-3 10BASE-T. Using 1.25:1 ratio reduces current MLT-3 10BASE-T. cost using 1.25:1 option impedance coupling. reflected capacitance increased square ratio (1.252 1.56). Thus, reflected capacitance media side roughly times
capacitance board. Extra care layout control capacitance board required. Power Down Most NetPHY-1LP device disabled Power Down Register Setting this Register port will power down entire device with exception MDIO/MDC management circuitry. Unplugged output driver limits drive capability receiver detect link partner within seconds. This prevents "wasted" power. receiver detects absence link partner, transmitter limited transmitting normal link pulses. energy detected receiver enables full transmit receive capabilities. power savings most notable when port unconnected ports. Typical power becomes Idle Wire This achieved writing Register During this mode, there data other than idles coming receive clock (RX_CLK) will turn save power attached controller. RX_CLK will resume operation clock period prior assertion RX_DV. receive clock will again shut clock cycles after RX_DV gets deasserted.
Am79C874
CONTROL MANAGEMENT BLOCK (PCM BLOCK) Register Administration 100BASE-X Device
management interface specified Clause IEEE 802.3u standard provides simple wire, serial interface connect management entity managed purpose controlling gathering status information. lines Management Data Input/Output (MDIO), Table
READ WRITE
Management Data Clock (MDC). station management entity which attached multiple entities must have prior knowledge appropriate address each entity.
Description Methodology
management interface physically transports management information across MII. information encapsulated frame format specified Clause IEEE 802.3u draft standard shown Table
Clause Management Frame Format
PHYAD AAAAA AAAAA REGADD RRRRR RRRRR DATA IDLE
PHYAD field, which five bits wide, allows unique addresses. managed layer device that connected station management entity interface respond transactions
addressed address. station management entity attached multiple PHYs, such managed 802.3 Repeater Ethernet switch, required have prior knowledge appropriate address.
Table
READ WRITE
Address Setting Frame Structure
REGADD RRRRR RRRRR DATA XXXXXXXXXPPAAAAA XXXXXXXXXPPAAAAA IDLE
PHYAD 00000 00000
MDIO (STA)
MDIO (PHY)
Idle
Idle
Start
Opcode (Read)
Address 16h, Port
Register Address Status,
Register Data
Read Operation
MDIO (STA)
Idle
Idle
Start
Opcode (Write)
Address 16h, Port
Register Address Control,
Register Data
Write Operation
22236B-7
Figure
Management Read Write Operations
Am79C874
Management Frame Handling management block device recognize management frames without preambles (preamble suppression). However, receives management frame, will into Management Frame state. will stay this state will respond management frame without preambles until frame with full 32-bit preamble received, then will return normal operation. management frame frame that does comply with IEEE standard specification. with less than 32-bit preamble, with illegal field, etc. However, frame with more than preamble bits considered good frame.
Serial Management Registers
detailed definition each Serial Management register follows. mode legend shown below.
Table
Type
Legend Register Tables
Description
Readable writable Self Clearing Latch until clear Read Only Cleared read operation Latch high until clear
REGISTER DESCRIPTIONS
following registers supported (register numbers decimal) Table Physical Address using pins defined PHYAD[4:0]. These input signals strapped externally sampled when reset goes high. PHYAD pins reprogrammed software. Table
Register Address Decimal) 8-15 25-31
Register Summary
Description Management Control Register Management Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Next Page Advertisement Register Reserved Miscellaneous Features Register Interrupt Control/Status Register Diagnostic Register Power Management Loopback Register Reserved Mode Control Register Reserved Disconnect Counter Receive Error Counter Reserved
Am79C874
Management Control Register (Register Table
Name reset. Reset Normal operation. This self-clearing. Loopback Enable loopback mode. This will loopback RXD, thus will ignore activity cable media. Disable Loopback mode. Normal operation. Speed Select Mbps, Mbps. This will ignored Auto Negotiation enabled (0.12 Refer Table determine when this changed. Enable auto-negotiate process (overrides 0.13 0.8). Auto-Neg Enable Disable auto-negotiate process. Mode selection controlled 0.8, 0.13 through TECH[2:0] pins. Refer Table determine when this changed. Power down. NetPHY-1LP device will shut blocks except MDIO/MDC interface. Setting PWRDN high will achieve same result. Normal operation. Electrically isolate from MII. However, still able respond MDC/MDIO. default value this depends ISODEF pin, i.e., ISODEF=1, will ISODEF=0, will Normal operation. Restart AutoNegotiation Duplex Mode Restart Auto-Negotiation process. Normal operation. Full duplex, Half duplex. Refer Table determine when this changed. Enable collision test, which issues signal response assertion TX_EN signal. Collision test disabled PCSBP high. Collision test enabled regardless duplex mode. disable test. Reserved Write ignore when read. RW/SC TECH[2:0] pins ISODEF ANEGA TECH[2:0] pins RW/SC
Management Control Register (Register
Description Read/ Write Default
Power Down
Isolate
Collision Test
Am79C874
Management Status Register (Register Table
Name 100BASE-T4 100BASE-T4 able. 100BASE-T4 able.
Management Status Register (Register
Description Read/ Write Default TECH[2:0] pins TECH[2:0] pins TECH[2:0] pins TECH[2:0] pins
100BASE-TX Full 100BASE-TX Full Duplex. Duplex 100BASE-TX Full Duplex ability. 100BASE-TX Half 100BASE-TX Half Duplex. Duplex half-duplex ability. 10BASE-T Full Duplex 10BASE-T Half Duplex Reserved Auto-Negotiation Complete 10BASE-T Full Duplex. 10BASE-T Full Duplex ability. 10BASE-T Half Duplex. 10BASE-T ability. Ignore when read. Auto-Negotiation process completed. Registers valid after this set. Auto-Negotiation process completed. Remote fault condition detected. remote fault. This will remain until read management interface.
10:6
Remote Fault
RO/LH
Auto-Negotiation Ability
Able perform Auto-Negotiation function; value determined ANEGA pin. Unable perform Auto-Negotiation function. Link established; however, NetPHY-1LP device link fails, this will cleared remain cleared until Register read management interface. link down. Jabber condition detected. Jabber condition detected. Extended register capable. This tied permanently one.
ANEGA
Link Status
RO/LL
Jabber Detect Extended Capability
RO/LH
Identifier Register (Register Table
Name
Identifier Register (Register
Description Read/ Write Default Xxxx(H)
Composed through 18th bits Organizationally Unique Identifier (OUI), respectively.
Am79C874
Identifier Register (Register Table
15:10 Model Number Revision Number Name
Identifier Register (Register
Description Read/ Write Default Xxxxx 010001 0001
Assigned 19th through 24th bits OUI. Six-bit manufacturer's model number; encoded 010001. Four-bit manufacturer's revision number; 0001 stands Rev. etc.
Auto-Negotiation Advertisement Register (Register Table
12:10 Name Next Page Acknowledge Remote Fault Reserved 100BASE-T4 100BASE-TX Full Duplex Next Page enabled. Next Page disabled. This will internally after receiving three consecutive consistent bursts. Remote fault supported. remote fault. future technology. NetPHY-1LP device does support 100BASE-T4 function, i.e., this ties zero. 100BASE-TX Full Duplex. 100BASE-TX Full Duplex ability. Default Register 1.14. 100BASE-TX Half Duplex. 100BASE-TX Half Duplex 100BASE-TX Half Duplex capability. Default Register 1.13 Mbps Full Duplex. 10BASE-T Full Duplex Mbps Full Duplex capability. Default Register 1.12. Mbps Half Duplex. 10BASE-T Half Duplex Selector Field Mbps Half DuplexHalf Duplex capability Default Register 1.11. [00001] IEEE 802.3.
Auto-Negotiation Advertisement Register (Register
Description Read/ Write Default TECH [2:0] pins TECH[2:0] pins TECH[2:0] pins TECH[2:0] pins 00001
Am79C874
Auto-Negotiation Link Partner Ability Register Base Page Format (Register Table
12:10
Auto-Negotiation Link Partner Ability Register Base Page Format (Register
Name Next Page Acknowledge Remote Fault Reserved 100BASE-T4 100BASE-TX Full Duplex 100BASE-TX Half Duplex 10BASE-T Full Duplex 10BASE-T Half Duplex Selector Field Description Next Page Requested Link Partner Next Page Requested Link Partner Acknowledgement Link Partner Acknowledgement Link Partner Remote Fault Request Link Partner Remote Fault Request Reserved Future Technology Remote Partner 100BASE-T4 Capable Remote Partner 100BASE-T4 Capable Link Partner capable 100BASE-TX Full Duplex Link Partner Capable 100BASE-TX Full Duplex Link Partner Capable 100BASE-TX Half Duplex Link Partner Capable 100BASE-TX Half Duplex Link Partner capable 10BASE-T Full Duplex Link Partner Capable 10BASE-T Full Duplex Link Partner capable 10BASE-T Half Duplex Link Partner Capable 10BASE-T Half Duplex Link Partner Selector Field Read/ Write Default
Auto-Negotiation Link Partner Ability Register Next Page Format (Register Table
10:0
Auto-Negotiation LInk Partner Ability Register Next Page Format (Register
Name Next Page Acknowledge Message Page Acknowledge Toggle Message Field Description Next Page Requested Link Partner Next Page Requested Link Partner Acknowledgement Link Partner Acknowledgement Link Partner message Page Request Link partner Message Page Request Link Partner Comply Next Page Request Link Partner cannot Comply Next Page Request Link Partner Toggle Link Partner's Message Code Read/ Write Default
Am79C874
Auto-Negotiation Expansion Register (Register Table
15:5 Name Reserved Parallel Detection Fault Link Partner Next Page Able Next Page Able Page Received Ignore when read. Fault detected parallel detection logic. This fault more than technology detecting concurrent link conditions. This cleared upon reading this register. fault detected parallel detection logic. Link partner supports next page function. Link partner does support next page function. Next page supported. This permanently tied This when link code word been received into Auto-Negotiation Link Partner Ability Register. This cleared upon reading this register. RO/LH
Auto-Negotiation Expansion Register (Register
Description Read/ Write Default
RO/LH
Link Partner Auto- Link partner auto-negotiation able. Negotiation Able Link partner auto-negotiation able.
Am79C874
Auto-Negotiation Next Page Advertisement Register (Register Table
Reserved Name Next page indication: Another Next Page desired. other Next Page Transfer desired. Ignore when read. Message page: Message page. Un-formatted page. Acknowledge ACK2 Will comply with message. Cannot comply with message. Toggle: 10:0 TOG_TX CODE Previous value transmitted link code word equals Previous value transmitted link code word equals Message/Un-formatted Code Field.
Auto-Negotiation Next Page Advertisement Register (Register
Description Read/ Write Default
Reserved Registers (Registers 8-15, 25-31) NetPHY-1LP device contains reserved registers addresses 8-15, 25-31. These registers should ignored when read should witten time.
Am79C874
Miscellaneous Features Register (Register Table
Name Repeater
Miscellaneous Features Register (Register
Description Read/ Write Default RPTR
Repeater mode, full-duplex inactive, only responds receive activity. test function also disabled. INTR will active high this register requires external pull-down resistor. INTR will active this register requires external pull-up resistor. Write ignore when read. Disable 10BASE-T testing. Enable 10BASE-T testing. pulse generated following completion packet transmission. Enable normal loopback 10BASE-T mode. Disable normal loopback 10BASE-T mode. When GPIO_1 this reflects value GPIO[1] pin. When GPIO_1 value this will presented GPIO[1] pin. GPIO[1] input. GPIO[1] output. When GPIO_0 this reflects value GPIO[0] pin. When GPIO[0] value this will presented GPIO[0] pin. GPIO[0] input. GPIO[0] output. Disable auto polarity detection/correction. Enable auto polarity detection/correction. When Register 16.5 this will reverse polarity detected media. Otherwise, will
INTR_LEVL
13:12
Reserved Test Inhibit 10BASE-T Loopback GPIO_1 Data
GPIO_1
GPIO_0 Data
GPIO_0 Auto polarity Disable
Reverse Polarity
When Register 16.5 writing this will reverse polarity transmitter. Note: Reverse polarity detected either through eight inverted NLPs through burst inverted FLP.
Reserved
Write ignore when read. Writing this will shut RX_CLK when incoming data present. RX_CLK will resume activity clock cycle prior RX_DV going high, shut clock cycles after RX_DV goes low. loopback bypass modes, writing this does affect RX_CLK. Receive clock will constantly active.
Receive Clock Control
Am79C874
Interrupt Control/Status Register (Register Table
Name Jabber_IE Rx_Er_IE Page_Rx_IE PD_Fault_IE LP_Ack_IE Link_Not_OK_ R_Fault_IE ANeg_Comp_IE Jabber_Int Rx_Er_Int Page_Rx_Int PD_Fault_Int LP_Ack_Int Link_Not_OK R_Fault_Int A_Neg_Comp Jabber Interrupt Enable Receive Error Interrupt Enable Page Received Interrupt Enable Parallel Detection Fault Interrupt Enable Link Partner Acknowledge Interrupt Enable Link Status Interrupt Enable Remote Fault Interrupt Enable Auto-Negotiation Complete Interrupt Enable This when jabber event detected. This when RX_ER transitions high. This when page received from link partner during Auto-Negotiation. This parallel detection fault. This when with acknowledge received. This when link status switches from status Not-OK (Fail Ready). This when remote fault detected. This when Auto-Negotiation complete.
Interrupt Control/Status Register (Register
Description Read/ Write Default
Note: Interrupt Source Table assignments.
Diagnostic Register (Register Table
15:12 Name Reserved DPLX Speed Ignore when read. This indicates result Auto-Negotiation duplex arbitration. This indicates result Auto-Negotiation data speed arbitration. 10BASE-T mode, this indicates that Manchester data been detected. 100BASE-T mode, indicates that valid signal been received necessarily locked onto. Indicates receive locked onto received signal selected speed operation (10BASE-T 100BASE-TX). This whenever cycle-slip occurs remains until read. Ignore when read.
Diagnostic Register (Register
Description Read/ Write Default
RX_PASS
RX_LOCK
RO/RC
Reserved
Am79C874
Power/Loopback Register (Register Table
14:7 Name Reserved Transmit transformer ratio selection: 1.25:1 TP125 default value this controlled reset-read value Enable advanced power saving mode. Power Mode Disable advanced power saving mode
Power/Loopback Register (Register
Description Read/ Write Default
Note: Under normal operating conditions, this mode should never disable.
Test Loopback Digital loopback LP_LPBK Link Integrity Test Reduce Timer Enable test loopback. Data will transmitted from interface clock recovery loopback received data. Enable loopback. Normal operation. Enable link pulse loopback. Normal operation. Auto-Negotiation test mode, send instead order test receive integrity. Sending Auto-Negotiation test mode. Reduce time constant Auto-Negotiation timer. Normal operation.
Am79C874
Mode Control Register (Register Table
Name Reserved
Force_Link_10
Mode Control Register (Register
Description Read/ Write Default
Force link without checking NLP. Normal Operation. Ignore link 100BASE-TX transmit data. AutoNegotiation must disabled this time (pin tied low). Normal Operation. Disable Jabber function PHY. Enable Jabber function PHY. Enable 7-wire interface 10BASE-T operation. This useful only when chip bypass mode. Normal operation. Activity only responds receive operation. Activity responds receive transmit operations Half Duplex. responds receive activity Full Duplex operation. This should ignored when Register during repeater mode operation. Select NetPHY-1LP device configuration.
Force_Link_100
Jabber Disable
7_Wire_Enable
CONF_ALED
LED_SEL
configuration which compatible with TSC78Q2120. Enable far-end-fault generation detection function.
TECH[2:0], FX_SEL, ANEGA pins
FEF_DISABLE
Disable far-end-fault. This should ignored when mode disabled.
Force Transmit
This force transmit Fault (FEF) pattern.
RX_ER_CNT Full When Receive Error Counter full, this will Disable RX_ER_CNT DIS_WDT EN_RPBK Disable Receive Error Counter. Enable Receive Error Counter. Disable watchdog timer decipher. Enable watchdog timer. Enable remote loopback. Disable remote loopback. Disable data scrambling. Enable data scrambling. When mode selected, this will forced Bypass PCS. Enable mode selected. Disable mode.
DIS_SCRM
PCSBP
FX_SEL
PCSBP FX_SEL
Am79C874
Disconnect Counter Register (Register Table
15:0 Name DLOCK drop counter
Disconnect Counter (Register
Description Read/ Write Default 0000
Count lock drop events
Receive Error Counter Register (Register Table
15:0 Name RX_ER counter
Receive Error Counter Register (Register
Description Read/ Write Default 0000
Count receive error events
Am79C874
ABSOLUTE MAXIMUM RATINGS
Storage Temperature .-65°C +150°C Ambient Temperature Under Bias .-65°C +150°C Supply Voltage -0.3 +3.9 Voltage Applied input pin. -0.5 +6.0
Operating Ranges Operating Temperature (TA) +70°C Supply Voltage (all DVDD) +3.3
Operating ranges define those limits between which functionality device guaranteed.
Stresses above those listed under Absolute Maximum Ratings cause manent device failure. Functionality above these limits implied. Exposure absolute maximum ratings extended periods affect device reliability.
CHARACTERISTICS
Symbol VCMP VIDIFFP VOHP VOLP VSDA VSDD VTXOUT VTXOS VTXR VRXCM VTSQ VTHS Parameter Description Input Voltage Input HIGH Voltage Output Voltage Output HIGH Voltage Input Common-Mode Voltage PECL (Note Differential Input Voltage PECL (Note Output HIGH Voltage PECL (Note Output Voltage PECL (Note Signal Detect Assertion Threshold (Note Signal Detect Deassertion Threshold (Note Input Current Input HIGH Current Differential Output Voltage (Note Differential Output Overshoot (Note Differential Output Voltage Ratio (Note5 Note Differential Receiver Input Common Mode Voltage 10BASE-T Squelch Threshold Sinusoid MHz<f<10 Maximum PECL Load PECL Load MLT-3/10BASE-T Test Load MLT-3/10BASE-T Test Load Maximum Maximum MLT-3/10BASE-T Test Load MLT-3/10BASE-T Test Load MLT-3/10BASE-T Test Load 0.98 Maximum -IOL/2 1.025 1.81 1,100 0.60 1.62 1000 -200 -100 1050 0.05 VTXOUT 1.02 Test Conditions Minimum Maximum Units
Post-Squelch Differential Sinusoid MHz<f<10 Threshold 10BASE-T 10BASE-T Differential Switching Threshold Sinusoid MHz<f<10
VRXDTH
Am79C874
Symbol VTX10NE Parameter Description 10BASE-T Near-End Peak Differential Voltage (Note IOLL IOHM Output Current (Note Output Current Output HIGH Current Output HIGH Current Port (Note Output Leakage Current (Note Input Leakage Current VOUT 10BASE-T, idle 10BASE-T, normal activity Power Supply Current 10BASE-T, peak 100BASE-TX 100BASE-TX, cable Power down 10BASE-T, idle 10BASE-T, normal activity (75%) (Note Power Consumption 10BASE-T, peak (100%) 100BASE-TX (Idle 100%) 100BASE-TX, cable Power down -4.0 -IOL/2 Test Conditions MLT-3/10BASE-T Test Load Minimum Maximum Units
Notes: Applies FXR+, FXR-, SDI+ inputs only. Valid only when PECL mode. Applies inputs when MLT-3 mode only. input guaranteed assert internal signal detect valid peak-to-peak input signal greater than VSDA MIN. Applies inputs when MLT-3 mode only. input guaranteed de-assert internal signal peak peak signal less than VSDD MAX. Applies FXT+ FXT- outputs only. Valid only when PECL mode. Applies differential outputs only. Valid only when MLT-3 mode. VTXR ratio magnitude positive direction magnitude negative direction. Only valid output when 10BASE-T mode. IOLL value applies pins. Applies output pins port. applies high-impedance output pins bi-directional pins. activity means data. 100% activity means minimum IPG.
Am79C874
VSDD
VSDA
22236B-8
Figure
MLT-3 Receive Input
49.9
Isolation Transformer TX0.1 0.01 Chassis Ground
49.9
22236B-9
Figure
MLT-3 10BASE-T Test Load with Transformer Ratio
78.1
Isolation Transformer 1:25:1 TX0.1 0.01 Chassis Ground
78.1
22236B-10
Figure
MLT-3 10BASE-T Test Load with 1.25:1 Transformer Ratio
Am79C874
VTXOS
+VTXOUT
VTXOUT
-VTXOUT
22236B-11
Figure Near-End 100BASE-TX Waveform
VTX10NE
10BASE-T
22236B-12
Figure
10BASE-T Waveform With Transformer Ratio
82.5
22236B-13
Figure
PECL Test Load
Am79C874
SWITCHING CHARACTERISTICS System Clock Signal
Symbol tCLK tCLKH tCLKL tCLR tCLF TX_CLK Period TX_CLK Width HIGH TX_CLK Width TX_CLK Rise Time TX_CLK Fall Time Parameter Description Min. 39.998 Max. 40.002 Unit
tCLK tCLKH TX_CLK tCLKL tCLF tCLR
22236B-14
Figure
Clock Signal
MLT-3 Signals
Symbol tTXR tTXF tTXRFS tTXDCD tTXJ Parameter Description Rise Time MLT-3 Signal Fall Time MLT-3 Signal Rise Time Fall Time Symmetry MLT-3 Signal Duty Cycle Distortion Peak Peak Transmit Jitter Using Scrambled Idle Signals Min. Max. Unit
tTXR
tTXF
tXTDCD
tXTDCD
22236B-15
Figure
MLT-3 Test Waveform
Am79C874
Management Signals
Symbol tMDPER tMDWH tMDWL tMDPD tMDS tMDH Period Pulse Width HIGH Pulse Width MDIO Delay From Rising Edge MDIO Setup Time Rising Edge MDIO Hold Time From Rising Edge Parameter Description Min. Max. Unit
tMDPER tMDWH tMDPD MDIO mdio_tx.vsd tMDWL
22236B-16
Figure Management Transmit Timing
tMDS MDIO tMDH
22236B-17
Figure Management Receive Timing
Am79C874
Signals
Mbps Transmit Timing
Symbol tMTS100 tMTH100 tMTEJ100 tMTECRH100 tMTECOH100 tMTDCRL100 tMTDCOL100 tMTIDLE100
Parameter Description TX_ER,TX_EN, TXD[3:0] Setup Time TX_CLK Rising Edge TX_ER, TX_EN, TXD[3:0] Hold time From TX_CLK Rising Edge Transmit Latency TX_EN Sampled TX_CLK First Assert From TX_EN Sampled HIGH Assert From TX_EN Sampled HIGH De-assert From TX_EN Sampled De-assert From TX_EN Sampled Required De-assertion Time Between Packets
Min.
Max.
Unit
tMTP100 tMTWH100 tMTWL100
TX_CLK tMTS100
TX_EN tMTECRL100
tMTECOL100
tMTS100 TX_ER TXD[3:0] tMTEJ100 tMTH100
22236B-18
Figure
Mbps Transmit Start Packet Timing
Am79C874
TX_CLK tMTIDLE100 TX_EN tMTDCRL100
tMTDCOL100
22236B-19
Figure
Mbps Transmit Packet Timing
Am79C874
Mbps Receive Timing
Symbol tMRP100 tMRWH100 tMRWL100 tMRJCRH100 tMRJCOH100 tMRCE100 tMRERD100 tMRRDC100 tMRCRD100 tMRTCRL100 tMRTCOL100 tMRERL100 tMRER100 tMRCNE100 Period
Parameter Description Pulse Width HIGH Pulse Width HIGH After First HIGH After First Required Delay RX_EN After Rising Edge RXD[3:0], RX_DV, RX_ER Active After Rising Edge RX_EN RXD[3:0], RX_DV, RX_ER Valid Prior Rising Edge RX_EN RXD[3:0], RX_DV, RX_ER Valid After Rising Edge RX_EN First First First RXD[3:0], RX_DV, RX_CLK, De-Asserting (Going LOW) RX_EN RXD[3:0], RX_DV, RX_ER, HighImpedance RX_EN deasserted.
Min. 39.998
Max. 40.002
Unit
tMRJCRH100 tMRJCOH100
tMRCE100 RX_EN tMRP100 tMRERD100 RX_CLK tMRRDC100 RXD[3:0] RX_DV RX_ER tMRCRD100 tMRWH100 tMRWL100
22236B-20
Figure
Mbps Receive Start Packet Timing
Am79C874
tMRTCRL100 tMRTCOL100
/T/R/
tMRCNE100
RX_EN tMRERZ100 RX_CLK tMRERL100 RXD[3:0] RX_DV RX_ER
22236B-21
Figure
Mbps Receive Packet Timing
Am79C874
Mbps Transmit Timing
Symbol tMTS10 tMTH10 tMTEP10 tMTECRH10 tMTECOH10 tMTDCRL10 tMTDCOL10 tMTIDLE10 Parameter Description TX_EN, TXD10[3:0] Setup Time RX_CLK Rising Edge TX_EN, TXD10[3:0] Hold time From RX_CLK Rising Edge Transmit Latency TX_EN Sampled RX_CLK Start Packet Assert from TX_EN Sampled HIGH Assert from TX_EN Sampled HIGH De-assert From TX_EN Sampled De-assert From TX_EN Sampled Required De-assertion Time Between Packets Min. Max. Unit
RX_CLK tMTS10 TX_EN tMTS10 TXD[3:0] tMTECRH10 tMTECLH10 tMTEP10 tMTH100
22235B-22
Figure
Mbps Transmit Start Packet Timing
RX_CLK tMTIDLE10 TX_EN tMTDCRL10 tMTDCOL10
22235B-23
Figure
Mbps Transmit Packet Timing
Am79C874
Mbps Receive Timing
Symbol tMRP10 tMRWH10 tMRWL10 tMJCRH10 tMJCOH10 tMRCE10 tMRERD10 tMRRC10 tMRCRD10 tMRECRL10 tMRECOL10 tMRERL100 tMRERZ10 RX_CLK Period
Parameter Description RX_CLK Pulse Width HIGH RX_CLK Pulse Width HIGH After Start Packet HIGH After Start Packet Required Delay RX_EN After Rising Edge RXD[3:0], RX_DV, RX_ER Active After Rising Edge RX_EN RXD[3:0], RX_DV, RX_ER Valid Prior Rising RX_CLK10 RXD[3:0], RX_DV, RX_ER Valid After Rising Edge RX_CLK Packet Packet Packet RXD[3:0], RX_DV, RX_ER, RX_CLK De-Asserting (Going LOW) RX_EN RXD[3:0], RX_DV, RX_ER, RX_CLK High Impedance
Min. 399.98
Max. 400.02
Unit
tMRPCRH10 tMRPCOH10 tMRCE10 RX_EN tMRERD10 RX_CLK tMRRC10 RXD[3:0] RX_DV RX_ER tMRCR10
22236B-24
Figure
Mbps Receive Start Packet Timing
Am79C874
tMRECRL10 tMRECOL10 tMRCNE10 RX_EN tMRERZ10 RX_CLK tMRERL10 RXD[3:0] RX_DV RX_ER
22236B-25
Figure
Mbps Receive Packet Timing
Am79C874
PHYSICAL DIMENSIONS* PQT80 (measured millimeters)
12.00 0.10 14.20 0.25 0.22 0.05
12.00 0.10 14.20 0.25
0.60 0.15 1.00 0.12
1.00 0.05
0.50
1.20 0.05 0.15
22235B-26
*For reference only. ANSI standard Basic Space Centering.
contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks
Copyright 1999 Advanced Micro Devices, Inc. rights reserved. AMD, logo, combinations thereof trademarks Advanced Micro Devices, Inc. NetPHY trademark Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.
Am79C874

NetPHYTM-1LP Power 10/100-TX/FX Ethernet Transceiver DISTINCTIVE

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