MEMORY CMOS FAST PAGE MODE DRAM MB814400A-60/-70/-80 CMOS 1,

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MEMORY CMOS FAST PAGE MODE DRAM MB814400A-60/-70/-80 CMOS 1,

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DS05-10144-5E
MEMORY
CMOS FAST PAGE MODE DRAM MB814400A-60/-70/-80
CMOS 1,048,576 Fast Page Mode Dynamic DESCRIPTION
Fujitsu MB814400A fully decoded CMOS Dynamic (DRAM) that contains total 4,194,304 memory cells accessible 4-bit increments. MB814400A features "fast page" mode operation whereby high-speed random access 1,024-bits data within same selected. MB814400A DRAM ideally suited mainframe, buffers, hand-held computers video imaging equipment, other memory applications where very power dissipation high bandwidth basic requirements design. Since standby current MB814400A very small, device used non-volatile memory equipment that uses batteries primary and/or auxiliary power. MB814400A fabricated using silicon gate CMOS Fujitsu's advanced four-layer polysilicon process. This process, coupled with three-dimensional stacked capacitor memory cells, reduces possibility soft errors extends time interval between memory refreshes. Clock timing requirements MB814400A critical inputs compatible.
PRODUCT LINE FEATURES
Parameter Access Time Access Time Address Access Time Randam Cycle Time Fast Page Mode Cycle Time power Dissipation Operating current Standby current MB814400A-60 max. max. max. min. min. max. MB814400A-70 max. max. max. min. min. max. MB814400A-80 max. max. max. min. min. max.
max. (TTL level)/5.5 max. (CMOS level) Early write controlled write capability only CAS-before-RAS, Hidden Refresh Fast page Mode, Read-Modify-Write capability chip substrate bias generator high performance
1,048,576 words organization Silicon gate, CMOS, 3D-Stacked Capacitor Cell input output areTTL compatible 1024 refresh cycles every16.4
This device contains circuitry protect inputs against damage high static voltages electric fields. However, advised that normal precautions taken avoid application voltage higher than maximum rated voltages this high impedance circuit.
ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Voltage relative Voltage supply relative Power Dissipation Short Circuit Output Current Storage Temperature Symbol VIN, VOUT TSTG Value +125 Unit
WARNING: Permanent device damage occur above Absolute Maximum Ratings exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability.
PACKAGE
Marking side
LCC-26P-M04
ZIP-20P-M02
(Normal Bend)
Marking side (Reverse Bend)
FPT-26P-M01
FPT-26P-M02
Package Ordering Information
26-pin plastic (300 mil) SOJ, order MB814400A-xxPJN 20-pin plastic ZIP, order MB814400A-xxPZ 26-pin plastic (300 mil) TSOP-ll, with normal bend leads, order MB814400A-xxPFTN 26-pin plastic (300 mil) TSOP-ll, with reverse bend leads, order MB814400A-xxPFTR
Fig. MB814400A DYNAMIC BLOCK DIAGRAM
Clock
Write Clock Mode Control
Clock
Refresh Address Counter Substrate Bias Address Buffer PreDecoder Decoder Column Decoder Sense Ampl Gate
Data Buffer
Data Buffer
4,194,304 Storage Cell
DOUT
CAPACITANCE
25°C, MHz)
Parameter Input Capacitance, toA9, Input Capacitance, RAS, CAS, Input/Output Capacitance,
Symbol CIN1 CIN2
Typ.
Max.
Unit
ASSIGNMENTS DESCRIPTIONS
26-Pin SOJ: (Top View) 26-Pin FPT: (Top View) <Normal Bend FPT-26P-M01>
20-Pin ZIP: (Top View) <Reverse Bend FPT-26P-M02>
Designator
Function
DOUT
Data Input/Output Data Output. Write Enable. Address Strobe. Connection. Address Inputs. volt Power Supply. Column Address Strobe. Circuit Ground.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage, inputs Input Voltage, inputs Input Voltage, DQ(*) Notes Symbol VILD Min. -2.0 -1.0 Typ. Max. Unit +70°C Ambient Operating Temp.
Undershoots -2.0 volts with pulse width exceeding acceptable.
FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty input bits required decode four 4,194,304 cell addresses memory matrix. Since only address bits available, column inputs separately strobed shown Figure First, address bits input pins A0-through-A9 latched with address strobe (RAS) then, column address bits input latched with column address strobe (CAS). Both column addresses must stable before falling edge RAS, respectively. address latches flow-through type; thus, address information appearing after tRAH (min.)+ automatically treated column address.
WRITE ENABLE
read write mode determined logic state When active Low, write cycle initiated; when High, read cycle selected. During read mode, input data ignored.
DATA INPUT
Input data written into memory either three basic ways-an early write cycle, (delayed) write cycle, read-modify-write cycle. falling edge CAS, whichever later, serves input data-latch strobe. early write cycle, input data (DQ1 DQ4) strobed setup/hold times referenced because goes before CAS. delayed write read-modify-write cycle, goes after CAS; thus, input data strobed setup/hold times referenced write-enable signal.
DATA OUTPUT
three-state buffers compatible with fanout loads. Polarity output data identical that input; output buffers remain high-impedance state until column address strobe goes Low. When read read-modify-write cycle executed, valid outputs obtained under following conditions: tRAC tCAC tOEA from falling edge when tRCD (max.) satisfied. from falling edge when tRCD greater than tRCD (max.). from column address input when tRAD greater than tRAD (max.). from falling edge when brought after tRAC, tCAC, tAA.
data remains valid until either returns High logic level. When early write executed, output buffers remain high-impedance state during entire cycle.
FAST PAGE MODE OPERATION
fast page mode operation provides faster memory access lower power dissipation. fast page mode implemented keeping same address strobing successive column addresses. satisfy these conditions, held contiguous memory cycles which addresses common. each fast page memory, 1,024-bits accessed and, when multiple 814400s used, decoded select desired memory fast page. Fast page mode operations need addressed sequentially combinations read, write, and/or ready-modify-write cycles permitted.
CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter Output High Voltage Output Voltage Notes Symbol Conditions other pins under test VOUT Data disabled cycling; min. ICC2 -0.2 VIH, cycling; min.
Note
Values Min. Typ. Max. Unit
Input Leakage Current (Any Input)
II(L)
Output Leakage Current Operating Current (Average Power Supply Current) Standby Current (Power Supply Current) Refresh Current#1 (Average Power Supply Current) Fast Page Mode Current MB814400A-60 MB814400A-70 MB814400A-80 level CMOS level MB814400A-60 MB814400A-70 MB814400A-80 MB814400A-60 MB814400A-70 MB814400A-80 Refresh Current#2 (Average Power Supply Current) MB814400A-60 MB814400A-70 MB814400A-80
IDO(L)
ICC1
ICC3
ICC4
VIL, cycling; min.
ICC5
cycling; CAS-before-RAS; min.
CHARACTERISTICS
recommended operating conditions unless otherwise noted.)
Parameter Time Between Refresh Random Read/Write Cycle Time Read-Modify-Write Cycle Time Access Time from Access Time from Column Address Access Time Output Hold Time Output Buffer Turn Delay Time Output Buffer Turn Delay Time Notes Symbol tREF tRWC tRAC tCAC tOFF tRAS tRSH tCRP tRCD tCAS tCSH tCPN tASR tRAH tASC tCAH tRAD tRAL tCAL tRCS tRRH tRCH tWCS tWCH Min. Max. 16.4 10000 Min.
Notes
Max. 16.4 10000 Min. Max. 16.4 10000 Unit
MB814400A-60 MB814400A-70 MB814400A-80
Transition Time Precharge Time Pulse Width Hold Time Precharge Time Delay Time Pulse Width Hold Time Precharge Time (Normal)
Address Time Address Hold Time Column Address Time Column Address Hold Time Column Address Delay Time
Column Address Lead Time Column Address Lead Time Read Command Time Read Command Hold Time Referenced Read Command Hold Time Referenced Write Command Time
Write Command Hold Time
CHARACTERISTICS (Continued)
recommended operating conditions unless otherwise noted.)
Parameter Notes Symbol tRWL tCWL tRWD tCWD tAWD tRPC tCSR tCHR tWSR tWHR tOEA tOEZ tOEL tOEH tOED tDZC tDZO tPRWC tCPA tRASP tRHCP tCPWD Min. Max. 200000 Min.
Notes
Max. 200000 Min. Max. 200000 Unit
MB814400A-60 MB814400A-70 MB814400A-80
Pulse Width Write Command Lead Time Write Command Lead Time Time Hold Time Delay Time Delay Time Column Address Delay Time
Precharge Time Active Time (Refresh Cycles) Time CAS-beforeRAS Refresh Hold Time CAS-before-RAS Refresh
SetUp Time from Hold Time from Access time from Output Buffer Turn Delay from Hold Time Referenced
Lead Time Valid Data
Data Delay Time Delay Time Delay Time
Fast Page Mode Read/Write Cycle Time Fast Page Mode Read-ModifyWriteCycle Time Access Time from Precharge
Fast Page Mode Precharge Time Fast Page Mode Hold Time from Precharge Fast Page Mode Precharge Delay Time
Fast Page Mode Pulse width
Notes: Referenced VSS. depends output load conditions cycle rates; specified values obtained with output open. depends number address change VIH, -0.5 ICC1, ICC3 ICC5 specified time address change during VIH. ICC4 specified time address change during Page cycle. Initial pause (RAS VIH) required after power-up followed eight RASonly cycles before proper device operation achieved. case using internal refresh counter, minimum eight CAS-before-RAS initialization cycles instead cycles required. characteristics assume (min.) (max.) reference levels measuring timing input signals. Also transition times measured between (min.) (max.). Assumes that tRCD tRCD (max.), tRAD tRAD (max.). tRCD greater than maximum recommended value shown this table, tRAC will increased amount that tRCD exceeds value shown. Refer Fig. tRCD tRCD (max.), tRAD tRAD (max.), tASC tCAC access time tCAC. tRAD tRAD (max.) tASC tCAC access time tAA. Measured with load equivalent loads tOFF tOEZ specified that output buffer change high impedance state. Operation within tRCD (max.) limit ensures that tRAC (max.) met. tRCD (max.) specified reference point only; tRCD greater than specified tRCD (max.) limit, access time controlled exclusively tCAC tAA. tRCD (min.) tRAH (min.)+ tASC (min.). Operation within tRAD (max.) limit ensures that tRAC (max.) met. tRAD (max.) specified reference point only; tRAD greater than specified tRAD (max.) limit, access time controlled exclusively tCAC tAA. Either tRRH tRCH must satisfied read cycle. tWCS specified reference point only. tWCS tWCS (min.) data output will remain High-Z state through entire cycle. Assumes that tWCS tWCS (min.) Either tDZC tDZO must satisfied. tCPA access time from selection column address (that caused changing from "H"). Therefore, long, tCPA longer than tCPA (max.). Assumes that CAS-before-RAS refresh. Assumes that Test mode function.
Fig. tRAC tRCD
tRAC (ns) tRAC (ns)
Fig. tRAC tRAD
tCPA (ns)
Fig. tCPA
Version Version Version
Version Version Version Version ns/80 Version
tRCD (ns)
tRAD (ns)
(ns)
FUNCTIONAL TRUTH TABLE
Clock Input Operation Mode Standby Read Cycle Write Cycle (Early Write) Read-ModifyWrite Cycle RAS-only Refresh Cycle CAS-before-RAS Refresh Cycle Hidden Refresh Cycle Test mode Cycle (CBR) Test Mode Cycle (Hidden) Address Valid Valid Valid Valid Column Valid Valid Valid Input Data Input Valid Valid Output High-Z Valid High-Z Valid High-Z High-Z Valid High-Z Valid Refres Yes* Yes* Yes* tCSR tCSR (min.) Previous data kept. tCSR tCSR (min.) tWSR tWSR (min.) tCSR tCSR (min.) tWSR tWSR (min.) tRCS tRCS (min.) tWCS tWCS (min.) tCWD tCWD (min.) Note
Note: impossible Fast Page Mode.
Fig. READ CYCLE
tRAS tCRP tRCD tASR tRAH tRAD tRAL tCAL tASC tCAH COLUMN tRCS tRAC (Output) (Input) tDZO Invalid Data
DESCRIPTION implement read operation,a valid address latched address strobes with High level level, output valid once memory access time elapsed. access time determined (tRAC) (tCAC), (tOEA) column addresses (tAA) under following conditions: tRCD> tRCD (max.), access time tCAC. tRAD> tRAD (max.), access time tAA. brought after tRAC,tCAC, (which ever occurs later), access time tOEA. However, either goes High, output returns high-impedance state after satisfied.
tCSH tRSH tCAS
tOEL
tRRH tRCH tCAC tOFF VALID DATA HIGH-Z tOED tOEA tOEZ HIGH-Z
HIGH-Z tDZC
Fig. EARLY WRITE CYCLE "L")
tRAS tCSH tCRP tRCD tASR tRAD tRAH tASC COLUMN tRAL tCAL tCAH tRSH tCAS
tWCS
tWCH
(Input)
VALID DATA
(Output)
HIGH-Z
DESCRIPTION write cycle similar read cycle except state signal. write cycle implemented either three ways early write, write (delayed write), read-modify-write. During write cycles, timing parameters tRWL, tCWL tRAL must satisfied. early write cycle shown above tWCS satisfied, data latched with falling edge written into memory.
Fig. (DELAYED WRITE CYCLE)
tRAS tCSH tCRP tASR tRAH tASC tCWL tWCH tRWL tDZC (Input) HIGH-Z tRAC HIGH-Z tDZO tOED tCAC VALID DATA tCAH tRAD tCAL tRAL tRCD tCAS tRSH
(Output)
HIGH-Z tOEA tOEZ tOEH
Invalid Data
DESCRIPTION (delayed write) cycle, tWCS satisfied; thus, data pins latched with falling edge written into memory. Output Enable (OE) signal must changed from High before goes (tOED tDS).
Fig. READ-MODIFY-WRITE-CYCLE
tRWC tRAS tCRP tASR tRAH tCSH tRCD tCAS tRSH
tRAD tASC tCAH tRAL tRWD tRCS tCWL tRWL
tCWD tAWD tDZC HIGH-Z tOED tCAC tRAC HIGH-Z tOEA tDZO tOEZ
VALID
(Input)
VALID DATA tOEH
(Output)
HIGH-Z
DESCRIPTION read-modify-write cycle executed changing from High after data appears pins. read-modifywrite cycle, must changed from High after memory access time.
Fig. FAST PAGE MODE READ CYCLE (Early Write)
tRASP tRAD tCRP tASR tRAH
tRCD
tRHCP
tCSH tCAS tASC
tRSH tCAS tCAS tCAH tASC
tCAH
tASC
tCAH
tRRH
tRAL
tRCS tDZC (Input)
tRCH
tRCS tRCH
tRCS
tRCH
tOEL tCPA tDZC tDZC
HIGH-Z
HIGH-Z
HIGH-Z
tDZO tRAC
tCAC tOFF
tDZO tCAC
tOFF
tDZO
(Output)
HIGH-Z tOEA tOEZ tOEA tOEZ
tOED tOED
Valid Data
DESCRIPTION fast page mode operation permits faster successive memory operations multiple column locations same address. This operation performed strobing address maintaining level High level during successive memory cycles which address latched. access time determined tCAC, tAA, tCPA, tOEA, whichever latest occurring.
Fig. FAST PAGE MODE WRITE CYCLE "L")
tRASP tCSH tCRP tRCD tRAH tASR tWCS (Input) VALID DATA VALID DATA tASC tWCH tWCS tCWL tCWL tRAD tCAH tASC tCAH tCAL tWCH tWCS tWCH tCWL tASC tCAH tRAL tCAS tCAS tCAS tRHCP tRSH
VALID DATA
(Output)
HIGH-Z
DESCRIPTION fast page mode write cycle executed same manner fast page mode read cycle except states reversed. Data appearing pins latched falling edge written into memory. During fast page mode write cycle, including delayed (OE) write read-modify-write cycles, tCWL must satisfied.
Fig. FAST PAGE MODE WRITE CYCLE
tRAD tCRP tRAH tASR
ADD.
tRASP tRCD tCSH tCAS tRSH tCAS tCAS tASC tCAH
tASC
tCAH
tASC
tCAH
tRAL
tCWL tDZC (Input)
VALID
tRCS
tCWL
tRWL tCWL
VALID
VALID
tCAC tRAC
HIGH-Z
tOED tOED tOEH tCAC tOEH tCAC tOED
(Output)
tDZO tOEA tOEZ tOEA tOEZ
tOEA tOEZ
tOEH
Invalid Data
DESCRIPTION fast page mode (delayed) write cycle executed same manner fast page mode write cycle except states Input data pins latched falling edge written into memory. fast page mode delayed write cycle, must changed from High before goes (tOED tDS).
Fig. FAST PAGE MODE READ-MODIFY-WRITE CYCLE
tRAD tCRP tRAH tASR tRCS tDZC (Input) tOED tCAC tASC tCWL tCWD tAWD VALID (Output) VALID tOED tCAC VALID tCPWD tRCS tCWD tCWL tCAH tPRWC tRCD tCSH tCAS tRSH tCAS tASC tCAH tRCS tCWL tRWL tASC tCAH tCAS tRAL tRASP
HIGH-Z tDZO tOEZ
tOEH tOEZ
tOEA tCPA tOEA
Valid Data
DESCRIPTION During fast page mode operation, read-modify-write cycle executed switching from High after input date appears pins during normal cycle.
Fig. RAS-ONLY REFRESH "L")
tRAS tASR tCRP DOUT HIGH-Z
DESCRIPTION Refresh memory cells accomplished performing read, write, read-modify-write cycle each 1024 addresses every 16.4-milliseconds. Three refresh modes available: RAS-only refresh, CAS-before-RAS refresh, hidden refresh. RAS-only refresh performed keeping High throughout cycle; address refreshed latched falling edge RAS. During RAS-only refresh, kept high-impedance state.
tRAH ADDRESS tRPC
tOFF
Fig. CAS-BEFORE-RAS REFRESH (ADDRESSES "L")
tCPN tWSR tOFF (Output)
DESCRIPTION
tRAS tCSR
tCHR
tRPC
tWHR
HIGH-Z
CAS-before-RAS refresh on-chip refresh capability that eliminates need external refresh addresses. held specified setup time (tCSR) before goes Low, on-chip refresh control clock generators refresh address counter enabled. internal refresh operation automatically occurs refresh address counter internally incremented preparation next CAS-before-RAS refresh operation. must held High specified time (tWSR) before goes order enter "test mode".
Fig. HIDDEN REFRESH CYCLE
tRAS tRCD tRAD tASR tRAH tASC ADDRESS tRCS tRAC tDZC (Input) (Output) tRCS [Test Mode] tRAC tDZC (Input) (Output) HIGH-Z tDZO tOEA tCAC tRRH HIGH-Z tDZO tOEA tCAC tRAL tCAH COLUMN ADDRESS tRRH tRSH tOEL
tRAS tCRP tCHR
[Normal Mode]
tWSR
tWHR
HIGH-Z tOFF VALID DATA tOEZ tOED
tWSR
tWHR
HIGH-Z VALID DATA tOEZ
tOFF
tOED
DESCRIPTION hidden refresh cycle performed while maintaining latest valid data output extending active time cycling RAS. refresh address provided on-chip refresh address counter. This eliminates need external address that required DRAMs that have CAS-before-RAS refresh capability. must held High specified time (tWSR) before goes order enter "test mode"
Fig. TEST MODE CYCLE "L")
tRAS
tCPN tCSR tCHR
tRPC
tWSR tOFF DOUT
tWHR
HIGH-Z
DESCRIPTION Test Mode purpose this test mode reduce device test time eighth that required test device conventionally. test mode function entered performing CAS-before-RAS (WCBR) refresh entry cycle. test mode, read write operations executed units eights bits which selected address combination RA10, CA10. write mode, data written into eight cells simultaneously. data must input from only. read mode, data eight cells selected addresses read back from checked following manner. When eight bits "H", level output. When eight bits show combination "H", level output. test mode function exited performing RAS-only refresh CAS-before-RAS refresh exit cycle. test mode operation, following parameters delayed approximately from specified value data sheet. tRC, tRWC, tRAC, tAA, tRAS, tCSH, tRAL, tRWD, tAWD, tPC, tPRWC, tCPA, tRHCP tCPWD
Fig. CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tWSR tCSR
tCHR
tFRSH tFCAS tFCAH tRAL
tASC tWHR tRCS tDZC
COLUMN ADDRESS tCWL tFCWD
tRWL
(Input)
(Output)
HIGH-Z tOED tFCAC HIGH-Z tDZO tOEA tOEZ
VALID DATA
HIGH-Z tOEH
DESCRIPTION
Valid Data
special timing sequence using CAS-before-RAS refresh counter test cycle provides convenient method verify functionality CAS-before-RAS refresh circuitry. after CAS-before-RAS refresh cycle. makes transition from High while held Low, read write operations enabled shown above. column addresses defined follows: Address: Bits through defined on-chip refresh counter. Column Address: Bits through defined latching levels A0-A9 second falling edge CAS. CAS-before-RAS Counter Test procedure follows Initialize internal refresh address counter using only refresh cycles. same column address throughout test. Write 1024 addresses same column address using normal write cycles. Read written procedure check; simultaneously write same addresses using CAS-before-RAS refresh counter test (read-modify-write cycles). Repeat this procedure 1024 times with addresses generated internal refresh address counter. Read check data written procedure using normal read cycle 1024 memory locations. Reverse test data repeat procedures
recommended operating conditions unless otherwise noted.) Parameter Access Time from Column Address Hold Time Delay Time Pulse Width Hold Time Symbol tFCAC tFCAH tFCWD tFCAS tFRSH MB814400A-60 MB814400A-70 MB814400A-80 Unit Min. Max. Min. Max. Min. Max.
Note Assumes that CAS-before-RAS refresh counter test cycle only.
PACKAGE DIMENSIONS
(Suffix: -PJN) 26-LEAD PLASTIC LEADED CHIP CARRIER (CASE No.: LCC-26P-M04)
.140(3.55)MAX. *.675±.005 (17.15±0.13) .089(2.25)NOM. .025(0.64)MIN.
.332±.005 (8.43±0.13)
.268±.020
INDEX
.300(7.62) NOM.
LEAD .050±.005 (1.27±0.13)
.100(2.54) TYP. .600(15.24)REF.
Details part .032(0.81) MAX.
.098(2.50) NOM.
.017±.004 (0.43±0.10)
.004(0.10) *:Resin protrusion. (Each side:.006(0.15)MAX.) Note: Although this package leads only, positions same that 26-lead package. ©1991 FUJITSU LIMITED C26054S-1C Dimensions inches (millimeters)
PACKAGE DIMENSIONS (Continued)
(Suffix: -PZ) 26-LEAD PLASTIC ZIG-ZAG IN-LINE PACKAGE (CASE No.: ZIP-20P-M02)
1.019
±.008 ±0.20 (25.88 -.012 -0.30
.112±.008 (2.85±0.20)
INDEX
.335±.010 (8.50±0.25)
.387±.013 (9.83±0.33)
.010±.002 (0.25±0.05) .050(1.27) .020±.004 (0.50±0.10)
.118(3.00)
.100(2.54) (Row Space)
LEAD
(Bottom View)
©1991 FUJITSU LIMITED Z20002S-4C
Dimensions inches (millimeters)
PACKAGE DIMENSIONS (Continued)
(Suffix: -PFTN) 26-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-26P-M01)
Details part .006(0.15)
LEAD .010(0.25) INDEX .006(0.15)MAX. .020(0.50)MAX.
*.675±.004 (17.14±0.10) .016±.004 (0.40±0.10) .008(0.21)
+.004 +0.10 .043 (1.10 -.002 -0.05 (Mounting Height)
.363±.008 (9.22±0.20) .300±.004 (7.62±0.10) .006±.002 (0.15±0.05)
.050(1.27)
.004(0.10) .600(15.24)REF 0(0) MIN. (Stand Height)
.020±.004 (0.50±0.10)
.324±.008 (8.22±0.20)
Resin protrusion.(Each side .006(0.15) MAX)
©1991 FUJITSU LIMITED F26001S-3C
Dimensions inches (millimeters)
PACKAGE DIMENSIONS (Continued)
(Suffix: -PFTR) 26-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-26P-M02)
Details part .006(0.15)
.010(0.25) INDEX .006(0.15)MAX. .020(0.50)MAX.
LEAD
.600(15.24)REF.
.050(1.27) .004(0.10)
0(0) MIN. (Stand Height) .020±.004 (0.50±0.10) .324±.008 (8.22±0.20)
.016±.004 (0.40±0.10)
.008(0.21) *.675±.004 (17.14±0.10) +.004 +0.10 (1.10 -.002 -0.05 (Mounting Height) .043
.300±.004 (7.62±0.10) .363±.008 (9.22±0.20)
.006±.002 (0.15±0.05)
Resin protrusion.(Each side .006(0.15) MAX.)
©1991 FUJITSU LIMITED F26002S-3C
Dimensions inches (millimeters)
FUJITSU LIMITED
further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street Jose, 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED Bras Basah Road, Plaza Park, #06-04 #06-07 Singapore 189554 Tel: 336-1600 Fax: 336-1609
Rights Reserved. Circuit diagrams utilizing Fujitsu products included means illustrating typical semiconductor applications. Complete information sufficient construction purposes necessarily given. information contained this document been carefully checked believed reliable. However, Fujitsu assumes responsibility inaccuracies. information contained this document does convey license under copyrights, patent rights trademarks claimed owned Fujitsu. Fujitsu reserves right change products specifications without notice. part this publication copied reproduced form means, transferred third party without prior written consent Fujitsu. information contained this document intended with equipments which require extremely high reliability such aerospace equipments, undersea repeaters, nuclear control systems medical equipments life support.
F9607 FUJITSU LIMITED Printed Japan

MEMORY CMOS FAST PAGE MODE DRAM MB814400A-60/-70/-80 CMOS 1,

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