MEMORY CMOS FAST PAGE MODE DRAM MB814100A-60/-70/-80 CMOS 4,

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MEMORY CMOS FAST PAGE MODE DRAM MB814100A-60/-70/-80 CMOS 4,

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DS05-10142-4E
MEMORY
CMOS FAST PAGE MODE DRAM MB814100A-60/-70/-80
CMOS 4,194,304 Fast Page Mode Dynamic DESCRIPTION
Fujitsu MB814100A fully decoded CMOS Dynamic (DRAM) that contains total 4,194,304 memory cells configuration. MB814100A features "fast page" mode operation whereby highspeed random access 2,048-bits data within same selected. MB814100A DRAM ideally suited mainframe, buffers, hand-held computers video imaging equipment, other memory applications where very power dissipation high bandwidth basic requirements design. Since standby current MB814100A very small, device used non-volatile memory equipment that uses batteries primary and/or auxiliary power. MB814100A fabricated using silicon gate CMOS Fujitsu's advanced four-layer polysilicon process. This process, coupled with three-dimensional stacked capacitor memory cells, reduces possibility soft errors extends time interval between memory refreshes. Clock timing requirements MB814100A critical inputs compatible.
PRODUCT LINE FEATURES
Parameter Access Time Access Time Address Access Time Randam Cycle Time Fast Page Mode Cycle Time Power Dissipation Operating current Standby current MB814100A-60 max. max. max. min. min. max. MB814100A-70 max. max. max. min. min. max. MB814100A-80 max. max. max. min. min. max.
max. (TTL level) max. (CMOS level) only, CAS-before-RAS, Hidden Refresh Fast page Mode, Read-Modify-Write capability chip substrate bias generator high performance
4,194,304 words organization Silicon gate, CMOS, 3D-Stacked Capacitor Cell input output areTTL compatible 1024 refresh cycles every16.4 Common capability using early write
This device contains circuitry protect inputs against damage high static voltages electric fields. However, advised that normal precautions taken avoid application voltage higher than maximum rated voltages this high impedance circuit.
ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Voltage relative Voltage supply relative Power Dissipation Short Circuit Output Current Storage Temperature Symbol VIN, VOUT TSTG Value +125 Unit
WARNING: Permanent device damage occur above Absolute Maximum Ratings exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability.
PACKAGE
Marking Side
LCC-26P-M04 ZIP-20P-M02
(Normal Bend)
Marking Side (Reverse Bend)
FPT-26P-M01
FPT-26P-M02
Package Ordering Information
26-pin plastic (300 mil) SOJ, order MB814100A-xxPJN 20-pin plastic order MB814100A-xxPZ 26-pin plastic (300 mil) TSOP with normal bend leads, order MB814100A-xxPFTN 26-pin plastic (300 mil) TSOP with reverse bend leads, order MB814100A-xxPFTN
Fig. MB814100A DYNAMIC BLOCK DIAGRAM
Clock Write Clock Mode Control
Clock
Refresh Address Counter Substrate Bias Address Buffer PreDecoder Decoder
Data Buffer
Column Decoder Sense Ampl Gate
4,194,304 Storage Cell
Data Buffer
DOUT
CAPACITANCE
(TA=25°C, MHZ)
Parameter Input Capacitance, A10, Input Capacitance, RAS, CAS, Input Capacitance, DOUT
Symbol CIN1 CIN2 COUT
Typ.
Max.
Unit
ASSIGNMENT DESCRIPTION
26-Pin SOJ:
(Top View) N.C.
26-Pin FPT:
(Top View) DOUT N.C. <Normal Bend FPT-26P-M01> N.C.
DOUT N.C.
20-Pin ZIP: (Top View)
N.C.
<Reverse Bend FPT-26P-M02> DOUT N.C.
DOUT N.C.
N.C.
Designator DOUT N.C. Data Input.
Function
Data Output. Write Enable. Address Strobe. Connection. Address Inputs. volt Power Supply. Column Address Strobe. Circuit Ground.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage, inputs Input Voltage, inputs Notes Symbol Min. -2.0 Typ. Max. Unit +70°C Ambient Operating Temp
FUNCTIONAL OPERATION
ADDRESS INPUTS Twenty-two input bits required decode 4,194,304 cell addresses memory matrix. Since only eleven address bits (A0-A10) available, column inputs separately strobed shown Figure First, eleven address bits applied pins A0-through-A10 latched with address strobe (RAS) then, eleven column address bits applied latched with column address strobe (CAS). Both column addresses must stable before falling edge CAS, respectively. address latches flow-through type; thus, address information appearing after tRAH (min.)+ automatically treated column address. WRITE ENABLE read write mode determined logic state When active Low, write cycle initiated; when High, read cycle selected. During read mode, input data ignored. DATA INPUT Input data written into memory either basic ways-an early write cycle read-modify-write cycle. falling edge CAS, whichever later, serves input data-latch strobe. early write cycle, input data strobed setup/hold times referenced because goes before CAS. delayed write read-modify-write cycle, goes after CAS; thus, input data strobed setup/hold times referenced write-enable signal. DATA OUTPUT three-state buffers compatible with fanout loads. Polarity output data identical that input; output buffers remain high-impedance state until column address strobe goes Low. When read read-modify-write cycle executed, valid outputs obtained under following conditions: tRAC tCAC from falling edge when tRCD (max.) satisfied. from falling edge when tRCD greater than tRCD (max.). from column address input when tRAD greater than tRAD (max.).
data remains valid until either returns High logic level. When early write executed, output buffers remain high-impedance state during entire cycle. FAST PAGE MODE OPERATION fast page mode operation provides faster memory access lower power dissipation. fast page mode implemented keeping same address strobing successive column addresses. satisfy these conditions, held contiguous memory cycles which addresses common. each fast page memory, 2,048-bits accessed and, when multiple 814100s used, decoded select desired memory fast page. Fast page mode operations need addressed sequentially combinations read, write, and/or ready-modify-write cycles permitted.
CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter Output High Voltage Output Voltage Notes Symbol Conditions VVIN5.5 VVCC5.5 other pins under test VVOUT5.5 Data disabled cycling; min. ICC2 -0.2 VIH, cycling; min.
Note
Values Min. Typ. Max. Unit
Input Leakage Current (Any input)
II(L)
Output Leakage Current Operating current (Average Power Supply Current) Standby Current (Power Supply Current) Refresh Current (Average Power Supply Current) FastPageModeCurrent Refresh Current (Average Power Supply Current) MB814100A-60 MB814100A-70 MB814100A-80 Level CMOS level MB814100A-60 MB814100A-70 MB814100A-80 MB814100A-60 MB814100A-70 MB814100A-80 MB814100A-60 MB814100A-70 MB814100A-80
IO(L)
ICC1
ICC3
ICC4
=VIL, cycling; min.
ICC5
cycling; CAS-before-RAS; min.
CHARACTERISTICS
recommended operating conditions unless otherwise noted.) Notes
Parameter Time Between Refresh Random Read/Write Cycle Time Read-Modify-WriteCycle Time Access Time from Access Time from Column Address Access Time Output Hold Time Output Buffer Turn Delay Time Output Buffer Turn Delay Time Notes Symbol tREF tRWC tRAC tCAC tOFF tRAS tRSH tCRP 11,12 tRCD tCAS tCSH tCPN tASR tRAH tASC tCAH tRAD tRAL tCAL tRCS tRRH MB814100A-60 MB814100A-70 MB814100A-80 Min. Max. 16.4 100000 Min. Max. 16.4 100000 Min. Max. 16.4 100000 Unit
Transition Time Precharge Time Pulse Width Hold Time Precharge Time Delay Time Pulse Width Hold Time Precharge Time (Normal)
Address Time Address Hold Time Column Address Time Column Address Hold Time Column Address Delay Time
Column Address Lead Time Column Address Lead time Read Command Time Read Command Hold Time Referenced
CHARACTERISTICS (Continued)
recommended operating conditions unless otherwise noted.) Notes
Parameter Read Command Hold Time Referenced Write Command Time Notes Symbol tRCH tWCS tWCH tRWL tCWL tRWD tCWD tAWD tRPC tCSR tCHR tWSR tWHR tPRWC tCPA tRASP tRHCP tCPWD MB814100A-60 MB814100A-70 MB814100A-80 Min. Max. 200000 Min. Max. 200000 Min. Max. 200000 Unit
Write Command Hold Time Pulse Width Write Command Lead Time Write Command Lead Time Time Hold Time Delay Time Delay Time Column Address Delay Time
Precharge time Active Time (Refresh cycles) Time CAS-beforeRAS Refresh Hold Time CAS-beforeRAS Refresh
Time from Hold Time from Fast Page Mode Read/Write Cycle Time
Fast Page Mode Read-Modify-Write Cycle Time Access Time from Precharge 9,16
Fast Page Mode Precharge Time Fast Page Mode Hold Time from Precharge Fast Page Mode Precharge Delay Time
Fast Page Mode Pulse width
Notes: Referenced depends output load conditions cycle rates; specified values obtained with output open. depends number address change VIH. ICC1, ICC3 ICC5 specified time address change during VIH. ICC4 specified time address change during Page Cycle. Initial pause (RAS=CAS=VIH) required after power-up followed eight RAS-only cycles before proper device operation achieved. case using internal refresh counter, minimum eight CAS-before-RAS initialization cycles instead cycles required. characteristics assume (min.) (max.) reference levels measuring timing input signals. Also transition times measured between (min.) (max.). Assumes that tRCD tRCD (max.), tRAD tRAD (max.). tRCD greater than maximum recommended value shown this table, tRAC will increased amount that tRCD exceeds value shown. Refer Fig. tRCD tRCD (max.), tRAD tRAD(max.), tASC tAA- tCAC access time tCAC. tRAD tRAD (max.) tASC tAA- tCAC access time tAA. Measured with load equivalent loads tOFF specified that output buffer change high impedance state. Operation within tRCD (max.) limit ensures that tRAC (max.) met. tRCD (max.) specified reference point only; tRCD greater than specified tRCD (max.) limit, access time controlled exclusively tCAC tAA. tRCD (min.) tRAH (min.)+ tASC (min.). Operation within tRAD (max.) limit ensures that tRAC (max.) met. tRAD (max.) specified reference point only; tRAD greater than specified tRAD (max.) limit, access time controlled exclusively tCAC tAA. Either tRRH tRCH must satisfied read cycle. tWCS, tCWD tRWD tAWD restrictive operating parameter. They included data sheet electrical characteristic only. tWCS (min.), cycle early write cycle Dout will maintain high impedance state thoughout entire cycle. tCWD (min.), tRWD tRWD (min.), tAWD tAWD(min.), cycle read modify-write cycle data from selected cell will apper Dout pin. neither above conditions satisfied, cycle delayed write cycle invalid data will appear Dout write operation exected satisfying tCWL, tCAL tRAL specifications. tCPA access time from selection column address (that caused changing from "H"). Therefore, long, tCPA longer than tCPA (max.). Assumes that CAS-before- refresh. Assumes that Test mode function.
Fig. tRAC tRCD
tRAC (ns) tRAC (ns)
Fig. tRAC tRAD
tCPA (ns)
Fig. tCPA
Version Version Version
Version
ns/80 Version Version
Version Version
tRCD (ns)
tRAD (ns)
(ns)
FUNCTIONAL TRUTH TABLE
Operation Mode Standby Read Cycle Write Cycle (Early Write) Read-ModifyWrite Cycle RAS-only Refresh Cycle CAS-before-RAS Refresh Cycle Hidden Refresh Cycle Test mode cycle (CBR) Test mode cycle (Hidden) Clock Input Address Input Valid Valid Valid Valid Column Valid Valid Valid Input Valid Valid Data Output High-Z Valid High-Z Valid High-Z High-Z Valid High-Z Valid Refresh tCSR tCSR (min.) Previous data kept tCSR tCSR (min.) tWSR tWSR (min.)
tCSR (min.) tWSR tWSR (min.)
Note
tRCS tRCS (min.) tWCS tWCS (min.) tCWD tCWD (min.)
Note impossible Fast Page Mode.
Fig. READ CYCLE
tRAS tCRP tRCD tASR tRAH tCSH tRSH tCAS tRAD tRAL tASC tCAL tCAH
COLUMN
tRCS tRAC DOUT
HIGH-Z VALID DATA
tRRH tRCH tCAC tOFF
HIGH-Z
Invalid Data
DESCRIPTION read cycle executed keeping both keeping throughout cycle. column addresses latched with CAS, respectively. data output remains valid with "L", i.e., goes data becomes invalid after satisfied. access time determined (tRAC), (tCAC), Column address input (tAA). tRCD (RAS delay time) greater than specification, access time tAA.
Fig. WRITE CYCLE (Early Write)
tRAS tCSH tCRP tRCD tASR tRAD tRAH tASC
COLUMN
tRSH tCAS
tRAL tCAH tCAL
tWCS
tWCH
VALID DATA
DOUT
HIGH-Z
DESCRIPTION write cycle executed same manner read cycle except state pins. data latched with later falling edge written into memory. addition, during write cycle, tRWL tRAL must satisfied with specifications.
Fig. READ WRITE/READ-MODIFY-WRITE CYCLE
tRWC tRAS tCSH tCRP tASR tRAH tRCD tCAS tRAD tASC tAWD tCAH
ADD. COLUMN ADDRESS
tRSH
tRAL tCWL tRWL
tRCS
tCWD
tRWD tCAC
tRAC
VALID DATA
tOFF
DOUT
HIGH-Z
VALID DATA
Invalid Data DESCRIPTION read-modify-write cycle executed changing from after data appears DOUT pin. After current data read out, modified data rewritten into same address quickly.
Fig. FAST PAGE MODE READ CYCLE
tRASP tCRP
tRCD
tRHCP tRSH tCAS tCAS tCAS
tCSH
tASR
tRAD tCAH tRAH tASC tCAH tASC tASC tRAL tCAH
tRCS
tRCS tRCH tRRH
tRCH
tCPA tCAC tOFF
tCAC tRAC DOUT
HIGH-Z
tOFF
VALID
VALID
VALID
DESCRIPTION fast page mode read cycle executed after normal cycle with holding "L", applying column address CAS, keeping Once address selected normally using CAS, other addresses same selected only changing column address applying CAS. During fast page mode, access time tCAC, tAA, tCPA, whichever occurs later. 2048 bits belonging each accessed.
Fig. FAST PAGE MODE WRITE CYCLE (Early Write)
tRASP tCSH tCRP tRCD tRAH tASR
tRHCP tRSH tCAS tCAS tCAS
tRAD tCAH tASC
tASC
tCAH tCAL
tCAH tRAL tASC
tWCS
tWCH tCWL tWCS tCWL
tWCH tWCS tWCH tCWL
VALID DATA
VALID DATA
tRWL
VALID DATA
DOUT
HIGH-Z
DESCRIPTION fast page mode write cycle executed same manner fast page mode read cycle except state data latched with falling edge written into memory. During fast page mode write cycle, tCWL must satisfied. 2048 bits belonging each accessed.
Fig. FAST PAGE MODE READ-MODIFY-WRITE CYCLE
tCRP tRCD tCAS tCSH tPRWC
tRASP tCAS tRSH
tRAD tRAH tASR tASC
COLUMN ADDRESS
tCAH tASC tRAH tRAL tCWL
COLUMN ADDRESS
ADDR.
COLUMN ADDRESS
tRWD tAWD tRCS tCWD
tCWL tCPWD tCWD
tCWL
tRWL
tRAC tCAC tOFF DOUT
VALID VALID VALID DATA
VALID
VALID
VALID
tCPA tCAC tOFF
tCAC
Invalid Data DESCRIPTION During fast page mode, read-modify-write cycle executed changing high after data appears DOUT well normal cycle. 2048 bits belonging each accessed.
Fig. RAS-ONLY REFRESH (WE, DIN, "L")
tRAS tASR tCRP DOUT
HIGH-Z
tRAH
ADDRESS
tRPC
tOFF
DESCRIPTION
refresh DRAM executed normal read, write read-modify-write cycle, i.e., cells line also refreshed executing three cycles. 1024 address must refreshed every 16.4 period. During refresh cycle, cell data connected selected sent sense amplifier re-written cell. MB814100A three types refresh modes, RAS-only refresh, CAS-before-RAS refresh, Hidden refresh. only refresh executed keeping throughout cycle. address refreshed latched falling edge RAS. During RAS-only refresh, DOUT kept high impedance state.
Fig. CAS-BEFORE-RAS REFRESH A10, "L")
tCPN tWSR tOFF DOUT
HIGH-Z
tRAS tCSR
tCHR
tRPC
tWHR
DESCRIPTION CAS-before-RAS refresh executed bringing before RAS. this timing combination, MB814100A executes CASbefore-RAS refresh. address input necessary because generated internally. must held specified time (tWSR) before goes order enter "test mode".
Fig. HIDDEN REFRESH CYCLE
tRAS tRCD tCRP tASR tRAD tRAH tASC tRAL tCAH
COLUMN ADD.
tRAS
tRSH tCHR
ADDRESS
[Normal mode]
(Read)
tRCS tCAC tRAC tRWD tCWD tRCS tAWD
tRRH
tWSR
tWHR
VALID DATA
tOFF
DOUT
HIGH-Z
tWSR
tWHR
(Read/Write Cycle)
VALID
tRCS tCAC tRAC
HIGH-Z
[Test mode]
(Read)
tWSR
tWHR
VALID DATA
tOFF
DOUT
tRWD tRCS tCWD tAWD
VALID
tWSR
tWHR
(Read/Write Cycle)
DESCRIPTION
hidden refresh executed keeping next cycle, i.e., output data previous cycle kept during next refresh cycle. Since kept continuously from previous cycle, followed refresh cycle should CAS-before-RAS refresh. must held specified time (tWSR) before goes secound time order enter "test mode" specified later.
Fig. TEST MODE CYCLE A10, "L")
tRAS
tCPN
tCSR
tRPC tCHR
tWSR tOFF DOUT
tWHR
HIGH-Z
DESCRIPTION Test Mode purpose this test mode reduce device test time eighth that required test device conventionally. test mode function entered performing CAS-before-RAS (WCBR) refresh entry cycle. test mode, read write operations executed units eights bits which selected address combination RA10, CA10. write mode, data written into eight cells simultaneously. read mode, eight cells selected addresses read back checked following manner. When eight bits "H", level output. When eight bits show combination "H", level output. test mode function exited performing RAS-only refresh CAS-before-RAS refresh exit cycle. test mode operation, following parameters delayed approximately from specified value data sheet. tRC, tRWC, tRAC, tAA, tRAS, tCSH, tRAL, tRWD, tAWD, tPC, tPRWC, tCPA, tRHCP tCPWD
Fig. CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tCSR
tCHR
tFRSH tFCAS tFCAH tRAL
tWSR
(Read)
tASC tWHR tRSC
COLUMN ADDRESS
tRRH tFCAC
HIGH-Z
tRCS
tRCH
VALID DATA
tOFF
DOUT
(Write)
tFCWD
tCWL tRWL
VALID DATA
DESCRIPTION special timing sequence using CAS-before-RAS refresh counter test cycle provides convenient method verify functionality CAS-before-RAS refresh circuitry. after CAS-before-RAS refresh cycle. makes transition from High while held Low, read write operations enabled shown above. column addresses defined follows: Address: Bits through defined on-chip refresh counter. Column Address: Bits through defined latching levels A0-A9 second falling edge CAS. CAS-before-RAS Counter Test procedure follows Initialize internal refresh address counter using only refresh cycles. same column address throughout test. Write 1024 addresses same column address using normal write cycles. Read written procedure check; simultaneously write same addresses using CAS-before-RAS refresh counter test (read-modify-write cycles). Repeat this procedure 1024 times with addresses generated internal refresh address counter. Read check data written procedure using normal read cycle 1024 memory locations. Reverse test data repeat procedures recommended operating conditions unless otherwise noted.) Note: Parameter Access Time from Column Address Hold Delay Puls width Hold Time Symbol tFCAC tFCAH tFCWD tFCAS tFRSH MB814100A-60 Min. Max. MB814100A-70 Min. Max. MB814100A-80 Min. Max. Unit
Assumes that CAS-before-RAS refresh counter test cycle only.
PACKAGE DIMENTIONS
(Suffix: -PJN) 26-LEAD PLASTIC LEADED CHIP CARRIER (CASE No.: LCC-26P-M04)
.140(3.55)MAX. *.675±.005 (17.15±0.13) .089(2.25)NOM. .025(0.64)MIN.
.332±.005 (8.43±0.13) .268±.020 (6.81±0.51)
INDEX
.300(7.62) NOM.
LEAD .050±.005 (1.27±0.13)
.100(2.54) TYP. .600(15.24)REF.
Details part .032(0.81) MAX.
.098(2.50) NOM. .017±.004 (0.43±0.10) .004(0.10) *:Resin protrusion. (Each side:.006(0.15)MAX.) Note: Although this package leads only, positions same that 26-lead package. Dimensions inches (millimeters)
©1991 FUJITSU LIMITED C26054S-1C
PACKAGE DIMENSIONS (Continued)
(Suffix: -PZ) 20-LEAD PLASTIC ZIG-ZAG IN-LINE PACKAGE (CASE No.: ZIP-20P-M02)
1.019
+.008 +0.20 (25.88 -.012 -0.30
.112±.008 (2.85±0.20)
INDEX
.335±.010 (8.50±0.25)
.387±.013 (9.83±0.33)
.010±.002 (0.25±0.05) .050(1.27) TYP. .020±.004 (0.50±0.10)
.118(3.00) MIN.
.100(2.54) (Row Space)
LEAD
(Bottom View)
©1991 FUJITSU LIMITED Z20002S-4C
Dimensions inches (millimeters)
PACKAGE DIMENSIONS (Continued)
(Suffix: -PFTN) 26-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-26P-M01)
Details part .006(0.15)
.010(0.25) INDEX .006(0.15)MAX. .020(0.50)MAX.
LEAD
*.675±.004 (17.14±0.10) .016±.004 (0.40±0.10) .008(0.21)
+.004 +0.10 .043 (1.10 -.002 -0.05 (Mounting Height)
.363±.008 (9.22±0.20) .300±.004 (7.62±0.10)
.006±.002 (0.15±0.05)
.050(1.27) TYP.
.004(0.10) .600(15.24)REF. 0(0) MIN. (STAND HEIGHT)
.020±.004 (0.50±0.10)
.324±.008 (8.22±0.20)
Resin protrusion.(Each side .006(0.15) MAX.)
©1991 FUJITSU LIMITED F26001S-3C
Dimensions inches (millimeters)
PACKAGE DIMENSIONS (Continued)
(Suffix: -PFTR) 26-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-26P-M02)
Details part .006(0.15)
.010(0.25) INDEX .006(0.15)MAX. .020(0.50)MAX.
LEAD
.600(15.24)REF.
.050(1.27) .004(0.10)
0(0) MIN. (STAND HEIGHT) .020±.004 (0.50±0.10) .324±.008 (8.22±0.20)
.016±.004 (0.40±0.10)
.008(0.21) *.675±.004 (17.14±0.10)
+.004 +0.10 (1.10 -.002 -0.05 (Mounting Height) .043
.300±.004 (7.62±0.10) .363±.008 (9.22±0.20)
.006±.002 (0.15±0.05)
Resin protrusion.(Each side .006(0.15) MAX.) ©1991 FUJITSU LIMITED F26002S-3C
Dimensions inches (millimeters)
FUJITSU LIMITED
further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street Jose, 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED Bras Basah Road, Plaza Park, #06-04 #06-07 Singapore 189554 Tel: 336-1600 Fax: 336-1609
Rights Reserved. Circuit diagrams utilizing Fujitsu products included means illustrating typical semiconductor applications. Complete information sufficient construction purposes necessarily given. information contained this document been carefully checked believed reliable. However, Fujitsu assumes responsibility inaccuracies. information contained this document does convey license under copyrights, patent rights trademarks claimed owned Fujitsu. Fujitsu reserves right change products specifications without notice. part this publication copied reproduced form means, transferred third party without prior written consent Fujitsu. information contained this document intended with equipments which require extremely high reliability such aerospace equipments, undersea repeaters, nuclear control systems medical equipments life support.
F9607 FUJITSU LIMITED Printed Japan

MEMORY CMOS FAST PAGE MODE DRAM MB814100A-60/-70/-80 CMOS 4,

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