ASSP Image Control CMOS Intelligent On-screen Display Contro

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ASSP Image Control CMOS Intelligent On-screen Display Contro

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DS04-28823-2E
ASSP Image Control
CMOS
Intelligent On-screen Display Controller (IOSDC)
MB90091A
DESCRIPTION
MB90091A multisync, on-screen display controller that supports variety systems such NTSC, PAL, double-scan NTSC, double-scan PAL, 1250HDTV, 1125HDTV well personal computer monitor display systems such XGA. MB90091A contains display memory (VRAM) character font ROM, allowing characters displayed with external devices. device also contains command table storing display command data, minimizing load microcomputer. on-screen display configuration characters lines, with each character consisting dots. font integrates different character patterns. character signal output RGB1 digital output. display color each character specified from among colors. color/monochrome select signal output also provided display either different colors 16-level gray scale. character display functions include character background display, shaded background display, sprite character display functions, contributing providing colorful display screens.
PACKAGES
pin, Plastic SH-DIP pin, Plastic
(DIP-64P-M01)
(FPT-64P-M06)
MB90091A
FEATURES
Screen display capacity Font size Font types characters lines (288 characters) dots (horizontal vertical) different characters (character codes 000H 1FFH) different sprite characters (character codes 1F8H 1FFH) (Internal external selectable) Trimmed display (pattern background none) Character background (settable each character) Shaded background (settable each character) Capable displaying character (selectable from among types characters) screen Sprite character colors colors Sprite trimming colors colors Sprite display position Settable 2-dot units screen Normal, double width, double height, double width double height, quadruple width, quadruple width double height (Set each line)
Display modes
Sprite character display
Character sizes
Display colors
Character color colors (set each character) Trimmed background color colors (set each line) Character background color colors (set each character) Screen background color colors Display position control Horizontal display start position 8-dot units Vertical display start position 2-dot units Line spacing control 2-dot units dots) Character/color signal output ROUT, GOUT, BOUT, IOUT (color signals) COLOR (color/monochrome control signal) VOB1 (character pattern background character background screen background: all-output signal) VOB2 (character pattern background character background: specifiedcharacter output signal) Supported systems NTSC, PAL, double-scan NTSC, double-scan PAL, 1250HDTV, 1125HDTV, etc. Personal computer monitor display systems such Intelligent features Automatic control operation using command table Command table ROM: Internal bytes external bytes available Microcontroller/microcomputer interface 8-bit serial input signal input pins Chip select: Serial clock: SCLK Serial data: Package SH-DIP-64, QFP-64 Power-on reset circuit integrated
Miscellaneous
MB90091A
ASSIGNMENTS
(TOP VIEW)
COLOR DOCK TESTCK TESTSW HBLNK VBLNK HSYNC VSYNC EVEN FLTIN FLTOUT RESET TEST TA16 TA17 TA18
VOB2 VOB1 IOUT BOUT GOUT ROUT SCLK FSEL TSEL RA15 RA14 RA13 RA12 RA11 RA10
(SH-DIP-64P)
(Continued)
MB90091A
(Continued)
(TOP VIEW)
VBLNK HBLNK TESTSW TESTCK DOCK COLOR VOB2 VOB1 IOUT BOUT GOUT ROUT HSYNC VSYNC EVEN FLTIN FLTOUT RESET TEST
SCLK FSEL TSEL RA15 RA14 RA13 RA12 RA11 RA10
TA16 TA17 TA18
(FPT-64P-M06)
MB90091A
DESCRIPTION
name HSYNC VSYNC Function Horizontal sync signal input clock generation based cycle signal. Vertical sync signal input Field control signal input Input level signal this causes font address (RA0) output level signal. Input level signal this causes font address (RA0) output level signal (when normal-size characters displayed). This disabled noninterlaced mode. Output horizontal-sync phase comparison result signal This connected external lowpass filter. Internal voltage input This inputs voltage signal from external lowpass filter. Output AFC-generated horizontal sync signal Reset This enabled after release from power-on reset.
EVEN
FLTIN FLTOUT RESET TEST TA16 TA17 TA18
External data input This inputs data from external font external command data ROM.
Test signal input This inputs level (fixed) signal during normal operation. Test signal output External font chip select Chip select external command table
(Continued)
MB90091A
(Continued)
name RA10 RA11 RA12 RA13 RA14 RA15
Function
External address signal output This outputs signal specifying external font external command table address. External font addresses Raster addresses RA11 Character codes RA12, RA13 Character horizontal address Left byte Center byte Right byte RA14, RA15 Character codes (M7,
TSEL
Address control input command table level input 0000H 7FFFH Internal 8000H FFFFH External level input 0000H 7FFFH External 8000H FFFFH Internal Internal/external font select level input Select internal ROM. level input Select external ROM. Shift clock input serial transfer Serial data input Chip select serial transfer, this level. This also used cancel power-on reset. Output signal indicating internal operation This outputs level signal during data transfer from command table ROM. Chrominance signal output output character, character background, pattern background, shaded background, screen background, sprite character (including pattern background), this outputs chrominance signal. specifying chrominance signal output period This outputs level signal output character, character background, pattern background, shaded background, screen background, sprite character (including pattern background. specifying specified character output period When command "1", this outputs level signal character output period period) when command "1". used display control external circuit, example, halftone display control.
FSEL SCLK
ROUT GOUT BOUT IOUT
VOB1
VOB2
(Continued)
MB90091A
(Continued)
name
Function Color/monochrome select signal output This allows level output each character, character background, line background, screen background, sprite output periods specified depending internal register setting. Color/monochrome display controlled external circuit. (The following correspondence used convenience: level: Monochrome display level: Color display) clock output This outputs clock signal when command 11:DOT "1". Test signal input This inputs level (fixed) signal during normal operation. Test signal input This inputs level (fixed) signal during normal operation. Horizontal blanking signal input This stops display signal output ("L" level output) when inputs level signal. Vertical blanking signal input This stops display signal output ("L" level output) when inputs level signal. power supply
COLOR
DOCK TESTCK TESTSW HBLNK
VBLNK
AVCC AVSS
Ground power supply Ground
MB90091A
BLOCK DIAGRAM
MB90091A
SCLK
TSEL Serial input control Command table control
Command table
FLTIN FLTOUT clock generator
Command table
DOCK
HSYNC VSYNC EVEN Display memory control
Font Font control
FSEL
Display memory (VRAM)
Font
Display data output control
BOUT ROUT GOUT IOUT COLOR
RESET
Resets each block.
MB90091A
ABSOLUTE MAXIMUM RATINGS
(VSS AVSS Parameter Power supply voltage Input voltage
Symbol AVCC VOUT Tstg
Ratings Min. Max.
Unit
Output voltage Power consumption Operating temperature Storage temperature
AVCC must have equal potential. Neither VOUT must exceed "VCC WARNING: Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings.
RECOMMENDED OPERATING CONDITIONS
(VSS AVSS Parameter Power supply voltage level input voltage level input voltage Operating temperature Analog input voltage Symbol AVCC VIHS1 VIHS2 VILS1 VILS2 Values Min. 4.75 4.75 Max. 5.25 5.25 0.45 Unit FLTOUT input inputs Other inputs inputs Other inputs Remarks Specification guarantee range
AVCC must have equal potential. WARNING: Recommended operating conditions normal operating ranges semiconductor device. device's electrical characteristics warranted when operated within these ranges. Always semiconductor devices within recommended operating conditions. Operation outside these ranges adversely affect reliability could result device failure. warranty made with repect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their FUJITSU representative beforehand.
MB90091A
ELECTRICAL CHARACTERISTICS
Characteristics
Parameter level output voltage level output voltage Symbol Conditions 4.75 4.75 Values Min. Typ. Max. Unit
output pins HSYNC VSYNC EVEN RESET TSEL FSEL SCLK HBLNK VBLNK AVCC
Input current
5.25
Supply current
AVCC 5.25 DOCK load
MB90091A
Characteristics
Serial input timing (VCC AVCC AVSS +70°C) Values Symbol Unit Min. Max. tCVC tWCH tWCL tCRC tCFC SCLK SCLK SCLK SCLK 1000
Parameter Shift clock cycle time Shift clock pulse width Shift clock signal rise/fall time Shift clock start time Data setup time Data hold time Chip select time Chip select signal rise/fall time
SCLK
MB90091A
Vertical horizontal sync signal input timings (VCC AVCC AVSS +70°C) Values Symbol Unit Min. Max. tHVST tHVHD HSYNC HSYNC VSYNC VSYNC HSYNC VSYNC VSYNC VSYNC
Parameter Horizontal sync signal rise time Horizontal sync signal fall time Vertical sync signal rise time Vertical sync signal fall time Horizontal sync signal pulse width Vertical sync signal pulse width Horizontal sync signal setup time Vertical sync signal setup time
HSYNC
VSYNC
HSYNC
HVST
HVHD
VSYNC
MB90091A
MB90091A outputs display signals synchronization with sync signals input from external circuits. signals required controlling synchronization horizontal sync signal (input HSYNC pin), vertical sync signal (input VSYNC pin), field control signal (input EVEN pin). following examples illustrate external sync signal input timings applicable general interlaced display. Noninterlaced display does require EVEN signal.
External sync signal input timing examples
Field VSYNC (HSYNC) EVEN Slow
Field VSYNC (HSYNC) EVEN Fast
Input horizontal sync signal HSYNC pin. Input composite sync signal change signal cycle lock disturbed around VSYNC pulse, requiring caution used timing input EVEN pin. (See below.) input levels EVEN input signal fields determined depending relationship between VSYNC pulse positions. EVEN pin, input level signal field which pulse after rise VSYNC pulse appears fast. level signal field which appears slow. EVEN input signal should vary undisplay period such around VSYNC pulse.
MB90091A
RESET signal input timing Parameter Reset input pulse width (VCC AVCC AVSS +70°C) Values Symbol Unit Min. Max. RESET
RESET
MB90091A
Address data hold timing Parameter read cycle Address valid delay Address invalid delay Read data setup Read data hold TCS, active delay TCS, inactive delay clock (VCC AVCC AVSS +70°C) Values Symbol Unit Min. Max. trcyc RA15 TCS, clock*
rcyc
DOCK
TCS,
MB90091A
Display data output timing Parameter Symbol (VCC AVCC AVSS +70°C) Values Unit Min. Max. ROUT, GOUT, BOUT IOUT, VOB1, VOB2 COLOR
Display data output delay
DOCK
ROUT, GOUT, BOUT IOUT, VOB1, VOB2 COLOR
MB90091A
Power-on Reset Specifications
Power ON-OFF timing +70°C) Parameter Power-supply rise time Power-supply shut-off time Symbol VCC, AVCC toff Values Min. 0.05 Max. Unit Remarks Power-on reset circuit activating conditions Conditions which circuit repeatedly operate normally
4.75
Note: power supply must activated smoothly
MB90091A
Power-on reset cancel timing +70°C) Parameter Time after rise Reset cancel pulse width Symbol tWIT tWRH tWRL Values Min. Max. Unit Power-on reset cancel timing Remarks
4.75
Internal reset
CRC* CFC*
table "(1) Serial timing" Section Characteristics".
MB90091A
COMMAND LIST
List display control commands Command First byte Command code/data 76543 10000 10001 10010 10011 10100 10110 10111 10111 Second byte Data write address character color character code Line control Screen control Screen control vertical display start position horizontal display start position sprite vertical display position sprite horizontal display position Function
Line control
10101
11000 11001 11010 11011 11011 11100 11100 11101 11101 11110 11111
Sprite control
Synchronization control
Synchronization control SA0*2 transfer start address transfer start address transfer address transfer address (Reserved) (Reserved)
bits only "1", respectively. bits "1".
MB90091A
Command (Set Write Address)
Command format
First byte Second byte
VRAM address
Function Command specifies write address display memory (VRAM). Before writing data using commands this command determine address write that data Description VRAM address, specify vertical column address horizontal address A0). VRAM address incremented automatically when character code command VRAM address VRAM address. bits specify vertical column address; bits specify horizontal address. address valid between 17H. column address valid between column address value outside above valid range.
MB90091A
Command (Set Character Color)
Command format
First byte Second byte
Specify character qualification display. (Specify display character background, blinking, inverted shading.) Specify shaded background display. character background color. character color.
Function Command sets character color character background color specifies character qualification display shaded background display. Description character color, character background color, character qualification display, shaded background display set/specified each character. Character background display, blinking, inverted shading used characters which character qualification display specified. These settings written VRAM applied display screen moment command (Set Character Code) issued. Specify character qualification display. (Specify display character background, blinking, inverted shading.) Normal display (without character qualification) This setting suppresses character background display, blinking, inverted shading shaded background display. output level VOB2 becomes "L". Character qualification display This setting enables character background display, blinking, inverted shading shaded background display. level output enabled VOB2 pin. Setting command (Screen Control specifies character background display. Setting command (Screen Control specifies blinking. Setting both bits command (Screen Control specifies inverted shading. Setting command (Screen Control sets output level VOB2 "H". Specify shaded background display. Normal display (without shaded background display) Shaded background display Setting both bits command (Screen Control specifies inverted shading. character color. background color.
MB90091A
Command (Set Character Code)
Command format
First byte Second byte
Character code
Function Command writes character code display memory (VRAM). Description character code data this command written display memory (VRAM) along with character color, character background color, shaded background display, character qualification display data command (Set Character Color). Character code represented nine bits from enabling different character patterns from 000H 1FFFH stored internal external font ROM. Upon completion writing data, write address incremented automatically. Character code 000H 1FFFH specify different characters.
MB90091A
Command (Line Control
Command format
First byte Second byte
Line horizontal display start position Character size Specify shaded background left/right joint display Specify shaded background downward joint display Specify shaded background upward joint display
Function Command sets line horizontal display start position, character size, shaded background joint display each line. Description Line control data this command applied display screen when command (Line Control issued. Line horizontal display start position offset value each line, relative horizontal display start position command (Set Horizontal Display Start Position). valid range values 2-character units: characters)
Line horizontal display start position
(X9,
characters characters
MB90091A
Character size Normal Single height double width Double height single width Double height double width Single height quadruple width (Setting prohibited) Double height quadruple width (Setting prohibited) Character size
Note: horizontal display start position "double width single double height" display shifted three dots right from that normal-size display. horizontal display start position "quadruple width single double height" display shifted nine dots right from that normal-size display. careful when displaying normal-size enlarged lines same time.
KGR: Specify shaded background left/right joint display. Display shaded backgrounds horizontally adjacent each other, joined together (without display their adjacent, vertical sides). Display shaded backgrounds horizontally adjacent each other, separately each character (while displaying their adjacent, vertical sides). KGD: Specify shaded background downward joint display. Display shaded background including lower side. Display shaded background excluding lower side. KGU: Specify shaded background upward joint display Display shaded background including lower side. Display shaded background excluding lower side.
MB90091A
Command (Line Control
Command format
First byte Second byte
Control pattern background color. pattern background color.
Function Command sets pattern background color controls between color monochrome modes. Description data this command written column specified VRAM column address command (Set Write Address), along with line control data command (Line Control Line Control data applied display screen column address incremented moment this command issued. Control pattern background color. Display pattern background monochrome. During pattern background color output period, COLOR remains output level. Display pattern background color. During pattern background color output period, COLOR remains output level. pattern background color.
MB90091A
Command (Screen Control
Command format
First byte Second byte
Control inverted shading. Control character background display. Control blinking. Control line spacing. Specify shadow frame szize. Control pattern background. Control displ
Function Command controls display screen. Description ATK: Control inverted shading. Normal display Inverted display disabled. Enable inverted display. This mode displays those characters reverse video (with inverted, shaded background) which bits command (Set Character Color) have been both "1". ATR: Control character background display. Normal display Character background display disabled. Enable character background display. Character background display applies those characters which bits command (Set Character Color) have been "1", respectively. ATB: Control blinking. Normal display Blinking disabled. Enable blinking. This mode causes those characters blink which command (Set Character Color) been "1". Control line spacing. line spacing 2-dot units. dots specified.
MB90091A
K24: Specify shadow frame size. height shadow frames shaded background display dots. height shadow frames shaded background display dots. Control pattern background. pattern background mode "pattern background data displayed character dot. pattern background mode "pattern background Character pattern background dots separately generated automatically from data array. Note: Note: pattern background mode, mode used when relevant font designed. Control display. Disable output operation displaying characters sprite characters. Only screen background color output. Enable output operation displaying characters sprite characters. screen background color also output.
MB90091A
Command (Screen Control
Command format
First byte Second byte
Control sprite character color. Control character color. Control character background. Control specified character output. Control screen background color. Control screen beckground color output. screen background color.
Function Command specifies character color, character background color, screen background color, sprite character color, color/monochrome mode, specified character output. This command also enables disables screen background color output sets screen background color. Description Control sprite character color. Display sprite character sprite pattern background monochrome. During sprite character/pattern background output period, COLOR outputs level signal. Display sprite character sprite pattern background color. During sprite character/pattern background output period, COLOR outputs level signal. Control character color. Display characters monochrome. During character output period, COLOR outputs level signal. Display characters color. During character output period, COLOR outputs level signal. Control character background. Display character background monochrome. During character background output period, COLOR outputs level signal. Display character background color. During character background output period, COLOR outputs level signal. Note: Note: external circuit control display mode between monochrome color using COLOR pin.
MB90091A
ATH: Control specified character output. Normal display VOB2 outputs level signal. VOB2 outputs level signal during output period dots period) those characters which command (Set Character Color) been Note: Note: external circuit handle VOB2 signal, allowing specified character displayed halfbright, translucent, other special display mode. Control screen background color. Display screen background monochrome. During screen background output period, COLOR outputs level signal. Display screen background color. During screen background output period, COLOR outputs level signal. UON: Control screen background color output. Prevent screen background color from being output. During screen background color output period, IOUT, GOUT, ROUT, BOUT, VOB1 pins output level signals. Output screen background color. During screen background color output period, IOUT, GOUT, ROUT, BOUT pins output screen background color VOB1 outputs level signal. screen background color.
MB90091A
Command (Set Vertical Display Start Position)
Command format
First byte Second byte
vertical display start position.
Function Command sets vertical display start position. Description vertical display start position. position start vertical display. valid range values setting 2-dot units dots). following illustrates relationship between vertical display start position *VSYNC signal.
Vertical display start position
VSYNC
Vertical display start position
MB90091A
Command (Set Horizontal Display Start Position)
Command format
First byte Second byte
horizontal display start position.
Function Command sets horizontal display start position. Description horizontal display start position. position start horizontal display. valid range values setting 8dot units. following illustrates relationship between horizontal display start position YSYNC signal.
Horizontal display start position
Horizontal operation started* Horizontal display start position
HSYNC
Character size: About 100-dot clock normal display Double quadruple width display shifted further right from above value. details, Page
MB90091A
10.Command (Sprite Control)
Command format
First byte Second byte
sprite character code. sprite character color. sprite pattern background. sprite pattern background color.
Function Command sets sprite character code, character color, pattern background display, pattern background color. Description SP0: sprite character code. Specify sprite character type from among character codes 1F8H 1FFH representing eight character types. Sprite character 1F8H 1F9H 1FAH 1FBH 1FCH 1FDH 1FEH 1FFH
SCB: sprite character color. SBP: Control sprite pattern background display. Display pattern background sprite. This display mode pattern background" (displaying only those character dots displayed "Pattern background mode). Display pattern background sprite. This display mode "Pattern background SBB: sprite pattern background color.
MB90091A
11.Command (Set Sprite Vertical Display Position)
Command format
First byte Second byte
SY0: sprite vertical display position.
Function Command sets sprite character vertical display position. Description SY0: sprite vertical display position. vertical display position sprite character. valid range values 000H 1FFH setting 2-dot units 1022 dots). following illustrates relationship between sprite vertical display position VSYNC signal.
Sprite vertical display position
VSYNC
Sprite vertical display position
MB90091A
12.Command (Set Sprite Horizontal Display Position)
Command format
First byte Second byte
SX0: sprite horizontal display position.
Function Command sets sprite character horizontal display position. Description SY0: sprite horizontal display position. horizontal display position sprite character. valid range values 000H 1FFH setting 2-dot units 1022 dots). Setting these bits 000H disables sprint display. following illustrates relationship between sprite horizontal display position HSYNC signal.
Sprite horizontal display position
Sprite horizontal display started* Sprite horizontal display position HSYNC
About 80-dot clock.
MB90091A
13.Command 11-0 (Synchronization Control
Command format
First byte Second byte
Control clock output. PR1, Control prescaler. SC1, Control scan system. this "1".
Function Command controls synchronization. Description DOT: Control clock output. output clock signal DOCK pin. Output clock signal dock pin. PR1, PR0: Control prescaler. Prescaler operation Corresponding clock 25.0 42.0 16.7 28.3 10.0 17.0 14.1
SC1, SC0: Control scan system. Interlaced scan Noninterlaced scan Step scan (Setting prohibited) Scan system
Interlaced step scan operation requires field control signal input EVEN pin.
MB90091A
14.Command 11-1 (Synchronization control
Command format
First byte Second byte
DK0: Control clock signals. this "1".
Function Command 11-1 controls clock signals. Description DK0: Control clock signals. divisor 16-dot units generating clock signals dividing (horizontal frequency). valid range values 7FH. This enables horizontal frequency divided 2032.
15.Command 12-0 (Set Transfer Start Address
Command format
First byte Second byte SA0*
SA0: Lower address starting transfer from command table only "0".
Function Command 12-0 sets lower address starting transfer data from command table ROM. Description SA0: Lower address starting transfer from command table These bits only even address. internally "0". Data transfer from initiated issuing command 13-1 (Set Transfer Address
MB90091A
16.Command 12-1 (Set Transfer Start Address
Command format
First byte Second byte
SA8: Upper address starting transfer from command table
Function Command 12-1 sets upper address starting transfer data from command table ROM. Description SA8: Upper address starting transfer from command table Data transfer from initiated issuing command 13-1 (Set Transfer Address
17.Command 13-0 (Set Transfer Address
Command format
First byte Second byte EA0*
SA0: Lower address ending transfer from command table onlybe "1".
Function Command 13-0 sets lower address ending transfer data from command table ROM. Description EA0: Lower address ending transfer from command table These bits only address. internally "1". Data transfer from initiated issuing command 13-1 (Set Transfer Address
MB90091A
18.Command 13-1 (Set Transfer Address
Command format
First byte Second byte
Control transfer period. Upper address ending transfer from command table
Function Command 13-1 sets upper address ending data transfer from command table specifies transfer period initiate data transfer. Description VBS: Control transfer period. Transfer data during horizontal vertical blanking intervals. Transfer data during vertical blanking interval. EA8: Upper address ending transfer from command table Issuing this command initiates command table transfer operation sets output level. Upon completion transfer operation, output becomes level. When output level, issue command serial input (commands issued).
MB90091A
APPLICATION EXAMPLES
This section provides useful information designing application systems using MB90091A.
Power Supply
MB90091A pairs digital (VCC, VSS) analog (AVCC, AVSS) power-supply ground pins. AVCC power-supply pins independent each other; AVSS ground pins internally common. Since analog power supply supplies power control voltage internal VCO, requires special consideration separately from digital power supply. general, attention following points: Design system that ground power supply impedances suppressed. addition, ground line should laid ground plane including peripheral analog circuits. digital (VCC, VSS) analog (AVCC, AVSS) power supplies must separated from each other. AVCC pins, AVSS pins must have potential different between. supply digital analog power from same power source, separately route wires from source choke coil prevent digital noise from interfering with analog subsystem power source. Insert relatively high-capacity electrolytic capacitor bypass capacitor between power supply ground, separately between digital analog subsystems.
Interface with Microcontroller Microcomputer
Operation MB90091 controlled micro (controller microcomputer). MB90091 interfaces with micro 8-bit serial transfer using four signal liens shown below: Microcontroller/microcomputer interface
Micro Data Serial clock Chip select Port Internal operation flag Port interrupt input)
MB90091A
SCLK
Although most micros used controlling MB90091A, with 8-bit serial interface (serial port) recommended because connected directly MB90091A high-speed command/data transfer means hardware. (The micro with 4-bit serial interface transfer data separate blocks.)
Note: Keep mind that some micros cannot connected serial port depending type. Fujitsu 8-bit microcontrollers have problem with MB90091A.
MB90091A
Treatment Unused Pins
Pins unused MB90091A must treated follows. Treatment unused pins name HSYNC VSYNC EVEN FLTIN FLTOUT RESET TEST TA16 TA17 TA18 RA10 RA11 RA12 RA13 RA14 RA15 TSEL FSEL SCLK Leave open. Connect leave open. Connect leave open. Connect leave open. Connect leave open. Connect leave open. Connect leave open. Connect leave open. Connect leave open. Connect leave open. Connect VSS. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Treatment Connect leave open.
(Continued)
MB90091A
(Continued)
name ROUT GOUT BOUT IOUT VOB1 VOB2 COLOR DOCK TESTCK TESTSW HBLNK VBLNK
Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open. Leave open.
Treatment
Connect leave open. Connect VCC. Connect leave open. Connect leave open.
MB90091A
APPLIED CIRCUIT EXAMPLE
MB90091A Sync signal separation RA10 RA11 RA12 RA13 RA14 RA15 HSYNC VSYNC EVEN HBLNK VBLNK SCLK ROUT GOUT BOUT IOUT VOB1 COLOR VOB2 DOCK Display control (digital)
Ground (digital) (analog) AGND Grond (analog) This circuit required when internal used. (512-character font ROM) 64K-byte
Micro
FSEL
TSEL
TA16 TA17 TA18 TEST
TESTSW TESTCK
(Command table ROM) 32K-byte
0.1µ
RESET
0.1µ
AGND
FLTOUT
FLTIN
AGND
Adjustment required depending synchronization system.
MB90091A
ORDERING INFORMATION
Part number MB90091AP MB90091APF Package 64-pin plastic SH-DIP (DIP-64P-M01) 64-pin plastic (FPT-64P-M06) Remarks
MB90091A
PACKAGE DIMENSIONS
pin, Plastic SH-DIP (DIP-64P-M01)
58.00 -0.55 +.008 2.283 -.022
+0.22
INDEX-1 INDEX-2
17.00±0.25 (.669±.010)
5.65(.222)MAX 3.00(.118)MIN 1.00 +.020 .039 1.778±0.18 (.070±.007) 1.778(.070) 55.118(2.170)REF
+0.50
0.25±0.05 (.010±.002) 0.45±0.10 (.018±.004) 0.51(.020)MIN 15°MAX 19.05(.750)
1994 FUJITSU LIMITED D64001S-3C-4
Dimensions (inches).
(Continued)
MB90091A
pin, Plastic (FPT-64P-M06)
24.70±0.40(.972±.016)
3.35(.132)MAX
(Mounting height)
20.00±0.20(.787±.008)
0.05(.002)MIN (STAND OFF)
14.00±0.20 (.551±.008) INDEX
18.70±0.40 (.736±.016)
12.00(.472)
16.30±0.40 (.642±.016)
LEAD
1.00(.0394)
0.40±0.10 (.016±.004)
0.15±0.05(.006±.002) 0.20(.008)
Details part 0.25(.010) 0.10(.004) 18.00(.709)REF 22.30±0.40(.878±.016) 0.30(.012) 0.18(.007)MAX 0.63(.025)MAX
Details part
1.20±0.20 (.047±.008)
1994 FUJITSU LIMITED F64013S-3C-2
Dimensions (inches).
MB90091A
FUJITSU LIMITED
further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street Jose, 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, Lorong Chuan Tech Park Singapore 556741 Tel: (65) 0770 Fax: (65) 0220
Rights Reserved. contents this document subject change without notice. Customers advised consult with FUJITSU sales representatives before ordering. information circuit diagrams this document presented examples semiconductor device applications, intended incorporated devices actual use. Also, FUJITSU unable assume responsibility infringement patent rights other rights third parties arising from this information circuit diagrams. FUJITSU semiconductor devices intended standard applications (computers, office automation other office equipment, industrial, communications, measurement equipment, personal household devices, etc.). CAUTION: Customers considering products special applications where failure abnormal operation directly affect human lives cause physical injury property damage, where extremely high levels reliability demanded (such aerospace systems, atomic energy controls, floor repeaters, vehicle operating controls, medical devices life support, etc.) requested consult with FUJITSU sales representatives before such use. company will responsible damages arising from such without prior approval. semiconductor devices have inherently certain rate failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Control Japan, prior authorization Japanese government should required export those products from Japan.
F9704 FUJITSU LIMITED
Printed Japan

ASSP Image Control CMOS Intelligent On-screen Display Contro

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