PCnetTM-ISA Jumperless, Full Duplex Single-Chip Ethernet Controller
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Am79C961A
PCnetTM-ISA Jumperless, Full Duplex Single-Chip Ethernet Controller
DISTINCTIVE CHARACTERISTICS
Single-chip Ethernet controller Industry Standard Architecture (ISA) Extended Industry Standard Architecture (EISA) buses Supports IEEE 802.3/ANSI 8802-3 Ethernet standards Supports full duplex operation 10BASE-T, AUI, GPSI ports Direct interface EISA compatible Am79C961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller Software compatible with AMD's Am7990 LANCE register descriptor architecture power, CMOS design with sleep mode allows reduced power consumption critical battery powered applications Individual 136-byte transmit 128-byte receive FIFOs provide packet buffering increased system latency, support following features: Automatic retransmission with FIFO reload Automatic receive stripping transmit padding (individually programmable) Automatic runt packet rejection Automatic deletion received collision frames Dynamic transmit generation programmable frame-by-frame basis Single power supply Internal/external loopback capabilities Supports 16K, 32K, Boot PROMs Flash diskless node applications Supports Microsoft's Plug Play System configuration jumperless designs Supports staggered drive reduced noise ground bounce Integrated Magic Packetsupport remote wake Green Supports interrupts chip Look Ahead Packet Processing (LAPP) allows protocol analysis begin before receive frame Supports channels chip Supports locations Supports boot PROM locations Provides integrated Attachment Unit Interface (AUI) 10BASE-T transceiver with modes port selection: Automatic selection 10BASE-T Software selection 10BASE-T Automatic Twisted Pair receive polarity detection automatic correction receive polarity Supports bus-master, programmed I/O, shared-memory architectures application Supports edge level-sensitive interrupts Buffer Management Unit reduced intervention which allows higher throughput by-passing platform JTAG Boundary Scan (IEEE 1149.1) test access port interface board level production test Integrated Manchester Encoder/Decoder Supports following types network interfaces: external 10BASE2, 10BASE5, 10BASE-T 10BASE-F Internal 10BASE-T transceiver with Smart Squelch Twisted Pair medium Supports LANCE General Purpose Serial Interface (GPSI) 132-pin PQFP 144-pin TQFP packages
Supports Shared Memory modes Supports PCMCIA mode (144-TQFP version only) Support operation industrial temperature range (-40°C +85°C) available both packages
Publication# 19364 Rev: Amendment/0 Issue Date: January 1998
GENERAL DESCRIPTION
PCnet-ISA controller, single-chip Ethernet controller, highly integrated system solution PC-AT Industry Standard Architecture (ISA) architecture. designed provide flexibility compatibility with existing application. This highly integrated VLSI device specifically designed reduce parts count cost, addresses applications where higher system throughput desired. PCnet-ISA controller fabricated with AMD's advanced low-power CMOS process provide standby current power sensitive applications. PCnet-ISA controller configured into three different architecture modes suit particular application. Master mode, transfers performed using integrated controller. This configuration enhances system performance allowing PCnet-ISA controller bypass platform controller directly address full 24-bit memory space. implementation Master mode allows minimum parts count majority applications. PCnet-ISA also configured Slave with either Shared Memory Programmed architecture compatibility with low-end machines, such PC/XTs that support Masters, high-end machines that require local packet buffering increased system latency. PCnet-ISA controller designed directly interface with EISA system bus. contains Plug Play interface unit, Buffer Management Unit, 802.3 Media Access Control function, individual 136-byte transmit 128-byte receive FIFOs, IEEE 802.3 defined Attachment Unit Interface (AUI), Twisted Pair Transceiver Media Attachment Unit. Full duplex network operation enabled device's network ports. PCnet-ISA controller also register compatible with LANCE (Am7990) Ethernet controller PCnet-ISA (Am79C960). Buffer Management Unit supports LANCE descriptor software model. External remote boot Ethernet physical address PROMs Electrically Erasable Proms also supported. This advanced Ethernet controller built-in capability automatically selecting either port Twisted Pair transceiver. Only interface active time. individual 136-byte transmit 128-byte receive FIFOs optimize system overhead, providing sufficient latency during packet transmission reception, minimizing intervention during normal network error recovery. integrated Manchester encoder/decoder eliminates need external Serial Interface Adapter (SIA) node system. support external encoding/decoding scheme desired, embedded General Purpose Serial Interface (GPSI) allows direct access to/from MAC. addition, device provides programmable on-chip drivers transmit, receive, collision, receive polarity, link integrity activity, jabber status. PCnet-ISA controller also provides External Address Detection Interface(EADITM) allow external hardware address filtering internetworking applications. power sensitive applications where stand-by current desired, device incorporates sleep function reduce over-all system power consumption, excellent notebooks Green PCs. conjunction with this power mode, PCnet-ISA controller also integrated functions support Magic Packet, inexpensive technology that allows remote wake Green PCs. With rise embedded networking applications operating harsh environments where temperatures exceed normal commercial temperature (0°C +70°C) window, industrial temperature (-40°C +85°C) version available packages; 132-pin PQFP 144-pin TQFP. industrial temperature version PCnet-ISA Ethernet controller characterized across industrial temperature range (-40°C +85°C) within published power supply specification (4.75 5.25 i.e., VCC). Thus, conformance PCnet-ISA performance over this temperature range guaranteed design characterization monitor.
Am79C961A
BLOCK DIAGRAM: MASTER MODE
DACK[3, 5-7] DRQ[3, 5-7] IOCHRDY IOCS16 IRQ[3, MASTER MEMR MEMW RESET SBHE BALE FIFO Control Private Control RXD+/- 10BASE-T TXD+/- TXPD+/- Interface Unit FIFO 802.3 Core DXCVR/EAR
CI+/- Encoder/ Decoder (PLS) Port FIFO DI+/- XTAL1 XTAL2 DO+/-
SD[0-15]
IRQ15/APCS BPCS LED[0-3] PRDB[0-7]
LA[17-23] SA[0-19] SLEEP SHFBUSY EEDO EEDI EESK EECS
Buffer Management Unit
EEPROM Interface Unit JTAG Port Control
DVDD[1-7] DVSS[1-13] AVDD[1-4] AVSS[1-2]
19364B-1
Am79C961A
TABLE CONTENTS
DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM: MASTER MODE. ORDERING INFORMATION CONNECTION DIAGRAM: MASTER MODE DESIGNATIONS: MASTER MODE LISTED NUMBER LISTED NAME LISTED GROUP DESCRIPTIONS: MASTER MODE. IEEE P996 TERMINOLOGY INTERFACE BOARD INTERFACE. CONNECTION DIAGRAMS: SLAVE MODE BLOCK DIAGRAM: SLAVE MODE DESIGNATIONS: SLAVE MODE LISTED NUMBER LISTED NAME LISTED GROUP DESCRIPTIONS: SLAVE MODE. INTERFACE DESCRIPTIONS: NETWORK INTERFACES TWISTED PAIR INTERFACE. IEEE 1149.1 (JTAG) TEST ACCESS PORT DESCRIPTIONS: POWER SUPPLIES. CONNECTION DIAGRAM (TQFP 144). DESCRIPTIONS: MASTER MODE (TQFP 144) LISTED NUMBER LISTED NAME DESCRIPTIONS: SLAVE (PIO SHARED MEMORY) MODES (TQFP 144) LISTED NUMBER LISTED NAME BLOCK DIAGRAM: PCMCIA MODE DESCRIPTIONS: PCMCIA MODE (TQFP 144) LISTED NUMBER LISTED NAME DESCRIPTION: PCMCIA MODE BLOCK DIAGRAM: PCMCIA MODE FUNCTIONAL DESCRIPTION PCMCIA OPERATION. SERIAL EEPROM SUPPORT FLASH MEMORY FLASH MEMORY PROGRAMMING SHARED MEMORY PROGRAMMED IMPLICATIONS FLASH MEMORY CARD REGISTERS FUNCTIONAL DESCRIPTION IMPORTANT NOTE ABOUT EEPROM MASTER MODE SLAVE MODE PLUG PLAY OPERATION AUTO-CONFIGURATION PORTS INITIATION ISOLATION PROTOCOL HARDWARE PROTOCOL.
Am79C961A
SOFTWARE PROTOCOL PLUG PLAY CARD CONTROL REGISTERS. PLUG PLAY CARD STATE TRANSITIONS PLUG PLAY LOGICAL DEVICE CONFIGURATION REGISTERS. DETAILED FUNCTIONS EEPROM DEVICE DRIVER COMPATIBLE EEPROM BYTE PLUG PLAY REGISTER PCNET-ISA II'S LEGACY FEATURE DESCRIPTION PLUG PLAY REGISTER LOCATIONS DETAILED DESCRIPTION. VENDOR DEFINED BYTE (PNP 0XF0) CHECKSUM FAILURE WITHOUT EEPROM EXTERNAL SCAN CHAIN. FLASH PROM INTERFACE. OPTIONAL IEEE ADDRESS PROM EISA CONFIGURATION REGISTERS INTERFACE UNIT (BIU) TRANSFERS. INITIALIZATION BLOCK TRANSFERS DESCRIPTOR TRANSFERS FIFO TRANSFERS BUFFER MANAGEMENT UNIT (BMU) INITIALIZATION REINITIALIZATION SUSPEND BUFFER MANAGEMENT DESCRIPTOR RINGS DESCRIPTOR RINGS ACCESS MECHANISM POLLING TRANSMIT DESCRIPTOR TABLE ENTRY (TDTE) RECEIVE DESCRIPTOR TABLE ENTRY (RDTE) MEDIA ACCESS CONTROL TRANSMIT RECEIVE MESSAGE DATA ENCAPSULATION. MANCHESTER ENCODER/DECODER (MENDEC). EXTERNAL CRYSTAL CHARACTERISTICS EXTERNAL CLOCK DRIVE CHARACTERISTICS MENDEC TRANSMIT PATH TRANSMITTER TIMING OPERATION RECEIVE PATH INPUT SIGNAL CONDITIONING CLOCK ACQUISITION TRACKING CARRIER TRACKING MESSAGE DATA DECODING DIFFERENTIAL INPUT TERMINATIONS COLLISION DETECTION JITTER TOLERANCE DEFINITION ATTACHMENT UNIT INTERFACE (AUI) TWISTED PAIR TRANSCEIVER (T-MAU) TWISTED PAIR TRANSMIT FUNCTION TWISTED PAIR RECEIVE FUNCTION LINK TEST FUNCTION POLARITY DETECTION REVERSAL. TWISTED PAIR INTERFACE STATUS COLLISION DETECT FUNCTION. SIGNAL QUALITY ERROR (SQE) TEST (HEARTBEAT) FUNCTION
Am79C961A
JABBER FUNCTION POWER DOWN FULL DUPLEX OPERATION. EADI (EXTERNAL ADDRESS DETECTION INTERFACE). GPSI (GENERAL PURPOSE SERIAL INTERFACE) IEEE 1149.1 TEST ACCESS PORT INTERFACE BOUNDARY SCAN CIRCUIT SUPPORTED INSTRUCTIONS INSTRUCTION REGISTER DECODING LOGIC BOUNDARY SCAN REGISTER (BSR) OTHER DATA REGISTERS POWER SAVING MODES. ACCESS OPERATIONS (SOFTWARE) RESOURCES REGISTER ACCESS IEEE ADDRESS ACCESS BOOT PROM ACCESS STATIC ACCESS CYCLES (HARDWARE) MASTER MODE ADDRESS PROM CYCLES EXTERNAL PROM. ADDRESS PROM CYCLES USING EEPROM DATA. ETHERNET CONTROLLER REGISTER CYCLES TRANSMIT OPERATION. TRANSMIT FUNCTION PROGRAMMING AUTOMATIC GENERATION. TRANSMIT GENERATION TRANSMIT EXCEPTION CONDITIONS RECEIVE OPERATION RECEIVE FUNCTION PROGRAMMING AUTOMATIC STRIPPING. RECEIVE CHECKING. RECEIVE EXCEPTION CONDITIONS LOOPBACK OPERATION LEDs MAGIC PACKET OPERATION MAGIC PACKET MODE ACTIVATION MAGIC PACKET RECEIVE INDICATORS PCNET-ISA CONTROLLER REGISTERS REGISTER ACCESS. RAP: REGISTER ADDRESS PORT CONTROL STATUS REGISTERS CSR0: PCnet-ISA Controller Status Register CSR1: IADR[15:0] CSR2: IADR[23:16] CSR3: Interrupt Masks Deferral Control CSR4: Test Features Control CSR5: Control CSR6: RCV/XMT Descriptor Table Length CSR8: Logical Address Filter, LADRF[15:0]. CSR9: Logical Address Filter, LADRF[31:16]. CSR10: Logical Address Filter, LADRF[47:32]. CSR11: Logical Address Filter, LADRF[63:48]. CSR12: Physical Address Register, PADR[15:0] .100 CSR13: Physical Address Register, PADR[31:16] .100 CSR14: Physical Address Register, PADR[47:32] .100 CSR15: Mode Register. .100
Am79C961A
CSR16: Initialization Block Address Lower. .102 CSR17: Initialization Block Address Upper .102 CSR18-19: Current Receive Buffer Address .102 CSR20-21: Current Transmit Buffer Address .102 CSR22-23: Next Receive Buffer Address .103 CSR24-25: Base Address Receive Ring .103 CSR26-27: Next Receive Descriptor Address .103 CSR28-29: Current Receive Descriptor Address .103 CSR30-31: Base Address Transmit Ring .103 CSR32-33: Next Transmit Descriptor Address .103 CSR34-35: Current Transmit Descriptor Address. .103 CSR36-37: Next Next Receive Descriptor Address .103 CSR38-39: Next Next Transmit Descriptor Address .103 CSR40-41: Current Receive Status Byte Count .103 CSR42-43: Current Transmit Status Byte Count .104 CSR44-45: Next Receive Status Byte Count. .104 CSR46: Poll Time Counter .104 CSR47: Polling Interval. .104 CSR48-49: Temporary Storage .104 CSR50-51: Temporary Storage .104 CSR52-53: Temporary Storage .105 CSR54-55: Temporary Storage .105 CSR56-57: Temporary Storage .105 CSR58-59: Temporary Storage .105 CSR60-61: Previous Transmit Descriptor Address .105 CSR62-63: Previous Transmit Status Byte Count .105 CSR64-65: Next Transmit Buffer Address .105 CSR66-67: Next Transmit Status Byte Count .105 CSR70-71: Temporary Storage .106 CSR72: Receive Ring Counter .106 CSR74: Transmit Ring Counter .106 CSR76: Receive Ring Length. .106 CSR78: Transmit Ring Length .106 CSR80: Burst FIFO Threshold Control .106 CSR82: Activity Timer .107 CSR84-85: Address. .108 CSR86: Buffer Byte Counter .108 CSR88-89: Chip .108 CSR92: Ring Length Conversion .108 CSR94: Transmit Time Domain Reflectometry Count. .108 CSR96-97: Interface Scratch Register .109 CSR98-99: Interface Scratch Register .109 CSR104-105: SWAP .109 CSR108-109: Buffer Management Scratch .109 CSR112: Missed Frame Count. .109 CSR114: Receive Collision Count .109 CSR124: Buffer Management Unit Test .109 CONFIGURATION REGISTERS .111 ISACSR0: Master Mode Read Active/SRAM Data Port .111 ISACSR1: Master Mode Write Active/SRAM Address Pointer .111 ISACSR2: Miscellaneous Configuration .112 ISACSR3: EEPROM Configuration .113 ISACSR4: LED0 Status (Link Integrity) .114 ISACSR5: LED1 Status .114 ISACSR6: LED2 Status .115 ISACSR7: LED3 Status .116 ISACSR8: Software Configuration Register (Read-Only Register) .117 ISACSR9: Miscellaneous Configuration .117
Am79C961A
Initialization Block .117 RLEN TLEN .117 RDRA TDRA. .118 LADRF. .118 PADR. .118 MODE .118 Receive Descriptors. .119 RMD0 .119 RMD1 .119 RMD2 .119 RMD3 .120 Transmit Descriptors .120 TMD0. .120 TMD1. .120 TMD2. .121 TMD3. .121 Register Summary .123 Ethernet Controller Registers (Accessed Port) .123 REGISTER SUMMARY .125 ISACSR-ISA Configuration Registers (Accessed Port). .125 SYSTEM APPLICATION .126 Interface .126 Compatibility Considerations. .126 Master .126 Shared Memory. .126 Optional Address PROM Interface. .129 Boot PROM Interface. .129 Static Interface (for Shared Memory Only) .130 .130 EEPROM Interface .130 10BASE-T Interface .130 ABSOLUTE MAXIMUM RATINGS. .131 OPERATING RANGES .131 Commercial Devices .131 CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES .131 SWITCHING CHARACTERISTICS: MASTER MODE .134 SWITCHING CHARACTERISTICS: MASTER MODE-FLASH READ CYCLE .137 SWITCHING CHARACTERISTICS: MASTER MODE-FLASH WRITE CYCLE .137 SWITCHING CHARACTERISTICS: SHARED MEMORY MODE .138 SWITCHING CHARACTERISTICS: SHARED MEMORY MODE-FLASH READ CYCLE. .141 SWITCHING CHARACTERISTICS: SHARED MEMORY MODE-FLASH WRITE CYCLE .141 SWITCHING CHARACTERISTICS: EADI .142 SWITCHING CHARACTERISTICS: JTAG (IEEE 1149.1) INTERFACE .142 SWITCHING CHARACTERISTICS: GPSI .143 SWITCHING CHARACTERISTICS: .144 SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE .145 SWITCHING CHARACTERISTICS: SERIAL EEPROM INTERFACE .145 SWITCHING TEST CIRCUITS .146 SWITCHING WAVEFORMS: MASTER MODE .149 SWITCHING WAVEFORMS: SHARED MEMORY MODE. .159 SWITCHING WAVEFORMS: GPSI .169 SWITCHING WAVEFORMS: EADI .170 SWITCHING WAVEFORMS: JTAG (IEEE 1149.1) INTERFACE .170 SWITCHING WAVEFORMS: AUI. .171 SWITCHING WAVEFORMS: 10BASE-T INTERFACE .175 PHYSICAL DIMENSIONS .177 PQB132 (TRIMMED FORMED) .177 PQB132 (MOLDED) .178 APPENDIX PCNET-II COMPATIBLE MEDIA INTERFACE MODULES. .179 Am79C961A
PCnet-ISA COMPATIBLE 10BASE-T FILTERS TRANSFORMERS .179 PCnet-ISA Compatible Isolation Transformers .179 PCnet-ISA Compatible DC/DC Converters. .180 MANUFACTURER CONTACT INFORMATION .180 APPENDIX LAYOUT RECOMMENDATIONS REDUCING NOISE. .181 DECOUPLING LOW-PASS FILTER DESIGN .181 Digital Decoupling .181 Analog Decoupling. .181 AVSS1 AVDD3 .181 AVSS2 AVDD2 .181 AVSS2 AVDD2/AVDD4 .182 APPENDIX SAMPLE PLUG PLAY CONFIGURATION RECORD .183 SAMPLE CONFIGURATION FILE .183 APPENDIX ALTERNATIVE METHOD INITIALIZATION. .185 APPENDIX INTRODUCTION LOOK AHEAD PACKET PROCESSING (LAPP) CONCEPT .186 Outline LAPP Flow: .186 SETUP: .187 FLOW: .187 LAPP Enable Software Requirements .189 LAPP Enable Rules Parsing Descriptors .189 Some Examples LAPP Descriptor Interaction .190 Buffer Size Tuning .191 APPENDIX SOME CHARACTERISTICS XXC56 SERIAL EEPROM .195 SWITCHING CHARACTERISTICS TYPICAL XXC56 SERIAL EEPROM INTERFACE .195 INSTRUCTION XXC56 SERIES EEPROMs .196
Am79C961A
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination
AM79C961A
ALTERNATE PACKAGING OPTION \W=Trimmed Formed (PQB132) OPTIONAL PROCESSING Blank=Standard Processing TEMPERATURE RANGE C=Commercial (0°C +70°C) =Industrial (-40°C +85°C) PACKAGE TYPE (per Prod. Nomenclature/16-038) K=132-pin Plastic Quad Flat Pack (PQR132) V=144-pin Thin Quad Flat Package (PQT144) SPEED Applicable DEVICE NUMBER/DESCRIPTION Am79C961A PCnet-ISA Jumperless Single-Chip Ethernet Controller
Valid Combinations KC\W AM79C961A VC\W KI\W AM79C961A VI\W
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am79C961A
CONNECTION DIAGRAMS: MASTER MODE
PQFP
DVDD2 EECS BPCS SHFBUSY PRDB0/EESK PRDB1/EEDI PRDB2/EEDO PRDB3 DVSS2 PRDB4 PRDB5 PRDB6 PRDB7 DVDD1 LED0 LED1 DVSS1 LED2 LED3 DXCVR/EAR AVDD2 AVDD1 AVSS1 DVSS3 MASTER DRQ7 DRQ6 DRQ5 DVSS10 DACK7 DACK6 DACK5 LA17 LA18 LA19 LA20 DVSS4 LA21 LA22 LA23 SBHE DVDD3 DVSS5 DVSS6 SA10 SA11
Am79C961AKC
XTAL2 AVSS2 XTAL1 AVDD3 TXD+ TXPD+ TXD- TXPD- AVDD4 RXD+ RXD- DVSS13 SD15 SD14 DVSS9 SD13 SD12 DVDD7 SD11 SD10 DVSS8 SLEEP DVDD6
DVDD4 SA12 SA13 SA14 SA15 DVSS7 SA16 SA17 SA18 SA19 IOCHRDY MEMW MEMR DVSS11 IRQ15/APCS IRQ12/FLASHWE IRQ11 DVDD5 IRQ10 IOCS16 BALE IRQ3 IRQ4 IRQ5 DVSS12 DRQ3 DACK3 IRQ9 RESET
19364B-2
Am79C961A
DESIGNATIONS: MASTER MODE Listed Number
Name DVSS3 MASTER DRQ7 DRQ6 DRQ5 DVSS10 DACK7 DACK6 DACK5 LA17 LA18 LA19 LA20 DVSS4 LA21 LA22 LA23 SBHE DVDD3 DVSS5 DVSS6 SA10 SA11 Name DVDD4 SA12 SA13 SA14 SA15 DVSS7 SA16 SA17 SA18 SA19 IOCHRDY MEMW MEMR DVSS11 IRQ15/APCS IRQ12/FlashWE IRQ11 DVDD5 IRQ10 IOCS16 BALE IRQ3 IRQ4 IRQ5 DVSS12 DRQ3 DACK3 IRQ9 RESET Name DVDD6 SLEEP DVSS8 SD10 SD11 DVDD7 SD12 SD13 DVSS9 SD14 SD15 DVSS13 RXD- RXD+ AVDD4 TXPD- TXD- TXPD+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 Name AVSS1 AVDD1 AVDD2 DXCVR/EAR LED3 LED2 DVSS1 LED1 LED0 DVDD1 PRDB7 PRDB6 PRDB5 PRDB4 DVSS2 PRDB3 PRDB2/EEDO PRDB1/EEDI PRDB0/EESK SHFBUSY BPCS EECS DVDD2
Am79C961A
DESIGNATIONS: MASTER MODE Listed Name
Name AVDD1 AVDD2 AVDD3 AVDD4 AVSS1 AVSS2 BALE BPCS DACK3 DACK5 DACK6 DACK7 DRQ3 DRQ5 DRQ6 DRQ7 DVDD1 DVDD2 DVDD3 DVDD4 DVDD5 DVDD6 DVDD7 DVSS1 DVSS10 DVSS11 Name DVSS12 DVSS13 DVSS2 DVSS3 DVSS4 DVSS5 DVSS6 DVSS7 DVSS8 DVSS9 DXCVR/EAR EECS IOCHRDY IOCS16 IRQ10 IRQ11 IRQ12/FlashWE IRQ15/APCS IRQ3 IRQ4 IRQ5 IRQ9 LA17 LA18 LA19 LA20 LA21 LA22 LA23 LED0 LED1 Name LED2 LED3 MASTER MEMR MEMW PRDB0/EESK PRDB1/EEDI PRDB2/EEDO PRDB3 PRDB4 PRDB5 PRDB6 PRDB7 RESET RXD- RXD+ SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 Name SBHE SD10 SD11 SD12 SD13 SD14 SD15 SHFBUSY SLEEP TXD- TXD+ TXPD- TXPD+ XTAL1 XTAL2
Am79C961A
DESIGNATIONS: MASTER MODE Listed Group
Name Interface BALE DACK[3, 5-7] DRQ[3, 5-7] IOCHRDY IOCS16 IRQ[3, LA[17-23] MASTER MEMR MEMW RESET SA[0 -19] SBHE SD[0 -15] Board Interfaces IRQ15/APCS BPCS DXCVR/EAR LED0 LED1 LED2 LED3 PRDB[3-7] SLEEP XTAL1 XTAL2 SHFBUSY PRDB(0)/EESK PRDB(1)/EEDI PRDB(2)/EEDO EECS IRQ15 Address PROM Chip Select Boot PROM Chip Select Disable Transceiver LED0/LNKST LED1/SFBD/RCVACT LED2/SRD/RXDATPOL LED3/SRDCLK/XMTACT PROM Data Sleep Mode Crystal Input Crystal Output Read access from EEPROM process Serial Shift Clock Serial Shift Data Serial Shift Data EEPROM Chip Select Address Enable Address Latch Enable Acknowledge Request Channel Ready Chip Select Read Select Write Select Interrupt Request Unlatched Address Master Transfer Progress Memory Read Select Memory Write Select Memory Refresh Active System Reset System Address System Byte High Enable System Data TS3/OD3 Function Driver
Am79C961A
DESIGNATIONS: MASTER MODE (continued) Listed Group
Name Attachment Unit Interface (AUI) Twisted Pair Transceiver Interface (10BASE-T) RXD± TXD± TXPD± 10BASE-T Receive Data 10BASE-T Transmit Data 10BASE-T Predistortion Control Collision Inputs Receive Data Transmit Data Function Driver
IEEE 1149.1 Test Access Port Interface (JTAG) Power Supplies AVDD AVSS DVDD DVSS Analog Power [1-4] Analog Ground [1-2] Digital Power [1-7] Digital Ground [1-13] Test Clock Test Data Input Test Data Output Test Mode Select
Output Driver Types
Name Type Tri-State Tri-State Tri-State Open Drain (mA) (mA)
Am79C961A
DESCRIPTION: MASTER MODE
These pins part master mode. order understand descriptions, definition some terms from draft IEEE P996 included.
between back-to-back requests. Back-to-Back Requests section details. Because operation Plug Play registers, Channels PCnet-ISA must attached specific DACK signals PC/AT indicated names.
IEEE P996 Terminology
Alternate Master: device that take control through assertion MASTER signal. ability generate addresses control signals order perform operations. Alternate Masters must devices drive SBHE. Ownership: Current Master possesses ownership assert control, address data lines. Current Master: Permanent Master, Temporary Master Alternate Master which currently ownership bus. Permanent Master: Each P996 will have device known Permanent Master that provides certain signals control functions described Section IEEE P996 spec.), "Permanent Master". Permanent Master function reside Adapter backplane itself. Temporary Master: device that capable generating request obtain control directly asserting only memory strobes during transfer. Addresses generated device Permanent Master.
IOCHRDY
Channel Ready
Input/Output
When PCnet-ISA controller being accessed, IOCHRDY HIGH indicates that valid data exists data reads that data been latched writes. When PCnet-ISA controller Current Master bus, extends cycle long IOCHRDY LOW.
IOCS16
Chip Select
Output
When read write operation performed, PCnet-ISA controller will drive IOCS16 indicate that chip supports 16-bit operation this address. motherboard does receive this signal, then motherboard will convert 16-bit access 8-bit accesses). PCnet-ISA controller follows IEEE P996 specification that recommends this function implemented pure decode SA0-9 AEN, with dependency IOR, IOW; however, some PC/AT clone systems compatible with this approach. this reason, PCnet-ISA controller recommended configured 8-bit machines. Since data moved memory cycles there virtually performance loss incurred running 8-bit compatibility problems virtually eliminated. PCnet-ISA controller configured 8-bit-only clearing Plug Play register
Interface
Address Enable
Input
This signal must driven when performs access device.
BALE
Used latch LA20-23 address lines.
Read
Input
DACK
Acknowledge
Input
Asserted when Permanent Master acknowledges request. When DACK asserted PCnet-ISA controller becomes Current Master asserting MASTER signal.
driven host indicate that Input/ Output Read operation taking place. only valid signal external address matches PCnet-ISA controller's predefined address location. valid, indicates that slave read operation performed.
Request
Input/Output
Write
Input
When PCnet-ISA controller needs perform transfer, asserts DRQ. Permanent Master acknowledges with assertion DACK. When PCnet-ISA does need desserts DRQ. PCnet-ISA provides fair bandwidth sharing between mastering devices through adaptive delay which inserted
driven host indicate that Input/ Output Write operation taking place. only valid signal external address matches PCnet-ISA controller's predefined address location. valid, indicates that slave write operation performed.
Am79C961A
Interrupt Request
Output
(DRQ), Ethernet controller asserts MASTER signal indicate Permanent Master that PCnet-ISA controller becoming Current Master.
attention signal which indicates that more following status flags set: BABL, MISS, MERR, RINT, IDON, RCVCCO, JAB, MPCO, TXDATSTRT. status flags have mask which allows suppression assertion. These flags have following meaning:
BABL RCVCCO MISS MERR MPCO RINT IDON TXDATSTRT Babble Receive Collision Count Overflow Jabber Missed Frame Memory Error Missed Packet Count Overflow Receive Interrupt Initialization Done Transmit Start
MEMR
Memory Read Input/Output MEMR goes perform memory read operation.
MEMW
Memory Write Input/Output MEMW goes perfor memor operation.
Memory Refresh Input When asserted, memory refresh active. PCnet-ISA controller uses this signal mask inadvertent Acknowledge assertion during memory refresh periods. DACK asserted when active, DACK assertion ignored. monitored eliminate arbitration problem observed some platforms.
Because operation Plug Play registers, interrupts PCnet-ISA must attached specific signals PC/AT bus.
RESET
Reset Input When RESET asserted HIGH PCnet-ISA controller performs internal system reset. RESET must held minimum XTAL1 periods before being deasserted. While reset state, PCnet-ISA controller will tristate deassert outputs predefined reset levels. PCnet-ISA controller resets itself upon power-up.
LA17-23
Unlatched Address
Input/Output
unlatched address driven PCnet-ISA controller during master cycle. functions these unlatched address pins will change when GPSI mode invoked. following table shows configuration GPSI mode. Please refer section General Purpose Serial Interface detailed information accessing this mode.
Number Function Master Mode LA17 LA18 LA19 LA20 LA21 LA22 LA23 Function GPSI Mode RXDAT SRDCLK RXCRS CLSN STDCLK TXEN TXDAT
SA0-19
System Address Input/Output This contains address information, which stable during operation, regardless source. SA17-19 contain same values unlatched address LA17-19. When PCnet-ISA controller Current Master, SA0-19 will driven actively. When PCnet-ISA controller Current Master, SA0-19 lines continuously monitored determine address match exists slave transfers Boot PROM accesses.
SBHE
System Byte High Enable Input/Output This signal indicates high byte system data used. SBHE driven PCnet-ISA controller when performing mastering operations.
MASTER
Master Mode Input/Output This signal indicates that PCnet-ISA controller become Current Master bus. After PCnet-ISA controller received Acknowledge (DACK) response Request
SD0-15
System Data Input/Output These pins used transfer data from PCnet-ISA controller system resources data bus. SD0-15 driven PCnet-ISA control-
Am79C961A
when performing master writes slave read operations. Likewise, data SD0-15 latched PCnet-ISA controller when performing master reads slave write operations. EADI mode selected, this becomes input. incoming frame will checked against internally active address detection mechanisms result this check will OR'd with value pin. defined REJECT. (See EADI section details regarding function timing this signal).
Board Interface
IRQ12/FlashWE Flash Write Enable Output Optional interface Flash memory boot PROM Write Enable.
LEDO-3
Drivers Output These pins sink each driving LEDs. Their meaning software configurable (see section Configuration Registers) they active LOW. When EADI mode selected, pins named LED1, LED2, LED3 change function while LED0 continues indicate 10BASE-T Link Status.
EADI Function SF/BD SRDCLK
IRQ15/APCS
Address PROM Chip Select Output When programmed APCS Plug Play Register this signal asserted when external Address PROM read. When read operation performed first bytes PCnet-ISA controller's space, APCS asserted. outputs external Address PROM drive PROM Data Bus. PCnet-ISA controller buffers contents PROM data drives them lower eight bits System Data Bus. When programmed IRQ15 (default), this same function
BPCS
Boot PROM Chip Select Output This signal asserted when Boot PROM read. SA0-19 lines match predefined address block MEMR active inactive, BPCS signal will asserted. outputs external Boot PROM drive PROM Data Bus. PCnet-ISA controller buffers contents PROM data drives them lower eight bits System Data Bus.
PRDB3-7
Private Data Input/Output This data Boot PROM Address PROM.
PRDB2/EEDO
Private data 2/Data Input/Output multifunction which serves PRDB2 private data and, when ISACSR3 set, changes become DATA from EEPROM.
DXCVR/EAR
Disable Transceiver/ External Address Reject
PRDB1/EEDI
Input/Output
Private data 1/Data Input/Output multifunction which serves PRDB1 private data and, when ISACSR3 set, changes become DATA EEPROM.
This used disable external transceiver circuitry attached interface when internal 10BASE-T port active. polarity this DXCVRP (PnP register 0xF0, When DXCVRP cleared (default), DXCVR driven HIGH when Twisted Pair port active SLEEP mode been entered driven when port active. When DXCVRP set, DXCVR driven when Twisted Pair port active SLEEP mode been entered driven HIGH when port active.
PRDB0/EESK
Private data Serial Clock Input/Output multifunction which serves PRDB0 private data and, when ISACSR3 set, changes become Serial Clock EEPROM.
Am79C961A
SHFBUSY
Shift Busy Input/Output This indicates that read from external EEPROM progress. active only when data being shifted EEPROM hardware RESET assertion EE_LOAD (ISACSR3, 14). this left unconnected pulled with pull-down resistor, EEPROM checksum error forced. Normally, this should connected through pull-up resistor.
reset proceeds into power savings mode. outputs will placed their normal reset condition. PCnet-ISA controller inputs will ignored except SLEEP itself. Deassertion SLEEP results device waking system must delay starting network controller seconds allow internal analog circuits stabilize.
XTAL1
Crystal Connection Input internal clock generator uses crystal that attached pins XTAL1 XTAL2. Alternatively, external CMOS-compatible clock signal used drive this pin. Refer section External Crystal Characteristics more details.
EECS
EEPROM CHIP SELECT Output This signal asserted when read write accesses being performed EEPROM. controlled ISACSR3. driven Reset during EEPROM Read.
XTAL2
Crystal Connection Output internal clock generator uses crystal that attached pins XTAL1 XTAL2. external clock used, this should left unconnected.
SLEEP
Sleep Input When SLEEP asserted (active LOW), PCnet-ISA controller performs internal system
Am79C961A
CONNECTION DIAGRAMS: SLAVE MODE
PQFP
DVDD2 EECS BPCS SHFBUSY PRDB0/EESK PRDB1/EEDI PRDB2/EEDO PRDB3 DVSS2 PRDB4 PRDB5 PRDB6 PRDB7 DVDD1 LED0 LED1 DVSS1 LED2 LED3 DXCVR/EAR AVDD2 AVDD1 AVSS1 DVSS3 DVSS10 DVSS4 SA10 SA11 SA12 SBHE DVDD3 PRAB0 PRAB1 PRAB2 DVSS5 PRAB3 PRAB4 PRAB5 PRAB6 PRAB7 PRAB8 PRAB9 DVSS6 PRAB10 PRAB11
Am79C961AKC
XTAL2 AVSS2 XTAL1 AVDD3 TXD+ TXPD+ TXD- TXPD- AVDD4 RXD+ RXD- DVSS13 SD15 SD14 DVSS9 SD13 SD12 DVDD7 SD11 SD10 DVSS8 SLEEP DVDD6
DVDD4 PRAB12 PRAB13 PRAB14 PRAB15 DVSS7 SA13 SA14 SA15 SRWE IOCHRDY MEMW MEMR DVSS11 APCS/IRQ15 SRCS/IRQ12 IRQ11 DVDD5 IRQ10 IOCS16 BPAM IRQ3 IRQ4 IRQ5 DVSS12 SROE SMAM IRQ9 RESET
19364B-3
Am79C961A
BLOCK DIAGRAM: SLAVE MODE
802.3 Core DXCVR/EAR
IOCHRDY IRQ[3, IOCS16 MEMR MEMW RESET SA[0-15] SBHE Interface Unit
FIFO
CI+/Encoder/ Decoder (PLS) Port FIFO DI+/XTAL1 XTAL2 DO+/-
RXD+/10BASE-T TXD+/TXPD+/-
FIFO Control SD[0-15] Private Control
Buffer Management Unit SLEEP BPAM SMAM SHFBUSY EEDO EEDI EESK EECS
IRQ15/APCS BPCS LED[0-3] PRAB[0-15] PRDB[0-7] SROE SRWE
EEPROM Interface Unit JTAG Port Control
DVDD[1-7] DVSS[1-13] AVDD[1-4] AVSS[1-2]
19364B-4
Am79C961A
DESIGNATIONS: SLAVE MODE Listed Number
Name DVSS3 DVSS10 DVSS4 SA10 SA11 SA12 SBHE DVDD3 PRAB0 PRAB1 PRAB2 DVSS5 PRAB3 PRAB4 PRAB5 PRAB6 PRAB7 PRAB8 PRAB9 DVSS6 PRAB10 PRAB11 DVDD4 PRAB12 PRAB13 PRAB14 PRAB15 DVSS7 SA13 SA14 SA15 SRWE Name IOCHRDY MEMW MEMR DVSS11 IRQ15 IRQ12 IRQ11 DVDD5 IRQ10 IOCS16 BPAM IRQ3 IRQ4 IRQ5 DVSS12 SROE SMAM IRQ9 RESET DVDD6 SLEEP DVSS8 SD10 SD11 DVDD7 SD12 SD13 DVSS9 SD14 SD15 DVSS13 Name RXDRXD+ AVDD4 TXPDTXDTXPD+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 AVSS1 DODO+ AVDD1 DIDI+ CICI+ AVDD2 DXCVR/EAR LED3 LED2 DVSS1 LED1 LED0 DVDD1 PRDB7 PRDB6 PRDB5 PRDB4 DVSS2 PRDB3 PRDB2/EEDO PRDB1/EEDI PRDB0/EESK SHFBUSY BPCS EECS DVDD2
Am79C961A
DESIGNATIONS: SLAVE MODE Listed Name
Name AVDD1 AVDD2 AVDD3 AVDD4 AVSS1 AVSS2 BPAM BPCS CICI+ DIDI+ DODO+ DVDD1 DVDD2 DVDD3 DVDD4 DVDD5 DVDD6 DVDD7 DVSS1 DVSS10 DVSS11 DVSS12 DVSS13 DVSS2 DVSS3 DVSS4 DVSS5 DVSS6 DVSS7 DVSS8 DVSS9 DXCVR/EAR EECS IOCHRDY IOCS16 IRQ10 IRQ11 IRQ12 Pin# Name IRQ15 IRQ3 IRQ4 IRQ5 IRQ9 LED0 LED1 LED2 LED3 MEMR MEMW PRAB0 PRAB1 PRAB10 PRAB11 PRAB12 PRAB13 PRAB14 PRAB15 PRAB2 PRAB3 PRAB4 PRAB5 PRAB6 PRAB7 PRAB8 PRAB9 PRDB0/DO PRDB0/D1 PRDB0/SCLK PRDB3 PRDB4 PRDB5 PRDB6 PRDB7 RESET RXDRXD+ SA10 SA11 SA12 Pin# Name SA13 SA14 SA15 SBHE SD10 SD11 SD12 SD13 SD14 SD15 SHFBUSY SLEEP SMAM SROE SRWE TXDTXD+ TXPDTXPD+ XTAL1 XTAL2 Pin#
Am79C961A
DESIGNATIONS: SLAVE MODE Listed Group
Name Interface IOCHRDY IOCS16 IRQ[3, MEMR MEMW RESET SA[0-15] SBHE SD[0-15] Board Interfaces IRQ15/APCS BPCS BPAM DXCVR/EAR LED0 LED1 LED2 LED3 PRAB[0-15] PRDB[3-7] SLEEP SMAM SROE SRWE XTAL1 XTAL2 SHFBUSY PRDB(0)/EESK PRDB(1)/EEDI PRDB(2)/EEDO EECS IRQ15 Address PROM Chip Select Boot PROM Chip Select Boot PROM Address Match Disable Transceiver LED0/LNKST LED1/SFBD/RCVACT LED2/SRD/RXDATD01 LED3/SRDCLK/XMTACT PRivate Address PRivate Data Sleep Mode Slave Mode Architecture Shared Memory Address Match Static Output Enable Static Write Enable Crystal Oscillator Input Crystal Oscillator OUTPUT Read access from EEPROM process Serial Shift Clock Serial Shift Data Serial Shift Data EEPROM Chip Select Address Enable Channel Ready Chip Select Read Select Write Select Interrupt Request Memory Read Select Memory Write Select Memory Refresh Active System Reset System Address System Byte High Enable System Data TS3/OD3 Function Driver
Am79C961A
DESIGNATIONS: SLAVE MODE Listed Group
Name Attachment Unit Interface (AUI) Twisted Pair Transceiver Interface (10BASE-T) RXD± TXD± TXPD± 10BASE-T Receive Data 10BASE-T Transmit Data 10BASE-T Predistortion Control Collision Inputs Receive Data Transmit Data Function Driver
IEEE 1149.1 Test Access Port Interface (JTAG) Power Supplies AVDD AVSS DVDD DVSS Analog Power [1-4] Analog Ground [1-2] Digital Power [1-7] Digital Ground [1-13] Test Clock Test Data Input Test Data Output Test Mode Select
Output Driver Types
Name Type Tri-State Tri-State Tri-State Open Drain (mA) (mA)
Am79C961A
DESCRIPTION: SLAVE MODE Interface
IRQ3,
Interrupt Request Output attention signal which indicates that more following status flags set: BABL, MISS, MERR, RINT, IDON TXSTRT. status flags have mask which allows suppression assertion. These flags have following meaning:
BABL RCVCCO MISS MERR Babble Receive Collision Count Overflow Jabber Missed Frame Memory Error Missed Packet Count Overflow Receive Interrupt Initialization Done Transmit Start
Input Address Enable This signal must driven when performs access device.
IOCHRDY
Channel Ready Output When PCnet-ISA controller being accessed, HIGH IOCHRDY indicates that valid data exists data reads that data been latched writes.
IOCS16
Chip Select Input/Output When read write operation performed, PCnet-ISA controller will drive this indicate that chip supports 16-bit operation this address. motherboard does receive this signal, then motherboard will convert 16-bit access 8-bit accesses). PCnet-ISA controller follows IEEE P996 specification that recommends this function implemented pure decode SA0-9 AEN, with dependency IOR, IOW; however, some PC/AT clone systems compatible with this approach. this reason, PCnet-ISA controller recommended configured 8-bit machines. Since data moved memory cycles there virtually performance loss incurred running 8-bit compatibility problems virtually eliminated. PCnet-ISA controller configured 8-bit-only clearing Plug Play Register
MPCO RINT IDON TXSTRT
MEMR
Memory Read Input MEMR goes perfor memor read operation.
MEMW
Memory Write Input MEMW goes perform memory write operation.
Memory Refresh Input When asserted, memory refresh cycle progress. During refresh cycle, MEMR assertion ignored.
Read Input perform Input/Output Read operation device must asserted. only valid signal external address matches PCnet-ISA controller's predefined address location. valid, indicates that slave read operation performed.
RESET
Reset Input When RESET asserted HIGH, PCnet-ISA controller performs internal system reset. RESET must held minimum XTAL1 periods before being deasserted. While reset state, PCnet-ISA controller will tristate deassert outputs predefined reset levels. PCnet-ISA controller resets itself upon power-up.
Write Input perform Input/Output write operation device must asserted. only valid signal external address matches PCnet-ISA controller's predefined address location. valid, indicates that slave write operation performed.
SA0-15
System Address Input This carries address inputs from system address bus. Address data stable during command active cycle.
Am79C961A
SBHE
System High Enable Input This signal indicates HIGH byte system data used. There weak pull-up resistor this pin. PCnet-ISA controller installed 8-bit only system like PC/XT, SBHE will always HIGH PCnet-ISA controller will perform only 8-bit operations. There must least going edge this signal before PCnet-ISA controller will perform 16-bit operations.
DXCVR/EAR
Disable Transceiver/ External Address Reject Input/Output This disables transceiver. DXCVR output configured initialization sequence. high level indicates Twisted Pair Interface active inactive, SLEEP mode been entered. level indicates active Twisted Pair interface inactive. EADI mode selected, this becomes input. incoming frame will checked against internally active address detection mechanisms result this check will OR'd with value pin. defined REJECT. (See EADI section details regarding function timing this signal).
SD0-15
System Data Input/Output This used transfer data from PCnet-ISA controller system resources data bus. SD0-15 driven PCnet-ISA controller when performing slave read operations. Likewise, data SD0-15 latched PCnet-ISA controller when performing slave write operations.
LED0-3
Drivers Output These pins sink each driving LEDs. Their meaning software configurable (see section Configuration Registers) they active LOW. When EADI mode selected, pins named LED1, LED2, LED3 change function while LED0 continues indicate 10BASE-T Link Status. DXCVR input becomes input.
EADI Function SF/BD SRDCLK
Board Interface APCS/IRQ15
Address PROM Chip Select Output This signal asserted when external Address PROM read. When read operation performed first bytes PCnet-ISA controller's space, APCS asserted. outputs external Address PROM drive PROM Data Bus. PCnet-ISA controller buffers contents PROM data drives them lower eight bits System Data Bus. IOCS16 asserted during this cycle.
BPAM
Boot PROM Address Match Input This indicates Boot PROM access cycle. Boot PROM installed, this default value HIGH thus left connected VDD.
PRAB0-15
Private Address Input/Output Private Address address used drive Address PROM, Remote Boot PROM, SRAM.
BPCS
Boot PROM Chip Select Output This signal asserted when Boot PROM read. BPAM active MEMR active, BPCS signal will asserted. outputs external Boot PROM drive PROM Data Bus. PCnet-ISA controller buffers contents PROM data drives them System Data Bus. IOCS16 asserted during this cycle. 16-bit cycles performed, responsibility external logic assert MEMCS16 signal.
PRDB3-7
Private Data Input/Output This data static RAM, Boot PROM, Address PROM.
PRDB2/EEDO
Private Data 2/Data Input/Output multifunction which serves PRDB2 private data and, when ISACSR3 set, changes become DATA from EEPROM.
Am79C961A
PRDB1/EEDI
Private Data 1/Data Input/Output multifunction which serves PRDB1 private data and, when ISACSR3 set, changes become DATA EEPROM.
access Programmed access through PIOSEL (ISACSR2, 13).
SMAM
Shared Memory Input Address Match When Shared Memory architecture selected (ISACSR2, 13), this input that indicates access shared memory when asserted. type access decided MEMR MEMW. When Programmed architecture selected, this should permanently tied HIGH.
PRDB0/EESK
Private Data Serial Clock Input/Output multifunction which serves PRDB0 private data and, when ISACSR3 set, changes become Serial Clock EEPROM.
SHFBUSY
Shift Busy Input/Output This indicates that read from external EEPROM progress. active only when data being shifted EEPROM hardware RESET assertion EE_LOAD (ISACSR3, 14). this left unconnected pulled with pull-down resistor, EEPROM checksum error forced. Normally, this should connected through pull-up resistor.
SROE
Static Output Enable Output This directly controls external SRAM's pin.
SRCS/IRQ12
Static Chip Select Output This directly controls external SRAM's chip select (CS) when Flash boot option selected. When Flash boot option selected, this becomes IRQ12.
EECS
EEPROM CHIP SELECT Output This signal asserted when read write accesses being performed EEPROM. controlled ISACSR3. driven Reset during EEPROM Read.
SRWE/WE
Static Write Enable/ Write Enable Output This (SRWE) directly controls external SRAM's implemented. When Flash memory device implemented, this becomes global write enable (WE) pin.
SLEEP
Sleep Input When SLEEP input asserted (active LOW), PCnet-ISA controller performs internal system reset proceeds into power savings mode. outputs will placed their normal reset condition. PCnet-ISA controller inputs will ignored except SLEEP itself. Deassertion SLEEP results device waking system must delay starting network controller seconds allow internal analog circuits stabilize.
XTAL1
Crystal Connection Input internal clock generator uses crystal that attached pins XTAL1 XTAL2. Alternatively, external CMOS-compatible clock signal used drive this pin. Refer section External Crystal Characteristics more details.
Slave Mode Architecture Input This must permanently pulled operation Slave mode. sampled after hardware RESET sequence. Slave mode, PCnet-ISA programmed Shared Memory
XTAL2
Crystal Connection Output internal clock generator uses crystal that attached pins XTAL1 XTAL2. external clock used, this should left unconnected.
Am79C961A
DESCRIPTION: NETWORK INTERFACES CI+,
Control Input Input This differential input pair used detect Collision (Signal Quality Error Signal).
Test Data Output Output This test data output path from PCnet-ISA controller. tri-stated when JTAG port inactive.
Test Mode Select Input This serial input stream used define specific boundary scan test executed. left unconnected, this default value HIGH.
DI+,
Data Input This differential receive data input pair PCnet-ISA controller.
DESCRIPTION: POWER SUPPLIES
power pins with prefix digital pins connected digital circuitry digital buffers. power pins with prefix analog power pins connected analog circuitry. analog pins quiet special precaution must taken when doing board layout. Some analog pins more noisy than others must separated from other analog pins.
DO+,
Data Output This differential transmit data output pair from PCnet-ISA controller.
Twisted Pair Interface RXD+, RXD-
Receive Data Input This 10BASE-T port differential receive input pair.
AVDD1-4
Analog Power Pins) Power Supplies power analog portions PCnet-ISA controller. Special attention should paid printed circuit board layout avoid excessive noise these lines.
TXD+, TXD-
Transmit Data Output These 10BASE-T port differential transmit drivers.
TXP+, TXP-
Transmit Predistortion Control Output These 10BASE-T transmit waveform pre-distortion control differential outputs.
AVSS1-2
Analog Ground Pins) Power Supplies ground reference analog portions PCnet-ISA controller. Special attention should paid printed circuit board layout avoid excessive noise these lines.
DESCRIPTION: IEEE 1149.1 (JTAG) TEST ACCESS PORT
Test Clock Input This clock input boundary scan test mode operation. operate MHz. does have internal pull-up resistor must connected valid level high low. must left unconnected.
DVDD1-7
Digital Power Pins) Power Supplies power digital portions PCnet-ISA controller. Four pins used Input/Output buffer drivers used internal digital circuitry.
DVSS1-13
Digital Ground Pins) Power Supplies ground reference digital tions PCnet-ISA controller. pins used Input/Output buffer drivers used internal digital circuitry.
Test Data Input Input This test data input path PCnet-ISA controller. left unconnected, this default value HIGH.
Am79C961A
CONNECTION DIAGRAM
TQFP
Am79C961AVC
19364B-5
Am79C961A
DESIGNATIONS: MASTER MODE (TQFP 144) Listed Number
Name DVSS3 MASTER DRQ7 DRQ6 DRQ5 DVSS10 DACK7 DACK6 DACK5 LA17 LA18 LA19 LA20 DVSS4 LA21 SA22 SA23 SBHE DVDD3 DVSS5 DVSS6 SA10 SA11 Name DVDD4 SA12 SA13 SA14 SA15 DVSS7 SA16 SA17 SA18 SA19 IOCHRDY MEMW MEMR DVSS11 IRQ15/APCS IRQ12/FlashWE IRQ11 DVDD5 IRQ10 IOCS16 BALE IRQ3 IRQ4 IRQ5 DVSS12 DRQ3 DACK3 IRQ9 RESET Name DVDD6 SLEEP DVSS8 SD10 SD11 DVDD7 SD12 SD13 DVSS9 SD14 SD15 DVSS13 RXD- RXD+ AVDD4 TXPD- TXD- TXPD+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 Name AVSS1 AVDD1 AVDD2 DXCVR/EAR LED3 LED2 DVSS1 LED1 LED0 DVDD1 PRDB7 PRDB6 PRDB5 PRDB4 DVSS2 PRDB3 PRDB2/EEDO PRDB1/EEDI PRDB0/EESK SHFBUSY BPCS EECS DVDD2
Am79C961A
DESIGNATIONS: MASTER MODE (TQFP 144) Listed Name
Name AVDD1 AVDD2 AVDD3 AVDD4 AVSS1 AVSS2 BALE BPCS DACK3 DACK5 DACK6 DACK7 DRQ3 DRQ5 DRQ6 DRQ7 DVDD1 DVDD2 DVDD3 DVDD4 DVDD5 DVDD6 DVDD7 DVSS1 DVSS10 DVSS11 DVSS12 DVSS13 DVSS2 Name DVSS3 DVSS4 DVSS5 DVSS6 DVSS7 DVSS8 DVSS9 DXCVR/EAR EECS IOCHRDY IOCS16 IRQ10 IRQ11 IRQ12/FlashWE IRQ15/APCS IRQ3 IRQ4 IRQ5 IRQ9 LA17 LA18 LA19 LA20 LA21 LED0 LED1 LED2 LED3 MASTER MEMR MEMW Name PRDB0/EESK PRDB1/EEDI PRDB2/EEDO PRDB3 PRDB4 PRDB5 PRDB6 PRDB7 RESET RXD+ RXD- SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA22 SA23 Name SBHE SD10 SD11 SD12 SD13 SD14 SD15 SHFBUSY SLEEP TXD+ TXD- TXPD+ TXPD- XTAL1 XTAL2
Am79C961A
DESIGNATIONS: SLAVE (PIO SHARED MEMORY) MODES (TQFP 144) Listed Number
Name DVSS3 DVSS10 DVSS4 SA10 SA11 SA12 SBHE DVDD3 PRAB0 PRAB1 PRAB2 DVSS5 PRAB3 PRAB4 PRAB5 PRAB6 PRAB7 PRAB8 PRAB9 DVSS6 PRAB10 PRAB11 Name DVDD4 PRAB12 PRAB13 PRAB14 PRAB15 DVSS7 SA13 SA14 SA15 SRWE IOCHRDY MEMW MEMR DVSS11 IRQ15 IRQ12 IRQ11 DVDD5 IRQ10 IOCS16 BPAM IRQ3 IRQ4 IRQ5 DVSS12 SROE SMAM IRQ9 RESET PCMCIA_MODE Name DVDD6 SLEEP DVSS8 SD10 SD11 DVDD7 SD12 SD13 DVSS9 SD14 SD15 DVSS13 RXDRXD+ AVDD4 TXPDTXDTXPD+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 Name AVSS1 DODO+ AVDD1 DIDI+ CICI+ AVDD2 DXCVR/EAR LED3 LED2 DVSS1 LED1 LED0 DVDD1 PRDB7 PRDB6 PRDB5 PRDB4 DVSS2 PRDB3 PRDB2/ EEDO PRDB1/EEDI PRDB0/EESK SHFBUSY BPCS EECS DVDD2
Am79C961A
DESIGNATIONS: SLAVE (PIO SHARED MEMORY) MODES (TQFP 144) Listed Name
Name AVDD1 AVDD2 AVDD3 AVDD4 AVSS1 AVSS2 BPAM BPCS DVDD1 DVDD2 DVDD3 DVDD4 DVDD5 DVDD6 DVDD7 DVSS1 DVSS10 DVSS11 DVSS12 DVSS13 DVSS2 DVSS3 DVSS4 DVSS5 DVSS6 DVSS7 DVSS8 DVSS9 DXCVR/EAR Name EECS IOCHRDY IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ3 IRQ4 IRQ5 IRQ9 LED0 LED1 LED2 LED3 MEMR MEMW PCMCIA_MODE PRAB0 PRAB1 PRAB10 PRAB11 PRAB12 Name PRAB13 PRAB14 PRAB15 PRAB2 PRAB3 PRAB4 PRAB5 PRAB6 PRAB7 PRAB8 PRAB9 PRDB0/EESK PRDB1/EEDI PRDB2/EEDO PRDB3 PRDB4 PRDB5 PRDB6 PRDB7 RESET RXD+ RXD- SA10 SA11 SA12 SA13 SA14 SA15 Name SBHE SD10 SD11 SD12 SD13 SD14 SD15 SHFBUSY SLEEP SMAM SROE SRWE TXD+ TXD- TXPD+ TXPD- XTAL1 XTAL2
Am79C961A
BLOCK DIAGRAM: PCMCIA MODE
WAIT INPACK STSCHG IORD IOWR IREQ IOIS16 RESET A[0-15] FIFO Control Private Control RXD± 10BASE-T TXD± TXPD± PCMCIA Interface Unit FIFO 802.3 Core DXCVR/EAR
Encoder/ Decoder (PLS) Port FIFO XTAL1 XTAL2
D[0-15]
PCMCIA_MODE SLEEP SMAM SHFBUSY EEDO EEDI EESK EECS
Buffer Management Unit
FLCS LED[0-3] PRAB[0-15] PRDB[0-7] SROE SRWE SRCS
EEPROM Interface Unit JTAG Port Control
Optional
DVDD[1-7] DVSS[1-13] AVDD[1-4] AVSS[1-2]
19364B-6
Am79C961A
DESIGNATIONS: PCMCIA MODE (TQFP 144) Listed Number
Name DVSS3 DVSS10 DVSS4 SA10 SA11 SA12 DVDD3 PRAB0 PRAB1 PRAB2 DVSS5 PRAB3 PRAB4 PRAB5 PRAB6 PRAB7 PRAB8 PRAB9 DVSS6 PRAB10 PRAB11 Name DVDD4 PRAB12 PRAB13 PRAB14 PRAB15 DVSS7 SA13 SA14 SA15 SRWE WAIT DVSS11 SRCS INPACK DVDD5 STSCHG IOIS16 IREQ DVSS12 SROE SMAM IORD IOWR RESET PCMCIA_MODE Name DVDD6 SLEEP DVSS8 SD10 SD11 DVDD7 SD12 SD13 DVSS9 SD14 SD15 DVSS13 RXD- RXD+ AVDD4 TXPD- TXD- TXPD+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 Name AVSS1 AVDD1 AVDD2 DXCVR/EAR LED3 LED2 DVSS1 LED1 LED0 DVDD1 PRDB7 PRDB6 PRDB5 PRDB4 DVSS2 PRDB3 PRDB2/EEDO PRDB1/EEDI PRDB0/EESK SHFBUSY FLCS EECS DVDD2
Am79C961A
DESIGNATIONS: PCMCIA MODE (TQFP 144) Listed Name
Name AVDD1 AVDD2 AVDD3 AVDD4 AVSS1 AVSS2 DVDD1 DVDD2 DVDD3 DVDD4 DVDD5 DVDD6 DVDD7 DVSS1 DVSS10 DVSS11 DVSS13 DVSS2 DVSS3 DVSS4 DVSS5 DVSS6 DVSS7 DVSS8 DVSS9 DXCVR/EAR EECS FLCS Name INPACK IOIS16 IORD IOWR IREQ LED0 LED1 LED2 LED3 PCMCIA_MODE PRAB0 PRAB1 PRAB10 PRAB11 PRAB12 PRAB13 PRAB14 PRAB15 PRAB2 PRAB3 Name PRAB4 PRAB5 PRAB6 PRAB7 PRAB8 PRAB9 PRDB0/EESK PRDB1/EEDI PRDB2/EEDO PRDB3 PRDB4 PRDB5 PRDB6 PRDB7 RESET RXD+ RXD- SA10 SA11 SA12 SA13 SA14 SA15 Name SD10 SD11 SD12 SD13 SD14 SD15 SHFBUSY SLEEP SMAM SMAM SRCS SROE SRWE STSCHG TXD+ TXD- TXPD+ TXPD- WAIT XTAL1 XTAL2
Am79C961A
DESCRIPTION: PCMCIA MODE
PCMCIA pins function described PCMCIA Specification Revision 2.1. Please refer more details. non-PCMCIA pins used 144-pin TQFP package have same functions described "Pin Description: Slave Mode" operation beginning page Am79C961A PCnet-ISA data sheet (PID #19364A) with exception PCMCIA_MODE. PCMCIA_MODE
Input
Sets device PCMCIA operation when tied high. This available 132-pin PQFP package option.
Am79C961A
PCMCIA Pinout Comparison
pins listed below definition changes specific PCMCIA mode: PCMCIA mode, number input pins have internal resistors turned with
resistance greater than These resistors either connected diagram below shows connections slave mode PCMCIA mode.
PCMCIA Input Resistance
Number TQFP144
Slave Mode SBHE IOCHRDY MEMW MEMR IRQ15 IRQ12 IRQ11 IRQ10 IOCS16 BPAM IRQ3 IRQ4 IRQ5 IRQ9 RESET PCMCIA_MODE1 SLEEP SD0-SD15 SA0-SA15
PCMCIA Mode WAIT SRCS INPACK STSCHG IOIS16 IREQ IORD IOWR RESET PCMCIA_MODE2 SLEEP3 D0-D15 A0-A15
PCMCIA Specification Changes
mode, IOCHRDY IOCS16 signals defined Open Drain outputs. PCMCIA mode, WAIT IOIS16 signals full CMOS drivers. PCMCIA mode, values tIOR8, tMR8 tSFR10 change from
PCMCIA-MODE1 should tied slave mode PCMCIA-MODE2 should tied PCMCIA mode SLEEP3 remains functional PCMCIA mode, recommended
Am79C961A
PCMCIA MODE BLOCK DIAGRAM
A[1-19] A[0]
D[0-7] Flash/EPROM
SA[0-15] System Address PCMCIA PCMCIA Control PCnet-ISA Controller
PRDB[0-7] FLCS SROE PRAB[0-15]
A[0-15] SRWE 16-Bit System Data SD[0-15] SMAM SRCS SRAM
D[0-7]
(Upper Address pin)
19364B-7
Note: SMAM shown only Shared Memory architecture designs. SMAM should tied HIGH PCnet-ISA Programmed architecture designs order access flash memory common memory location zero.
Plug Play Compatible with Flash Memory Support
Am79C961A
FUNCTIONAL DESCRIPTION PCMCIA Operation
When PCMCIA card first plugged into PCMCIA host, PCMCIA cards respond memory only device. PCMCIA standard there memory spaces, common memory attribute memory. determines which memory space selected. After host detects that PCMCIA card inserted, host reads section attribute memory called (Card Information Structure) which provides configuration information about inserted card. attribute memory byte wide memory which only addressable even bytes. Consequently, byte accesses defined attribute memory. Mapped area four Card Configuration Registers which physically located inside PCnet-ISA device. PCnet-ISA device there four registers which located decimal byte address 1008, 1010, 1012 1014, respectively. Inside data structure, there information which provides base address Card Configuration Registers. Inside first Card Configuration Register configuration index region which allows programming device support accesses. PCnet-ISA supports PCMCIA's Independent address window mechanism. When Enable register PCnet-ISA controller will respond commands. lower address bits decode register accesses. PCMCIA host expected decode address bits above only assert and/or upper address lines match. After host mapped PCMCIA's card resources system, card should visible system driver loaded.
EEPROM. cost purposes, recommended place IEEE address (Card Information Structure) Attribute Memory.
Flash Memory
PCnet-ISA device supports either single Flash EPROM device. external flash device contains area well area located common memory used hold software drivers. attribute memory origin located byte common memory region accessed when deasserted access common memory occurs. SMAM normally connected upper address line PCMCIA card. When high order address asserted Flash Memory will selected. Accesses common memory when SMAM will access Shared when Shared Memory mode selected. Programmed mode used, SMAM tied high which will result Flash's base address being mapped location zero.
Flash Memory Programming
Flash Memory device read anytime. order program flash device, APWEN must ISACSR2 register allow write operations Flash non-volatile EEPROM device.
Shared Memory Programmed Implications
PCnet-ISA controller PCMCIA modes allows local packet buffer memory mapped into common memory indirectly accessed through accesses. shared memory chosen, local SRAM will mapped memory resource. Consequently, will have indicate this requirement system. Programmed used additional memory resources will required allocated system.
Serial EEPROM Support
Serial EEPROM required PCMCIA mode used hold contents IEEE address
Am79C961A
FLASH MEMORY CARD REGISTERS
131070 Byte (1FFFEh)
Common Memory
FLASH Common Memory
1024 Byte (400h) 1022 Byte (3FEh) Reserved 1016 Byte (3F8h) Attribute Memory (Not Available) Data 1014 Byte (3F6h) 1012 Byte (3F4h) 1010 Byte (3F2h) 1008 Byte (3F0h) 1006 Byte (3EEh)
(Unused)
Byte (0h)
19364B-8
Am79C961A
FUNCTIONAL DESCRIPTION
PCnet-ISA controller highly integrated system solution PC-AT architecture. provides Full Duplex Ethernet controller, port, 10BASE-T transceiver. PCnet-ISA controller directly interfaced system bus. PCnet-ISA controller contains interface unit, Buffer Management Unit, 802.3 Media Access Control function, separate 136-byte transmit 128-byte receive FIFOs, IEEE defined Attachment Unit Interface (AUI), Twisted-Pair Transceiver Media Attachment Unit. addition, Sleep function been incorporated which provides standby current power sensitive applications. PCnet-ISA controller register compatible with LANCE (Am7990) Ethernet controller PCnet-ISA (Am79C960). Buffer Management Unit supports LANCE descriptor software model PCnet-ISA controller software compatible with Novell NE2100 NE1500T add-in cards. External remote boot PROMs Ethernet physical address PROMs supported. location registers, Ethernet address PROM, boot PROM determined programming registers internal PCnet-ISA These registers loaded RESET from EEPROM, EEPROM utilized. Normally, Ethernet physical address will stored EEPROM with other configuration data. This reduces parts count, board space requirements, power consumption. option standard parallel PROM provided manufactures concerned about non-volatile nature EEPROMs. PCnet-ISA controller's master architecture brings system manufacturers (adapter card motherboard makers alike) something they have been able enjoy with other architectures-a low-cost system solution that provides lowest parts count highest performance. bus-mastering device, costly power-hungry external SRAMs needed packet buffering. This results lower system cost fewer components, less real-estate less power. PCnet-ISA controller's advanced mastering architecture also provides high data throughput utilization even better performance. offer greater flexibility, PCnet-ISA controller Slave mode meet varying application needs. slave mode utilizes local SRAM memory store descriptors buffers that located system memory when Master mode. SRAM slave accessed through memory cycles Shared Memory mode cycles Programmed mode. Shared Memory Programmed architectures offer maximum compatibility with low-end machines, such PC/XTs that support mastering, very high machines
which require local packet buffering increased system latency. network interface provides Attachment Unit Interface Twisted-Pair Transceiver functions. Only interface active particular time. allows connection isolation transformer 10BASE5 10BASE2, thick thin based coaxial cables. Twisted-Pair Transceiver interface allows connection unshielded twisted-pair cables specified Section supplement IEEE 802.3 Standard (Type 10BASE-T).
Important Note About EEPROM Byte
user cautioned that while Am79C961A (PCnet-ISA associated EEPROM compatible their predecessors Am79C961 (PCnet-ISA+) associated EEPROM, byte structure each EEPROMs different from each other. EEPROM byte structure used Am79C961A PCnet-ISA addition "MISC Config ISACSR9" word location 10Hex. EEPROM byte structure used Am79C961 PCnet-ISA+ does have this. Therefore, should user intend replace PCnet-ISA+ with PCnet-ISA care MUST taken reprogram EEPROM reflect byte structure needed used PCnet-ISA additional information, refer section this data sheet under EEPROM Am79C961 PCnet-ISA+ data sheet (PID #18183) under sections entitled EEPROM Serial EEPROM Byte Map.
Master Mode
System Interface PCnet-ISA controller fundamental operating modes, Master Slave. Within Slave mode, PCnet-ISA programmed Shared Memory Programmed architecture. selection either Master mode Slave mode must done through hard wiring; software configurable. When Slave mode, selection Shared Memory Programmed architecture done through software with PIOSEL (ISACSR2, 13). optional Boot PROM memory address space expected 8-64K. On-chip address comparators control device selection based value EEPROM. address PROM, board configuration registers, Ethernet controller occupy bytes space located different starting addresses.
Am79C961A
16-Bit System Data SD[0-15]
BPCS PRDB[0-7]
D[0-7]
PRDB[2]/EEDO PCnet-ISA PRDB[1]/EEDI Controller PRDB[0]/EESK 24-Bit System Address SA[0-19] LA[17-23] SHFBUSY EECS
Boot PROM (Optional)
A[0-15]
EEPROM (Optional, Common)
19364B-9
Master Block Diagram Plug Play Compatible
SD[0-15] 16-Bit System Data PCnet-ISA Controller
BPCS PRDB[0-7] PRDB[0]/EESK PRDB[1]/EEDI PRDB[2]/EEDO
A[0-4] D[0-7]
IEEE Address PROM (Optional)
A[0-15] D[0-7] Flash (Optional)
24-Bit System Address
SA[0-19] LA[17-23]
EECS
IRQ15/APCS IRQ12/FlashWE SHFBUSY
EEPROM (Optional, Common)
19364B-10
Master Block Diagram Plug Play Compatible with Flash parallel Address PROM Support
Am79C961A
Slave Mode
System Interface Slave mode other fundamental operating mode available PCnet-ISA controller. Within Slave mode, PCnet-ISA programmed Shared Memory Programmed architecture. Slave mode PCnet-ISA controller uses same descriptor buffer architecture Master mode, these data structures stored static controlled PCnet-ISA controller. When operating with Shared Memory architecture, local SRAM visible memory resource which accessed through memory cycles interface. When operating with Programmed architecture, local SRAM accessible through cycles bus. Specifically, SRAM accessible using ports access ISACSR0 ISACSR1 registers, which serve SRAM Data port SRAM Address Pointer port, respectively. Slave mode, PCnet-ISA registers optional Ethernet physical address PROM look same accessed same Master mode. Boot PROM selected external device which drives Boot PROM Address Match (BPAM) input PCnet-ISA controller. PCnet-ISA controller perform 8-bit accesses from 8-bit Boot PROM present 16-bits data accommodate read accesses bus. When using Shared Memory architecture mode, access local SRAM works same access Boot PROM, with external device generating Shared Memory Address Match (SMAM) signal PCnet-ISA controller performing SRAM read write 8/16 data conversion. External logic must also drive MEMCS16 appropriately 128Kbyte segment decoded from LA[23:17] signals.
Programmed architecture mode uses ports allow access local SRAM hence, external address decoding necessary SMAM used Programmed architecture mode (SMAM should tied HIGH Programmed architecture mode). Similar Shared Memory architecture mode, Programmed architecture mode, 8/16 conversion occurs when reads writes performed SRAM Data Port (ISACSR1). Converting local SRAM accesses from 8-bit cycles 16-bit cycles allows much faster 16-bit cycle timing while cutting number cycles half. This raises performance more than 400% what could achieved with 8-bit cycles. When Shared Memory architecture mode used, converting boot PROM accesses 16-bit cycles allows memory resources same Kbyte block memory without clash between devices with different data widths. PCnet-ISA prefetches data from SRAM allow fast, minimum wait-state read accesses consecutive SRAM addresses. both Shared Memory architecture Programmed architecture, prefetch data read from speculated address that assumes that successive reads time will from adjacent ascending addresses SRAM. beginning each SRAM read cycle, PCnet-ISA determines whether prefetched data assumed valid. prefetched data assumed valid, driven onto without inserting wait states. prefetched data cannot assumed valid, PCnet-ISA will insert wait states into read cycle until correct word read from SRAM.
Am79C961A
A[0-15] Flash (Optional)
D[0-7]
16-Bit System Data SD[0]
PRAB[0-15]
PRDB[0] BPCS SROE PRDB[2]/EEDO PRDB[1]/EEDI PRDB[0]/EESK
24-Bit System Address
PCnet-ISA Controller SA[0]
EEPROM
EECS SRWE SHFBUSY SMAM BPAM IRQ12/SRCS
A[0-15] SRAM
D[0-7] MEMCS16
BPAM
External Glue Logic SMAM SHFBUSY SA[16] LA[17-23]
19364B-11
Note: SMAM shown only Shared Memory architecture designs. SMAM should tied HIGH PCnet-ISA Programmed architecture designs.
Slave Block Diagram Plug Play Compatible with Flash Memory Support
Am79C961A
PLUG PLAY
Plug Play standardized method configuring jumperless adapter cards system. Plug Play Microsoft standard based central software configuration program, either operating system elsewhere, which responsible configuring Plug Play cards system. Plug Play fully supported PCnet-ISA ethernet controller. copy Microsoft Plug Play specification contact Microsoft Inc. This specification should referenced addition PCnet-ISA Technical Reference Manual this data sheet.
Port Name ADDRESS WRITE-DATA Location 0X279 (Printer Status Port) 0xA79 (Printer status port 0x0800) Relocatable range 0x0203-0x03FF Type Write-only Write-only
READ-DATA
Read-only
Operation
PCnet-ISA ethernet controller used boot network, device will come active RESET, otherwise will come inactive. Information stored serial EEPROM used identify card describe system resources required card, such space, Memory space, IRQs channels. This information stored standardized Read Only format. Operation Plug Play system shown follows: Isolate Plug Play card Read cards resource data Identify card Configure resources Plug Play mode operation allows following benefits user. Eliminates jumpers switches from adapter card Ease greatly enhanced Allows ability uniquely address identical cards system, without conflict Allows software configuration program read system resource requirements required card Defines mechanism modify current configuration each card Maintain backward compatibility with other adapters
address Write_DATA ports located fixed, predefined addresses. Write_Data port located alias Address port. three auto-configuration ports 12-bit address decode. READ_DATA port relocatable within range WRITE_DATA port. ADDRESS PORT internal Plug Play registers accessed writing address ADDRESS PORT then either reading READ_DATA PORT writing WRITE_DATA PORT. Once ADDRESS PORT been written, number reads writes occur without having rewrite ADDRESS PORT. ADDRESS PORT also address which initiation written which described later. WRITE_DATA PORT WRITE_DATA PORT address which writes internal Plug Play registers occur. destination data written WRITE_DATA PORT determined last value written ADDRESS PORT. READ_DATA PORT READ_DATA PORT used read information from internal Plug Play registers. register read determined last value ADDRESS PORT. address READ_DATA PORT writing chosen location Plug Play Register isolation protocol determine that address chosen free from conflict with other devices ports.
Auto-Configuration Ports
Three ports used Plug Play configuration software each Plug Play device communicate with Plug Play registers. ports listed table below. software configuration space defined registers. These registers used Plug Play software configuration issue commands, access resource information, check status, configure PCnet-ISA controller hardware.
Initiation
PCnet-ISA controller disabled reset when operating Plug Play mode. will respond memory accesses, will PCnet-ISA controller drive interrupts channels. initiation places PCnet-ISA device into configuration mode. This done writing predefined pattern ADDRESS PORT. proper sequence writes detected PCnet-ISA device, Plug Play auto-configuration ports
Am79C961A
enabled. This pattern must sequential, i.e., other access this port will reset state machine which checking pattern. Interrupts should disabled during this time eliminate extraneous cycles. exact sequence initiation listed below hexadecimal. element this mechanism that each card contains unique number, referred serial identifier rest discussion. serial identifier 72-bit unique, non-zero, number composed two, 32-bit fields 8-bit checksum. first 32-bit field vendor identifier. other bits value, example, serial number, part address, static number, long there will never cards single system with same number. serial identifier accessed bit-serially isolation logic used differentiate cards.
Isolation Protocol
simple algorithm used isolate each Plug Play card. This algorithm uses signals requires lock-step operation between Plug Play hardware isolation software.
Checksum
Serial Vendor Number Byte Byte Byte Byte Byte Byte Byte Byte Byte
Shift
19364B-13
Shifting Serial Identifier
State Isolation Read from serial isolation register from serial identifier
shift order Plug Play serial isolation resource data defined bit[0], bit[1], through bit[7].
Hardware Protocol
isolation protocol invoked Plug Play software time. initiation key, described earlier, puts cards into configuration mode. hardware each card expects pairs read accesses READ_DATA card's response these reads depends value each serial identifier which being examined time sequence shown above. current serial identifier "1", then card will drive data 0x55 complete first read cycle. "0", then card puts data driver into high impedance. cards high impedance will check data during read cycle sense another card driving D[1:0] "01". During second read, card(s) that drove 0x55, will drive 0xAA. high impedance cards will check data sense another card driving D[1:0] "10". Between pairs Reads, software should wait least high impedance card sensed another card driving data with appropriate data during both cycles, then that card ceases participate current iteration card isolation. Such cards, which lose out, will participate future iterations isolation protocol.
19364B-12
"1H"
Drive "55H" SD[7:0]
Leave high-impedance SD[1:0] "01"
Wait next read from serial isolation register Drive "AAH" SD[7:0] Leave high-impedance After read completes, fetch next from serial identifier Read bits from serial identifier Card Isolated SD[1:0] "10" other card
State Sleep
Plug Play Card Isolation Algorithm
Note: During each read cycle, Plug Play hardware drives entire 8-bit databus, only checks lower bits.
Am79C961A
card driving card high impedance sense another card driving bus, then should prepare next pair reads. card shifts serial identifier uses shifted decide response. above sequence repeated entire 72-bit serial identifier. this process, card remains. This card assigned handle referred Card Select Number (CSN) that will used later select card. Cards which have been assigned will participate subsequent iterations isolation protocol. Cards must assigned before they will respond other commands defined specification. should noted that protocol permits 8-bit checksum stored non-volatile memory card generated on-card logic real-time. same LFSR algorithm described initiation section Plug Play specification used checksum generation. During first bits, software generates checksum using received data. checksum compared with checksum read back last bits sequence. There other special considerations software protocol. During iteration, possible that 0x55 0xAA combination never detected. also possible that checksum does match either these cases occur first iteration, must assumed that READ_DATA port conflict. conflict detected, then READ_DATA port relocated. above process repeated until nonconflicting location READ_DATA port found. entire range between 0x203 0x3FF available, however practice expected that only locations will tried before software determines that Plug Play cards present. During subsequent iterations, occurrence either these special cases should interpreted absence further Plug Play cards (i.e. last card found previous iteration). This terminates isolation protocol.
Software Protocol
Plug Play software sends initiation Plug Play cards place them into configuration mode. software then ready perform isolation protocol. Plug Play software generates pairs read cycles from READ_DATA port. software checks data returned from each pair reads 0x55 0xAA driven hardware. both 0x55 0xAA read back, then software assumes that hardware that position. other results assumed "0."
Note: software must delay prior starting first pair isolation reads, must wait µsec between each subsequent pair isolation reads. This delay gives card time access information from possibly very slow storage devices.
Plug Play Card Control Registers
state transitions card control commands PCnet-ISA controller shown following figure.
Am79C961A
Power RESET_DRV State Active Commands active commands Initiation State Active Commands Reset Wait Wake[CSN]
Wait
Sleep
Lose serial location WAKE (WAKE CSN) State Active Commands Reset Wait RD_DATA Port Serial Isolation Wake[CSN] State Active Commands Reset Wait Wake[CSN] Resource Data Status Logical Device Range Check Activate Configuration Registers
Isolation
Config
Notes: Card Select Number. RESET_DRV causes state transition from current state Wait sets CSNs zero. logical devices their power-up configuration values. Wait command causes state transition from current state Wait Key.
19364B-14
Plug Play Card State Transitions
Plug Play Registers PCnet-ISA controller supports defined Plug Play card control registers. Refer tables following pages detailed information.
Am79C961A
Plug Play Standard Registers
Name RD_DATA Port Address Port Value 0x00 Definition Writing this location modifies address port used reading from Plug Play cards. Bits[7:0] become read port address bits [9:2]. Reads from this register ignored. Address bits 11:10 should Serial Isolation 0x01 read this register causes Plug Play card Isolation state compare board's This process fully described above. This register read only. Bit[0] Reset logical devices restore configuration registers their power-up values. Bit[1] Return Wait state Bit[2] Reset write bit[0] this register performs reset function logical devices. This resets contents configuration registers their default state. card's logical devices enter their default state preserved. write bit[1] this register causes cards enter Wait state CSNs preserved logical devices affected. write bit[2] this register causes cards reset their zero. This register write-only. values sticky, that hardware will automatically clear them there need software clear bits. Wake[CSN] 0x03 write this port will cause cards that have that matches write data[7:0] from Sleep state either Isolation state write data this command zero Config state write data zero. This register write-only. Writing this register resets EEPROM pointer beginning Plug Play Data Structure. read from this address reads next byte resource information. Status register must polled until bit[0] before this register read. This register read-only. Bit[0] when indicates okay read next data byte from Resource Data register. This register read-only. write this port sets card's CSN. value uniquely assigned each card after serial identification process that each card individually selected during Wake [CSN] command. This register read/write. Selects current logical device. This register read only. PCnet-ISA controller only logical device, this register contains value 0x00
Config Control
0x02
Resource Data
0x04
Status Card Select Number
0x05 0x06
Logical Device Number
0x07
Am79C961A
Plug Play Logical Device Configuration Registers
PCnet-ISA controller supports subset defined Plug Play logical device control registers. reason only supporting subset registers that PCnet-ISA controller does require many system resources Plug Play allows. instance, Memory Descriptor used, PCnet-ISA controller only requires memory descriptors, Boot PROM/Flash, SRAM Shared Memory Mode.
Plug Play Logical Device Control Registers Name Activate Address Port Value 0x30 Definition each logical device there activate register that controls whether logical device active bus. Bit[0], set, activates logical device. Bits[7:1] reserved must zero. This read/write register. Before logical device activated, range check must disabled. This register used perform conflict check port range programmed logical device. Bit[7:2] Reserved 1[1] Enable Range check, then Range Check enabled. range check only valid when logical device inactive. Bit[0], set, forces logical device respond reads logical device's assigned range with 0x55 when range check operation. clear, logical device drives 0xAA. This register read/write. Memory Space Configuration Name Memory base address bits[23:16] descriptor Memory base address bits [15:08] descriptor Memory control Register Index 0x40 0x41 0x42 Definition Read/write value indicating selected memory base address bits[23:16] memory descriptor This Boot Prom Space. Read/write value indicating selected memory base address bits[15:08] memory descriptor Bit[1] specifies 8/16-bit control. encoding relates memory control (bits[4:3]) information field memory descriptor. Bit[0], indicates next field used range length decode (implies range length base alignment memory descriptor equal). Bit[0] read-only. Memory upper limit address; bits [23:16] range length; bits [15:08] descriptor Memory upper limit bits [15:08] range length; bits [15:08] descriptor Memory descriptor 0x43 Read/write value indicating selected memory high address bits[23:16] memory descriptor bit[0] memory control this range length. bit[0] memory control this considered invalid.
Range Check
0x31
0x44
Read/write value indicating selected memory high address bits[15:08] memory descriptor either memory address range length described above.
0x48-0x4C
Memory descriptor This SRAM Space Shared Memory. Space Configuration
Name port base address bits[15:08] descriptor port base address bits[07:00] descriptor
Register Index 0x60
Definition Read/write value indicating selected lower limit address bits[15:08] descriptor logical device indicates only uses encoding, then bits[15:10] need supported. Read/write value indicating selected lower limit address bits[07:00] descriptor
0x61
Am79C961A
Interrupt Configuration Register Index 0x70
Name Interrupt request level select
Definition Read/write value indicating selected interrupt level. Bits[3:0] select which interrupt level used Interrupt selects IRQL fifteen selects IRQL fifteen. IRQL valid interrupt selection represents interrupt selection. Read/write value indicating which type interrupt used Request Level selected above.
Interrupt request type select
0x71
Bit[1] Level, Bit[0] Type,
high, level, edge
PCnet-ISA controller only supports Edge High Level Interrupts.
Channel Configuration
Name channel select channel select Register Index 0x74 0x75 Definition Read/write value indicating selected channels. Bits[2:0] select which channel Zero selects channel seven selects channel channel cascade channel used indicate channel active. Read only with value 0x04.
DETAILED FUNCTIONS EEPROM
Interface EEPROM supported PCnet-ISA controller industry standard 93C56 2-Kbit EEPROM device which uses 4-wire interface. This device directly interfaces PCnet-ISA controller through 4-wire interface which uses private data pins Data Data Out, Serial Clock. Chip Select dedicated from PCnet-ISA controller.
Important Note About EEPROM Byte
user cautioned that while Am79C961A (PCnet-ISA associated EEPROM compatible their predecessors Am79C961 (PCnet-ISA+) associated EEPROM, byte structure each EEPROMs different from each other. EEPROM byte structure used Am79C961A PCnet-ISA addition "MISC Config ISACSR9" word location 10Hex. EEPROM byte structure used Am79C961 PCnet-ISA+ does have this. Therefore, should user intend replace PCnet-ISA+ with PCnet-ISA care MUST taken reprogram EEPROM reflect byte structure needed used PCnet-ISA additional infor mation, refer Am79C961 PCnet-ISA+ data sheet (PID #18183) under sections entitled EEPROM Serial EEPROM Byte Map.
Note: data stored EEPROM stored bit-reversal format. Each word bits) must written into EEPROM with swapped with swapped with etc. This 2-Kbit device organized words. device used PCnet-ISA controller below. information stored EEPROM follows:
IEEE address bytes Reserved10 bytes EISA bytes ISACSRs14 bytes Plug Play Defaults19 bytes 8-Bit Checksum1 byte External Shift Chain2 bytes Plug Play Config Info192 bytes
Am79C961A
Basic EEPROM Byte
following byte XXC56 series EEPROMs used PCnet-ISA Ether
Controller. This byte case where non-PCnet Family compatible software driver implemented.
Byte IEEE Address (0h) (Bytes Byte Byte Byte Byte Byte Byte Byte (8h) EISA Config Reg. (Ah) EISA Byte EISA Byte
Byte Byte Byte Byte Byte Byte Byte Byte EISA Byte EISA Byte MSRDA, ISACSR0 MSWRA, ISACSR1 MISC Config ISACSR2
Word Location Vendor Byte Memory Ports Interrupts Channels Memory
Internal Registers
LED1 Config, ISACSR5 LED2 Config, ISACSR6 LED3 Config, ISACSR7 MISC Config ISACSR9
(11h)
0x61 0x71 Unused
0x60 0x70 0x74 0x40 0x42 0x44 0x48 0x4A 0x4C 0xF0
Plug Play Reg.
0x41 0x43 Unused 0x49 0x4B Unused
(1Ah) (1Bh) (1Ch)
8-Bit Checksum External Shift Chain Unused Locations
(20h)
Plug Play Starting Location
Note: Checksum calculated words through 0x1Bh (first bytes).
Am79C961A
Device Driver Compatible EEPROM Byte
following byte XXC56 series EEPROMs used PCnet-ISA Ethernet Controller. This byte case where
PCnet Family compatible software driver implemented. (This byte application reference developing software devices.)
Word Location EISA Config Reg. Internal Registers Plug Play Reg.
Byte Byte Byte Reserved HWID (01H) User Space 16-Bit Checksum ASCII 57H) EISA Byte EISA Byte
Byte Byte Byte Reserved Reserved IEEE Address (Bytes 0-5)
ASCII 57H) EISA Byte EISA Byte
MSRDA, ISACSR0 MSWRA, ISACSR1 MISC Config, ISACR2 LED1 Config, ISACSR5 LED2 Config, ISACSR6 LED3 Config, ISACSR7 MISC Config ISACSR9 0x61 0x71 Unused 0x41 0x43 Unused 0x49 0x4B Unused 8-Bit Checksum External Shift Chain Unused Locations 0x60 0x70 0x74 0x40 0x42 0x44 0x48 0x4A 0x4C 0xF0 Vendor Byte Memory Ports Interrupts Channels Memory
Appendix
Plug Play Starting Location
Appendix
Note: Checksum calculated words through plus word Checksum calculated words through 0x1Bh (first bytes).
Am79C961A
Plug Play Register
following chart descriptions show internal configuration registers associated with
Plug Play Register 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x30 0x31
Plug Play operation. These registers control configuration PCnet-ISA controller.
READ_DATA SERIAL ISOLATION WAKE [CSN] RESOURCE_DATA LOGICAL DEVICE NUMBER IORNG ACTIVATE IORNG READ STATUS WAIT
READ_DATA SERIAL_ISOLATION RST_CSN WAIT_KEY RST_ALL WAKE [CSN] READ_STATUS RESOURCE_DATA ACTIVATE IORNG
Address Plug Play READ_DATA Port. Used Serial Isolation process. Resets register zero. Resets Wait State. Resets logical devices. Will wake write data matches Register. Read Status RESOURCE DATA. Next pending byte read from EEPROM. Plug Play Value. Indicates that PCnet-ISA device should activated. Bits used enable Range Check Command.
Am79C961A
following chart descriptions show internal command registers associated with Plug
Plug Play Register 0x60 0x61 0x70 0x71 0x74 0x40 0x41 0x42 0x43 0x44 0x48 0x49 0x4A 0x4B 0x4c 0xF0 IOAM2 BPAM2 BPSZ2 SRAM2 SRSZ2 IOAM1 BPAM1 BPSZ1 SRAM1 SRSZ1 LGCY_EN IOAM0 BPAM0 BPSZ0 SRAM0 SRSZ0 DXCVRP FL_SEL
Play operation. These registers control PCnet-ISA controller Plug Play operation.
IRQ3 BP_CS IRQ2 DMA2 APROM_EN IRQ1 IRQ_LVL DMA1 BP_16B SRAM4 SR16B AEN_CS IOAM3 IRQ0 IRQ_TYPE DMA0 BPAM3 BPSZ3 SRAM3 SRSZ3 IO_MODE
PCnet-ISA II's Legacy Feature Description
current PCnet-ISA chip designed such that always responds Plug Play configuration software. There situations where this response Plug Play software undesirable. example this when fixed configuration required, when only possible resource available PCnet-ISA conflicts with present used resource such IRQ, when chip used system with buggy BIOS. function situations above, feature been added PCnet-ISA chip. This feature
makes chip ignore software's special initiation sequence (6A). This will effectively turn chip into "Legacy" mode operation, where will visible space, only special setup programs will able reconfigure case EEPROM missing, empty, corrupted, chip will still recognize AMD's special initiation sequence (6B). enable this feature, written into LGCY_EN bit, which Plug Play register 0xF0. preferred method would this Vendor Byte (PnP 0xF0) field EEPROM located word offset 0x1A.
Am79C961A
Plug Play Register Locations Detailed Description (Refer Plug Play Register above).
IOAM[3:0] Address Match bits [8:5] (PnP 0x60-0x61). Controls base address PCnet-ISA IOAM will written with value from EEPROM.
Base Address (Hex) DMA[2:0]
register will written with value from EEPROM. {For Master Mode Only} signals will driven unless Plug Play activate register set.
Channel (DRQ/DACK Pair) Channel Channel Channel Channel Channel
IOAM[3:0]
BPAM[3:0]
Boot PROM Address Match bits [16:13] (PnP 0x40-0x41). Selects location where Boot PROM Address match decode started. BPAM will written with value from EEPROM.
Address Location (Hex) C0000 C2000 C4000 C6000 C8000 CA000 CC000 CE000 D0000 D2000 D4000 D6000 D8000 DA000 DC000 DE000 Size Supported bytes)
IRQ[3:0]
selection (PnP 0x70). Controls which interrupt will asserted. Edge sensitive EISA level mode controlled IRQ_TYPE 0x71. Default Edge Sensitive. signals will driven unless activate register set.
IRQ3 (Default) IRQ4 IRQ5 IRQ9 IRQ10 IRQ11 IRQ12 IRQ15
IRQ[3:0]
BPAM[3:0]
BP_16B
Boot PROM 16-bit access (PnP 0x42). asserted Boot PROM cycles should respond 16-bit device. Master mode, boot PROM cycles will only bits width. Boot PROM Size (PnP 0x43-0x44). Selects size boot PROM selected.
Boot PROM Size Boot PROM Selected
BPSZ[3:0]
Type
Type(PnP 0x71). Indicates type interrupt setting; Level Edge Level (PnP 0x71). read-only register that indicates type setting, active high low. Always complement IRQ_TYPE. Channel Select (PnP 0x74). Controls selection PCnet-ISA DMA[2:0]
IRQ_LVL
BPSZ[3:0]
DMA[2:0]
SRAM[4:0]
Static Address Match bits [17:13] (PnP 0x48-0x49). Selects starting location Shared Memory when using
Am79C961A
Shared Memory architecture mode. SRAM[2:0] bits used performing address decoding SA[15:13] address bits shown table below. SRAM[4] SRAM[3] must reflect external address match logic SA[17] SA[16], respectively. SRAM[4:0] bits ignored when Master mode Programmed Architecture mode.
SRAM[2:0] SA[15:13] SRAM Size bytes)
PCnet-ISA will respond sequence EEPROM read successful, otherwise will respond sequence. DXCVRP DXCVR Polarity. DXCVRP sets polarity DXCVR pin. When DXCVRP cleared (default), DXCVR driven HIGH when Twisted Pair port active SLEEP mode been entered driven when port active. When DXCVRP set, DXCVR driven when Twisted Pair port active SLEEP mode been entered driven HIGH when port active. DXCVRP should generally left cleared when PCnet-ISA being used with external DC-DC converter that active enable pin. DXCVRP should PCnet-ISA being used with external DC-DC converter that active high enable pin. IO_MODE Mode. When one, internal selection will respond 16-bit port, (i.e. drive IOCS16 pin). When IO_MODE zero, (Default), internal selection will respond 8-bit port. External Decode Logic Registers. When written with one, PCnet-ISA will chip select bar, allow external decode logic upper address [9:5]. purpose this allow locations, supported with IOAM[3:0], selection, defined outside range 0x200-0x3F7. When zero, (Default), Selection will IOAM[3:0]. External Parallel IEEE Address PROM. When set, IRQ15 reconfigured Address Chip Select low, similar APCS existing PCnet-ISA (Am79C960) device. purpose this allow both serial EEPROM parallel PROM coexist. When address located serial EEPROM will ignored parallel access will occur over PRDB
SR_16B
Static 16-bit access (PnP 0x4A). asserted, PCnet-ISA will respond SRAM cycles 16-bit device. This should external logic designed assert MEMCS16 signal when accesses shared memory decoded. This ignored when Master mode Programmed Architecture mode. Static size (PnP 0x4B-0x4C). Selects size static RAM. SRSZ[3:0] bits ignored when Master mode Programmed Architecture mode.
Shared Memory Size Static Selected
AEN_CS
SRSZ[3:0]
SRSZ[3:0]
APROM_EN
Vendor Defined Byte (PnP 0xF0)
LGCY_EN Legacy mode enable. When written with one, PCnet-ISA will respond Plug Play initiation sequence (6A) will respond sequence (6B). Therefore, cannot reconfigured Plug Play software. When zero (default),
Am79C961A
bus. When APROM_EN cleared, default state, IEEE address will read from serial device written internal RAM. When space IEEE PROM selected, PCnet-ISA will access contents this read cycles. write cycles will ignored. BP_CS Boot PROM Chip Select. When BP_CS one, BALE will external chip select (active low) above address bus. BALE will select boot PROM when MEMR asserted BP_CS BPAM[2:0] match SA[15:13] BPSZ[3:0] matches selected size. When BP_CS zero. BALE will normal address latch strobe capture upper address bits memory access boot PROM. BP_CS default low. primary purpose this allow non-ISA applications support larger Boot PROMS non-standard Boot PROM/Flash locations. Flash Memory Device Selected. replaced with external Flash memory device. Master Flash_WE. Flash's grounded. shared memory mode, BPCS replaced with Flash_CS. IRQ12 becomes Static_RAM_CS pin. SROE SRWE signals connected both SRAM Flash memory devices. FL_SEL cleared reset, which default. supports. Instead, different used bring PCnet-ISA controller Wait state. This follows:
Without EEPROM
some designs, especially motherboard applicat EEPROM altogether. This would save money, space, power consumption. operation this mode similar when PCnet-ISA controller encounters checksum error, except that enter this mode SHFBUSY left unconnected. device will enter software relocatable mode, BIOS motherboard wake device, configure load IEEE address (possibly stored Flash ROM) into PCnet-ISA controller, activate device.
External Scan Chain
External Scan Chain bits stored EEPROM which used PCnet-ISA controller which used with external hardware allow jumperless configuration external devices. begins reading EEPROM storing information registers inside PCnet-ISA controller. SHFBUSY held high during read EEPROM. external circuitry added, such shift register, which clocked from SCLK attached from EEPROM, data read EEPROM will shifted into shift register. After reading EEPROM External Shift Chain, there correct checksum, SHFBUSY will low. This will used latch information from EEPROM into shift register. checksum invalid, SHFBUSY will low, indicating that EEPROM bad.
FL_SEL
Checksum Failure
After RESET, PCnet-ISA controller begins reading EEPROM storing information registers inside PCnet-ISA controller. PCnet-ISA controller does checksum word locations 0-1Bh inclusive byte checksum FFh, then data read from EEPROM considered good. PCnet-ISA controller enters what called software relocatable mode. software relocatable mode, device functions same Plug Play mode, except that does respond same initiation Plug Play
Flash PROM
Instead using PROM EPROM Boot PROM, desirable Flash EEPROM type device storing Boot code. This would allow in-system updates changes information Boot without opening also desirable store statistics drivers Flash device.
Am79C961A
Interface
Flash-type device with PCnet-ISA controller, Flash Select register 0F0h Plug Play registers. Flash Select cleared RESET (default). master mode, BPCS becomes Flash_OE IRQ12 becomes Flash_WE. Flash devices connected ground. shared memory mode, BPCS becomes Flash_CS IRQ12 becomes static Chip Select, SROE SRWE signals connected both SRAM Flash devices.
received. IOCHRDY asynchronously driven PCnet-ISA controller needs wait state. released synchronously when PCnet-ISA controller ready. When PCnet-ISA controller Current Master, signals generates synchronous on-chip clock.
Transfers
will initiate transfers according type operation being performed. There three primary types transfers: Initialization Block Transfers During initialization, PCnet-ISA transfers words from initialization block memory internal registers. These words transferred through different mastership period sequences, depending whether TIMER (CSR4, and, TIMER set, value Activity Timer register (CSR82). TIMER reset (default), words always transferred during three separate mastership periods. During each mastership period, four words bytes) will read from contiguous memory addresses. TIMER set, words transferred using anywhere from mastership periods, depending value Activity Timer register (CSR82). During each mastership period, minimum four words bytes) will read from contiguous memory addresses. TIMER value Activity Timer register allows words initialization block read during single mastership period. Descriptor Transfers Descriptor transfers performed read write transmit receive descriptors. transmit receive descriptor READ accesses require word reads (TMD1, TMD0, then TMD2 transmit descriptors RMD1, RMD0, then RMD2 receive descriptors). Transmit receive descriptor WRITE accesses unchained descriptors last descriptor chain (ENP set) require word writes (TMD1 then TMD3 transmit RMD1 then RMD3 receive). Transmit receive descriptor WRITE accesses chained descriptors that have require word write (TMD1 transmit RMD1 receive). During descriptor write accesses, only bytes which need written written, controlled SBHE pins. TIMER reset (default), accesses during single mastership period will either read write will only descriptor. Hence, when TIMER reset, mastership periods
Optional IEEE Address PROM
Normally, Ethernet physical address will stored EEPROM with other configuration data. This reduces parts count, board space requirements, power consumption. option standard parallel PROM provided manufacturers EEPROMs. parallel PROM store IEEE address data instead storing EEPROM, APROM_EN Plug Play registers EEPROM upon RESET. IRQ15 redefined setting this APCS, ADDRESS PROM CHIP SELECT. This connected external PROM, such 27LS19. address pins PROM connected lower address pins bus, data lines connected private data bus. this mode, accesses IEEE address will passed external PROM data will passed through PCnet-ISA controller system data bus.
EISA Configuration Registers
PCnet-ISA controller support 4-byte EISA Configuration Registers. These used EISA systems identify card load appropriate configuration file that card. This feature enabled using ISACSR2. When EISA Configuration registers will enabled will read location 0xC80-0xC83. contents these registers stored EEPROM automatically read RESET.
Interface Unit (BIU)
interface unit mixture state machine asynchronous logic. handles types accesses; accesses where PCnet-ISA controller slave accesses where PCnet-ISA controller Current Master. slave mode, signals like IOCS16 asserted deasserted soon appropr iate inputs
Am79C961A
descriptor accesses always either cycles long, depending which descriptor operation being performed. TIMER set, cycles required descriptor access performed part mastership period which combination descriptor reads writes buffer reads writes performed. When TIMER set, Activity Timer (CSR82) access requirements PCnet-ISA govern operations performed during single mastership period. FIFO Transfers FIFO transfers occur when PCnet-ISA microcode determines that transfers and/or from FIFOs required. Once PCnet-ISA been granted mastership, will perform series consecutive transfer cycles before relinquishing bus. When Activity Timer disabled clearing TIMER (CSR4, bit, FIFO transfers within mastership period will either read write cycles, transfers will adjacent, ascending addresses. When Activity Timer enabled setting TIMER bit, transfers within mastership period consist mixture read write cycles, without restriction address ordering. This mode operation allows PCnet-ISA accomplish more during each ownership period. number data transfer cycles contained within single mastership period general dependent programming DMAPLUS (CSR4, TIMER (CSR4, options. Several other factors will also affect length mastership period. possibilities follows: DMAPLUS TIMER maximum transfers from FIFO will performed default. This default value changed writing Burst Register (CSR80, bits 7:0). Since TIMER FIFO transfers within mastership period will either read write cycles, transfers will adjacent, ascending addresses. Note that DMAPLUS merely sets maximum value number FIFO transfers that occur during mastership period. minimum number transfers mastership period will determined settings FIFO watermarks conditions FIFOs, value Activity Timer (CSR82) TIMER set. DMAPLUS TIMER mastership period will continue until transmit FIFO filled high threshold (read transfers) receive FIFO emptied threshold (write transfers). Other variables also affect point mastership period this mode, including particular conditions existing within FIFOs, receive transmit status conditions. Since TIMER FIFO transfers within mastership period will either read write cycles, transfers will adjacent, ascending addresses. TIMER mastership period will continue until "pending operations" completed until Activity Timer value (CSR82) expired. These operations consist mixture descriptor buffer read write accesses. DMAPLUS "pending operations" includes descriptor accesses buffer accesses that need performed. DMAPLUS "pending operations" include descriptor accesses that need performed buffer accesses that need performed limit specified Burst Register (CSR80, bits 7:0). Note that when TIMER=1, following last transaction during mastership period, PCnet-ISA keep ownership approximately 1µs. PCnet-ISA determines whether there further pending operations waiting approximately after completion every operation (e.g. descriptor FIFO access). during period, further operations requested internal Buffer Management Unit, PCnet-ISA determines that there further pending operations gives ownership. This unused ownership time more than made efficiency gained being able perform mixture descriptor buffer read write accesses during single ownership period. FIFO thresholds programmable (see description CSR80), Burst Register Activity Timer values. exact number transfer cycles case DMAPLUS will dependent latency system PCnet-ISA controller's request speed operation, will limited value Activity Timer register TIMER set), FIFO condition, receive transmit status. Barring time-out either these registers, exceptional receive transmit events, packet signal from FIFO, FIFO watermark settings extent Grant latency will major factors determining number accesses performed during given arbitration cycle when DMAPLUS IOCHRDY response memory device will also affect number transfers when DMAPLUS since speed accesses will affect state FIFO. During accesses, FIFO filling emptying network end. slower memory response will allow additional data accumulate inside FIFO (during write transfers from receive FIFO). accesses slow enough, com-
Am79C961A
plete word become available before arbitration cycle thereby increase number transfers that cycle. general rule that longer Grant latency slower transfer operations clock speed) higher transmit watermark lower receive watermark combination thereof, longer will average mastership period. Reinitialization done initialization block setting STOP CSR0, followed writing CSR15, then setting START CSR0. Note that this form restart will perform same PCnet-ISA controller LANCE. particular, PCnet-ISA controller reloads transmit receive descriptor pointers (working registers) with their respective base addresses. This means that software must clear descriptor's bits reset descriptor ring pointers before restart PCnet-ISA controller. reload descriptor base addresses performed LANCE only after initialization, restart LANCE without initialization leaves LANCE pointing same descriptor locations before restart. Suspend PCnet-ISA controller offers suspend mode that allows easy updating registers without going through full reinitialization device. suspend mode also allows stopping device with orderly termination network activity. host requests PCnet-ISA controller enter suspend mode setting SPND (CSR5, ONE. host must poll SPND until reads back determine that PCnet-ISA controller entered suspend mode. When host sets SPND ONE, PCnet-ISA controller first finishes on-going transmit activity updates corresponding transmit descriptor entries. then finishes on-going receive activity updates corresponding receive descriptor entries. then sets read-version SPND enters suspend mode. suspend mode, registers accessible. long PCnet-ISA controller reset while suspend mode asserting RESET pin, reading RESET register, setting STOP bit), reinitialization device required after device comes suspend mode. When SPND ZERO, PCnet-ISA controller will leave suspend mode will continue transmit receive descriptor ring locations where left when entered suspend mode. Buffer Management Buffer management accomplished through message descriptor entries organized ring structures memory. There rings, receive ring transmit ring. size message descriptor entry words bytes). Descriptor Rings Each descriptor ring must organized contiguous area memory. initialization time (setting INIT CSR0), PCnet-ISA controller reads user-defined base address transmit receive descriptor rings, which must 8-byte boundary, well number entries contained
Buffer Management Unit (BMU)
buffer management unit microcoded state machine which implements initialization block descriptor architecture. Initialization PCnet-ISA controller initialization includes reading initialization block memory obtain operating parameters. initialization block read when INIT CSR0 set. INIT should before concurrent with STRT insure correct operation. previous section Initialization Block Transfer." Once initialization block been read processed, knows where receive transmit descriptor rings are. completion read operation after internal registers have been updated, IDON will CSR0, interrupt generated IENA set. Initialization Block vectored contents CSR1 (least significant bits address) CSR2 (most significant bits address). block contains user defined conditions PCnet-ISA controller operation, together with address length information allow linkage transmit receive descriptor rings. There alternative method initialize PCnet-ISA controller. Instead initialization initialization block memory, data written directly into appropriate registers. Either method used discretion programmer. registers written directly, INIT must set, initialization block will read thus overwriting previously written information. Please refer Appendix details this alternative method. Reinitialization transmitter receiver section PCnet-ISA controller turned initialization block (MODE Register DTX, bits; CSR15[1:0]). state transmitter receiver monitored through CSR0 (RXON, TXON bits). PCnet-ISA controller should reinitialized transmitter and/ receiver were turned during original initialization subsequently required activate them, either section shut detection error condition (MERR, UFLO, BUFF error).
Am79C961A
descriptor rings. default, maximum ring entries permitted when utilizing initialization block, which uses values TLEN RLEN specify transmit receive descriptor ring lengths. However, ring lengths manually defined 65535) writing transmit receive ring length registers (CSR76,78) directly. Each ring entry contains following information: address actual message data buffer user host memory length message buffer Status information indicating condition buffer Receive descriptor entries similar (but identical) transmit descriptor entries. Both composed four registers, each bits wide total bytes. permit queuing de-queuing message buffers, ownership each buffer allocated either PCnet-ISA controller host. within descriptor status information, either (see section RMD), used this purpose. "Deadly Embrace" conditions avoided ownership mechanism. Only owner permitted relinquish ownership write field descriptor entry. device that current owner descriptor entry cannot assume ownership change field entry. Descriptor Ring Access Mechanism initialization, PCnet-ISA controller reads base address both transmit receive descriptor rings into CSRs PCnet-ISA controller during subsequent operation. When transmit receive functions begin, base address each ring loaded into current descriptor address registers address next descriptor entry transmit receive rings computed loaded into next descriptor address registers.
Am79C961A
24-Bit Base Address Pointer Initialization Block
Descriptor Ring DESCRIPTOR RINGS CSR1 desc. start desc. start
CSR2 IADR[23:16]
IADR[15:0] RMD0 RMD1 RMD2 RMD0 RMD3
Initialization Block MODE PADR[15:0] PADR[31:16] PADRF[47:32] LADRF[15:0] LADRF[31:16] LADRF[47:32] LADRF[63:48] RDRA[15:0] RLEN TLEN RDRA[23:16] TDRA[15:0] TDRA[23:16] Buffers Data Buffer Data Buffer Data Buffer
DESCRIPTOR RINGS Descriptor Ring DESCRIPTOR RINGS desc. start desc. start
TMD0 TMD1 TMD2
TMD0 TMD3
Buffers
Data Buffer
Data Buffer
Data Buffer
19364B-15
Initialization Block Descriptor Rings
Polling When there channel activity there preor post-receive transmit activity being performed PCnet-ISA controller then PCnet-ISA controller will periodically poll current receive transmit descriptor entries order ascertain their ownership. DPOLL CSR4 set, then transmit polling function disabled.
typical polling operation consists following: PCnet-ISA controller will current receive descriptor address stored internally vector appropriate Receive Descriptor Table Entry (RDTE). will then current transmit descriptor address (stored internally) vector appropriate Transmit Descriptor Table Entry (TDTE). These accesses will made RMD1 RMD0 current RDTE TMD1 TMD0 current TDTE periodic poll-
Am79C961A
intervals. information collected during polling activity will stored internally appropriate CSRs. (i.e. CSR18-19, CSR40, CSR20-21, CSR42, CSR50, CSR52). Unowned descriptor status will internally ignored. typical receive poll occurs under following conditions: PCnet-ISA controller does possess ownership current RDTE poll time elapsed RXON PCnet-ISA controller does possess ownership next RDTE poll time elapsed RXON RXON PCnet-ISA controller will never poll RDTE locations. RXON system should always have least RDTE available possibility receive event. When there only RDTE, there polling next RDTE. typical transmit poll occurs under following conditions: PCnet-ISA controller does possess ownership current TDTE DPOLL TXON poll time elapsed, PCnet-ISA controller does possess ownership current TDTE DPOLL TXON packet just been received, PCnet-ISA controller does possess ownership current TDTE DPOLL TXON packet just been transmitted. poll time interval nominally defined 32,768 crystal clock periods, However, poll time register controlled internally microcode, other microcode controlled operation will interrupt incrementing poll count register. example, when receive packet accepted PCnet-ISA controller, device suspends execution poll-time-incrementing microcode that receive microcode routine instead executed. Poll-time-incrementing code resumed when receive operation completely finished. Note, how66 ever, that following completion receive transmit operation, poll operation will always performed. poll time count register never reset. Note that non-default desired, then strict sequence setting INIT CSR0, waiting IDON CSR0, then writing CSR47, then setting STRT CSR0 must observed, otherwise default value will overwritten. CSR47 section details. Setting TDMD CSR0 will cause microcode controller exit poll counting code immediately perform polling operation. RDTE ownership been previously established, then RDTE poll will performed ahead TDTE poll. Transmit Descriptor Table Entry (TDTE) after TDTE access, PCnet-ISA controller finds that that TDTE set, then PCnet-ISA controller resumes poll time count re-examines same TDTE next expiration poll time count. TDTE set, PCnet-ISA controller will immediately request order reset this descriptor; this condition would normally found following LCOL RETRY error that occurred middle transmit packet chain buffers. After resetting this descriptor, PCnet-ISA controller will again immediately request order access next TDTE location ring. buffer length will reset. LANCE buffer length interpreted 4096-byte buffer. acceptable have length buffer transmit with STP=1 STP=1 acceptable have length buffer with start packet (STP) set, then microcode control proceeds routine that will enable transmit data transfers FIFO. transmit buffers data chained (ENP first buffer), then PCnet-ISA controller will look ahead next transmit descriptor after performed least transmit data transfer from first buffer. More than transmit data transfer possibly take place, depending upon state transmitter. transmit descriptor look ahead reads TMD0 first TMD1 second. contents TMD0 TMD1 will stored Next Descriptor Address (CSR32), Next Byte Count (CSR66) Next Status (CSR67) regardless state bit. This transmit descriptor lookahead operation performed only once. PCnet-ISA controller does next TDTE (i.e. second TDTE this packet), then will complete transmission current buffer then
Am79C961A
update status current (first) TDTE with BUFF UFLO bits being set. DXSUFLO (bit CSR3), then this will cause transmitter disabled (CSR0, TXON PCnet-ISA controller will have restarted restore transmit function. situation that matches this description implies that system been able stay ahead PCnet-ISA controller transmit descriptor ring therefore, condition treated fatal error. avoid this situation, system should always transmit chain descriptor bits reverse order. PCnet-ISA controller does second TDTE chain, will gradually empty contents first buffer bytes needed transmit operation), perform single-cycle transfer upda
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