PCnetTM-32 Single-Chip 32-Bit Ethernet Controller DISTINCTIVE CHA
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Am79C965
PCnetTM-32 Single-Chip 32-Bit Ethernet Controller
DISTINCTIVE CHARACTERISTICS
Single-chip Ethernet controller Video Electronics Standards Association (VESA) local buses Supports 8802-3 (IEEE/ANSI 802.3) Ethernet standards Direct interface local VESA VL-Bus Enhanced burst mode with support Am486burst read/write operations Software-compatible with AMD's Am7990 LANCE, Am79C90 C-LANCE, Am79C960 PCnet-ISA, Am79C961 PCnet-ISA+, Am79C961A PCnet-ISA Am79C970A PCnet-PCI Am79C900 ILACCregister descriptor architecture Compatible with Am2100/Am1500T Novell® NE2100/NE1500 driver software High-performance Master architecture with integrated buffer management unit utilization Built-in byte-swap logic supports both little endian byte alignment MicrowireEEPROM interface supports jumperless design Single power supply operation Low-power, CMOS design with sleep modes allows reduced power consumption critical battery-powered applications Green Look-Ahead Packet Processing (LAPP) allows protocol analysis begin before receive frame Integrated Manchester encoder/decoder Individual 136-byte transmit 128-byte receive FIFOs provide frame buffering increased system latency tolerance support following features: Automatic retransmission with FIFO reload Automatic receive stripping transmit padding (individually programmable) Automatic runt packet rejection Automatic deletion received collision frames JTAG Boundary Scan (IEEE 1149.1) test access port interface board-level production test Provides integrated attachment unit interface (AUI) 10BASE-T transceiver with automatic port selection Automatic twisted-pair receive polarity detection automatic correction receive polarity Optional byte padding long-word boundary receive Dynamic transmit generation programmable frame-by-frame basis Internal/external loopback capabilities Supports following types network interfaces: external 10BASE-2, 10BASE-5, 10BASE-T 10BASE-F Internal 10BASE-T transceiver with Smart Squelch twisted-pair medium Supports LANCE/C-LANCE/PCnet-ISA general purpose serial interface (GPSI) 160-pin PQFP package
GENERAL DESCRIPTION
PCnet-32 single-chip 32-bit Ethernet controller highly integrated Ethernet system solution designed address high-performance system application requirements. flexible bus-mastering device that used networking application, including networkready PCs, printers, modems, bridge/router designs. bus-master architecture provides high data throughput system utilization. PCnet-32 controller fabricated with AMD's advanced low-power CMOS process provide operating standby current power-sensitive applications.
Publication# 18219 Rev: Amendment/0 Issue Date: January 1998
This document contains information product under development Advanced Micro Devices. information intended help evaluate this product. reserves right change discontinue work this proposed product without notice.
PCnet-32 controller complete Ethernet node integrated into single VLSI device. contains interface unit, buffer management unit, 8802-3 (IEEE/ANSI 802.3)-defined media access control (MAC) function, individual 136-byte transmit 128-byte receive FIFOs, 8802-3 (IEEE/ANSI 802.3)-defined attachment unit interface (AUI) twisted-pair transceiver medium attachment unit (10BASE-T MAU), microwire EEPROM interface. PCnet-32 controller also register-compatible with LANCE (Am7990) Ethernet controller, C-LANCE (Am79C90) Ethernet controller, ILACC (Am79C900) Ethernet controller, Ethernet controllers PCnet family, including PCnet-ISA controller (Am79C960), PCnet-ISA+ controller (Am79C961), PCnet-ISA (Am79C961A), PCnet-PCI controller (Am79C970A). buffer mana (Am79C900), PCnet descriptor software models. PCnet-32 controller software-compatible with Novell NE2100 NE1500 Ethernet adapter card architectures. addition, Sleep function been incorporated provide standby current, which essential notebooks Green PCs. 32-bit demultiplexed interface unit provides direct interface VESA VL-Bus series microprocessors, simplifying design Ethernet node system. With built-in support both little endian byte alignment, this controller also addresses proprietary non-PC applications. PCnet-32 configuration parameters, including unique IEEE physical address, read from external non-volatile memory (serial EEPROM) immediately following system reset. addition, location which internal registers accessed stored EEPROM, allowing software model device located appropriately system space during system initialization. controller capability select automatically either port twisted-pair transceiver. Only interface active time. individual transmit receive FIFOs reduce system overhead, providing sufficient latency during frame transmission reception, minimizing intervention during normal network error recovery. integrated Manchester encoder/decoder (MENDEC) eliminates need external serial interface adapter (SIA) node system. built-in general purpose serial interface (GPSI) allows MENDEC bypassed. addition, device provides programmable on-chip drivers transmit, receive, collision, receive polarity, link integrity, jabber status. PCnet-32 controller also provides external address detection interface (EADI) allow external hardware address filtering internetworking applications.
RELATED PRODUCTS
Part Am79C98 Am79C100 Am7996 Am79C981 Am79C987 Am79C940 Am7990 Am79C90 Am79C900 Am79C960 Am79C961 Am79C970 Am79C974 Description Twisted Pair Ethernet Transceiver (TPEX) Twisted Pair Ethernet Transceiver Plus (TPEX+) IEEE 802.3/Ethernet/Cheapernet Transceiver Integrated Multiport Repeater Plus (IMR+) Hardware Implemented Management Information Base (HIMIB) Media Access Controller Ethernet (MACE) Local Area Network Controller Ethernet (LANCE) CMOS Local Area Network Controller Ethernet (C-LANCE) Integrated Local Area Communications Controller (ILACC) PCnet-ISA Single-Chip Ethernet Controller (for bus) PCnet-ISA+ Single-Chip Ethernet Controller (with Microsoft Plug Play support) PCnet-PCI Single-Chip Ethernet Controller (for bus) PCnet-SCSI Combination Ethernet SCSI Controller Systems
Am79C965
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (valid combination) formed combination elements below.
AM79C965
ALTERNATIVE PACKAGE OPTION Trimmed Formed Tray (PQJ160)
OPTIONAL PROCESSING Blank Standard Processing
OPERATING CONDITIONS Commercial (0°C +70°C)
PACKAGE TYPE (per Prod. Nomenclature/16-038) Plastic Quad Flat Pack (PQR160)
SPEED Applicable DEVICE NUMBER/DESCRIPTION Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller
Valid Combinations AM79C965 KC\W
Valid Combinations Valid combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am79C965
PRELIMINARY TABLE CONTENTS
DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION RELATED PRODUCTS ORDERING INFORMATION BLOCK DIAGRAM: VESA VL-BUS MODE CONNECTION DIAGRAM: VESA VL-BUS MODE DESIGNATIONS: VESA VL-BUS MODE LISTED NUMBER LISTED NAME LISTED GROUP DRIVER TYPE DESCRIPTION: VESA VL-BUS MODE CONFIGURATION PINS CONFIGURATION SETTINGS SUMMARY CONNECTIONS VESA VL-BUS INTERFACE BOARD INTERFACE MICROWIRE EEPROM INTERFACE ATTACHMENT UNIT INTERFACE TWISTED PAIR INTERFACE EXTERNAL ADDRESS DETECTION INTERFACE GENERAL PURPOSE SERIAL INTERFACE IEEE 1149.1 TEST ACCESS PORT INTERFACE POWER SUPPLY PINS VESA VL-BUS/LOCAL CROSS-REFERENCE BLOCK DIAGRAM: LOCAL MODE CONNECTION DIAGRAM: LOCAL MODE DESIGNATIONS: LOCAL MODE LISTED NUMBER LISTED NAME LISTED GROUP DRIVER TYPE DESCRIPTION: LOCAL MODE CONFIGURATION PINS CONFIGURATION SETTINGS SUMMARY CONNECTIONS LOCAL INTERFACE BOARD INTERFACE
Am79C965
MICROWIRE EEPROM INTERFACE ATTACHMENT UNIT INTERFACE TWISTED PAIR INTERFACE EXTERNAL ADDRESS DETECTION INTERFACE GENERAL PURPOSE SERIAL INTERFACE IEEE 1149.1 TEST ACCESS PORT INTERFACE POWER SUPPLY PINS BASIC FUNCTIONS SYSTEM INTERFACE FUNCTION SOFTWARE INTERFACE NETWORK INTERFACES DETAILED FUNCTIONS INTERFACE UNIT Acquisition Master Transfers Initialization Block Transfers Descriptor Transfers FIFO Transfers Linear Burst Transfers Slave Timing VESA VL-Bus Mode Timing Master Slave Data Byte Placement BUFFER MANAGEMENT UNIT Initialization Re-initialization Buffer Management Descriptor Rings Descriptor Ring Access Mechanism Polling Transmit Descriptor Table Entry (TDTE) Receive Descriptor Table Entry (RDTE) MEDIA ACCESS CONTROL Transmit Receive Message Data Encapsulation Media Access Management MANCHESTER ENCODER/DECODER (MENDEC) External Crystal Characteristics External Clock Drive Characteristics MENDEC Transmit Path Transmitter Timing Operation Receiver Path Input Signal Conditioning Clock Acquisition Tracking
Am79C965
PRELIMINARY Carrier Tracking Message Data Decoding Jitter Tolerance Definition ATTACHMENT UNIT INTERFACE (AUI) Differential Input Terminations Collision Detection TWISTED-PAIR TRANSCEIVER (T-MAU) Twisted Pair Transmit Function Twisted Pair Receive Function Link Test Function Polarity Detection Reversal Twisted Pair Interface Status Collision Detect Function Signal Quality Error (SQE) Test (Heartbeat) Function Jabber Function Power Down 10BASE-T Interface Connection IEEE 1149.1 TEST ACCESS PORT INTERFACE Boundary Scan Circuit Supported Instructions Instruction Register Decoding Logic Boundary Scan Register (BSR) Other Data Register EADI (EXTERNAL ADDRESS DETECTION INTERFACE) GENERAL PURPOSE SERIAL INTERFACE (GPSI) POWER SAVINGS MODES SOFTWARE ACCESS Resources Register Access HARDWARE ACCESS PCnet-32 Controller Master Accesses Slave Access Resources EEPROM Microwire Access TRANSMIT OPERATION Transmit Function Programming Automatic Generation Transmit Generation Transmit Exception Conditions RECEIVE OPERATION Receive Function Programming Automatic Stripping Receive Checking Receive Exception Conditions
Am79C965
LOOPBACK OPERATION SUPPORT H_RESET, S_RESET STOP H_RESET S_RESET STOP USER ACCESSIBLE REGISTERS SETUP REGISTERS RUNNING REGISTERS REGISTER CONTROL STATUS REGISTERS CSR0: PCnet-32 Controller Status CSR1: IADR[15:0] CSR2: IADR[31:16] CSR3: Interrupt Masks Deferral Control CSR4: Test Features Control CSR6: RX/TX Descriptor Table Length CSR8: Logical Address Filter, LADRF[15:0] CSR9: Logical Address Filter, LADRF[31:16] CSR10: Logical Address Filter, LADRF[47:32] CSR11: Logical Address Filter, LADRF[63:48] CSR12: Physical Address Register, PADR[15:0] CSR13: Physical Address Register, PADR[31:16] CSR14: Physical Address Register, PADR[47:32] CSR15: Mode Register CSR16: Initialization Block Address Lower CSR17: Initialization Block Address Upper CSR18: Current Receive Buffer Address Lower CSR19: Current Receive Buffer Address Upper CSR20: Current Transmit Buffer Address Lower CSR21: Current Transmit Buffer Address Upper CSR22: Next Receive Buffer Address Lower CSR23: Next Receive Buffer Address Upper CSR24: Base Address Receive Ring Lower CSR25: Base Address Receive Ring Upper CSR26: Next Receive Descriptor Address Lower CSR27: Next Receive Descriptor Address Upper CSR28: Current Receive Descriptor Address Lower CSR29: Current Receive Descriptor Address Upper CSR30: Base Address Transmit Ring Lower CSR31: Base Address Transmit Ring Upper CSR32: Next Transmit Descriptor Address Lower CSR33: Next Transmit Descriptor Address Upper CSR34: Current Transmit Descriptor Address Lower CSR35: Current Transmit Descriptor Address Upper
Am79C965
PRELIMINARY CSR36: Next Next Receive Descriptor Address Lower CSR37: Next Next Receive Descriptor Address Upper CSR38: Next Next Transmit Descriptor Address Lower CSR39: Next Next Transmit Descriptor Address Upper CSR40: Current Receive Status Byte Count Lower CSR41: Current Receive Status Byte Count Upper CSR42: Current Transmit Status Byte Count Lower CSR43: Current Transmit Status Byte Count Upper CSR44: Next Receive Status Byte Count Lower CSR45: Next Receive Status Byte Count Upper CSR46: Poll Time Counter CSR47: Polling Interval CSR48: Temporary Storage Lower CSR49: Temporary Storage Upper CSR50: Temporary Storage Lower CSR51: Temporary Storage Upper CSR52: Temporary Storage Lower CSR53: Temporary Storage Upper CSR54: Temporary Storage Lower CSR55: Temporary Storage Upper CSR56: Temporary Storage Lower CSR57: Temporary Storage Upper CSR58: Software Style CSR59: Register CSR60: Previous Transmit Descriptor Address Lower CSR61: Previous Transmit Descriptor Address Upper CSR62: Previous Transmit Status Byte Count Lower CSR63: Previous Transmit Status Byte Count Upper CSR64: Next Transmit Buffer Address Lower CSR65: Next Transmit Buffer Address Upper CSR66: Next Transmit Status Byte Count Lower CSR67: Next Transmit Status Byte Count Upper CSR68: Transmit Status Temporary Storage Lower CSR69: Transmit Status Temporary Storage Upper CSR70: Temporary Storage Lower CSR71: Temporary Storage Upper CSR72: Receive Ring Counter CSR74: Transmit Ring Counter CSR76: Receive Ring Length CSR78: Transmit Ring Length CSR80: Burst FIFO Threshold Control CSR82: Activity Timer CSR84: Address Lower CSR85: Address Upper CSR86: Buffer Byte Counter
Am79C965
CSR88: Chip Lower CSR89: Chip Upper CSR92: Ring Length Conversion CSR94: Transmit Time Domain Reflectometry Count CSR96: Interface Scratch Register Lower CSR97: Interface Scratch Register Upper CSR98: Interface Scratch Register Lower CSR99: Interface Scratch Register Upper CSR100: Time-out CSR104: SWAP Register Lower CSR105: SWAP Register Upper CSR108: Buffer Management Scratch Lower CSR109: Buffer Management Scratch Upper CSR112: Missed Frame Count CSR114: Receive Collision Count CSR122: Receive Frame Alignment Control CSR124: Buffer Management Test CONFIGURATION REGISTERS BCR0: Master Mode Read Active BCR1: Master Mode Write Active BCR2: Miscellaneous Configuration BCR4: Link Status (LNKST) BCR5: LED1 Status BCR6: LED2 Status BRC7:LED3 Status BCR16: Base Address Lower BCR17: Base Address Upper BCR18: Burst Size Control BCR19: EEPROM Control Status BCR20: Software Style BCR21: Interrupt Control INITIALIZATION BLOCK RLEN TLEN RDRA TDRA LADRF PADR MODE RECEIVE DESCRIPTORS RMD0 RMD1 RMD2 RMD3 TRANSMIT DESCRIPTORS TMD0 TMD1
Am79C965
PRELIMINARY TMD2 TMD3 REGISTER SUMMARY CSRs Control Status Registers BCRs Configuration Registers
ABSOLUTE MAXIMUM RATINGS OPERATING RANGES CHARACTERISTICS SWITCHING CHARACTERISTICS INTERFACE 10BASE-T INTERFACE ATTACHMENT UNIT INTERFACE GENERAL PURPOSE SERIAL INTERFACE EXTERNAL ADDRESS DETECTION INTERFACE SWITCHING WAVEFORMS SWITCHING TEST CIRCUITS ESTIMATED OUTPUT VALID DELAY LOAD CAPACITANCE SWITCHING WAVEFORMS: SYSTEM INTERFACE SYSTEM INTERFACE 10BASE-T INTERFACE ATTACHMENT UNIT INTERFACE GENERAL PURPOSE SERIAL INTERFACE EXTERNAL ADDRESS DETECTION INTERFACE DATA SHEET REVISION SUMMARY APPENDIX PCNET-32 COMPATIBLE MEDIA INTERFACE MODULES APPENDIX RECOMMENDATION POWER GROUND DECOUPLING APPENDIX ALTERNATIVE METHOD INITIALIZATION APPENDIX INTRODUCTION LOOK-AHEAD PACKET PROCESSING CONCEPT
Am79C965
BLOCK DIAGRAM: VESA VL-BUS MODE
LCLK BE0-BE3 BRDY WBACK BLAST LRDY RDYRTN M/IO INTR1-INTR4 LREQ LREQI LGNT LGNTO SLEEP LDEV LEADS LBS16 RESET ADR2-ADR31 DAT0-DAT31 VLBEN LB/VESA
FIFO
802.3 Core Manchester Encoder/ Decoder (PLS) Port CI+/- DI+/- XTAL1 XTAL2 DO+/- RXD+/- 10BASE-T TXD+/- TXP+/- LNKST
VESA VL-Bus Interface Unit
FIFO
FIFO Control
Microwire, LED, JTAG Control Buffer Management Unit
EEDI EECS EESK EEDO SHFBUSY LED1-LED3
18219C-1
Am79C965
CONNECTION DIAGRAM: VESA VL-BUS MODE
SHFBUSY DVSSN15 EECS SLEEP EESK/LED1/SFBD EEDI/LNKST LB/VESA EEDO/LEDPRE3/SRD INTR1 ADR18 ADR19 ADR20 DVSSN14 ADR21 ADR22 ADR23 ADR24 DVDDO5 ADR25 ADR26 DVSSN13 ADR27 ADR28 DVSS4 DVDD3 ADR29 ADR30 ADR31 AVDD2 AVDD1 AVSS1 LED2/SRDCLK DVSSN1 ADR17 ADR16 ADR15 ADR14 DVDDO1 ADR13 ADR12 DVSSN2 ADR11 ADR10 ADR9 ADR8 ADR7 DVSSN3 ADR6 ADR5 DVSSPAD ADR4 ADR3 DVSSN4 ADR2 LBS16 DVDD1 LEADS DVSSCLK LCLK DVDDCLK VLBEN BLAST LGNT BRDY DVDDO2 LREQ DVSS1 LDEV
XTAL2 AVSS2 XTAL1 AVDD3 TXD+ TXP+ TXD- TXP- AVDD4 RXD+ RXD- DVSS3 JTAGSEL INTR2/EAR INTR3/TDI DVSSN12 INTR4/TMS LGNTO/TCK LREQI/TDO DAT0 DAT1 DVSSN11 DAT2 DVDD2 DAT3 DAT4 DAT5 DVDDO4 DAT6 DVSSN10 DAT7 DAT8 DAT9 DAT10 DAT11 DVSSN9 DAT12
RDYRTN LRDY M/IO RESET DVSSN5 WBACK DAT31 DAT30 DAT29 DAT28 DVSSN6 DAT27 DAT26 DAT25 DAT24 DAT23 DVDDO3 DAT22 DVSSN7 DAT21 DVSS2 DAT20 DAT19 DAT18 DAT17 DVSSN8 DAT16 DAT15 DAT14 DAT13
18219C-3
Am79C965
DESIGNATIONS: VESA VL-BUS MODE Listed Number
LED2/SRDCLK DVSSN1 ADR17 ADR16 ADR15 ADR14 DVDDO1 ADR13 ADR12 DVSSN2 ADR11 ADR10 ADR9 ADR8 ADR7 DVSSN3 ADR6 ADR5 DVSSPAD ADR4 ADR3 DVSSN4 ADR2 LBS16 DVDD1 LEADS DVSSCLK LCLK DVDDCLK VLBEN BLAST LGNT BRDY DVDDO2 LREQ DVSS1 LDEV Name RDYRTN LRDY M/IO RESET DVSSN5 WBACK DAT31 DAT30 DAT29 DAT28 DVSSN6 DAT27 DAT26 DAT25 DAT24 DAT23 DVDDO3 DAT22 DVSSN7 DAT21 DVSS2 DAT20 DAT19 DAT18 DAT17 DVSSN8 DAT16 DAT15 DAT14 DAT13 Name DAT12 DVSSN9 DAT11 DAT10 DAT9 DAT8 DAT7 DVSSN10 DAT6 DVDDO4 DAT5 DAT4 DAT3 DVDD2 DAT2 DVSSN11 DAT1 DAT0 LREQI/TDO LGNTO/TCK INTR4/TMS DVSSN12 INTR3/TDI INTR2/EAR JTAGSEL DVSS3 RXD- RXD+ AVDD4 TXP- TXD- TXP+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 Name AVSS1 AVDD1 AVDD2 ADR31 ADR30 ADR29 DVDD3 DVSS4 ADR28 ADR27 DVSSN13 ADR26 ADR25 DVDDO5 ADR24 ADR23 ADR22 ADR21 DVSSN14 ADR20 ADR19 ADR18 INTR1 EEDO/LEDPRE3/SRD LB/VESA EEDI/LNKST EESK/LED1/SFBD SLEEP EECS DVSSN15 SHFBUSY Name
Am79C965
DESIGNATIONS: VESA VL-BUS MODE Listed Name
Name ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR8 ADR9 ADR10 ADR11 ADR12 ADR13 ADR14 ADR15 ADR16 ADR17 ADR18 ADR19 ADR20 ADR21 ADR22 ADR23 ADR24 ADR25 ADR26 ADR27 ADR28 ADR29 ADR30 ADR31 AVDD1 AVDD2 AVDD3 AVDD4 AVSS1 AVSS2 BLAST BRDY DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7 DAT8 DAT9 DAT10 DAT11 DAT12 DAT13 DAT14 DAT15 DAT16 DAT17 DAT18 DAT19 DAT20 DAT21 DAT22 DAT23 DAT24 DAT25 DAT26 DAT27 DAT28 DAT29 DAT30 DAT31 Name DVDD1 DVDD2 DVDD3 DVDDCLK DVDDO1 DVDDO2 DVDDO3 DVDDO4 DVDDO5 DVSS1 DVSS2 DVSS3 DVSS4 DVSSCLK DVSSN1 DVSSN2 DVSSN3 DVSSN4 DVSSN5 DVSSN6 DVSSN7 DVSSN8 DVSSN9 DVSSN10 DVSSN11 DVSSN12 DVSSN13 DVSSN14 DVSSN15 DVSSPAD EECS EEDI/LNKST EEDO/LEDPRE3/SRD EESK/LED1/SFBD INTR1 INTR2/EAR INTR3/TDI INTR4/TMS Name Name JTAGSEL LB/VESA LBS16 LCLK LDEV LEADS LED2/SRDCLK LGNT LGNTO/TCK LRDY LREQ LREQI/TDO M/IO RDYRTN RESET RXD+ RXD- SHFBUSY SLEEP TXD+ TXD- TXP+ TXP- VLBEN WBACK XTAL1 XTAL2
Am79C965
DESIGNATIONS: VESA VL-BUS MODE Listed Group
Name VESA VL-Bus Interface ADR2-ADR31 BE0-BE3 BLAST BRDY DAT0-DAT31 INTR1 INTR2 INTR3 INTR4 JTAGSEL LB/VESA LBS16 LCLK LDEV LEADS LGNT LGNTO LRDY LREQ LREQI M/IO RDYRTN RESET VLBEN WBACK Board Interface EECS EEDI/LNKST EEDO/LEDPRE3 EESK/LED1 LED2 SHFBUSY SLEEP XTAL1 XTAL2 Microwire Serial EEPROM Chip Select Microwire Serial EEPROM Data In/Link Status Microwire Address EEPROM Data Out/LED3 predriver Microwire Serial EEPROM Clock/LED1 Output Number Shift Busy (for external EEPROM-programmable logic) Sleep Mode Crystal Input Crystal Output Address Address Status Byte Enable Burst Last Burst Ready Data/Control Select Data Interrupt Number Interrupt Number Interrupt Number Interrupt Number JTAG Select Local Bus/VESA VL-Bus Select Local Size Local Clock Local Device Local External Address Strobe Local Grant Local Grant Local Ready Local Request Local Request Memory/I/O Select Ready Return Reset Burst Enable Write/Read Select Write Back Function Type Driver Pins
Am79C965
DESIGNATIONS: VESA VL-BUS MODE (continued) Listed Group
Name Attachment Unit Interface (AUI) CI+/CI- DI+/DI- DO+/DO- Collision Differential Pair Data Differential Pair Data Differential Pair Function Type Driver Pins
Twisted-Pair Transceiver Interface (10BASE-T) RXD+/RXD- TXD+/TXD- TXP+/TXP- LNKST/EEDI Receive Differential Pair Transmit Differential Pair Transmit Predistortion Differential Pair Link Status/Microwire Serial EEPROM Data
IEEE 1149.1 Test Access Port Interface (JTAG) Test Clock Test Data Test Data Test Mode Select
External Address Detection Interface (EADI) SRDCLK SFBD Power Supplies AVDD AVSS DVDD DVDDCLK DVDDO DVSS DVSSCLK DVSSN DVSSPAD Analog Power Analog Ground Digital Power Digital Power Clock Buffer Digital Power Digital Ground Digital Ground Clock Buffer Digital Ground Digital Ground External Address Reject Serial Receive Data Serial Receive Data Clock Start Frame-Byte Delimiter
Am79C965
DESIGNATIONS: VESA VL-BUS MODE Driver Type
Table Output Driver Types
Name Type Tri-State Totem Pole Totem Pole Open Drain (mA) -0.4 (mA) -0.4 -0.4 -0.4
Table
Signal
Pins with Pullups
Pullup
Am79C965
PRELIMINARY PCnet-32 controller will programmed VESA-VL Mode. Note that setting LB/VESA determines functionality following pins (names parentheses pins local mode): VLBEN (Am486), RESET (RESET), LBS16 (AHOLD), LREQ (HOLD), LGNT (HLDA), LREQI (HOLDI) LGNTO (HLDAO).
DESCRIPTION: VESA VL-BUS MODE Configuration Pins JTAGSEL
JTAG Function Select Input value this will asynchronously select between JTAG Mode Multi-Interrupt Mode. value this will asynchronously affect function JTAG-INTR-Daisy chain arbitration pins, regardless state RESET regardless state LCLK pin. value "1", then PCnet-32 controller will programmed JTAG mode. value "0", then PCnet-32 controller will programmed Multi-Interrupt Mode. When programmed JTAG mode, four pins PCnet-32 controller will configured JTAG (IEEE 1149.1) Test Access Port. When programmed Multi-Interrupt Mode, JTAG pins will become interrupts JTAG pins will used daisy chain arbitration support. Table below outlines changes that will occur programming JTAGSEL pin. Table JTAG Changes
LGNT0/TCK LGNT1/TDO LGNT2/TDI LGNT3/TMS JTAGSEL=1 JTAG mode JTAGSEL=0 Multi-Interrupt Mode LGNTO LREQI INTR3 INTR4
VLBEN
Burst Enable Input This used determine whether bursting supported PCnet-32 device VESA VL-Bus mode. VLBEN sampled every rising edge LCLK while RESET asserted. VESA-VL mode (the LB/VESA tied VSS), sampled value VLBEN low, then BREADE BWRITE bits BCR18 will forced low, PCnet-32 controller will never attempt perform linear burst reads writes. sampled value VLBEN high, linear burst accesses permitted, consistent with values programmed into BREADE BWRITE. Because byte-duplication conventions within 32-bit Am386 system, PCnet-32 controller will always produce correct bytes correct byte lanes accordance with Am386DX data sheet. This byte duplication will automatically occur, regardless operating mode selected LB/VESA pin. VLBEN tied directly VSS. series resistor used necessary. VLBEN need only valid when RESET active (regardless connection LB/VESA pin) tied ID(3) VESA VL-Bus version system, logical ID(4), ID(3), ID(1), ID(0) VESA-VL-Bus version system.
JTAGSEL tied directly VSS. series resistor used necessary.
LB/VESA
Local Bus/VESA VL-Bus Select Input value this will asynchronously determine operating mode PCnet-32 controller, regardless state RESET regardless state LCLK pin. LB/VESA tied VDD, then PCnet-32 controller will programmed Local Mode. LB/VESA tied VSS, then
Note: This needs tied when LB/VESA been tied VDD. description Am486 Local Mode section.
Configuration Settings Summary
Table below shows possible configurations that invoked with PCnet-32 controller configuration pins.
Table Configuration Settings
LB/VESA VLBEN JTAGSEL Mode Selected mode with interrupts daisy chain arbitration mode with interrupts JTAG Am486 mode with interrupts daisy chain arbitration Am486 mode with interrupts JTAG Reserved
Don't care
Am79C965
Connections
Several pins connected various application options. Some pins required connected order controller into particular mode operation, while other pins might connected that pin's function implemented specific application. Table shows which pins require connection VSS, which pins optionally connected because application does support that pin's function. table also shows whether connections need resistive.
determine current access directed toward PCnet-32 controller. will driven when PCnet-32 controller performs master access local bus.
BE0-BE3
Byte Enable Input/Output These signals indicate which bytes data active during read write cycles. When active, byte DAT31-DAT24 valid. BE2-BE0 active indicate valid data pins DAT23-DAT16, DAT15- DAT8, DAT7-DAT0, respectively. byte enable signals outputs master inputs slave operations.
VESA VL-Bus Interface ADR2-ADR31
Address Input/Output Address information which stable during operation, regardless source. When PCnet-32 controller Current Master, A2-A31 will driven. When PCnet-32 controller Current Master, A2-A31 lines continuously monitored determine address match exists slave transfers.
BLAST
Burst Last Output When BLAST signal asserted, then next time that BRDY RDYRTN asserted, burst cycle complete.
BRDY
Burst Ready Input/Output BRDY functions input PCnet-32 controller during master cycles. When BRDY asserted during master cycle, indicates PCnet-32 controller that target device accepting burst transfers. also serves same function RDYRTN does nonburst accesses. That indicates that target device accepted data master write cycle, that target device presented valid data onto during master read cycles.
Address Status Input/Output When driven LOW, this signal indicates that valid cycle definition address available M/IO, D/C, A2-A31 pins local interface. that time, PCnet-32 controller will examine combination M/IO, D/C, W/R, A2-A31 pins
Table Connections Power/Ground
Supply Strapping Required Optional Required Optional Optional Required Optional Required Optional Required Optional Optional Resistive Connection Supply Required Required Optional Required Required Optional Required Optional Required Required Required Required Recommended Resistor Size series with LED, without series with LED, without series with LED, without
Name LED2/SRDCLK LBS16 VLBEN WBACK LREQI/TDO JTAGSEL EEDO/LEDPRE3/SRD LB/VESA EEDI/LNKST EESK/LED1/SFBD SLEEP Other Pins
Am79C965
BRDY RDYRTN sampled active same cycle, then RDYRTN takes precedence, causing next transfer cycle begin with cycle. BRDY functions output during PCnet-32 controller slave cycles always driven inactive (HIGH). BRDY floated PCnet-32 controller being accessed current slave device local bus.
INTR1-INTR4
Interrupt Request Output attention signal which indicates that more following status flags set: BABL, MISS, MERR, RINT, IDON, MFCO, RCVCCO, TXSTRT, JAB. Each these status flags mask which allows suppression INTR assertion. These flags have meaning shown Table Table Status Flags
BABL MISS MERR RINT IDON MFCO RCVCCO TXSTRT Babble (CSR0, Missed Frame (CSR0, Memory Error (CSR0, Receive Interrupt (CSR0, Initialization Done (CSR0, Missed Packet Count Overflow (CSR4, Receive Collision Count Overflow (CSR4, Transmit Start (CSR4, Jabber (CSR4,
Data/Control Select Input/Output During slave accesses PCnet-32 controller, pin, along with M/IO W/R, indicates type cycle that being performed. PCnet-32 controller will only respond local accesses which driven HIGH local master. During PCnet-32 controller master accesses, output will always driven HIGH. floated PCnet-32 controller current master local bus.
DAT0-DAT31
Data Input/Output Used transfer data from PCnet-32 controller system resources local bus. DAT31-DAT0 driven PCnet-32 controller when performing master writes slave read operations. Data DAT31-DAT0 latched PCnet-32 controller when performing master reads slave write operations. PCnet-32 controller will always follow Am386DX byte lane conventions. This means that word byte accesses which PCnet-32 controller drives data (i.e. master write operations slave read operations), PCnet-32 controller will produce duplicates active bytes unused half 32-bit data bus. Table illustrates cases which duplicate bytes created. Table Byte Duplication Data
BE3- 1110 1101 1011 0111 1100 1001 0011* 1000 0001 0000 [31:24] Undef Undef Undef Undef Undef Undef [23:16] Undef Undef Undef Undef [15:8] Undef Undef Copy Copy [7:0] Undef Copy Undef Undef Copy Undef
Note that there four possible interrupt pins, depending upon mode that been selected with JTAGSEL pin. Only interrupt used time. active interrupt selected programming interrupt select register (BCR21). default setting BCR121will select interrupt INTR1 active interrupt. Note that BCR21 EEPROM-programmable. Inactive interrupt pins floated. polarity interrupt signal determined INTLEVEL BCR2. interrupt pins programmed level-sensitive edge-sensitive operation. PCnet-32 controller interrupt pins will floated H_RESET will remain floated until either EEPROM been successfully read, following EEPROM read failure, Software Relocatable Mode sequence been successfully executed.
LBS16
Local Size Input BS16 sampled during PCnet-32 controller mastering activity determine target device VL-Bus bits width. LBS16 signal sampled active least clock period before assertion LRDY during PCnet-32 controller master transfer, then PCnet-32 controller will convert single 32-bit transfer into 16-bit transfers. 32-bit transfers need split into 16-bit transfers. Table shows sequence transfers that will executed each possible 32-bit transfer that encounters proper assertion LBS16 signal.
*Note: Byte duplication does apply during LBS16 access. Table
Am79C965
PRELIMINARY Table Data Transfer Sequence from 32-Bit Wide 16-Bit Wide
Current Access Next with LBS16
second access Required these cases
During accesses which PCnet-32 controller acting VL-Bus target device, LBS16 signal will driven. this case, expected that VL-Bus required pull-up device will bring LBS16 signal inactive level PCnet-32 controller will seen VL-Bus master 32-bit peripheral.
LGNTO
Local Grant Output This signal multiplexed with pin, available only when Multi-Interrupt mode been selected with JTAGSEL pin. additional local master daisy-chain LGNT signal through PCnet-32 controller LGNTO pin. PCnet-32 controller will deliver LGNTO signal additional local master whenever PCnet-32 controller receives LGNT from arbitration logic, simultaneously requesting internally. second local master must connect LREQ output LREQI input PCnet-32 controller order complete local daisy-chain arbitration control. When SLEEP asserted, daisy chain arbitration signals that pass through PCnet-32 controller will experience one-clock delay from input output (i.e. LREQI LREQ LGNT LGNTO). While SLEEP asserted (either snooze mode coma mode), PCnet-32 controller configured daisy chain (LREQI LGNTO signals have been selected with JTAGSEL pin), then system arbitration signal LGNT will passed directly daisychain signal LGNTO without experiencing one-clock delay. However, some combinatorial delay will introduced this path. Note that this changes polarity when Local mode been selected (see description HLDAO Local Interface section).
LCLK
Local Clock Input LCLK clock that follows same phase 486-type clock. LCLK always driven system logic VL-Bus controller VL-Bus masters targets. rising edge clock signifies change states, hence, change PCnet-32 controller states.
LDEV
Local Device Output LDEV driven PCnet-32 controller when recognizes access PCnet-32 controller space. Such recognition dependent upon valid sampled strobe plus valid M/IO, ADR31-ADR5 values.
LEADS
Local External Address Strobe Output During VL-Bus master write read accesses LEADS will asserted every cycle specified VESA VL-Bus specification, regardless settings GCIC BCR18 bits BCR18.
LGNT
Local Grant Input When LGNT asserted LREQ being asserted PCnet-32 controller, PCnet-32 controller assumes ownership bus. Note that this changes polarity when Local mode been selected (see description HLDA Local Interface section).
LRDY
Local Ready Output LRDY functions output from PCnet-32 controller during PCnet-32 controller slave cycles. During PCnet-32 controller slave read cycles, LRDY asserted indicate that valid data been presented
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data bus. During PCnet-32 controller slave write cycles, LRDY asserted indicate that data data been internally latched. LRDY will asserted clock period when PCnet-32 controller wishes terminate cycle. LRDY then driven high one-half clock period before being released. LRDY floated PCnet-32 controller current slave local bus.
M/IO
Memory Select Input/Output During slave accesses PCnet-32 controller, M/IO pin, along with W/R, indicates type cycle that being performed. PCnet-32 controller will only respond local accesses which M/IO sampled zero PCnet-32 controller. During PCnet-32 controller master accesses, M/IO output will always driven high. M/IO floated PCnet-32 controller current master local bus.
LREQ
Local Request Output LREQ used PCnet-32 controller gain control VL-Bus become active Master. LREQ active low. Once asserted, LREQ remains active until LGNT become active, independent subsequent assertion SLEEP setting STOP access S_RESET port (offset 14h). Note that this changes polarity when Local mode been selected (see description HOLD Local Interface section).
RDYRTN
Ready Return Input RDYRTN functions input PCnet-32 controller. RDYRTN used terminate master accesses performed PCnet-32 controller, except that linear burst transfers also terminated with BRDY signal. RDYRTN used terminate slave read accesses PCnet-32 controller space. When asserted during slave read accesses PCnet-32 controller space, RDYRTN indicates that mastering device seen LRDY that generated PCnet-32 controller accepted PCnet-32 controller slave read data. Therefore, PCnet-32 controller will hold slave read data until synchronously samples RDYRTN input active low. PCnet-32 controller will hold LRDY valid asserted during this time. duration LRDY pulse generated PCnet-32 controller will always single LCLK cycle. RDYRTN ignored during slave write accesses PCnet-32 controller space. Slave write accesses PCnet-32 controller space considered terminated PCnet-32 controller cycle during which PCnet-32 controller issues active RDY. systems where both LRDY RDYRTN equivalent) signals provided, then LRDY must tied RDYRTN. Most systems provide local device ready input memory controller that separate from READY signal. This second READY signal usually labeled READYIN. This signal should connected PCnet-32 controller LRDY signal. READY signal should connected PCnet-32 controller RDYRTN pin. systems where only READY signal provided, then PCnet-32 controller LRDY output tied PCnet-32 controller RDYRTN input.
LREQI
Local Request Input This signal multiplexed with pin, available only when Multi-Interrupt mode been selected with JTAGSEL pin. additional local master daisy-chain hold request signal through PCnet-32 controller LREQI pin. PCnet-32 controller will convey LREQI request arbitration logic PCnet-32 controller LREQ output. second local master must connect LGNT input LGNTO output PCnet-32 controller order complete local daisy-chain arbitration control. When SLEEP asserted, daisy chain arbitration signals that pass through PCnet-32 controller will experience one-clock delay from input output (i.e. LREQI LREQ LGNT LGNTO). While SLEEP asserted (either snooze mode coma mode), PCnet-32 controller configured daisy chain (LREQI LGNTO signals have been selected with JTAGSEL pin), then daisy-chain signal LREQI will passed directly system arbitration signal LREQ without experiencing one-clock delay. However, some combinatorial delay will introduced this path. Multi-Interrupt mode been selected daisychain arbitration feature used, then LREQI input should tied VDD. Note that this changes polarity when Local mode been selected (see description HOLDI Local Interface section).
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RESET
System Reset Input When RESET asserted LB/VESA been tied VSS, then PCnet-32 controller performs internal system reset H_RESET type (HARDWARE_RESET). RESET must held minimum LCLK periods when mode been selected. While H_RESET state, PCnet-32 controller will float deassert outputs.
LED2
LED2 Output This shared with SRDCLK function. When operating LED2, function polarity this programmable through BCR6. LED2 output from PCnet-32 controller capable sinking necessary current drive directly. This also selects address width Software Relocatable Mode. When this HIGH during Software Relocatable Mode, then device will programmed bits addressing while snooping accesses during Software Relocatable Mode. When this during Software Relocatable Mode, then device will programmed bits addressing while snooping accesses during Software Relocatable Mode. upper bits address will assumed match during snooping operation when LED2 LOW. 24-bit addressing mode intended systems that employ GPSI signals. more information GPSI function section General Purpose Serial Interface. circuit attached this pin, then pull pull down resistor must attached instead, order resolve Software Relocatable Mode address width setting.
Write/Read Select Input/Output During slave accesses PCnet-32 controller, pin, along with M/IO, indicates type cycle that being performed. During PCnet-32 controller master accesses, output. floated PCnet-32 controller current master local bus.
WBACK
Write Back Input WBACK monitored input during VL-Bus Master Accesses. When PCnet-32 controller current VL-Bus master, PCnet-32 controller will float appropriate mastering signals within clock period assertion WBACK. When WBACK deasserted, PCnet-32 controller will re-execute accesses that were suspended assertion WBACK then will proceed with other scheduled accesses, any. Register access cannot performed PCnet-32 device while WBACK asserted.
LEDPRE3
LEDPRE3 Output This shared with EEDO function. When operating LEDPRE3, function polarity this programmable through BCR7. This signal labeled "PRE" because multi-function nature this pin. circuit were directly attached this pin, would create requirement that could serial EEPROM that would also attached this pin. Therefore, this used additional output while EEPROM used system, then buffering required between LEDPRE3 circuit. EEPROM included system design, then LEDPRE3 signal directly connected without buffering. LEDPRE3 output from PCnet-32 controller capable sinking necessary current drive this case. more details regarding connection, section LEDs.
Board Interface LED1
LED1 Output This shared with EESK function. When operating LED1, function polarity this programmable through BCR5. LED1 output from PCnet-32 controller capable sinking necessary current drive directly. LED1 also used during EEPROM Auto-detection determine whether EEPROM present PCnet-32 controller microwire interface. trailing edge RESET, this sampled determine value EEDET BCR19. sampled HIGH value means that EEPROM present, EEDET will ONE. sampled value means that EEPROM present, EEDET will ZERO. "EEPROM Auto-detection" section more details. circuit attached this pin, then pull-up pull-down resistor must attached instead, order resolve EEDET setting.
LNKST
Link Status Output This provides driving LED. indicates active link connection 10BASE-T interface. function polarity programmable through BCR4. Note that this multiplexed with EEDI function. This remains active snooze mode.
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PRELIMINARY assertion SLEEP until three LCLK cycles after completion valid RESET operation.
SHFBUSY
Shift Busy Output function SHFBUSY signal indicate when last byte EEPROM contents been shifted EEPROM EEDO signal line. This information useful external EEPROM-programmable registers that microwire protocol, described herein: When PCnet-32 controller performing serial read EEPROM through microwire interface, SHFBUSY signal will driven HIGH. SHFBUSY serve serial shift enable allow EEPROM data serially shifted into external device series devices. SHFBUSY signal will remain actively driven HIGH until EEPROM read operation. EEPROM checksum verified, then SHFBUSY signal will driven EEPROM read operation. EEPROM checksum verification failed, then SHFBUSY signal will remain HIGH. This function effectively demarcates successful EEPROM read operation therefore useful programmable-logic low-active output enable signal. more details external EEPROM-programmable registers, EEPROM Microwire Access section under Hardware Access. This controlled host system writing BCR19, (EBUSY).
XTAL1-XTAL2
Crystal Oscillator Inputs Input/Output crystal frequency determines network data rate. PCnet-32 controller supports quartz crystals generate frequency compatible with 8802-3 (IEEE/ANSI 802.3) network frequency tolerance jitter specifications. section External Crystal Characteristics section Manchester Encoder/Decoder) more detail. network data rate one-half crystal frequency. XTAL1 alternatively driven using external CMOS level source, which case XTAL2 must left unconnected. Note that when PCnet-32 controller coma mode, there internal resistor from XTAL1 ground. external source drives XTAL1, some power will consumed driving this resistor. XTAL1 driven this time power consumption will minimized. this case, XTAL1 must remain active least cycles after assertion SLEEP deassertion LREQ.
Microwire EEPROM Interface EESK
EEPROM Serial Clock Output EESK signal used access external 8802-3 (IEEE/ANSI 802.3) address PROM. This designed directly interface serial EEPROM that uses microwire interface protocol. EESK connected microwire EEPROM's Clock pin. controlled either PCnet-32 controller directly during read entire EEPROM, indirectly host system writing BCR19, EESK used during programming external EEPROM-programmable registers that microwire protocol follows: When PCnet-32 controller performing serial read IEEE Address EEPROM through microwire interface, SHFBUSY signal will serve serial shift enable allow EEPROM data serially shifted into external device series devices. This same signal used gate output programmed logic avoid problem releasing intermediate values rest system board logic. EESK signal serve clock, EEDO will serve input data stream programmable shift register.
SLEEP
Sleep Input When SLEEP input asserted (active LOW), PCnet-32 controller performs internal system reset S_RESET type then proceeds into power savings mode. (The reset operation caused SLEEP assertion will affect registers.) outputs will placed their normal S_RESET condition. During sleep mode, PCnet-32 controller inputs will ignored except SLEEP itself. De-assertion SLEEP results wake-up. system must refrain from starting network operations PCnet-32 controller seconds following deassertion SLEEP signal order allow internal analog circuits stabilize. Both LCLK XTAL1 inputs must have valid clock signals present order SLEEP command take effect. SLEEP asserted while LREQ asserted, then PCnet-32 controller will perform internal system S_RESET then wait assertion LGNT. When LGNT asserted, LREQ signal will deasserted then PCnet-32 controller will proceed power savings mode. Note that internal system S_RESET will cause LREQ signal deasserted. SLEEP should asserted during power supply ramp-up. desired that SLEEP asserted power time, then system must delay
EEDO
EEPROM Data Input EEDO signal used access external 8802-3 (IEEE/ANSI 802.3) address PROM. This designed directly interface serial EEPROM that uses microwire interface protocol. EEDO connected microwire EEPROM's Data Output pin.
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PRELIMINARY controlled EEPROM during reads. read host system reading BCR19, EEDO used during programming external EEPROM-programmable registers that microwire protocol follows: When PCnet-32 controller performing serial read IEEE Address EEPROM through microwire interface, SHFBUSY signal will serve serial shift enable allow EEPROM data serially shifted into external device series devices. This same signal used gate output programmed logic avoid problem releasing intermediate values rest system board logic. EESK signal serve clock, EEDO will serve input data stream programmable shift register.
Data Output differential output pair from PCnet-32 controller transmitting Manchester encoded data network. Operates pseudo levels.
Twisted Pair Interface RXD±
10-BASE-T Receive Data 10BASE-T port differential receivers.
Input
TXD±
10BASE-T Transmit Data 10BASE-T port differential drivers.
Output
TXP±
10BASE-T Pre-distortion Control Output These outputs provide transmit predistortion control conjunction with 10BASE-T port differential drivers.
EECS
EEPROM Chip Select Output function EECS signal indicate microwire EEPROM device that being accessed. EECS signal active high. controlled either PCnet-32 controller during read entire EEPROM, indirectly host system writing BCR19,
External Address Detection Interface
EADI interface enabled through BCR2 (EADISEL).
External Address Reject Input EADI input signal. incoming frame will checked against internally active address detection mechanisms result this check will OR'd with value pin. defined REJECT. EADI section details regarding function timing this signal. Note that this multiplexed with INTR2 pin.
EEDI
EEPROM Data Output EEDI signal used access external 8802-3 (IEEE/ANSI 802.3) address PROM. EEDI functions output. This designed directly interface serial EEPROM that uses microwire interface protocol. EEDI connected microwire EEPROM's Data Input pin. controlled either PCnet-32 controller during command portions read entire EEPROM, indirectly host system writing BCR19,
SFBD
Start Frame-Byte Delimiter Output Start Frame-Byte Delimiter Enable. EADI output signal. initial rising edge this signal indicates that start frame delimiter been detected. serial stream will follow signal, commencing with destination address field. SFBD will high times (400 after detecting second (Start Frame Delimiter) received frame. SFBD will subsequently toggle every (1.25 frequency) with each rising edge indicating first each subsequent byte received serial stream. SFBD will inactive during frame transmission. Note that this multiplexed with LED1 pin.
Attachment Unit Interface
Collision Input differential input pair signaling PCnet-32 controller that collision been detected network media, indicated inputs being driven with pattern sufficient amplitude pulse width meet 8802-3 (IEEE/ANSI 802.3) standards. Operates pseudo levels.
Data Input differential input pair PCnet-32 controller carrying Manchester encoded data from network. Operates pseudo levels.
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PRELIMINARY Note that this signal must meet frequency stability requirement 8802-3 (IEEE/ANSI 802.3) specification crystal.
Serial Receive Data Output EADI output signal. decoded data from network. This signal used external address detection. Note that when 10BASE-T port selected, transitions will only occur during receive activity. When port selected, transitions will occur during both transmit receive activity. Note that this multiplexed with LEDPRE3 pin.
CLSN
Collision Input/Output CLSN input, indicating core logic that collision occurred network. Note that CLSN multiplexed with pin.
RXCRS
Receive Carrier Sense Input/Output RXCRS input. When this signal HIGH, indicates core logic that data RXDAT input valid. Note that RXCRS multiplexed with pin.
SRDCLK
Serial Receive Data Clock Output EADI output signal. Serial Receive Data synchronous with reference SRDCLK. Note that when 10BASE-T port selected, transitions SRDCLK will only occur during receive activity. When port selected, transitions SRDCLK will occur during both transmit receive activity. Note that this multiplexed with LED2 pin.
SRDCLK
Serial Receive Data Clock Input/Output SRDCLK input. Rising edges SRDCLK signal used sample data RXDAT input whenever RXCRS input HIGH. Note that SRDCLK multiplexed with pin.
General Purpose Serial Interface
GPSI interface selected through PORTSEL bits Mode register (CSR15) enabled through TSTSHDW[1] (BCR18) CORETEST (CSR124). Note that when GPSI test mode invoked, slave address decoding must restricted lower bits address setting IOAW24 BCR2 pulling LED2 during Software Relocatable Mode. upper bits address will always considered matched when examining incoming addresses. During master accesses while GPSI mode, PCnet-32 controller will drive upper bits address with address information. GPSI section more detail.
RXDAT
Receive Data Input/Output RXDAT input. Rising edges SRDCLK signal used sample data RXDAT input whenever RXCRS input HIGH. Note that RXDAT multiplexed with pin.
IEEE 1149.1 Test Access Port Interface
Test Clock Input clock input boundary scan test mode operation. operate MHz. left unconnected, this default value HIGH.
TXDAT
Transmit Data Input/Output TXDAT output, providing serial stream transmission, including preamble, data field, applicable. Note that TxDAT multiplexed with pin.
Test Data Input Input test data input path PCnet-32 controller. left unconnected, this default value HIGH.
TXEN
Transmit Enable Input/Output TXEN output, providing enable signal transmission. Data TXDAT valid unless TXEN signal HIGH. Note that TXEN multiplexed with pin.
Test Data Output Output test data output path from PCnet-32 controller. floated when JTAG port inactive.
Test Mode Select Input serial input stream used define specific boundary scan test executed. left unconnected, this default value HIGH.
STDCLK
Serial Transmit Data Clock Input STDCLK input, providing clock signal activity, both transmit receive. Rising edges STDCLK used validate TXDAT output data. STDCLK multiplexed with pin.
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Power Supply Pins AVDD
Analog Power Pins) Power There four analog Volt supply pins. Special attention should paid printed circuit board layout avoid excessive noise these lines. Refer Appendix PCnet Family Technical Manual (PID# 18216A) details.
DVDDO
Buffer Digital Power Pins) Power There digital power supply pins (DVDDO1- DVDDO5) used Input/Output buffer drivers.
DVSS
Digital Ground Pins) Ground There digital ground pins (DVSS1-DVSS4) used internal digital circuitry.
AVSS
Analog Ground Pins) Power There analog ground pins. Special attention should paid printed circuit board layout avoid excessive noise these lines. Refer Appendix PCnet Family Technical Manual details.
DVSSCLK
Digital Ground Clock Pin) Ground This used supply ground clock buffering circuitry.
DVSSN
Buffer Digital Ground Pins) Ground These ground pins (DVSSN1-DVSSN15) used Input/Output buffer drivers.
DVDD
Digital Power Pins) Power There digital power supply pins (DVDD1, DVDD DVDD3) used internal digital circuitry.
DVSSPAD
Digital Ground Pin) Ground This used Input/Output logic circuits.
DVDDCLK
Digital Power Clock Pin) Power This used supply power clock buffering circuitry.
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VESA VL-BUS LOCAL CROSS-REFERENCE Listed Number
VESA VL-Bus Mode Name LED2/SRDCLK DVSSN1 ADR17 ADR16 ADR15 ADR14 DVDDO1 ADR13 ADR12 DVSSN2 ADR11 ADR10 ADR9 ADR8 ADR7 DVSSN3 ADR6 ADR5 DVSSPAD ADR4 ADR3 DVSSN4 ADR2 LBS16 DVDD1 LEADS DVSSCLK LCLK DVDDCLK VLBEN BLAST LGNT BRDY DVDDO2 LREQ DVSS1 LDEV Local Mode Name LED2/SRDCLK DVSSN1 DVDDO1 DVSSN2 DVSSN3 DVSSPAD DVSSN4 AHOLD DVDD1 EADS DVSSCLK BCLK DVDDCLK Am486 BLAST HLDA BRDY DVDDO2 HOLD DVSS1 LDEV VESA VL-Bus Mode Name RDYRTN LRDY M/IO RESET DVSSN5 WBACK DAT31 DAT30 DAT29 DAT28 DVSSN6 DAT27 DAT26 DAT25 DAT24 DAT23 DVDDO3 DAT22 DVSSN7 DAT21 DVSS2 DAT20 DAT19 DAT18 DAT17 DVSSN8 DAT16 DAT15 DAT14 DAT13 Local Mode Name RDYRTN M/IO RESET DVSSN5 BOFF DVSSN6 DVDDO3 DVSSN7 DVSS2 DVSSN8
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VESA VL-BUS/LOCAL CROSS-REFERENCE (continued) Listed Number
VESA VL-Bus Mode Name DAT12 DVSSN9 DAT11 DAT10 DAT9 DAT8 DAT7 DVSSN10 DAT6 DVDDO4 DAT5 DAT4 DAT3 DVDD2 DAT2 DVSSN11 DAT1 DAT0 LREQI/TDO LGNTO/TCK INTR4/TMS DVSSN12 INTR3/TDI INTR2/EAR JTAGSEL DVSS3 RXDRXD+ AVDD4 TXPTXDTXP+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 Local Mode Name DVSSN9 DVSSN10 DVDDO4 DVDD2 DVSSN11 HOLDI/TDO HLDAO/TCK INTR4/TMS DVSSN12 INTR3/TDI INTR2/EAR JTAGSEL DVSS3 RXDRXD+ AVDD4 TXPTXDTXP+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 VESA VL-Bus Mode Name AVSS1 DODO+ AVDD1 DIDI+ CICI+ AVDD2 ADR31 ADR30 ADR29 DVDD3 DVSS4 ADR28 ADR27 DVSSN13 ADR26 ADR25 DVDDO5 ADR24 ADR23 ADR22 ADR21 DVSSN14 ADR20 ADR19 ADR18 INTR1 EEDO/LEDPRE3/SRD LB/VESA EEDI/LNKST EESK/LED1/SFBD SLEEP EECS DVSSN15 SHFBUSY Local Mode Name AVSS1 DODO+ AVDD1 DIDI+ CICI+ AVDD2 DVDD3 DVSS4 DVSSN13 DVDDO5 DVSSN14 INTR1 EEDO/LEDPRE3/SRD LB/VESA EEDI/LNKST EESK/LED1/SFBD SLEEP EECS DVSSN15 SHFBUSY
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BLOCK DIAGRAM: LOCAL MODE
BCLK BE0-BE3 BRDY BOFF BLAST RDYRTN M/IO INTR1-INTR4 HOLD HOLDI HLDA HLDAO SLEEP LDEV EADS AHOLD RESET A2-A31 D0-D31 Am486 LB/VESA
FIFO
802.3 Core CI+/- DI+/- XTAL1 XTAL2 DO+/- RXD+/- 10BASE-T TXD+/- TXP+/- LNKST
Manchester Encoder/ Decoder (PLS) Port Local Interface Unit FIFO
FIFO Control
Microwire, LED, JTAG Control Buffer Management Unit
EEDI EECS EESK EEDO SHFBUSY LED1-LED3
18219C-2
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CONNECTION DIAGRAM: LOCAL MODE
SHFBUSY DVSSN15 EECS SLEEP EESK/LED1/SFBD EEDI/LNKST LB/VESA EEDO/LEDPRE3/SRD INTR1 DVSSN14 DVDDO5 DVSSN13 DVSS4 DVDD3 AVDD2 AVDD1 AVSS1 LED2/SRDCLK DVSSN1 DVDD01 DVSSN2 DVSSN3 DVSSPAD DVSSN4 AHOLD DVDD1 EADS DVSSCLK BCLK DVDDCLK Am486 BLAST HLDA BRDY DVDDO2 HOLD DVSS1 LDEV
XTAL2 AVSS2 XTAL1 AVDD3 TXD+ TXP+ TXD- TXP- AVDD4 RXD+ RXD- DVSS3 JTAGSEL INTR2/EAR INTR3/TDI DVSSN12 INTR4/TMS HLDAO/TCK HOLDI/TDO DVSSN11 DVDD2 DVDDO4 DVSSN10 DVSSN9
RDYRTN M/IO RESET DVSSN5 BOFF DVSSN6 DVDDO3 DVSSN7 DVSS2 DVSSN8
18219C-4
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DESIGNATIONS: LOCAL MODE Listed Number
LED2/SRDCLK DVSSN1 DVDDO1 DVSSN2 DVSSN3 DVSSPAD DVSSN4 AHOLD DVDD1 EADS DVSSCLK BCLK DVDDCLK Am486 BLAST HLDA BRDY DVDDO2 HOLD DVSS1 LDEV Name RDYRTN M/IO RESET DVSSN5 BOFF DVSSN6 DVDDO3 DVSSN7 DVSS2 DVSSN8 Name DVSSN9 DVSSN10 DVDDO4 DVDD2 DVSSN11 HOLDI/TDO HLDAO/TCK INTR4/TMS DVSSN12 INTR3/TDI INTR2/EAR JTAGSEL DVSS3 RXD- RXD+ AVDD4 TXP- TXD- TXP+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 Name AVSS1 AVDD1 AVDD2 DVDD3 DVSS4 DVSSN13 DVDDO5 DVSSN14 INTR1 EEDO/LEDPRE3/SRD LB/VESA EEDI/LNKST EESK/LED1/SFBD SLEEP EECS DVSSN15 SHFBUSY Name
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DESIGNATIONS: LOCAL MODE Listed Name
Name AHOLD Am486 AVDD1 AVDD2 AVDD3 AVDD4 AVSS1 AVSS2 BCLK BLAST BOFF BRDY Name DVDD1 DVDD2 DVDD3 DVDDCLK DVDDO1 DVDDO2 DVDDO3 DVDDO4 DVDDO5 DVSS1 DVSS2 DVSS3 DVSS4 DVSSCLK DVSSN1 DVSSN2 DVSSN3 DVSSN4 DVSSN5 DVSSN6 DVSSN7 DVSSN8 DVSSN9 DVSSN10 DVSSN11 DVSSN12 DVSSN13 DVSSN14 DVSSN15 DVSSPAD EADS EECS EEDI/LNKST EEDO/LEDPRE3/SRD Name Name EESK/LED1/SFBD HLDA HLDAO/TCK HOLD HOLDI/TDO INTR1 INTR2/EAR INTR3/TDI INTR4/TMS JTAGSEL LB/VESA LDEV LED2/SRDCLK M/IO RDYRTN RESET RXD+ RXD- SHFBUSY SLEEP TXD+ TXD- TXP+ TXP- XTAL1 XTAL2
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DESIGNATIONS: LOCAL MODE Listed Group
Name 486/386DX Local Interface A2-A31 AHOLD Am486 BCLK BE0-BE3 BLAST BOFF BRDY D0-D31 EADS HLDA HLDAO HOLD HOLDI INTR1 INTR2 INTR3 INTR4 JTAGSEL LB/VESA LDEV M/IO RDYRTN Board Interface EECS EEDI/LNKST EEDO/LEDPRE3 EESK/LED1 LED2 RESET SHFBUSY SLEEP XTAL1 XTAL2 Microwire Serial PROM Chip Select Microwire Serial EEPROM Data In/Link Status Microwire Address PROM Data Out/LED3 predriver Microwire Serial PROM Clock/LED1 Output Number Reset Shift Busy (for external EEPROM-programmable logic) Sleep Mode Crystal Input Crystal Output Address Address Status Address Hold Am486 Mode Select Clock Byte Enable Burst Last Backoff Burst Ready Data/Control Select Data External Address Strobe Hold Acknowledge Hold Acknowledge Hold Request Hold Request Interrupt Number Interrupt Number Interrupt Number Interrupt Number JTAG Select Local Bus/VESA VL-Bus Select Local Device Memory/I/O Select Ready Ready Return Write/Read Select Function Type Driver Pins
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DESIGNATIONS: LOCAL MODE (continued) Listed Group
Name Attachment Unit Interface (AUI) CI+/CI- DI+/DI- DO+/DO- Collision Differential Pair Data Differential Pair Data Differential Pair Function Type Driver Pins
Twisted-Pair Transceiver Interface (10BASE-T) RXD+/RXD- TXD+/TXD- TXP+/TXP- LNKST/EEDI Receive Differential Pair Transmit Differential Pair Transmit Predistortion Differential Pair Link Status/Microwire Serial EEPROM Data
IEEE 1149.1 Test Access Port Interface (JTAG) Test Clock Test Data Test Data Test Mode Select
External Address Detection Interface (EADI) SRDCLK SFBD Power Supplies AVDD AVSS DVDD DVDDCLK DVDDO DVSS DVSSCLK DVSSN DVSSPAD Analog Power Analog Ground Digital Power Digital Power Clock Buffer Digital Power Digital Ground Digital Ground Clock Buffer Digital Ground Digital Ground External Address Reject Serial Receive Data Serial Receive Data Clock Start Frame-Byte Delimiter
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DESIGNATIONS: LOCAL MODE Driver Type
Table Output Driver Types
Name Type Tri-State Totem Pole Totem Pole Open Drain (mA) -0.4 (mA) -0.4 -0.4 -0.4
Table Pins with Pullups
Signal Pullup
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DESCRIPTION: LOCAL MODE Configuration Pins JTAGSEL
JTAG Function Select Input value this will asynchronously select between JTAG Mode Multi-Interrupt Mode. value this will asynchronously affect function JTAG-INTR-Daisy chain arbitration pins, regardless state RESET regardless state BCLK pin. value "1", then PCnet-32 controller will programmed JTAG mode. value "0", then PCnet-32 controller will programmed Multi-Interrupt Mode. When programmed JTAG mode, four pins PCnet-32 controller will configured JTAG (IEEE 1149.1) Test Access Port. When programmed Multi-Interrupt Mode, JTAG pins will become interrupts JTAG pins will used daisy chain arbitration support. Table below outlines changes that will occur programming JTAGSEL pin. Table JTAG Changes
HLDAO/TCK HOLDI/TDO INTR3/TDI INTR4/TMS JTAGSEL=1 JTAG mode JTAGSEL=0 Multi-Interrupt Mode HLDAO HOLDI INTR3 INTR4
JTAGSEL tied directly VSS. series resistor used necessary.
LB/VESA
Local Bus/VESA VL-Bus Select Input value this will asynchronously determine operating mode PCnet-32 controller, regardless state RESET regardless state BCLK pin. LB/VESA tied VDD, then PCnet-32 controller will programmed Local Mode. LB/VESA tied VSS, then PCnet-32 controller will programmed VESA VLBus Mode. Note that setting LB/VESA determines functionality following pins (names parentheses pins VESA VL-Bus Mode): Am486 (VLBEN), RESET (RESET), AHOLD (LBS16), HOLD (LREQ), HLDA(LGNT), HOLDI (LREQI), HLDAO (LGNTO).
Am486
Am486 Mode Select Input Am486 should tied directly VSS. series resistor used necessary. Note: This used enable bursing VESA VLBus mode when LB/VESA been tied VSS. description VLBEN VESA VL-Bus Mode section.
Configuration Settings Summary
Table shows possible configurations that invoked with PCnet-32 controller configuration pins.
Table Configuration Settings
LB/VESA Am486/Am386 JTAGSEL Mode Selected mode with interrupts daisy chain arbitration mode with interrupts JTAG Am486 mode with interrupts daisy chain arbitration Am486 mode with interrupts JTAG Reserved
Don't care
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PRELIMINARY Table Connections Power/Ground
Resistive Connection Supply Required Required Optional Required Required Optional Required Optional Required Required Required Required
Name LED2/SRDCLK AHOLD Am486 BOFF HOLDI/TDO JTAGSEL EEDO/LEDPRE3/SRD LB/VESA EEDI/LNKST EESK/LED1/SFBD SLEEP Other Pins
Supply Strapping Required Optional Required Optional Optional Required Optional Required Optional Required Optional Optional
Recommended Resistor Size series with LED, without series with LED, without series with LED, without
Connections
Several pins connected various application options. Some pins required connected order controller into particular mode operation, while other pins might connected that pin's function implemented specific application. Table shows which pins require connection VSS, which pins optionally connected because application does support that pin's function. table also shows whether connections need resistive.
Address Status Input/Output When driven LOW, this signal indicates that valid cycle definition address available M/IO, D/C, A2-A31 pins local interface. that time, PCnet-32 controller will examine combination M/IO, D/C, W/R, A2-A31 pins determine current access directed toward PCnet-32 controller. will driven when PCnet-32 controller performs master access local bus.
AHOLD
Address Hold Input This always input. PCnet-32 controller will some portion address into high impedance state whenever this signal asserted. AHOLD asserted external cache controller when cache invalidation cycle being performed. AHOLD asserted time, including times when PCnet-32 controller active master. Note that this multiplexed with VESA function: LBS16. Some portion Address will floated time address hold operation, which signaled with AHOLD pin. number Address pins floated will determined value Cache Line Length (CLL) register (BCR18, bits 15-11) shown Table
Local Interface A2-A31
Address Input/Output Address information which stable during operation, regardless source. When PCnet-32 controller Current Master, A1-A31 will driven. When PCnet-32 controller Current Master, A2-A31 lines continuously monitored determine address match exists slave transfers. Some portion Address will floated time address hold operation, which signaled with AHOLD pin. number Address pins floated will determined value Cache Line Length register (BCR18, bits 15-11).
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PRELIMINARY Table Value Floating Address Pins
Value 00000 00001 00010 00011 00100 00101-00111 01000 01001-01111 10000 10001-11111 Floated Portion Address During AHOLD None A31-A2 A31-A3 Reserved Value A31-A4 Reserved Values A31-A5 Reserved Values A31-A6 Reserved Values
that target device presented valid data onto during master read cycles. BRDY RDYRTN sampled active same cycle, then RDYRTN takes precedence, causing next transfer cycle begin with cycle. BRDY functions output during PCnet-32 controller slave cycles always driven inactive (HIGH). BRDY floated PCnet-32 controller being accessed current slave device local bus.
Data/Control Select Input/Output During slave accesses PCnet-32 controller, pin, along with M/IO W/R, indicates type cycle that being performed. PCnet-32 controller will only respond local accesses which driven HIGH local master. During PCnet-32 controller master accesses, output will always driven HIGH. floated PCnet-32 controller current master local bus.
BCLK
Clock Input Clock input that provides timing edges interface signals. This clock used drive system interface internal buffer management unit. This clock used drive network functions.
D0-D31
Data Input/Output Used transfer data from PCnet-32 controller system resources local bus. D31-D0 driven PCnet-32 controller when performing master writes slave read operations. Data D31-D0 latched PCnet-32 controller when performing master reads slave write operations. PCnet-32 controller will always follow Am386DX byte lane conventions. This means that word byte accesses which PCnet-32 controller drives data (i.e. master write operations slave read operations) PCnet-32 controller will produce duplicates active bytes unused half 32-bit data bus. Table illustrates cases which duplicate bytes created.
BE0-BE3
Byte Enable Input/Output These signals indicate which bytes data active during read write cycles. When active, byte D31-D24 valid. BE2-BE0 active indicate valid data pins D23-D16, D15-D8, D7-D0, respectively. byte enable signals outputs master inputs slave operations.
BLAST
Burst Last Output When BLAST signal asserted, then next time that BRDY RDYRTN asserted, burst cycle complete.
BOFF
Backoff Input BOFF monitored input during Master accesses. When PCnet-32 controller current local master, will float appropriate mastering signals within clock period assertion BOFF. When BOFF deasserted, PCnet-32 controller will restart accesses that were suspended assertion BOFF then will proceed with other scheduled accesses, any. Register access cannot performed PCnet-32 device while BOFF asserted.
BRDY
Burst Ready Input/Output BRDY functions input PCnet-32 controller during master cycles. When BRDY asserted during master cycle, indicates PCnet-32 controller that target device accepting burst transfers. also serves same function RDYRTN does nonburst accesses. That indicates that target device accepted data master write cycle, Am79C965
PRELIMINARY second local master must connect HOLD output HOLDI input PCnet-32 controller order complete local daisy-chain arbitration control. When SLEEP asserted, daisy chain arbitration signals that pass through PCnet-32 controller will experience one-clock delay from input output (i.e. HOLDI HOLD HLDA HLDAO). While SLEEP asserted (either snooze mode coma mode), PCnet-32 controller configured daisy chain (HOLDI HLDAO signals have been selected with JTAGSEL pin), then system arbitration signal HLDA will passed directly daisychain signal HLDAO without experiencing one-clock delay. However, some combinatorial delay will introduced this path. Note that this changes polarity when mode been selected (see description LGNTO VESA VL-Bus Interface section).
Table Byte Duplication Data
BE3- 1110 1101 1011 0111 1100 1001 0011* 1000 0001 0000 [31:24] Undef Undef Undef Undef Undef Undef [23:16] Undef Undef Undef Undef [15:8] Undef Undef Copy Copy [7:0] Undef Copy Undef Undef Copy Undef
*Note: Byte duplication does apply during LBS16 access. Table
HOLD
Hold Request Output PCnet-32 controller asserts HOLD signal that wishes become local master. HOLD active high. Once asserted, HOLD remains active until HLDA become active, independent subsequent assertion SLEEP setting STOP access S_RESET port (offset 14h). Note that this changes polarity when mode selected (see description LREQ VESA VL-Bus Interface section).
EADS
External Address Strobe Output During master write accesses which Generate Cache Invalidation Cycles mode been selected, EADS will asserted part PCnet-32 controller cache invalidation cycle. Cache invalidation cycles will occur often cache line reached. cache line size with cache line length bits BCR18 (bits [15:11]).
HLDA
Hold Acknowledge Input PCnet-32 controller examines HLDA signal determine when been granted ownership bus. HLDA active HIGH. When HLDA asserted HOLD being asserted PCnet-32 controller, PCnet-32 controller assumes ownership local bus. However, PCnet-32 controller asserting HOLD because HOLDI asserted daisy chain arbitration), then PCnet-32 controller will assert HLDAO will assume ownership local bus. Note that changes polarity when mode selected (see description LGNT VESA VL-Bus Interface section).
HOLDI
Hold Request Input This signal multiplexed with pin, available only when Multi-Interrupt mode been selected with JTAGSEL pin. additional local master daisy-chain hold request signal through PCnet-32 controller HOLDI pin. PCnet-32 controller will convey HOLDI request PCnet-32 controller HOLD output. second local master must connect HLDA input HLDAO output PCnet-32 controller order complete local daisy-chain arbitration control. When SLEEP asserted, daisy chain arbitration signals that pass through PCnet-32 controller will experience one-clock delay from input output (i.e. HOLDI HOLD HLDA HLDAO). While SLEEP asserted (either snooze mode coma mode), PCnet-32 controller configured daisy chain (HOLDI HLDAO signals have been selected with JTAGSEL pin), then daisy-chain signal HOLDI will passed directly system arbitration signal HOLD without experiencing one-clock delay. However, some combinatorial delay will introduced this path.
HLDAO
Hold Acknowledge Output This signal multiplexed with pin, available only when Multi-Interrupt mode been selected with JTAGSEL pin. additional local master daisy-chain HLDA signal through PCnet-32 controller HLDAO pin. PCnet-32 controller will deliver HLDAO signal additional local master whenever PCnet-32 controller receives HLDA from CPU, simultaneously requesting internally.
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PRELIMINARY Multi-Interrupt mode been selected daisychain arbitration feature used, then HOLDI input should tied through resistor. Note that this changes polarity when mode been selected (see description LREQI VESA VL-Bus Interface section).
M/IO
Memory Select Input/Output During slave accesses PCnet-32 controller, M/IO pin, along with W/R, indicates type cycle that being performed. PCnet-32 controller will only respond local accesses which M/IO sampled zero PCnet-32 controller. During PCnet-32 controller master accesses, M/IO output will always driven high. M/IO floated PCnet-32 controller current master local bus.
INTR1-INTR4
Interrupt Request Output attention signal which indicates that more following status flags set: BABL, MISS, MERR, RINT, IDON, MFCO, RCVCCO, TXSTRT, JAB. Each these status flags mask which allows suppression INTR assertion. These flags have meaning shown Table Table Status Flags
BABL MISS MERR RINT IDON MFCO RCVCCO TXSTRT Babble (CSR0, Missed Frame (CSR0, Memory Error (CSR0, Receive Interrupt (CSR0, Initialization Done (CSR0, Missed Packet Count Overflow (CSR4, Receive Collision Count Overflow (CSR4, Transmit Start (CSR4, Jabber (CSR4,
RESET
System Reset Input When RESET asserted high LB/VESA been tied VDD, then PCnet-32 controller performs internal system reset type H_RESET (HARDWARE_RESET). RESET must held minimum BCLK periods. While H_RESET state, PCnet-32 controller will float deassert outputs. Note that this changes polarity when mode been selected (see description RESET VESA VL-Bus Interface section).
Ready Output functions output from PCnet-32 controller during PCnet-32 controller slave cycles. During PCnet-32 controller slave read cycles, asserted indicate that valid data been presented data bus. During PCnet-32 controller slave write cycles, asserted indicate that data data been internally latched. asserted BCLK period. then driven high one-half clock period before being released. floated PCnet-32 controller current slave local bus. systems where both RDYRTN equivalent) signals provided, must tied RDYRTN. Most systems provide local device ready input memory controller that separate from READY signal. This second READY signal usually labeled READYIN. This signal should connected PCnet-32 controller signal. READY signal should connected PCnet-32 controller RDYRTN pin. systems where only READY signal provided, then tied RDYRTN.
Note that there four possible interrupt pins, depending upon mode that been selected with JTAGSEL pin. Only interrupt used time. active interrupt selected programming interrupt select register (BCR21). default setting BCR121will select interrupt INTR1 active interrupt. Note that BCR21 EEPROM-programmable. Inactive interrupt pins floated. polarity interrupt signal determined INTLEVEL BCR2. interrupt pins programmed level-sensitive edge-sensitive operation. PCnet-32 controller interrupt pins will floated H_RESET will remain floated until either EEPROM been successfully read, following EEPROM read failure, Software Relocatable Mode sequence been successfully executed.
LDEV
Local Device Output LDEV driven PCnet-32 controller when recognizes access PCnet-32 controller space. Such recognition dependent upon valid sampled strobe plus valid M/IO, A31-A5 values.
RDYRTN
Ready Return Input RDYRTN functions input PCnet-32 controller. RDYRTN used terminate master accesses
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PRELIMINARY trailing edge RESET, this sampled determine value EEDET BCR19. sampled HIGH value means that EEPROM present, EEDET will ONE. sampled value means that EEPROM present, EEDET will ZERO. "EEPROM Auto-detection" section more details. circuit attached this pin, then pull-up pull-down resistor must attached instead, order resolve EEDET setting.
performed PCnet-32 controller, except that linear burst transfers also terminated with BRDY signal. RDYRTN used terminate slave read accesses PCnet-32 controller space. When asserted during slave read accesses PCnet-32 controller space, RDYRTN indicates that mastering device seen that generated PCnet-32 controller accepted PCnet-32 controller slave read data. Therefore, PCnet-32 controller will hold slave read data until synchronously samples RDYRTN input active low. PCnet-32 controller will hold valid asserted during this time. duration pulse generated PCnet-32 controller will always single BCLK cycle. RDYRTN ignored during slave write accesses PCnet-32 controller space. Slave write accesses PCnet-32 controller space considered terminated PCnet-32 controller cycle during which PCnet-32 controller issues active RDY. systems where both RDYRTN equivalent) signals provided, then must tied RDYRTN. Most systems provide local device ready input memory controller that separate from READY signal. This second READY signal usually labeled READYIN. This signal should connected PCnet-32 controller signal. READY signal should connected PCnet-32 controller RDYRTN pin. systems where only READY signal provided, then PCnet-32 controller output tied PCnet-32 controller RDYRTN input.
LED2
LED2 Output This shared with SRDCLK function. When operating LED2, function polarity this programmable through BCR6. LED2 output from PCnet-32 controller capable sinking necessary current drive directly. This also selects address width Software Relocatable Mode. When this HIGH during Software Relocatable Mode, then device will programmed bits addressing while snooping accesses during Software Relocatable Mode. When this during Software Relocatable Mode, then device will programmed bits addressing while snooping accesses during Software Relocatable Mode. upper bits address will assumed match during snooping operation when LED2 LOW. 24-bit addressing mode intended systems that employ GPSI signals. more information GPSI function section General Purpose Serial Interface. circuit attached this pin, then pull pull down resistor must attached instead, order resolve Software Relocatable Mode address setting.
Write/Read Select Input/Output During slave accesses PCnet-32 controller, pin, along with M/IO, indicates type cycle that being performed. During PCnet-32 controller master accesses, output. floated PCnet-32 controller current master local bus.
LEDPRE3
LEDPRE3 Output This shared with EEDO function. When operating LEDPRE3, function polarity this programmable through BCR7. This signal labeled "PRE" because multi-function nature this pin. circuit were directly attached this pin, would create requirement that could serial EEPROM that would also attached this pin. Therefore, this used additional output while EEPROM used system, then buffering required between LEDPRE3 circuit. EEPROM included system design, then LEDPRE3 signal directly connected without buffering. LEDPRE3 output from PCnet-32 controller capable sinking necessary current drive this case. more details regarding connection, section LEDs.
Board Interface LED1
LED1 Output This shared with EESK function. When operating LED1, function polarity this programmable through BCR5. LED1 output from PCnet-32 controller capable sinking necessary current drive directly. LED1 also used during EEPROM Auto-detection determine whether EEPROM present PCnet-32 controller microwire interface.
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LNKST
LINK Status Output This provides driving LED. indicates active link connection 10BASE-T interface. signal programmable through BCR4. Note that this multiplexed with EEDI function. This remains active snooze mode.
HOLD signal will deasserted then PCnet-32 controller will proceed power savings mode. Note that internal system reset will cause HOLD/LREQ signal deasserted. SLEEP should asserted during power supply ramp-up. desired that SLEEP asserted power time, then system must delay assertion SLEEP until three BCLK cycles after completion valid RESET operation.
SHFBUSY
Shift Busy Output function SHFBUSY signal indicate when last byte EEPROM contents been shifted EEPROM EEDO signal line. This information useful external EEPROM-programmable registers that microwire protocol, described herein: When PCnet-32 controller performing serial read EEPROM through microwire interface, SHFBUSY signal will driven HIGH. SHFBUSY serve serial shift enable allow EEPROM data serially shifted into external device series devices. SHFBUSY signal will remain actively driven HIGH until EEPROM read operation. EEPROM checksum verified, then SHFBUSY signal will driven EEPROM read operation. EEPROM checksum verification failed, then SHFBUSY signal will remain HIGH. This function effectively demarcates successful EEPROM read operation therefore useful programmable-logic low-active output enable signal. more details external EEPROM-programmable registers, EEPROM. Microwire Access section under Hardware Access. This controlled host system writing BCR19, (EBUSY).
XTAL1-XTAL2
Crystal Oscillator Inputs Input/Output crystal frequency determines network data rate. PCnet-32 controller supports quartz crystals generate frequency compatible with 8802-3 (IEEE/ANSI 802.3) network frequency tolerance jitter specifications. section External Crystal Characteristics section Manchester Encoder/ Decoder) more detail. network data rate one-half crystal frequency. XTAL1 alternatively driven using external CMOS level source, which case XTAL2 must left unconnected. Note that when PCnet-32 controller coma mode, there internal resistor from XTAL1 ground. external source drives XTAL1, some power will consumed driving this resistor. XTAL1 driven this time power consumption will minimized. this case, XTAL1 must remain active least cycles after assertion SLEEP deassertion HOLD.
Microwire EEPROM Interface EESK
EEPROM Serial Clock Output EESK signal used access external 8802-3 (IEEE/ANSI 802.3) address PROM. This designed directly interface serial EEPROM that uses microwire interface protocol. EESK connected microwire EEPROM's Clock pin. controlled either PCnet-32 controller directly during read entire EEPROM, indirectly host system writing BCR19, EESK used during programming external EEPROM-programmable registers that microwire protocol follows: When PCnet-32 controller performing serial read IEEE Address EEPROM through microwire interface, SHFBUSY signal will serve serial shift enable allow EEPROM data serially shifted into external device series devices. This same signal used gate output programmed logic avoid problem releasing intermediate values rest system board logic. EESK signal serve clock, EEDO will serve input data stream programmable shift register.
SLEEP
Sleep Input When SLEEP input asserted (active LOW), PCnet-32 controller performs internal system reset then proceeds into power savings mode. (The reset operation caused SLEEP assertion will affect registers.) outputs will placed their normal reset condition. During sleep mode, PCnet-32 controller inputs will ignored except SLEEP itself. De-assertion SLEEP results wake-up. system must refrain from starting network operations PCnet-32 controller seconds following deassertion SLEEP signal order allow internal analog circuits stabilize. Both BCLK XTAL1 inputs must have valid clock signals present order SLEEP command take effect. SLEEP asserted while LREQ/HOLD asserted, then PCnet-32 controller will perform internal system reset then wait assertion LGNT/ HLDA. When LGNT/HLDA asserted, LREQ/
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EEDO
EEPROM Data Input EEDO signal used access external 8802-3 (IEEE/ANSI 802.3) address PROM. This designed directly interface serial EEPROM that uses microwire interface protocol. EEDO connected microwire EEPROM's Data Output pin. controlled EEPROM during reads. read host system reading BCR19, EEDO used during programming external EEPROM-programmable registers that microwire protocol follows: When PCnet-32 controller performing serial read IEEE Address EEPROM through microwire interface, SHFBUSY signal will serve serial shift enable allow EEPROM data serially shifted into external device series devices. This same signal used gate output programmed logic avoid problem releasing intermediate values rest system board logic. EESK signal serve clock, EEDO will serve input data stream programmable shift register.
Data Input differential input pair PCnet-32 controller carrying Manchester encoded data from network. Operates pseudo levels.
Data Output differential output pair from PCnet-32 controller transmitting Manchester encoded data network. Operates pseudo levels.
Twisted Pair Interface RXD±
10-BASE-T Receive Data 10BASE-T port differential receivers.
Input
TXD±
10BASE-T Transmit Data 10BASE-T port differential drivers.
Output
TXP±
10BASE-T Pre-distortion Control Output These outputs provide transmit predistortion control conjunction with 10BASE-T port differential drivers.
EECS
EEPROM Chip Select Output function EECS signal indicate microwire EEPROM device that being accessed. EECS signal active high. controlled either PCnet-32 controller during read entire EEPROM, indirectly host system writing BCR19,
External Address Detection Interface
EADI interface enabled through BCR2, (EADISEL).
External Address Reject Input EADI input signal. incoming frame will checked against internally active address detection mechanisms result this check will OR'd with value pin. defined REJECT. EADI section details regarding function timing this signal. Note that this multiplexed with INTR2 pin.
EEDI
EEPROM Data Output EEDI signal used access external 8802-3 (IEEE/ANSI 802.3) address PROM. EEDI functions output. This designed directly interface serial EEPROM that uses microwire interface protocol. EEDI connected microwire EEPROM's Data Input pin. controlled either PCnet-32 controller during command portions read entire EEPROM, indirectly host system writing BCR19,
SFBD
Start Frame-Byte Delimiter Output Start Frame-Byte Delimiter Enable. EADI output signal. initial rising edge this signal indicates that start frame delimiter been detected. serial stream will follow signal, commencing with destination address field. SFBD will high times (400 after detecting second (Start Frame Delimiter) received frame. SFBD will subsequently toggle every (1.25 frequency) with each rising edge indicating first each subsequent byte received serial stream. SFBD will inactive during frame transmission.
Attachment Unit Interface
Collision Input differential input pair signaling PCnet-32 controller that collision been detected network media, indicated inputs being driven with pattern sufficient amplitude pulse width meet 8802-3 (IEEE/ANSI 802.3) standards. Operates pseudo levels.
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PRELIMINARY Note that this multiplexed with LED1 pin.
TXEN
Transmit Enable Input/Output TXEN output, providing enable signal transmission. Data TXDAT valid unless TXEN signal HIGH. Note that TXEN multiplexed with pin.
Serial Receive Data Output EADI output signal. decoded data from network. This signal used external address detection. Note that when 10BASE-T port selected, transitions will only occur during receive activity. When port selected, transitions will occur during both transmit receive activity. Note that this multiplexed with LEDPRE3 pin.
STDCLK
Serial Transmit Data Clock Input STDCLK input, providing clock signal activity, both transmit receive. Rising edges STDCLK used validate TXDAT output data. STDCLK multiplexed with pin. Note that this signal must meet frequency stability requirement 8802-3 (IEEE/ANSI 802.3) specification crystal.
SRDCLK
Serial Receive Data Clock Output EADI output signal. Serial Receive Data synchronous with reference SRDCLK. Note that when 10BASE-T port selected, transitions SRDCLK will only occur during receive activity. When port selected, transitions SRDCLK will occur during both transmit receive activity. Note that this multiplexed with LED2 pin.
CLSN
Collision Input/Output CLSN input, indicating core logic that collision occurred network. Note that CLSN multiplexed with pin.
General Purpose Serial Interface
GPSI interface selected through PORTSEL bits Mode register (CSR15) enabled through TSTSHDW[1] (BCR18) GPSIEN (CSR124). Note that when GPSI test mode invoked, slave address decoding must restricted lower bits address setting IOAW24 BCR2 pulling LED2 during Software Reloactable Mode. upper bits address will always considered matched when examining incoming addresses. During master accesses while GPSI mode, PCnet-32 controller will drive upper bits address with address information. GPSI section more detail.
RXCRS
Receive Carrier Sense Input/Output RXCRS input. When this signal HIGH, indicates core logic that data RXDAT input valid. Note that RXCRS multiplexed with pin.
SRDCLK
Serial Receive Data Clock Input/Output SRDCLK input. Rising edges SRDCLK signal used sample data RXDAT input whenever RXCRS input HIGH. Note that SRDCLK multiplexed with pin.
TXDAT
Transmit Data Input/Output TXDAT output, providing serial stream transmission, including preamble, data field, applicable. Note that TxDAT multiplexed with pin.
RXDAT
Receive Data Input/Output RXDAT input. Rising edges SRDCLK signal used sample data RXDAT input whenever RXCRS input HIGH. Note that RXDAT multiplexed with pin.
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IEEE 1149.1 Test Access Port Interface
Test Clock Input clock input boundary scan test mode operation. operate MHz. left unconnected this default value HIGH.
Test Data Output Output test data output path from PCnet-32 controller. floated when JTAG port inactive.
Test Mode Select Input serial input stream used define specific boundary scan test executed. left unconnected, this default value HIGH.
Test Data Input Input test data input path PCnet-32 controller. left unconnected, this default value HIGH.
Power Supply Pins AVDD
Analog Power Pins) Power There four analog supply pins. Special attention should paid printed circuit board layout avoid excessive noise these lines. Refer Appendix PCnet Family Technical Manual (PID# 18216A) details.
DVDDO
Buffer Digital Power Pins) Power There digital power supply pins (DVDD01- DVDD05) used Input/Output buffer drivers.
DVSS
Digital Ground Pins) Ground There digital ground pins (DVSS1-DVSS4) used internal digital circuitry.
AVSS
Analog Ground Pins) Power There analog ground pins. Special attention should paid printed circuit board layout avoid excessive noise these lines. Refer Appendix PCnet Family Technical Manual details.
DVSSCLK
Digital Ground Clock Pin) Ground This used supply ground clock buffering circuitry.
DVSSN
Buffer Digital Ground Pins) Ground These ground pins (DVSSN1-DVSSN15) used Input/Output buffer drivers.
DVDD
Digital Power Pins) Power There digital power supply pins. (DVDD1, DVDD2, DVDD3) used internal circuitry.
DVSSPAD
Digital Ground Pin) Ground This used Input/Output logic circuits.
DVDDCLK
Digital Power Clock Pin) Power This used supply power clock buffering circuitry.
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BASIC FUNCTIONS System Interface Function
PCnet-32 controller designed operate Master during normal operations. Some slave accesses PCnet-32 controller required normal operations well. Initialization PCnet-32 controller achieved through combination Slave accesses, Master accesses optional read serial EEPROM that performed PCnet-32 controller. EEPROM read operation performed through microwire interface. 8802-3 (IEEE/ANSI 802.3) Ethernet Address reside within serial EEPROM. Some PCnet-32 controller configuration registers also programmed EEPROM read operation. address PROM, on-chip board-configuration registers, Ethernet controller registers occupy bytes space which located modifying base address register. default base address written EEPROM. PCnet-32 controller will automatically read Base Address from EEPROM after H_RESET, time that software requests that EEPROM should read. When EEPROM attached serial microwire interface, PCnet-32 controller detects condition, enters Software Relocatable Mode. While Software Relocatable Mode, PCnet-32 controller will respond accesses, will snoop accesses address 378h. When successfully executed uninterrupted sequence write operations seen this location, PCnet-32 controller will accept next sequence accesses carrying Base Address relocation interrupt programming information. After this point, PCnet-32 controller will begin respond directly accesses directed toward offsets from newly loaded Base Address. This scheme allows jumperless relocatable implementations.
controller occupies bytes space that must begin 32-byte block boundary. Base Address changed 32-bit quantity that begins 32-byte block boundary through function Software Relocatable Mode. also changed 32-bit value that begins 32-byte block boundary through automatic EEPROM read operation that occurs immediately after H_RESET function completed. This read operation automatically alters Base Address PCnet-32 controller. 32-byte space used software program PCnet-32 controller operating mode, enable disable various features, monitor operating status request particular functions executed PCnet-32 controller. other portion software interface descriptor buffer areas that shared between software PCnet-32 controller during normal network operations. descriptor area boundaries software change during normal network operations. There descriptor area receive activity there separate area transmit activity. descriptor space contains relocatable pointers network packet data used transfer packet status from PCnet-32 controller software. buffer areas locations that hold packet data transmission that accept packet data that been received.
Network Interfaces
PCnet-32 controller connected 802.3 network network interfaces. Attachment Unit Interface (AUI) provides 8802-3 (IEEE/ANSI 802.3) compliant differential interface remote on-board transceiver. 10BASE-T interface provides twisted-pair Ethernet port. While auto-selection mode, interface determined auto-sensing mechanism which checks link status 10BASE-T port. there active link status, then device assumes connection. driven/floated falling edges BCLK will change state rising edges BCLK. following sections describe various master slave operations that will performed PCnet-32 controller. timing diagrams that included these sections (Bus Acquisition section through Slave Timing section) show signals timings Am486 32-bit mode operation. sections from Acquisition through Linear Burst Transfers show master operations. Slave Timing section shows slave operations. Note that PCnet-32 controller operation Am486 32-bit mode represents merger requirements VESA VL-Bus specification Am486 specification,
Software Interface
software interface PCnet-32 controller divided into parts. part direct access resources PCnet-32 controller. PCnet-32
DETAILED FUNCTIONS Interface Unit
interface unit built several state machines that synchronously BCLK. interface unit state machine handles accesses where PCnet-32 controller slave, another handles accesses where PCnet-32 controller master. inputs synchronously sampled except ADS, M/IO, D/C, A[31:5] when this input PCnet-32 controller. outputs synchronously generated rising edge BCLK with following exceptions: LDEV generated asynchronously.
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PRELIMINARY Burst timing diagrams. more details, AHOLD Linear Burst Count sections. Acquisition PCnet-32 controller microcode buffer management section) will determine when transfer should initiated. first step PCnet-32 controller master transfer acquire ownership bus. This task handled synchronous logic within BIU. ownership requested with HOLD signal ownership granted arbiter) through HLDA signal. PCnet-32 controller additionally supplies HOLDI HLDAO signals allow daisy chaining devices through PCnet-32 controller. Priority HOLDI input versus PCnet-32 controller's internal request mastership using PRPCNET BCR17. Simple arbitration (HOLD, HLDA only) shown Figure Note that assertion STOP will cause deassertion HOLD signal. Note also that read S_RESET register (I/O resource offset from PCnet-32 controller base address) will cause deassertion HOLD signal. Either these actions will cause internal master state machine logic cease operations, HOLD signal will remain active until HLDA signal synchronously sampled asserted. Following either above actions, next clock cycle after HLDA signal synchronously sampled asserted, PCnet-32 controller will deassert HOLD signal. master accesses will have been performed during this brief ownership period.
whichever more stringent. concepts discussed following sections basic nature timings shown applicable general sense PCnet-32 controller operational modes. specific differences timing between modes examples timing diagrams showing basic transfers each modes, please consult following sections: Am486 32-bit mode: VESA VL-Bus mode:
Acquisition section through Slave Timing section VESA VL-Bus Mode Timing section
selection each mode, consult section Configuration Pins Description section. Note that timing diagrams this document have been drawn showing reference groups address pins: namely, A4-A31 A2-A3, BE0-BE3. AHOLD timing diagrams, groups shown separately, because upper address pins become floated, while lower address pins not. point division between groups address pins will depend upon value BCR18. case Linear Burst operations, upper address pins shown separately because that group does change value through single linear burst, while lower address pins change value. this case, point division between groups address pins will depend upon value LINBC BCR18. other timing diagrams, groups shown separately just maintain consistency with AHOLD Linear
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PRELIMINARY BCLK
A4-A31, M/IO,
A2-A3, BE0-BE3 RDYRTN
BRDY
BLAST
From PCnet-32
D0-D31
HOLD
HLDA
18219B-5
Figure Acquisition
Assertion minimum-width pulse RESET will cause HOLD signal deassert within clock cycles following assertion RESET pin. this case, PCnet-32 controller will wait assertion HLDA signal before deasserting HOLD signal. This description behavior identical VESA VL-Bus mode operation, except that HOLD, HLDA RESET signals replaced inverted
sense signals LREQ, LGNT, RESET, respectively; BCLK, BOFF, EADS, signals replaced LCLK, WBACK, LEADS, LRDY, respectively. Master Transfers There three primary types transfers. transfers will have wait states inserted until either RDYRTN BRDY asserted. Figure Figure show basic transfers read write without ready wait states then with ready wait states.
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BCLK
PRELIMINARY
A4-A31, M/IO,
A2-A3, BE0-BE3 RDYRTN
BRDY
BLAST
PCnet-32 PCnet-32 PCnet-32
D0-D31
HOLD
HLDA
18219B-6
Figure Basic Read Cycles without with Wait States
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PRELIMINARY BCLK
A4-A31, M/IO,
A2-A3, BE0-BE3 RDYRTN
BRDY
BLAST
From PCnet-32 From PCnet-32 From PCnet-32
D0-D31
HOLD
HLDA
18219B-7
Figure Basic Write Cycles without with Wait States
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PRELIMINARY BOFF signal deasserted. Simultaneous assertion RDYRTN BRDY) BOFF resolved favor BOFF. RDYRTN BRDY) ignored such cycle, when BOFF deasserted, cycle restarted. Figure detail.
Effect BOFF Assertion BOFF during master transfers will cause PCnet-32 controller float signals beginning next clock cycle. access which been interrupted BOFF will restarted when
BCLK
A4-A31, M/IO, A2-A3, BE0-BE3 RDYRTN
BRDY
BLAST
PCnet-32 PCnet-32
D0-D31
BOFF
HOLD
HLDA
18219B-8
Figure Restarted Read Cycle
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Effect AHOLD Assertion AHOLD during master transfers will cause PCnet-32 controller float some portion address beginning next clock cycle. RDYRTN returned while AHOLD active, then cycle completes, since data remain active during AHOLD. However, cycle will started while AHOLD active.
portion Address that will floated time address hold operation will determined value Cache Line Length register (BCR18, bits 15-11). Table lists legal values showing portion Address that will become floated during address hold operation. RDYRTN signal returned while AHOLD active, then PCnet-32 controller will resume driving same address onto address when AHOLD released. PCnet-32 controller will reissue signal this time. Figure Figure details.
BCLK
Table Value Floating Address Pins
Value 00000 00001 00010 00011 00100 00101-00111 01000 01001-01111 10000 10001-11111 Floated Portion Address During AHOLD None A31-A2 A31-A3 Reserved Value A31-A4 Reserved Values A31-A5 Reserved Values A31-A6 Reserved Values
Note: default value after H_RESET 00100. timing diagrams this document drawn with assumption that this value CLL.
A4-A31 M/IO, A2-A3, BE0-BE3 RDYRTN
BRDY
BLAST
PCnet-32 PCnet-32
D0-D31
AHOLD
HOLD
HLDA
18219B-9
Figure Read Cycle with AHOLD Note that initial access allowed complete spite AHOLD, next access prevented from beginning until AHOLD deasserted. Am79C965
BCLK
PRELIMINARY
A4-A31 M/IO, A2-A3, BE0-BE3 RDYRTN
BRDY
BLAST
PCnet-32 PCnet-32
D0-D31
AHOLD
HOLD
HLDA
18219B-80
Figure Read Cycle with AHOLD Address re-driven when AHOLD deasserted, since RDYRTN arrived.
Effect Preemption preemption event occurs during basic transfer cycle, then behavior PCnet-32 controller will depend upon which specific type access being performed. general response PCnet-32 controller that current operation will complete before PCnet-32 controller relinquishes response preemption. "Current operation" this sense refers general PCnet-32 controller operation, such
"descriptor access". Note that "descriptor access" consists basic transfers. Therefore, both transfers descriptor access must completed before will released response preemption. each sections Initialization Block transfers, Descriptor transfers, FIFO transfers Linear Burst Transfers more specific information.
Am79C965
Effect LBS16 (VL-Bus mode only) Dynamic sizing recognized PCnet-32 controller while operating VL-Bus mode. LBS16 signal used indicate PCnet-32 controller whether VL-Bus target 16-bit 32-bit peripheral. When target device indicates that bits width asserting LBS16 signal least LCLK period before asserting RDYRTN signal, then PCnet-32 controller will dynamically respond size constraints peripheral performing additional accesses. Table shows sequence accesses that will performed PCnet-32 controller response assertion LBS16.
Figure shows example exchange between 16-bit VL-Bus peripheral PCnet-32 controller. Note that LBS16 signal asserted during LCLK
that precedes assertion RDYRTN. this particular case, order maintain zero-wait state accesses, 16-bit target must generate LBS16 very short time order meet required setup time LBS16 into PCnet-32 controller. peripheral were incapable meeting required setup time, then wait state would needed order insure that LBS16 asserted least LCLK prior assertion RDYRTN signal. When assertion LBS16 during PCnet-32 controller master access created need second access specified table above, WBACK signal becomes active during second access, then, when WBACK deasserted, PCnet-32 controller will repeat both accesses pair.
Table Data Transfer Sequence from 32-Bit Wide 16-Bit Wide
Current Access Next with LBS16
second access Required these cases
Am79C965
LCLK
PRELIMINARY
ADR4- ADR31 M/IO, ADR2-ADR3, BE2-BE3 BE0-BE1
RDYRTN
BRDY
BLAST
PCnet-32 PCnet-32
DAT0- DAT31 LBS16
LREQ
LGNT
18219B-10
Figure VL-Bus Ready Cycle with LBS16 Asserted Four-byte single cycle access converted 2-byte accesses.
Am79C965
PRELIMINARY Initialization Block Transfers During execution PCnet-32 controller master initialization procedure, PCnet-32 controller microcode will repeatedly request transfers from BIU. During each these initialization block transfers, will perform data transfer cycles (eight bytes) then will relinquish (see Figure transfers within mastership period will always read cycles ascending contiguous addresses. transfers each initialization block transfer will never executed using linear burst mode. 32-bit software mode, number mastership periods needed complete initialization procedure There doublewords transfer during BCLK
master initialization procedure, four mastership periods needed order complete initialization sequence. Note that last doubleword transfer last mastership period initialization sequence accesses unneeded location. Data from this transfer discarded internally. preemption event occurs during initialization block transfer, then PCnet-32 controller will complete both data transfer cycles initialization block transfer before releasing HOLD signal relinquishing bus. When SSIZE32 (CSR58[8]/BCR20[8]), then number mastership periods needed complete initialization procedure
A4-A31, M/IO, IADD IADD
A2-A3, BE0-BE3 RDYRTN IADD IADD
BRDY
BLAST
PCnet-32 PCnet-32
D0-D31
18219B-11
Figure Initialization Transfer
Am79C965
PRELIMINARY Descriptor transfers will never executed using linear burst mode. During read accesses, byte enable signals will indicate that byte lanes active. Should some bytes needed, then PCnet-32 controller will internally discard extraneous information that gathered during such read. During write accesses, only bytes which need written enabled, activating corresponding byte enable pins. Figure Figure preemption event occurs during descriptor transfer, then PCnet-32 controller will complete both data transfer cycles descriptor transfer, before releasing HOLD signal relinquishing bus. only significant differences between descriptor transfers initialization transfers that addresses accesses follow different ordering.
Descriptor Transfers PCnet-32 controller will determine when descriptor access required. descriptor read will consist doubleword transfers. descriptor write will consist double word transfer. transfers within descriptor transfer mastership period will always same type (either read write). transfers will addresses order specified Table Table (note that indicates RMD). buffer chaining used (see Transmit Receive Descriptor Table Entry sections), writes descriptors that contain Packet will consist only doubleword. This write will same location second writes performed when Frame been processed (i.e. location that contains descriptor OWNership bit, MD1[31]).
Table Master Reads Descriptors
16-Bit Software Mode Address Sequence A[7:0] Break LANCE Item Accessed MD1[15:0], MD0[15:0] MD3[15:0], MD2[15:0] PCnet-32 Item Accessed MD1[31:24], MD0[23:0] MD2[15:0], MD1[15:0] Address Sequence A[7:0]* Break 32-Bit Software Mode LANCE Item Accessed MD1[15:8], MD2[15:0] MD1[7:0], MD0[15:0] PCnet-32 Item Accessed MD1[31:0] MD0[31:0]
Table Master Writes Descriptors
16-Bit Software Mode Address Sequence A[7:0] Break LANCE Item Accessed MD3[15:0], MD2[15:0] MD1[15:0], MD0[15:0] PCnet-32 Item Accessed MD2[15:0], MD1[15:0] MD1[31:24], MD0[23:0] Address Sequence A[7:0]* Break 32-Bit Software Mode LANCE Item Accessed MD3[15:0], MD2[15:0] MD1[15:8], MD2[15:0] PCnet-32 Item Accessed MD2[31:0] MD1[31:0]
*Address values A[31:8] constant throughout single descriptor transfer. Note that even though bits A[1:0] physically exist system, these bits must ZERO descriptor base address.
Am79C965
PRELIMINARY BCLK
A4-A31, M/IO, MD1* MD0*
A2-A3, BE0-BE3 RDYRTN MD1* MD0*
BRDY
BLAST
PCnet-32 PCnet-32
D0-D31
*Note that Message Descriptor addresses descending order.
18219B-12
Figure Descriptor Read
Am79C965
BCLK
PRELIMINARY
A4-A31, M/IO, MD2* MD1*
A2-A3, BE0-BE3 RDYRTN MD2* MD1*
BRDY
BLAST
From PCnet-32 From PCnet-32
D0-D31
*Note that Message Descriptor addresses descending order.
18219B-13
Figure Descriptor Write
FIFO Transfers PCnet-32 controller microcode will determine when FIFO transfer required. This transfer mode will used transfers data from PCnet-32 controller FIFOs. Once PCnet-32 controller been granted mastership, will perform series consecutive transfer cycles before relinquishing bus. Each transfer will performed sequentially, with issue address, transfer corresponding data with appropriate output signals indicate selection active data bytes during transfer. transfers within master cycle will either read write cycles, transfers will contiguous, ascending addresses. number data transfer cycles contained within single cycle general, dependent programming DMAPLUS option (CSR4, 14). Several other factors will also affect length cycle period. possibilities follows: DMAPLUS maximum transfers will performed default. This default value changed writing burst register (CSR80). Note that
DMAPLUS merely sets maximum value. minimum number transfers cycle will determined following variables: settings FIFO watermarks, particular conditions existing within FIFOs, receive transmit status conditions, value Burst Cycle (CSR80), value Activity Timer (CSR82), timing occurrence preemption that takes place during FIFO transfer. DMAPLUS cycle will continue until transmit FIFO filled high threshold (read transfers) receive FIFO emptied threshold (write transfers), until Activity Timer value (CSR82) expired. Other variables also affect point burst this mode. Among those variables are: particular conditions existing within FIFOs, receive transmit status conditions, preemption events. FIFO thresholds programmable (see description CSR80), Burst Cycle Activity Timer values. exact number transfer cycles case DMAPLUS will dependent latency
Am79C965
PRELIMINARY system PCnet-32 controller's mastership request speed operation, will limited value Activity Timer register, FIFO condition, receive transmit status, preemption events, any. Barring time-out either these registers, preemption another mastering device, exceptional receive transmit events, packet signal from FIFO, FIFO watermark settings extent Acknowledge latency will major factors determining number accesses performed during given arbitration cycle when DMAPLUS READY response memory device will also affect number transfers when DMAPLUS since speed accesses will affect state FIFO. (During accesses, FIFO filling emptying network end. slower memory reTi BCLK
sponse will allow additional data accumulate inside FIFO (during write transfers from receive FIFO). accesses slow enough, complete double word become available before arbitration cycle thereby increase number transfers that cycle.) general rule that longer grant latency slower transfer operations clock speed) higher transmit watermark lower receive watermark combination thereof longer will average burst length. preemption event occurs during FIFO transfer, then PCnet-32 controller will complete current transfer will complete maximum four additional data transfer cycles before releasing HOLD signal relinquishing bus.
A4-A31, M/IO,
A2-A3, BE0-BE3 RDYRTN
BRDY
BLAST
PCnet-32 PCnet-32 PCnet-32 PCnet-32 PCnet-32
D0-D31
18219B-14
Figure FIFO Read
Am79C965
BCLK
PRELIMINARY
A4-A31, M/IO,
A2-A3, BE0-BE3 RDYRTN
BRDY
BLAST
From PCnet-32 From PCnet-32 From PCnet-32 From PCnet-32 From PCnet-32
D0-D31
18219B-15
Figure FIFO Write
Note that A[1:0] exist 32-bit system, both these bits exist buffer pointers that passed PCnet-32 controller descriptor. A[1:0] values will decoded presented byte enable (BE0-BE3) values during FIFO transfers. Linear Burst Transfers Once PCnet-32 controller been granted mastership, PCnet-32 controller request perform linear burst cycles de-asserting BLAST signal. device being accessed wishes support linear bursting, then must assert BRDY de-assert RDYRTN, with same timing that RDYRTN would normally provided. Linear bursting only performed PCnet-32 controller BREADE and/or BWRITE bits BCR18 set. These bits individually enable/disable ability PCnet-32 controller perform linear burst accesses during master read operations master write operations, respectively. Only FIFO data transfers will make linear burst mode.
first transfer linear burst will consist both address data cycle, subsequent transfers will contain data only, until LINBC upper limit transfers have been executed. LINBC value from BCR18 register. linear burst "upper limit" created taking BCR18 LINBC[2:0] value multiplying result number transfers that will performed within single linear burst sequence. entire address will still driven with appropriate values during data cycles. When LINBC upper limit data transfers have been performed, asserted there more data transferred), with address A2-A31 pins. Following cycle, linear bursting data wi
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