PCnetTM-PCI Single-Chip Full-Duplex Ethernet Controller Local Product
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Am79C970A
PCnetTM-PCI Single-Chip Full-Duplex Ethernet Controller Local Product
DISTINCTIVE CHARACTERISTICS
Single-chip Ethernet controller Peripheral Component Interconnect (PCI) local Supports 8802-3 (IEEE/ANSI 802.3) Ethernet standards Direct interface local (Revision compliant) High-performance 32-bit Master architecture with integrated buffer management unit utilization Software-compatible with PCnet family, LANCE/C-LANCE, Am79C900 ILACC register descriptor architecture Compatible with PCnet family driver software Full-duplex operation increased network bandwidth endian little endian byte alignments supported signaling interface Low-power CMOS design with sleep modes allows reduced power consumption critical battery-powered applications Green Integrated Magic Packetsupport remote wake Green Individual 272-byte transmit 256-byte receive FIFOs provide frame buffering increased system latency support following features: Automatic retransmission with FIFO reload Automatic receive stripping transmit padding (individually programmable) Automatic runt frame rejection Automatic selection received collision frames Microwire EEPROM interface supports jumperless design provides through-chip programming Supports optional Boot PROM diskless node applications Look-Ahead Packet Processing (LAPP) data handling technique reduces system overhead allowing protocol analysis begin before receive frame Integrated Manchester encoder/decoder Provides integrated attachment unit interface (AUI) 10BASE-T transceiver with automatic port selection Automatic twisted-pair receive polarity detection automatic correction receive polarity Optional byte padding long-word boundary receive Dynamic transmit generation programmable frame-by-frame basis Internal/external loopback capabilities Supports following types network interfaces: external 10BASE-2, 10BASE-5, 10BASE-T, 10BASE-F Internal 10BASE-T transceiver with Smart Squelch twisted-pair medium JTAG Boundary Scan (IEEE 1149.1) test access port interface NAND Tree test mode board-level production connectivity test Supports LANCE general purpose serial interface (GPSI) Supports external address detection interface (EADI) programmable LEDs status indication 132-pin PQFP 144-pin TQFP packages Support operation industrial temperature range (-40°C +85°C) available both packages
GENERAL DESCRIPTION
32-bit PCnet-PCI single-chip full-duplex Ethernet controller highly integrated Ethernet system solution designed address high-performance system application requirements. flexible bus-mastering device
Publication# 19436 Rev: Amendment/0 Issue Date: March 1999
that used application, including networkready PCs, printers, modems, bridge/router designs. bus-master architecture provides high data throughput system system 1-611
This document contains information product under development Advanced Micro Devices. information intended help evaluate this product. reserves right change discontinue work this proposed product without notice.
utilization. PCnet-PCI controller fabricated with AMD's advanced low-power CMOS process provide operating standby current power-sensitive applications. PCnet-PCI controller complete Ethernet node integrated into single VLSI device. contains interface unit, buffer management unit, IEEE 802.3-compliant media access control (MAC) function, individual 272-byte transmit 256-byte receive FIFOs, IEEE 802.3-compliant attachment unit interface (AUI) twisted-pair transceiver medium attachment unit (10BASE-T MAU) that both operate either half-duplex full-duplex mode. PCnet-PCI controller register-compatible with LANCE (Am7990) Ethernet controller, C-LANCE (Am79C90) Ethernet controller, ILACC (Am79C900) Ethernet controller, Ethernet controllers PCnet family, including PCnet-ISA controller (Am79C960), PCnet-ISA+ controller (Am79C961), PCnet-ISA controller (Am79C961A), PCnet-32 controller (Am79C965), PCnet-PCI controller (Am79970), PCnet-SCSI controller (Am79C974). buffer management unit supports C-LANCE, ILACC, PCnet descriptor software models. PCnet-PCI controller software compatible with Novell® NE2100 NE1500 Ethernet adapter card architectures. 32-bit multiplexed interface unit provides direct interface local applications, simplifying design Ethernet node system. PCnet-PCI controller provides complete interface expansion ROM, allowing add-on card designs with only single load interface pin. With built-in support both little endian byte alignment, this controller also addresses proprietary non-PC applications. PCnet-PCI controller's advanced CMOS design allows interface connected either signaling environment. Both NAND Tree JTAG test interfaces provided. PCnet-PCI controller supports automatic configuration configuration space. Additional PCnet-PCI configuration parameters, including unique IEEE physical address, read from external non-volatile memory (microwire EEPROM) immediately following system reset. controller capability automatically select either port twisted-pair transceiver. Only interface active time. Both network interfaces programmed operate either halfduplex full-duplex mode. individual transmit receive FIFOs optimize system overhead, providing sufficient latency during frame transmission reception, minimizing intervention during normal network error recovery. integrated Manchester encoder/decoder (MENDEC) eliminates need external serial interface adapter (SIA) system. built-in general purpose serial interface (GPSI) allows MENDEC bypassed. addition, device provides programmable on-chip drivers transmit, receive, collision, receive polarity, link integrity, activity, jabber status. PCnet-PCI controller also provides external address detection interface (EADI) allow fast external hardware address filtering internetworking applications. power-sensitive applications where standby current desired, device incorporates sleep functions reduce overall system power consumption, excellent notebooks Green PCs. conjunction with these power modes, PCnet-PCI controller also integrated functions support Magic Packet, inexpensive technology that allows remote wakeup Green PCs. With rise embedded networking applications operating harsh environments where temperatures exceed normal commercial temperature window (0°C +70°C), industrial temperature (-40°C +85°C) version available both 132-pin PQFP 144-pin TQFP package. industrial temperature version PCnet-PCI Ethernet controller characterized across industrial temperature range (-40°C +85°C) within published power supply specification (4.75 5.25 i.e., VCC). Thus, conformance PCnet-PCI performance over this temperature range guaranteed design characterization monitor.
1-612
Am79C970A
BLOCK DIAGRAM
AD[31:00] C/BE[3:0] FRAME TRDY IRDY STOP LOCK IDSEL DEVSEL PERR SERR INTA NOUT SLEEP
DXCVR
FIFO 802.3 Core GPSI Port
Interface Unit
EADI Port FIFO Manchester Encoder/ Decoder (PLS) Port FIFO Control 10BASE-T
TXEN TXCLK TXDAT RXEN RXCLK RXDAT CLSN SRDCLK SF/BD XTAL1 XTAL2 DO+/DI +/CI+/TXD+/TXP+/RXD+/LNKST EECS EESK EEDI EEDO LED1 LED2 LED3 ERA[7:0] ERD[7:0] ERACLK EROE
Buffer Management Unit
Microwire EEPROM Interface
Control
JTAG Port Control
Expansion Interface
19436C-1
Am79C970A
1-613
TABLE CONTENTS
DISTINCTIVE CHARACTERISTICS 1-611 GENERAL DESCRIPTION 1-611 BLOCK DIAGRAM 1-613 CONNECTION DIAGRAM 1-621 ORDERING INFORMATION 1-623 DESIGNATIONS Listed Number Listed Group Listed Number Listed Group Listed Driver Type DESCRIPTION Interface Board Interface Microwire EEPROM Interface Expansion Interface Attachment Unit Interface Twisted Pair Interface General Purpose Serial Interface External Address Detection Interface IEEE 1149.1 Test Access Port Interface Test Interface Power Supply Pins BASIC FUNCTIONS System Interface Function Software Interface Network Interfaces DETAILED FUNCTIONS Slave Interface Unit Slave Configuration Transfers Slave Transfers Expansion Transfers Exclusive Access Slave Cycle Termination Disconnect When Busy Disconnect Burst Transfer Disconnect When Locked Parity Error Response Master Interface Unit Acquisition Master Transfers Basic Non-Burst Read Transfer Basic Burst Read Transfer Basic Non-Burst Write Transfer Basic Burst Write Transfer Target Initiated Termination Disconnect With Data Transfer 1-614 Am79C970A 1-624 1-624 1-625 1-627 1-628 1-630 1-631 1-631 1-633 1-634 1-635 1-635 1-635 1-635 1-636 1-636 1-637 1-637 1-638 1-638 1-638 1-638 1-639 1-639 1-639 1-641 1-641 1-644 1-644 1-644 1-646 1-648 1-649 1-651 1-651 1-652 1-652 1-653 1-654 1-655 1-657 1-657
1-658 1-659 1-660 1-660 1-661 1-662 1-663 1-664 1-665 1-667 1-671 1-671 1-672 1-675 1-675 1-675 1-676 1-676 1-676 1-678 1-679 1-680 1-681 1-681 1-681 1-681 1-682 1-682 1-682 1-683 1-684 1-684 1-684 1-685 1-685 1-686 1-686 1-686 1-686 1-686 1-686 1-687 1-688 1-688 1-689 1-689 1-689 1-689 1-690 1-690
Disconnect Without Data Transfer Target Abort Master Initiated Termination Preemption During Non-Burst Transaction Preemption During Burst Transaction Master Abort Parity Error Response Advanced Parity Error Handling Initialization Block Transfers Descriptor Transfers FIFO Transfers Non-Burst FIFO Transfers Burst FIFO Transfers BUFFER MANAGEMENT UNIT Initialization Re-Initialization Suspend Buffer Management Descriptor Rings Polling Transmit Descriptor Table Entry Receive Descriptor Table Entry Media Access Control Transmit Receive Message Data Encapsulation Framing Destination Address Handling Error Detection Media Access Management Medium Allocation Collision Handling TRANSMIT OPERATION Transmit Function Programming Automatic Generation Transmit Generation Transmit Exception Conditions Loss Carrier Late Collision Test Error Receive Operation Receive Function Programming Address Matching Automatic Stripping Receive Checking Receive Exception Conditions Loopback Operation GPSI Loopback Modes Loopback Modes T-MAU Loopback Modes Miscellaneous Loopback Features Magic Packet Mode
MANCHESTER ENCODER/DECODER 1-691 External Crystal Characteristics 1-691 External Clock Drive Characteristics 1-691 Am79C970A 1-615
PRELIMINARY 1-691 1-691 1-692 1-692 1-692 1-693 1-693 1-693 1-693 1-693 1-693 1-694 1-694 1-694 1-694 1-695 1-695 1-695 1-696 1-696 1-696 1-696 1-696 1-697 1-697 1-697 1-698 1-699 1-702 1-702 1-702 1-703 1-703 1-704 1-704 1-706 1-706 1-706 1-706 1-706 1-707 1-707 1-707 1-708 1-710 1-710 1-710 1-711 1-711 1-711 1-712 1-712 1-712 1-712 1-712
MENDEC Transmit Path Transmitter Timing Operation Receiver Path Input Signal Conditioning Clock Acquisition Tracking Carrier Tracking Message Data Decoding Jitter Tolerance Definition Attachment Unit Interface Differential Input Termination Collision Detection Twisted-Pair Transceiver Twisted Pair Transmit Function Twisted Pair Receive Function Link Test Function Polarity Detection Reversal Twisted Pair Interface Status Collision Detection Function Signal Quality Error Test Function Jabber Function Power Down 10BASE-T Interface Connection Full-Duplex Operation Full-Duplex Link Status Support General Purpose Serial Interface External Address Detection Interface Expansion Interface EEPROM Microwire Interface Automatic EEPROM Read Operation EEPROM Auto-Detection Direct Access Microwire Interface EEPROM-programmable Registers EEPROM Support Power Savings Modes IEEE 1149.1 Test Access Port Interface Boundary Scan Circuit Finite State Machine Supported Instructions Instruction Register Decoding Logic Boundary Scan Register Other Data Registers NAND Tree Testing Reset H_RESET S_RESET STOP Software Access Configuration Registers Resources Registers Address PROM Space Reset Register Word Mode 1-616 Am79C970A
Double Word Mode 1-713 USER ACCESSIBLE REGISTERS Configuration Registers Vendor Device Register Command Register Status Register Revision Register Programming Interface Register Sub-Class Register Base-Class Register Latency Timer Register Header Type Register Base Address Register Memory Mapped Base Address Register Expansion Base Address Register Interrupt Line Register Interrupt Register MIN_GNT Register MAX_LAT Register Register RAP: Register Address Port Control Status Registers CSR0: PCnet-PCI Controller Controller Status Register CSR1: Initialization Block Address CSR2: Initialization Block Address CSR3: Interrupt Masks Deferral Control CSR4: Test Features Control CSR5: Extended Control Interrupt CSR6: RX/TX Descriptor Table Length CSR8: Logical Address Filter CSR9: Logical Address Filter CSR10: Logical Address Filter CSR11: Logical Address Filter CSR12: Physical Address Register CSR13: Physical Address Register CSR14: Physical Address Register CSR15: Mode CSR16: Initialization Block Address Lower CSR17: Initialization Block Address Upper CSR18: Current Receive Buffer Address Lower CSR19: Current Receive Buffer Address Upper CSR20: Current Transmit Buffer Address Lower CSR21: Current Transmit Buffer Address Upper CSR22: Next Receive Buffer Address Lower CSR23: Next Receive Buffer Address Upper CSR24: Base Address Receive Descriptor Ring Lower CSR25: Base Address Receive Descriptor Ring Upper CSR26: Next Receive Descriptor Address Lower CSR27: Next Receive Descriptor Address Upper CSR28: Current Receive Descriptor Address Lower CSR29: Current Receive Descriptor Address Upper CSR30: Base Address Transmit Descriptor Ring Lower CSR31: Base Address Transmit Descriptor Ring Upper Am79C970A 1-714 1-715 1-715 1-715 1-716 1-717 1-718 1-718 1-718 1-718 1-718 1-718 1-719 1-719 1-720 1-720 1-720 1-721 1-721 1-721 1-721 1-721 1-721 1-724 1-724 1-725 1-727 1-729 1-731 1-731 1-732 1-732 1-732 1-732 1-732 1-732 1-733 1-735 1-735 1-735 1-735 1-736 1-736 1-736 1-736 1-736 1-736 1-737 1-737 1-737 1-737 1-737 1-737 1-617
PRELIMINARY 1-737 1-738 1-738 1-738 1-738 1-738 1-738 1-738 1-739 1-739 1-739 1-739 1-739 1-739 1-740 1-740 1-742 1-742 1-742 1-742 1-743 1-743 1-743 1-743 1-743 1-743 1-744 1-744 1-744 1-746 1-746 1-746 1-746 1-747 1-747 1-747 1-747 1-748 1-748 1-748 1-748 1-749 1-750 1-750 1-750 1-753 1-754 1-754 1-759 1-761 1-761 1-762 1-762 1-763 1-766
CSR32: Next Transmit Descriptor Address Lower CSR33: Next Transmit Descriptor Address Upper CSR34: Current Transmit Descriptor Address Lower CSR35: Current Transmit Descriptor Address Upper CSR36: Next Next Receive Descriptor Address Lower CSR37: Next Next Receive Descriptor Address Upper CSR38: Next Next Transmit Descriptor Address Lower CSR39: Next Next Transmit Descriptor Address Upper CSR40: Current Receive Byte Count CSR41: Current Receive Status CSR42: Current Transmit Byte Count CSR44: Next Receive Byte Count CSR45: Next Receive Status CSR46: Poll Time Counter CSR47: Polling Interval CSR58: Software Style CSR60: Previous Transmit Descriptor Address Lower CSR61: Previous Transmit Descriptor Address Upper CSR62: Previous Transmit Byte Count CSR63: Previous Transmit Status CSR64: Next Transmit Buffer Address Lower CSR65: Next Transmit Buffer Address Upper CSR66: Next Transmit Byte Count CSR67: Next Transmit Status CSR72: Receive Descriptor Ring Counter CSR74: Transmit Descriptor Ring Counter CSR76: Receive Descriptor Ring Length CSR78: Transmit Descriptor Ring Length CSR80: Transfer Counter FIFO Watermark Control CSR82: Activity Timer CSR84: Address Register Lower CSR85: Address Register Upper CSR86: Buffer Byte Counter CSR88: Chip Register Lower CSR89: Chip Register Upper CSR94: Transmit Time Domain Reflectometry Count CSR100: Timeout CSR112: Missed Frame Count CSR114: Receive Collision Count CSR122: Advanced Feature Control CSR124: Test Register Configuration Registers BCR0: Master Mode Read Active BCR1: Master Mode Write Active BCR2: Miscellaneous Configuration BCR4: Link Status (LNKST) BCR5: LED1 Status BCR6: LED2 Status BCR7: LED3 Status BCR9: Full-Duplex Control BCR16: Base Address Lower BCR17: Base Address Upper BCR18: Burst Control Register BCR19: EEPROM Control Status BCR20: Software Style 1-618 Am79C970A
1-768 1-768 1-768 1-769 1-770 1-770 1-771 1-771 1-771 1-772 1-772 1-773 1-774 1-774 1-775 1-775 1-776 1-777 1-778 1-778 1-779 1-782
BCR21: Interrupt Control BCR22: Latency Register Initialization Block RLEN TLEN RDRA TDRA LADRF PADR MODE Receive Descriptors RMD0 RMD1 RMD2 RMD3 Transmit Descriptors TMD0 TMD1 TMD2 TMD3 REGISTER SUMMARY Configuration Registers Control Status Registers Configuration Registers
ABSOLUTE MAXIMUM RATING 1-783 OPERATING RANGES 1-783 CHARACTERISTICS 1-783 SWITCHING CHARACTERISTICS Interface 10BASE-T Interface GPSI EADI 1-786 1-786 1-788 1-789 1-790 1-791
SWITCHING WAVEFORMS 1-792 SWITCHING TEST CIRCUITS 1-792 SWITCHING WAVEFORMS System Interface 10BASE-T Interface GPSI EADI APPENDIX PCnet-PCI Compatible Media Interface Modules 10BASE-T Filters Transformers Isolation Transformers DC/DC Converters Manufacturer Contact Information 1-794 1-794 1-798 1-800 1-803 1-804 1-805 1-805 1-806 1-806 1-807
APPENDIX Recommendation Power Ground Decoupling 1-808 APPENDIX Alternative Method Initialization 1-810
Am79C970A
1-619
PRELIMINARY 1-811 1-811 1-812 1-814 1-815 1-816 1-817 1-818 1-821 1-821 1-821 1-822 1-822 1-822 1-823 1-824 1-824 1-825
APPENDIX Look-Ahead Packet Processing Concept Introduction LAPP Concept Outline LAPP Flow LAPP Software Requirements LAPP Rules Parsing Descriptors Some Examples LAPP Descriptor Interaction Buffer Size Tuning Alternative LAPP Flow-the Interrupt Method APPENDIX PCnet-PCI PCnet-PCI Differences Overview Features List Register Changes Configuration Space Control Status Registers Configuration Registers Receive Descriptor Transmit Descriptor List Changes
1-620
Am79C970A
CONNECTION DIAGRAM
AD28 AD29 VSSB AD30 AD31 INTA RESERVED SLEEP EECS EESK/LED1/SFBD EEDI/LNSKT EEDO/LED3/SRD AVDD2 CIDI+ DIAVDD1 DOAVSS1 VDDB AD27 AD26 VSSB AD25 AD24 C/BE3
IDSEL AD23 AD22 VSSB AD21 AD20 VDDB AD19 AD18 VSSB AD17 AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP LOCK PERR SERR VDDB
XTAL2 AVSS2 XTAL1 AVDD3
TXD+ TXP+ TXDTXPAVDD4
Am79C970A PCnetTM-PCI
RXD+ RXDVSS LED2/SRDCLK ERD0/RXDAT ERD1/RXCLK ERD2/RXEN ERD3/CLSN ERD4/TXCLK ERD5 ERD6/TXEN ERD7/TXDAT ERA0 ERA1 ERA2 ERA3 ERA4 ERA5
marked orientation. RESERVED Don't connect
C/BE1 AD15 VSSB AD14 AD13 AD12 AD11 AD10 VSSB VDDB C/BE0 VSSB VSSB EROE DXCVR/NOUT ERACLK ERA7 ERA6
19436C-2
Am79C970A
1-621
CONNECTION DIAGRAM
AD28 AD29 VSSB AD30 AD31 INTA RESERVED SLEEP EECS EESK/LED1/SFBD EEDI/LNKST EED0/LED3/SRD AVDD2 AVDD1 AVSS1
VDDB AD27 AD26 VSSB AD25 AD24 C/BE3 IDSEL AD23 AD22 VSSB AD21 AD20 VDDB AD19 AD18 VSSB AD17 AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP LOCK PERR SERR VDDB
PCnet-PCI Am79C970AVC
XTAL2 AVSS2 XTAL1 AVDD3 TXD+ TXP+ TXD- TXP- AVDD4 RXD+ RXD- LED2/SRDCLK ERD0/RXDAT ERD1/RXCLK ERD2/RXEN ERD3/CLSN ERD4/TXCLK ERD5 ERD6/TXEN ERD7/TXDAT ERA0 ERA1 ERA2 ERA3 ERA4 ERA5
marked orientation. RESERVED Don't connect
C/BE1 AD15 VSSB AD14 AD13 AD12 AD11 AD10 VSSB VDDB C/BE0 VSSB VSSB EROE DXCVR/NOUT ERACLK ERA7 ERA6
19436C-3
1-622
Am79C970A
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination AM79C970A ALTERNATE PACKAGING OPTION Trimmed Formed Tray OPTIONAL PROCESSING Blank Standard Processing
TEMPERATURE RANGE Commercial (0°C +70°C) Industrial (-40°C +85°C)
PACKAGE TYPE Plastic Quad Flat Pack (PQB132) Thin Quad Flat Pack (PQJ144)
SPEED OPTION Applicable
DEVICE NUMBER/DESCRIPTION Am79C970A PCnet-PCI Single-Chip Full-Duplex Controller Local Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Valid Combinations AM79C970A AM79C970A KC\W, VC\W KI\W, VI\W
Am79C970A
1-623
DESIGNATIONS PQFP Listed Number
Name VDDB AD27 AD26 VSSB AD25 AD24 C/BE3 IDSEL AD23 AD22 VSSB AD21 AD20 VDDB AD19 AD18 VSSB AD17 AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP LOCK PERR SERR VDDB Name C/BE1 AD15 VSSB AD14 AD13 AD12 AD11 AD10 VSSB VDDB C/BE0 VSSB VSSB EROE DXCVR/NOUT ERACLK ERA7 ERA6 Name ERA5 ERA4 ERA3 ERA2 ERA1 ERA0 ERD7/TXDAT ERD6/TXEN ERD5 ERD4/TXCLK ERD3/CLSN ERD2/RXEN ERD1/RXCLK ERD0/RXDAT LED2/SRDCLK RXDRXD+ AVDD4 TXPTXDTXP+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 Name AVSS1 DODO+ AVDD1 DIDI+ CICI+ AVDD2 EEDO/LED3/SRD EEDI/LNKST EESK/LED1/SFBD EECS SLEEP RESERVED INTA AD31 AD30 VSSB AD29 AD28
1-624
Am79C970A
DESIGNATIONS PQFP Listed Group
Name Interface AD[31:0] C/BE[3:0] DEVSEL FRAME IDSEL INTA IRDY LOCK PERR SERR STOP TRDY Board Interface LED1 LED2 LED3 SLEEP XTAL1 XTAL2 Microwire EEPROM Interface EECS EEDI EEDO EESK Expansion Interface ERA[7:0] ERACLK ERD[7:0] EROE Expansion Address Expansion Address Clock Expansion Data Expansion Output Enable Microwire Serial EEPROM Chip Select Microwire Serial EEPROM Data Microwire Address EEPROM Data Microwire Serial PROM Clock LED1 LED2 LED3 Sleep Mode Crystal Input Crystal Output XTAL Address/Data Command/Byte Enable Clock Device Select Cycle Frame Grant Initialization Device Select Interrupt Initiator Ready Lock Parity Parity Error Request Reset System Error Stop Target Ready STS6 STS6 STS6 STS6 STS6 STS6 Function Type Driver Pins
Am79C970A
1-625
DESIGNATIONS PQFP Listed Group
Name Interface Attachment Unit Interface (AUI) CI+/CIDI+/DIDO+/DODXCVR 10BASE-T Interface LNKST RXD+/RXDTXD+/TXDTXP+/TXPLink Status Receive Differential Pair Transmit Differential Pair Transmit Pre-distortion Differential Pair Collision Differential Pair Data Differential Pair Data Differential Pair Disable Transceiver Function Type Driver Pins
General Purpose Serial Interface (GPSI) CLSN RXEN RXDAT RXCLK TXCLK TXDAT TXEN Collision Receive Enable Receive Data Receive Clock Transmit Clock Transmit Data Transmit Enable
External Address Detection Interface (EADI) SFBD SRDCLK External Address Reject Start Frame Byte Delimiter Serial Receive Data Serial Receive Data Clock
IEEE 1149.1 Test Access Port Interface (JTAG) Test Interface NOUT Power Supplies AVDD AVSS VDDB VSSB Analog Power Analog Ground Digital Power Digital Ground Buffer Power Buffer Ground NAND Tree Test Output Test Clock Test Data Test Data Test Mode Select
1-626
Am79C970A
DESIGNATIONS 144-PIN TQFP Listed Number
Name VDDB AD27 AD26 VSSB AD25 AD24 C/BE3 IDSEL AD23 AD22 VSSB AD21 AD20 VDDB AD19 AD18 VSSB AD17 AD16 C/BE2 FRAME IRDY TRDY DEVSEL STOP LOCK PERR SERR VDDB Name C/BE1 AD15 VSSB AD14 AD13 AD12 AD11 AD10 VSSB VDDB C/BE0 VSSB VSSB EROE DXCVR/NOUT ERACLK ERA7 ERA6 Name ERA5 ERA4 ERA3 ERA2 ERA1 ERA0 ERD7/TXDAT ERD6/TXEN ERD5 ERD4/TXCLK ERD3/CLSN ERD2/RXEN ERD1/RXCLK ERD0/RXDAT LED2/SRDCLK RXDRXD+ AVDD4 TXPTXDTXP+ TXD+ AVDD3 XTAL1 AVSS2 XTAL2 Name AVSS1 DODO+ AVDD1 DIDI+ CICI+ AVDD2 EEDO/LED3/SRD EEDI/LNKST EESK/LED1/SFBD EECS SLEEP Reserved INTA AD31 AD30 VSSB AD29 AD28
Indicates connect
Am79C970A
1-627
DESIGNATIONS 144-PIN TQFP Listed Group
Name Interface AD[31:0] C/BE[3:0] DEVSEL FRAME IDSEL INTA IRDY LOCK PERR SERR STOP TRDY Board Interface LED1 LED2 LED3 SLEEP XTAL1 XTAL2 Microwire EEPROM Interface EECS EEDI EEDO EESK Expansion Interface ERA[7:0] ERACLK ERD[7:0] EROE Expansion Address Expansion Address Clock Expansion Data Expansion Output Enable Microwire Serial EEPROM Chip Select Microwire Serial EEPROM Data Microwire Address EEPROM Data Microwire Serial PROM Clock LED1 LED2 LED3 Sleep Mode Crystal Input Crystal Output XTAL Address/Data Command/Byte Enable Clock Device Select Cycle Frame Grant Initialization Device Select Interrupt Initiator Ready Lock Parity Parity Error Request Reset System Error Stop Target Ready STS6 STS6 STS6 STS6 STS6 STS6 Function Type Driver Pins
1-628
Am79C970A
DESIGNATIONS 144-PIN TQFP Listed Group
Name Interface Attachment Unit Interface (AUI) CI+/CIDI+/DIDO+/DODXCVR 10BASE-T Interface LNKST RXD+/RXDTXD+/TXDTXP+/TXPLink Status Receive Differential Pair Transmit Differential Pair Transmit Pre-distortion Differential Pair Collision Differential Pair Data Differential Pair Data Differential Pair Disable Transceiver Function Type Driver Pins
General Purpose Serial Interface (GPSI) CLSN RXEN RXDAT RXCLK TXCLK TXDAT TXEN Collision Receive Enable Receive Data Receive Clock Transmit Clock Transmit Data Transmit Enable
External Address Detection Interface (EADI) SFBD SRDCLK External Address Reject Start Frame Byte Delimiter Serial Receive Data Serial Receive Data Clock
IEEE 1149.1 Test Access Port Interface (JTAG) Test Interface NOUT Power Supplies AVDD AVSS VDDB VSSB Analog Power Analog Ground Digital Power Digital Ground Buffer Power Buffer Ground NAND Tree Test Output Test Clock Test Data Test Data Test Mode Select
Am79C970A
1-629
DESIGNATIONS Listed Driver Type
next table describes various types drivers that used PCnet-PCI controller:
Name STS6 Type Totem Pole Open Drain Sustained Tri-State Tri-State Tri-State
(mA)
(mA) -0.4 -0.4
Load (pF)
values shown table above apply signaling. section Characteristics" values applying signaling. sustained tri-state signal active signal that driven high clock period before left floating.
differential output drivers. characteristic these XTAL output described section Characteristics".
1-630
Am79C970A
DESCRIPTION Interface AD[31:0]
Address Data Input/Output Address data multiplexed same interface pins. During first clock transaction AD[31:0] contain physical address bits). During subsequent clocks AD[31:0] contain data. Byte ordering little endian default. AD[7:0] defined least significant byte AD[31:24] defined most significant byte. FIFO data transfers, PCnet-PCI controller programmed endian byte ordering. CSR3, (BSWP) more details. During address phase transaction, when PCnet-PCI controller master, AD[31:2] will address active Double Word (DWord). PCnet-PCI controller always drives AD[1:0] `00' during address phase indicating linear burst order. When PCnet-PCI controller master, AD[31:0] lines continuously monitored determine address match exists slave transfers. During data phase transaction, AD[31:0] driven PCnet-PCI controller when performing master write slave read operations. Data AD[31:0] latched PCnet-PCI controller when performing master read slave write operations. When active, AD[31:0] inputs NAND tree testing.
defined with respect this edge. PCnet-PCI controller operates over range MHz. This clock used drive network functions. When active, input NAND tree testing.
DEVSEL
Device Select Input/Output PCnet-PCI controller drives DEVSEL when detects transaction that selects device target. device samples DEVSEL detect target claims transaction that PCnet-PCI controller initiated. When active, DEVSEL input NAND tree testing.
FRAME
Cycle Frame Input/Output FRAME driven PCnet-PCI controller when master indicate beginning duration transaction. FRAME asserted indicate transaction beginning. FRAME asserted while data transfers continue. FRAME deasserted before final data phase transaction. When PCnet-PCI controller slave mode, samples FRAME determine address phase transaction. When active, FRAME input NAND tree testing.
Grant Input This signal indicates that access been granted PCnet-PCI controller. PCnet-PCI controller supports parking. When idle system arbiter asserts without active from PCnet-PCI controller, device will drive AD[31:0], C/BE[3:0] lines. When active, input NAND tree testing.
C/BE[3:0]
Command Byte Enables Input/Output command byte enables multiplexed same interface pins. During address phase transaction, C/BE[3:0] define command. During data phase C/BE[3:0] used byte enables. byte enables define which physical byte lanes carry meaningful data. C/BE0 applies byte (AD[7:0]) C/BE3 applies byte (AD[31:24]). function byte enables independent byte ordering mode (BSWP, CSR3, When active, C/BE[3:0] inputs NAND tree testing.
IDSEL
Initialization Device Select Input This signal used chip select PCnet-PCI controller during configuration read write transactions. When active, IDSEL input NAND tree testing.
Clock Input This clock used drive system interface internal buffer management unit. signals sampled rising edge parameters
Am79C970A
1-631
PRELIMINARY read data phases device checks IRDY determine initiator ready accept data. When active, IRDY input NAND tree testing.
INTA
Interrupt Request Input/Output attention signal which indicates that more following status flags set: BABL, EXDINT, IDON, JAB, MERR, MISS, MFCO, MPINT, RCVCCO, RINT, SINT, SLPINT, TINT, TXSTRT UINT. Each status flag either mask enable which allows suppression INTA assertion. flags have following meaning: Table Interrupt Flags
BABL EXDINT IDON MERR MISS MFCO MPINT RCVCCO RINT SLPINT SINT TINT TXSTRT UINT Babble Excessive Deferral Initialization Done Jabber Memory Error Missed Frame Missed Frame Count Overflow Magic Packet Interrupt Receive Collision Count Overflow Receive Interrupt Sleep Interrupt System Error Transmit Interrupt Transmit Start User Interrupt
LOCK
Lock Input slave mode, LOCK input PCnet-PCI controller. master lock device guarantee atomic operation that requires multiple transactions. PCnet-PCI controller will never assert LOCK master. When active, LOCK input NAND tree testing.
Parity Input/Output Parity even parity across AD[31:0] C/BE[3:0]. When PCnet-PCI controller master, generates parity during address write data phases. checks parity during read data phases. When PCnet-PCI controller operates slave mode, checks parity during every address phase. When target cycle, checks parity during write data phases generates parity during read data phases. When active, input NAND tree testing.
PERR
Parity Error Input/Output During slave write transaction master read transaction, PCnet-PCI controller asserts PERR when detects data parity error reporting error enabled setting PERREN (PCI Command register, ONE. During master write transaction PCnet-PCI controller monitors PERR target reports data parity error. When active, PERR input NAND tree testing.
default INTA open-drain output. applications that need high-active edge sensitive interrupt signal, INTA configured this mode setting INTLEVEL (BCR2, ONE. When active, INTA input NAND tree testing.
IRDY
Initiator Ready Input/Output IRDY indicates ability initiator transaction complete current data phase. IRDY used conjunction with TRDY. Wait states inserted until both IRDY TRDY asserted simultaneously. data phase completed clock when both IRDY TRDY asserted. When PCnet-PCI controller master, asserts IRDY during write data phases indicated that valid data present AD[31:0]. During read data phases device asserts IRDY indicate that ready accept data. When PCnet-PCI controller target transaction, checks IRDY during write data phases determine valid data present AD[31:0]. During 1-632
Request Input/Output PCnet-PCI controller asserts signal that wishes become master. driven high when PCnet-PCI controller does request bus. When active, input NAND tree testing.
Reset Input When asserted low, then PCnet-PCI controller performs internal system reset type
Am79C970A
PRELIMINARY H_RESET (HARDWARE_RESET). must held minimum clock periods. While H_RESET state, PCnet-PCI controller will disable deassert outputs. asynchronous when asserted deasserted. recommended that deassertion synchronous guarantee clean bounce free edge. When active, NAND tree testing enabled. interface pins input mode. result NAND tree testing observed NOUT output (pin 62).
When active, TRDY input NAND tree testing.
Board Interface LED1
LED1 Output This output designed directly drive LED. default, LED1 indicates receive activity network. This also programmed indicate other network status (see BCR5). LED1 polarity programmable, default, active LOW. Note that LED1 multiplexed with EESK SFBD pins.
SERR
System Error Input/Output During slave transaction, PCnet-PCI controller asserts SERR when detects address parity error reporting error enabled setting PERREN (PCI Command register, SERREN (PCI Command register, ONE. default SERR open-drain output. component test programmed active-high totem-pole output. When active, SERR input NAND tree testing.
LED2
LED2 Output This output designed directly drive LED. default, LED2 indicates correct receive polarity 10BASE-T interface. This also programmed indicate other network status (see BCR6). LED2 polarity programmable, default, active LOW. Note that LED2 multiplexed with SRDCLK pin.
STOP
Stop Input/Output slave mode, PCnet-PCI controller drives STOP signal inform master stop current transaction. master mode, PCnet-PCI controller checks STOP determine target wants disconnect current transaction. When active, STOP input NAND tree testing.
LED3
LED3 Output This output designed directly drive LED. default, LED3 indicates transmit activity network. This also programmed indicate other network status (see BCR7). LED3 polarity programmable, default, active LOW. Note that LED3 multiplexed with EEDO pins. Special attention must given external circuitry attached this pin. When this used drive while EEPROM used system, then buffering required between LED3 circuit. circuit were directly attached this pin, would create requirement that could serial EEPROM attached this pin. EEPROM included system design, then LED3 signal directly connected without buffering. more details regarding connection, section "LED Support".
TRDY
Target Ready Input/Output TRDY indicates ability target transaction complete current data phase. TRDY used conjunction with IRDY. Wait states inserted until both IRDY TRDY asserted simultaneously. data phase completed clock when both IRDY TRDY asserted. When PCnet-PCI controller master, checks TRDY during read data phases determine valid data present AD[31:0]. During write data phases device checks TRDY determine target ready accept data. When PCnet-PCI controller target transaction, asserts TRDY during read data phases indicate that valid data present AD[31:0]. During write data phases device asserts TRDY indicate that ready accept data.
SLEEP
Sleep Input When SLEEP asserted, PCnet-PCI controller performs internal system reset S_RESET type then proceeds into power savings mode. PCnet-PCI controller outputs will placed their normal reset condition. PCnet-PCI controller inputs
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will ignored except SLEEP itself. Deassertion SLEEP results wake-up. system must refrain from starting network operations PCnet-PCI controller device following deassertion SLEEP signal order allow internal analog circuits stabilize. Both XTAL1 inputs must have valid clock signals present order SLEEP command take effect. SLEEP should asserted during power supply ramp-up. desired that SLEEP asserted power time, then system must delay assertion SLEEP until three clock cycles after completion hardware reset operation. SLEEP must left unconnected. should tied VDD, power savings mode used.
EEDI
EEPROM Data Output This designed directly interface serial EEPROM that uses Microwire interface protocol. EEDI connected Microwire EEPROM data input pin. controlled either PCnet-PCI controller during command portions read entire EEPROM, indirectly host system writing BCR19, Note that EEDI multiplexed with LNKST pin.
EEDO
EEPROM Data Input This designed directly interface serial EEPROM that uses Microwire interface protocol. EEDO connected Microwire EEPROM data output pin. controlled either PCnet-PCI controller during command portions read entire EEPROM, indirectly host system reading from BCR19, Note that EEDO multiplexed with LED3 pins.
XTAL1
Crystal Oscillator Input internal clock generator uses crystal that attached pins XTAL1 XTAL2. network data rate one-half crystal frequency. XTAL1 alternatively driven using external CMOS level clock signal. Refer section "External Crystal Characteristics" more details. Note that when PCnet-PCI controller coma mode, there internal resistor from XTAL1 ground. external source drives XTAL1, some power will consumed driving this resistor. XTAL1 driven this time power consumption will minimized. this case, XTAL1 must remain active least cycles after assertion SLEEP deassertion REQ.
EESK
EEPROM Serial clock Input/Output This designed directly interface serial EEPROM that uses Microwire interface protocol. EESK connected Microwire EEPROM clock pin. controlled either PCnet-PCI controller directly during read entire EEPROM, indirectly host system writing BCR19, Note that EESK multiplexed with LED1 SFBD pins. EESK also used during EEPROM Auto-detection determine whether EEPROM present PCnet-PCI controller Microwire interface. rising edge during last clock during which asserted, EESK sampled determine value EEDET BCR19. sampled HIGH value means that EEPROM present, EEDET will ONE. sampled value means that EEPROM present, EEDET will cleared ZERO. section "EEPROM Auto-Detection" more details. circuit attached this pin, then pull pull down resistor must attached instead, order resolve EEDET setting.
XTAL2
Crystal Oscillator Output internal clock generator uses crystal that attached pins XTAL1 XTAL2. network data rate one-half crystal frequency. external clock source used XTAL1, then XTAL should left unconnected.
Microwire EEPROM Interface EECS
EEPROM Chip Select Output This designed directly interface serial EEPROM that uses Microwire interface protocol. EECS connected Microwire EEPROM chip select pin. controlled either PCnet-PCI controller during command portions read entire EEPROM, indirectly host system writing BCR19,
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Expansion Interface ERA[7:0]
Expansion Address Output These pins provide address Expansion ROM. When EROE asserted ERACLK driven HIGH, ERA[7:0] contain upper bits Expansion address. They must latched externally. When EROE asserted ERACLK low, ERA[7:0] contain lower bits Expansion address. outputs forced constant level conserve power while access Expansion performed.
DXCVR
Disable Transceiver Output DXCVR signal provided power down external transceiver DC-to-DC converter designs that provide more than network connection. polarity asserted state DXCVR output controlled DXCVRPOL (BCR2, default, DXCVR output high when asserted. When 10BASE-T interface active network port, DXCVR output always deasserted. When GPSI interface active network port, assertion DXCVR output controlled setting DXCVRCTL (BCR2, Note that DXCVR multiplexed with NOUT pin.
ERACLK
Expansion Address Clock Output When EROE asserted ERACLK driven HIGH, ERA[7:0] contain upper bits Expansion address. ERACLK used latch address bits externally. Both '373 (transparent latch) '374 flip-flop) types address latch supported.
Twisted Pair Interface LNKST
Link Status Output This output designed directly drive LED. default, LNKST indicates active link connection 10BASE-T interface. This also programmed indicate other network status (see BCR4). LNKST polarity programmable, default, active LOW. Note that LNKST multiplexed with EEDI pin.
ERD[7:0]
Expansion Data Input Data from Expansion transferred ERD[7:0]. When EROE high, ERD[7:0] inputs internally disabled left floating. Note that ERD[7:0] pins multiplexed with GPSI interface.
EROE
Expansion Output Enable Output This signal asserted when Expansion read.
RXD±
10BASE-T Receive Data 10BASE-T port differential receivers. Input
Attachment Unit Interface
Collision Input differential input pair signaling PCnet-PCI controller that collision been detected network media, indicated inputs being driven with pattern sufficient amplitude pulse width meet 8802-3 (IEEE/ANSI 802.3) standards. Operates pseudo levels.
TXD± 10BASE-T Transmit Data
10BASE-T port differential drivers.
Output
TXP±
10BASE-T Pre-Distortion Control Output These outputs provide transmit pre-distortion control conjunction with 10BASE-T port differential drivers.
General Purpose Serial Interface CLSN
Collision Input CLSN input, indicating that collision occurred network. Note that CLSN multiplexed with ERD3 pin.
Data Input differential input pair PCnet-PCI controller carrying Manchester encoded data from network. Operates pseudo levels.
Data Output differential output pair from PCnet-PCI controller transmitting Manchester encoded data network. Operates pseudo levels.
RXCLK
Receive Clock Input RXCLK input. Rising edges RXCLK signal used sample data RXDAT input whenever RXEN input HIGH. 1-635
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PRELIMINARY result this check will with value pin. defined REJECT. value "OR"ed with internal address detection result determine current frame should accepted rejected. internally pulled-up left unconnected, EADI interface used.
Note that RXCLK multiplexed with ERD1 pin.
RXDAT
Receive Data Input RXDAT input. Rising edges RXCLK signal used sample data RXDAT input whenever RXEN input HIGH. Note that RXDAT multiplexed with ERD0 pin.
SFBD
Start Frame-Byte Delimiter Output initial rising edge SFBD signal indicates that start frame delimiter been detected. serial stream will follow signal, commencing with destination address field. SFBD will high times (400 after detecting second (Start Frame Delimiter) received frame. SFBD will subsequently toggle every (1.25 frequency) with each rising edge indicating first each subsequent byte received serial stream. SFBD will inactive during frame transmission. Note that SFBD multiplexed with EESK LED1 pins.
RXEN Receive Enable Input
RXEN input. When this signal HIGH, indicates core logic that data RXDAT input valid. Note that RXEN multiplexed with ERD2 pin.
TXCLK
Transmit Clock Input TXCLK input, providing clock signal activity, both transmit receive. Rising edges TXCLK used validate TXDAT output data. Note that TXCLK multiplexed with ERD4 pin.
Serial Receive Data Output decoded data from network. This signal used external address detection. When 10BASE-T port selected, transitions will only occur during receive activity. When GPSI port selected, transitions will occur during both transmit receive activity. Note that multiplexed with EEDO LED3 pins.
TXDAT
Transmit Data Output TXDAT output, providing serial stream transmission, including preamble, data field, applicable. TXDAT floats when GPSI interface enabled. Note that TXDAT multiplexed with ERD7 pin.
SRDCLK
Serial Receive Data Clock Output Serial Receive Data synchronous with reference SRDCLK. When 10BASE-T port selected, transitions SRDCLK will only occur during receive activity. When GPSI port selected, transitions SRDCLK will occur during both transmit receive activity. Note that SRDCLK multiplexed with LED2 pin.
TXEN
Transmit Enable Output TXEN output, providing enable signal transmission. Data TXDAT valid unless TXEN signal HIGH. TXEN should have external pull-down resistor attached (e.g. ensure output held inactive until GPSI interface enabled. Note that TXEN multiplexed with ERD6 pin.
IEEE 1149.1 Test Access Port Interface
Test Clock Input clock input boundary scan test mode operation. operate frequency MHz. internal pull-up resistor. input
External Address Detection Interface
External Address Reject Input incoming frame will checked against internally active address detection mechanisms
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PRELIMINARY operates same signaling environment interface.
Test Data Input test data input path PCnet-PCI controller. internal pull-up resistor. input operates same signaling environment interface.
avoid excessive noise these lines. Refer Appendix PCnet Family Board Design Layout Recommendations application note (PID #19595A) details.
AVSS
Analog Ground Pins) Power There analog ground pins. Special attention should paid printed circuit board layout avoid excessive noise these lines. Refer Appendix PCnet Family Board Design Layout Recommendations application note (PID #19595A) details.
Test Data Output test data output path from PCnet-PCI controller. tri-stated when JTAG port inactive. output operates same signaling environment interface.
Digital Power Pins) Power There power supply pins that used internal digital circuitry. pins must connected supply.
Test Mode Select Input serial input stream used define specific boundary scan test executed. internal pull-up resistor. input operates same signaling environment interface.
VDDB
Buffer Power Pins) Power There four power supply pins that used input/output buffer drivers. system with signaling environment, VDDB pins must connected supply. system with signaling nvironment, VDDB pins must connected +3.3 supply.
Test Interface NOUT
NAND Tree Output When asserted, results NAND tree testing observed NOUT pin. Note that NOUT multiplexed with DXCVR pin.
Digital Ground Pins) Ground There ground pins that used internal digital circuitry.
Power Supply Pins AVDD
Analog Power Pins) Power There four analog supply pins. Special attention should paid printed circuit board layout
VSSB
Buffer Ground Pins) Ground There ground pins that used input/output buffer drivers.
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PRELIMINARY dress space that must begin 32-byte block boundary. address space mapped into both memory space (memory mapped I/O). Base Address Register Configuration Space defines start address address space mapped space. Memory Mapped Base Address Register defines start address address space mapped memory space. 32-byte address space used software program PCnet-PCI controller operating mode, enable disable various features, monitor operating status, request particular functions executed PCnet-PCI controller. third portion software interface descriptor buffer areas that shared between software PCnet-PCI controller during normal network operations. descriptor area boundaries software change during normal network operations. There descriptor area receive activity there separate area transmit activity. descriptor space contains relocatable pointers network frame data used transfer frame status from PCnet-PCI controller software. buffer areas locations that hold frame data transmission that accept frame data that been received.
BASIC FUNCTIONS System Interface Function
PCnet-PCI controller designed operate master during normal operations. Some slave accesses PCnet-PCI controller required normal operations well. Initialization PCnet-PCI controller achieved through combination Configuration Space accesses, slave accesses, master accesses optional read serial EEPROM that performed PCnet-PCI controller. EEPROM read operation performed through Microwire interface. 8802-3 (IEEE/ANSI 802.3) Ethernet Address reside within serial EEPROM. Some PCnet-PCI controller configuration registers also programmed EEPROM read operation. Address PROM, on-chip bus-configuration registers, Ethernet controller registers occupy bytes address space. Both, memory mapped access supported. Base Address registers configuration space allow locating address space wide variety starting addresses. diskless stations, PCnet-PCI controller supports Expansion Kbytes size. host Expansion memory address that aligns boundary modifying Expansion Base Address register configuration space.
Network Interfaces
PCnet-PCI controller connected 802.3 network three network interfaces. Attachment Unit Interface (AUI) provides 8802-3 (IEEE/ANSI 802.3) compliant differential interface remote on-board transceiver. 10BASE-T interface provides twisted-pair Ethernet port. While auto-selection mode, interface determined auto-sensing mechanism which checks link status 10BASE-T port. there active link status, then device assumes connection. General Purpose Serial Interface (GPSI) allows bypassing Manchester Encoder/Decoder (MENDEC). PCnet-PCI controller implements half full-duplex Ethernet over three network interfaces.
Software Interface
software interface PCnet-PCI controller divided into three parts. part configuration registers. They used identify PCnet-PCI controller, also used setup configuration device. setup information includes memory mapped base address, mapping Expansion routing PCnet-PCI controller interrupt channel. This allows jumperless implementation. second portion software interface direct access resources PCnet-PCI controller. PCnet-PCI controller occupies bytes
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DETAILED FUNCTIONS Slave Interface Unit
slave interface unit (BIU) controls accesses configuration space, Control Status Registers (CSR), Configuration Registers
(BCR), Address PROM (APROM) locations Expansion ROM. table below shows response PCnet-PCI controller each commands slave mode.
Table Slave Commands
C[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Command Interrupt Acknowledge Special Cycle Read Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write Invalidate Read Configuration Space Write Configuration Space Aliased Memory Read Used Aliased Memory Read Aliased Memory Write Memory Mapped Read CSR, APROM Read Expansion Memory Mapped Write CSR, APROM Dummy Write Expansion Used Used Read CSR, APROM Write CSR, APROM
Slave Configuration Transfers host access PCnet-PCI controller configuration space with configuration read write command. PCnet-PCI controller will assert DEVSEL during address phase when IDSEL asserted, AD[1:0] both ZERO, access configuration cycle. AD[7:2] select DWord location configuration space. PCnet-PCI controller ignores AD[10:8], because single function device. AD[31:11] don't care. active bytes within DWord determined byte enable signals. 8-bit, 16-bit 32-bit transfers supported. DEVSEL asserted clock cycles after host asserted FRAME. configuration cycles fixed length. PCnet-PCI controller will assert TRDY clock data phase. PCnet-PCI controller does support burst transfers access configuration space. When
AD31 AD11 AD10 Don't care
host keeps FRAME asserted second data phase, PCnet-PCI controller will disconnect transfer. When host tries access configuration space while automatic read EEPROM after H_RESET on-going, PCnet-PCI controller will terminate access with disconnect/ retry response. PCnet-PCI controller supports fast back-to-back transactions different targets. This indicated Fast Back-To-Back Capable (PCI Status register, which hardwired ONE. PCnet-PCI controller capable detecting configuration cycle even when address phase immediately follows data phase transaction different target without idle state in-between. There will contention DEVSEL, TRDY STOP signals, since PCnet-PCI controller asserts DEVSEL second clock after FRAME asserted (medium timing).
Don't care
DWord index
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FRAME
ADDR
DATA
C/BE
1010
IRDY
TRDY
DEVSEL STOP
IDSEL
19436C-4
Figure Slave Configuration Read
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Am79C970A
FRAME
ADDR
DATA
C/BE
1011
IRDY
TRDY
DEVSEL STOP
IDSEL
19436C-5
Figure Slave Configuration Write
Slave Transfers After PCnet-PCI controller configured device setting IOEN (for regular mode) MEMEN (for memory mapped mode) Command register, starts monitoring access CSR, EEPROM locations. configured regular mode, PCnet-PCI controller will look address that falls within bytes address space (starting from base address). PCnet-PCI controller asserts DEVSEL detects address match access cycle. configured memory mapped mode, PCnet-PCI controller will look address that falls within bytes memory address space (starting from memory mapped base address). PCnet-PCI controller asserts DEVSEL detects address match access memory cycle. DEVSEL asserted clock cycles after host asserted FRAME. PCnet-PCI controller will assert DEVSEL detects address match, command correct type. memory mapped mode, PCnet-PCI controller aliases accesses resources command types "Memory Read Multiple"
"Memory Read Line" basic Memory Read command. accesses type "Memory Write Invalidate" aliased basic Memory Write command. 8-bit, 16-bit 32-bit non-burst transactions supported. PCnet-PCI controller decodes only upper address lines determine which resource accessed. typical number wait states added slave memory mapped read write access part PCnet-PCI controller clock cycles, depending upon relative phases internal Buffer Management Unit clock signal, since internal Buffer Management Unit clock divide-by-two version signal. PCnet-PCI controller does support burst transfers access resources. When host keeps FRAME asserted second data phase, PCnet-PCI controller will disconnect transfer. PCnet-PCI controller supports fast back-to-back transactions different targets. This indicated Fast Back-To-Back Capable (PCI Status register, 1-641
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PRELIMINARY contention DEVSEL, TRDY STOP signals, since PCnet-PCI controller asserts DEVSEL second clock after FRAME asserted (medium timing).
which hardwired ONE. PCnet-PCI controller capable detecting memory mapped cycle even when address phase immediately follows data phase transaction different target, without idle state in-between. There will
FRAME
ADDR
DATA
C/BE
0010
IRDY
TRDY
DEVSEL
STOP
19436C-6
Figure Slave Read Using Command
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FRAME
ADDR
DATA
C/BE
0111
IRDY
TRDY
DEVSEL
STOP
19436C-7
Figure Slave Write Using Memory Command
Expansion Transfers host must initialize Expansion Base Address register offset configuration space with valid address before enabling access device. base address must aligned boundary indicated ROMSIZE (PCI Expansion Base Address register, bits 15-11). PCnet-PCI controller will react access Expansion until both MEMEN (PCI Command register, ROMEN (PCI Expansion Base Address register, ONE. After Expansion enabled, PCnet-PCI controller will assert DEVSEL memory read accesses with address between ROMBASE ROMBASE PCnet-PCI controller aliases accesses Expansion command types "Memory Read Multiple" "Memory Read Line" basic Memory Read command. Eight-bit, 16-bit 32-bit read transfers supported. Since setting MEMEN also enables memory mapped access resources, attention must given Memory Mapped Base Address register, before enabling access Expansion ROM. host must Memory Mapped Base Address register
value that prevents PCnet-PCI controller from claiming memory cycles intended PCnet-PCI controller will always read four bytes every host Expansion read access. TRDY will asserted until four bytes loaded into internal scratch register. cycle TRDY asserted depends programming Expansion interface timing. following figure assumes that ROMTMG (BCR18, bits 15-12) default value. Since target latency Expansion access considerably long, PCnet-PCI controller disconnects second data phase, when host tries perform burst read operation Expansion ROM. This behavior complies with requirements latency issues environment allows other devices fair access bus. When host tries write Expansion ROM, PCnet-PCI controller will claim cycle asserting DEVSEL. TRDY will asserted clock cycle later. write operation will have effect. PCnet-PCI controller supports fast back-to-back transactions different targets. This indicated Fast Back-To-Back Capable (PCI Status register,
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PRELIMINARY idle state in-between. There will contention DEVSEL, TRDY STOP signals, since PCnet-PCI controller asserts DEVSEL second clock after FRAME asserted (medium timing).
which hardwired ONE. PCnet-PCI controller capable detecting memory cycle even when address phase immediately follows data phase transaction different target without
FRAME
ADDR
DATA
C/BE
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled
19436C-8
Figure Expansion Read
Exclusive Access host lock transactions PCnet-PCI controller. lock allows exclusive access device used guarantee atomic operations. PCnet-PCI controller transitions from unlocked locked state when LOCK deasserted during address phase transaction that selects device target. controller stays locked state until both FRAME LOCK deasserted, until device signals target abort. Note that this protocol means device locks itself normal transaction. controller will unlock automatically normal transaction, because FRAME LOCK will deasserted. lock spans over whole slave address space. lock only applies slave accesses. PCnet-PCI controller might perform master cycles while being locked slave mode. When another master tries 1-644
access PCnet-PCI controller while locked state, device terminates access with disconnect/retry sequence. Slave Cycle Termination There three scenarios besides normal completion transaction where PCnet-PCI controller target slave cycle will terminate access.
Disconnect When Busy
PCnet-PCI controller cannot service slave access while reading contents Microwire EEPROM. Simultaneous access possible avoid conflicts, since Microwire EEPROM used initialize some configuration space locations most BCRs. Microwire EEPROM read operation will always happen automatically after deassertion pin. addition, host start
Am79C970A
PRELIMINARY read operation setting PREAD (BCR19, 14). While EEPROM read on-going, PCnet-PCI controller will disconnect slave access where target asserting STOP together with DEVSEL, while driving TRDY high. STOP will stay asserted until host removes FRAME. Note that memory slave accesses will only disconnected they enabled setting IOEN MEMEN Command register. Without enable set, cycles will claimed all. Since
H_RESET clears IOEN MEMEN bits, automatic EEPROM read after H_RESET disconnect only applies configuration cycles. second situation where PCnet-PCI controller will generate disconnect/retry cycle when host tries access resources right after having read Reset register. Since access generates internal reset pulse about length, further slave accesses will deferred until internal reset operation completed.
FRAME
ADDR
DATA
C/BE
IRDY
TRDY
DEVSEL STOP
19436C-9
Figure Disconnect Slave Cycle When Busy
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PRELIMINARY When PCnet-PCI controller sees FRAME IRDY asserted clock cycle before wants asserts TRDY, also asserts STOP same time. transfer first data phase still successful, since IRDY TRDY both asserted.
Disconnect Burst Transfer
PCnet-PCI controller does support burst access configuration space, resources, Expansion ROM. host indicates burst transaction keeping FRAME asserted during data phase.
FRAME
DATA
DATA
C/BE
IRDY
TRDY
DEVSEL STOP
19436C-10
Figure Disconnect Slave Burst Transfer-No Host Wait States
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PRELIMINARY When host ready when PCnet-PCI controller asserts TRDY, device will wait host assert IRDY. When host asserts IRDY FRAME still asserted, PCnet-PCI controller will
finish first data phase deasserting TRDY clock later. same time, will assert STOP signal disconnect host. STOP will stay asserted until host removes FRAME.
FRAME
DATA
DATA
C/BE
IRDY
TRDY DEVSEL STOP
19436C-11
Figure Disconnect Slave Burst Transfer-Host Inserts Wait States
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PRELIMINARY another master tried access PCnet-PCI controller will respond access asserting STOP together with DEVSEL while driving TRDY high, thereby disconnecting cycle. STOP will stay asserted until other master removes FRAME.
Disconnect When Locked
When PCnet-PCI controller locked master another master tries access controller, device will disconnect access. When PCnet-PCI controller locked state sees LOCK asserted together with FRAME, knows that
FRAME
LOCK
ADDR
DATA
C/BE
IRDY
TRDY
DEVSEL STOP
19436C-12
Figure Disconnect Slave Cycle When Locked
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Parity Error Response
When PCnet-PCI controller current master, samples AD[31:0], C/BE[3:0] lines during address phase command parity error. When detects address parity error, controller sets PERR (PCI Status register, ONE. When reporting that error enabled setting SERREN (PCI Command register, PERREN
(PCI Command register, ONE, Pcnet-PCI controller also drives SERR signal clock cycle sets SERR (PCI Status register, ONE. assertion SERR follows address phase clock cycles. PCnet-PCI controller will assert DEVSEL transaction that address parity error, when PERREN SERREN ONE.
FRAME
ADDR
DATA
C/BE
SERR DEVSEL
19436C-13
Figure Address Parity Error Response
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PRELIMINARY asserting TRDY. corrupted data will written addressed location. Figure shows transaction that suffered parity error time data transferred (clock IRDY TRDY both asserted). PERR driven high beginning data phase then drops parity error clock clock cycles after data transferred. After PERR driven low, PCnet-PCI controller drives PERR high clock cycle, since PERR sustained tri-state signal.
During data phase write, memory mapped write configuration write command that selects PCnet-PCI controller target, device samples AD[31:0] C/BE[3:0] lines parity clock edge data transferred. sampled following clock cycle. parity error detected reporting that error enabled setting PERREN (PCI Command register, ONE, PERR asserted clock later. parity error will always PERR (PCI Status register, even when PERREN cleared ZERO. PCnet-PCI controller will finish transaction that data parity error normal
FRAME
ADDR
DATA
C/BE
PERR
IRDY
TRDY
DEVSEL
19436C-14
Figure Slave Cycle Data Parity Error Response
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Master Interface Unit
master interface unit (BIU) controls acquisition accesses initialization block, descriptor rings receive
transmit buffer memory. table below shows usage commands PCnet-PCI controller master mode.
Table Master Commands
C[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Command Interrupt Acknowledge Special Cycle Read Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write Invalidate Used Used Read Transmit Buffer Burst Mode Used Read Transmit Buffer Burst Mode Used Read Initialization Block Descriptor Rings Read Transmit Buffer Non-burst Mode Write Descriptor Rings Receive Buffer Used Used Used Used
Acquisition
PCnet-PCI controller microcode will determine when transfer should initiated. first step PCnet-PCI controller master transfer acquire ownership bus. This task handled synchronous logic within BIU. ownership requested with signal ownership granted arbiter through signal. Figure shows PCnet-PCI controller acquisition. asserted arbiter returns while another master transferring data. PCnet-PCI controller waits until idle (FRAME IRDY deasserted) before starts driving AD[31:0] C/BE[3:0] clock FRAME asserted clock indicating valid address command AD[31:0] C/BE[3:0]. PCnet-PCI controller does address stepping which reflected
ADSTEP (bit Command register being hardwired ZERO. burst mode, deassertion depends setting EXTREQ (BCR18, EXTREQ cleared ZERO deasserted same time FRAME asserted. (The PCnet-PCI controller never performs more than burst transaction within single mastership period). EXTREQ ONE, PCnet-PCI controller does deassert until starts last data phase transaction. Once asserted, remains active until become active, independent subsequent setting STOP (CSR0, SPND (CSR5, assertion H_RESET S_RESET, however, will cause inactive immediately.
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FRAME
ADDR
C/BE
IRDY
19436C-15
Figure Acquisition
Master Transfers
There four primary types transfers. PCnet-PCI controller uses non-burst well burst cycles read write access main memory. Basic Non-Burst Read Transfer default, PCnet-PCI controller uses non-burst cycles master read operations. PCnet-PCI controller non-burst read accesses command type Memory Read (type Note that during non-burst read operation, byte lanes will always active. PCnet-PCI controller will internally discard unneeded bytes.
PCnet-PCI controller typically performs more than non-burst read transactions within single mastership period. FRAME dropped between consecutive non-burst read cycles. however stays asserted until FRAME asserted last transaction. PCnet-PCI controller supports zero wait state read cycles. asserts IRDY immediately after address phase same time starts sampling DEVSEL.
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PRELIMINARY following figure shows non-burst read transactions. first transaction zero wait states.
second transaction, target extends cycle asserting TRDY clock later.
FRAME
ADDR
DATA
ADDR
DATA
C/BE
0110
0000
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
19436C-16
Figure Non-Burst Read Transfer
Basic Burst Read Transfer PCnet-PCI controller supports burst mode master read operations. burst mode must enabled setting BREADE (BCR18, allow burst transfers descriptor read operations, PCnet-PCI controller must also programmed SWSTYLE THREE (BCR20, bits 7-0). burst read accesses initialization block descriptor ring command type Memory Read (type Burst read accesses transmit buffer typically longer than data phases. When MEMCMD (BCR18, cleared ZERO, burst read accesses transmit buffer command type Memory Read Line (type 14). When MEMCMD (BCR18, ONE, burst read accesses transmit buffer
command type Memory Read Multiple (type 12). AD[1:0] will both ZERO during address phase indicating linear burst order. Note that during burst read operation, byte lanes will always active. PCnet-PCI controller will internally discard unneeded bytes. PCnet-PCI controller will always perform only single burst read transaction mastership period, where transaction defined address phase multiple data phases. PCnet-PCI controller supports zero wait state read cycles. asserts IRDY immediately after address phase same time starts sampling DEVSEL. FRAME deasserted when next last data phase completed.
Am79C970A
1-653
PRELIMINARY phase each access wait state. example assumes that EXTREQ (BCR18, cleared ZERO, therefore, deasserted same cycle FRAME asserted.
following figure shows typical burst read access. PCnet-PCI controller arbitrates bus, granted access, reads three 32-bit words (DWord) from system memory then releases bus. example, memory system extends data
FRAME
ADDR
DATA
DATA
DATA
C/BE
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
19436C-17
Figure Burst Read Transfer (EXTREQ MEMCMD mastership period. FRAME dropped between consecutive non-burst write cycles. however stays asserted until FRAME asserted last transaction. PCnet-PCI controller supports zero wait state write cycles except with case descriptor write transfers. (See section "Descriptor Transfers" only exception.) asserts IRDY immediately after address phase same time starts sampling DEVSEL.
Basic Non-Burst Write Transfer default, PCnet-PCI controller uses non-burst cycles master write operations. PCnet-PCI controller non-burst write accesses command type Memory Write (type byte enable signals indicate byte lanes that have valid data. PCnet-PCI controller typically performs more than non-burst write transactions within single
1-654
Am79C970A
PRELIMINARY following figure shows non-burst write transactions. first transaction wait states. target inserts wait state asserting DEVSEL clock late another wait state also asserting TRDY
clock late. second transaction shows zero wait state write cycle. target asserts DEVSEL TRDY same cycle PCnet-PCI controller asserts IRDY.
FRAME
ADDR
DATA
ADDR
DATA
C/BE
0111
0111
IRDY
TRDY
DEVSEL
DEVSEL sampled
19436C-18
Figure Non-Burst Write Transfer
Basic Burst Write Transfer PCnet-PCI controller supports burst mode master write operations. burst mode must enabled setting BWRITE (BCR18, allow burst transfers descriptor write operations, PCnet-PCI controller must also programmed SWSTYLE THREE (BCR20, bits 7-0). PCnet-PCI controller burst write transfers command type Memory Write (type AD[1:0] will both ZERO during address phase indicating linear burst order. byte enable signals indicate byte lanes that have valid data.
PCnet-PCI controller will always perform single burst write transaction mastership period, where transaction defined address phase multiple data phases. PCnet-PCI controller supports zero wait state write cycles except with case descriptor write transfers. (See section "Descriptor Transfers" only exception.) asserts IRDY immediately after address phase same time starts sampling DEVSEL. FRAME deasserted when next last data phase completed.
Am79C970A
1-655
PRELIMINARY data phases take clock cycle each, which determined timing TRDY. example assumes that EXTREQ (BCR18, ONE, therefore, deasserted until next last data phase finished.
following figure shows typical burst write access. PCnet-PCI controller arbitrates bus, granted access, writes four 32-bit words (DWords) system memory then releases bus. this example, memory system extends data phase first access wait state. following three
FRAME
ADDR
DATA
DATA
DATA
DATA
C/BE
0111
IRDY
TRDY
DEVSEL
DEVSEL sampled
19436C-19
Figure Burst Write Transfer (EXTREQ
1-656
Am79C970A
Target Initiated Termination
When PCnet-PCI controller master, cycles produces terminated target three different ways. Disconnect With Data Transfer figure below shows disconnection which last data transfer occurs after target asserted STOP. STOP asserted clock start termination
sequence. Data still transferred during this cycle, since both IRDY TRDY asserted. PCnet-PCI controller terminates current transfer with deassertion FRAME clock IRDY clock later. finally releases clock PCnet-PCI controller will re-request after clock cycles, wants transfer more data. starting address transfer will address next untransferred data.
FRAME
ADDRi
DATA
DATA
ADDRi+8
C/BE
0111
0000
0111
IRDY
TRDY
DEVSEL STOP
DEVSEL sampled
19436C-20
Figure Disconnect With Data Transfer
Am79C970A
1-657
Disconnect Without Data Transfer
PRELIMINARY clock cycle later. finally releases clock PCnet-PCI controller will re-request after clock cycles retry last transfer. starting address transfer will address last untransferred data.
figure below shows target disconnect sequence during which data transferred. STOP asserted clock without TRDY being asserted same time. PCnet-PCI controller terminates access with deassertion FRAME clock IRDY
FRAME
ADDRi
DATA
ADDRi
C/BE
0111
0000
0111
IRDY
TRDY
DEVSEL STOP
DEVSEL sampled
19436C-21
Figure Disconnect Without Data Transfer
1-658
Am79C970A
PRELIMINARY Target Abort figure below shows target abort sequence. target asserts DEVSEL clock. then deasserts DEVSEL asserts STOP clock target target abort sequence indicate that cannot service data transfer that does want transaction retried. Additionally, PCnet-PCI controller cannot make assumption about success previous data transfers current transaction. PCnet-PCI controller terminates current transfer with deassertion FRAME clock IRDY clock cycle later. finally releases clock Since data integrity guaranteed, PCnet-PCI controller cannot recover from target abort event. PCnet-PCI controller will reset locations their STOP_RESET values.
configuration registers will cleared. on-going network transmission terminated orderly sequence. less than bits have been transmitted onto network, transmission will terminated immediately, generating runt packet. bits more have been transmitted, message will have current inverted appended next byte boundary guarantee error detected receiving station. RTABORT (PCI Status register, will indicate that PCnet-PCI controller received target abort. addition, SINT (CSR5, will ONE. When SINT set, INTA asserted enable SINTE (CSR5, ONE. This mechanism used inform driver system error. host read Status register determine exact cause interrupt.
FRAME
ADDR
DATA
C/BE
0111
0000
IRDY
TRDY DEVSEL
STOP
DEVSEL sampled
19436C-22
Figure Target Abort
Am79C970A
1-659
Master Initiated Termination
There three scenarios besides normal completion transaction where PCnet-PCI controller will terminate cycles produces bus. Preemption During Non-Burst Transaction When PCnet-PCI controller performs multiple non-burst transactions, keeps asserted until
assertion FRAME last transaction. When removed, PCnet-PCI controller will finish current transaction then release bus. last transaction, will remain asserted regain ownership soon possible.
FRAME
ADDR
DATA
C/BE
0111
IRDY
TRDY
DEVSEL
DEVSEL sampled
19436C-23
Figure Preemption During Non-Burst Transaction
1-660
Am79C970A
PRELIMINARY Preemption During Burst Transaction When PCnet-PCI controller operates burst mode, only performs single transaction mastership period, where transaction defined address phase multiple data phases. central arbiter remove time during transaction. PCnet-PCI controller will ignore deassertion continue with data transfers, long Latency Timer expired. When Latency Timer ZERO deasserted, PCnet-PCI controller will finish current data phase, deassert FRAME, finish last data phase release bus. EXTREQ (BCR18, cleared ZERO, will immediately assert regain ownership
soon possible. EXTREQ ONE, will stay asserted. When preemption occurs after counter counted down ZERO, PCnet-PCI controller will finish current data phase, deassert FRAME, finish last data phase release bus. Note that important host program Latency Timer according bandwidth requirement PCnet-PCI controller. host determine this bandwidth requirement reading MAX_LAT MIN_GNT registers. figure below assumes that Latency Timer counted down ZERO clock
FRAME
ADDR
DATA
DATA
DATA
DATA
DATA
C/BE
0111
IRDY
TRDY
DEVSEL
DEVSEL sampled
19436C-24
Figure Preemption During Burst Transaction
Am79C970A
1-661
Master Abort
PRELIMINARY inverted appended next byte boundary guarantee error detected receiving station. RMABORT Status register, will indicate that PCnet-PCI controller terminated transaction with master abort. addition, SINT (CSR5, will ONE. When SINT set, INTA asserted enable SINTE (CSR5, ONE. This mechanism used inform driver system error. host read Status register determine exact cause interrupt.
PCnet-PCI controller will terminate cycle with Master Abort sequence DEVSEL asserted within clocks after FRAME asserted. Master Abort treated fatal error PCnet-PCI controller. PCnet-PCI controller will reset locations their STOP_RESET values. configuration registers will cleared. on-going network transmission terminated orderly sequence. less than bits have been transmitted onto network, transmission will terminated immediately, generating runt packet. bits more have been transmitted, message will have current
FRAME
ADDR
DATA
C/BE
0111
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
19436C-25
Figure Master Abort
1-662
Am79C970A
Parity Error Response
During every data phase read operation, when target indicates that data valid asserting TRDY, PCnet-PCI controller samples AD[31:0], C/BE[3:0] lines data parity error. When detects data parity error, controller sets PERR (PCI Status register, ONE. When reporting that error enabled setting PERREN (PCI Command register, ONE, PCnet-PCI controller also drives PERR signal sets DATAPERR (PCI Status register, ONE.
assertion PERR follows corrupted data/byte enables clock cycles clock cycle. figure below shows transaction that parity error data phase. PCnet-PCI controller asserts PERR clock clock cycles after data valid. data clock checked parity, since read access only required valid clock after target asserted TRDY. PCnet-PCI controller then drives PERR high clock cycle, since PERR sustained tri-state signal.
FRAME
ADDR
DATA
C/BE
0111
PERR IRDY
TRDY
DEVSEL DEVSEL sampled
19436C-26
Figure Master Cycle Data Parity Error Response
During every data phase write operation, PCnet-PCI controller checks PERR input target reports parity error. When sees PERR input asserted, controller sets PERR (PCI Status register, ONE. When PERREN (PCI Command register, ONE, PCnet-PCI controller also sets DATAPERR (PCI Status register, ONE. Whenever PCnet-PCI controller current master data parity error occurs, SINT (CSR5, will ONE. When SINT set, INTA
serted enable SINTE (CSR5, ONE. This mechanism used inform driver system error. host read Status register determine exact cause interrupt. setting SINT data parity error dependent setting PERREN (PCI Command register, default, data parity error does affect state engine. PCnet-PCI controller treats data master transfers that have parity
Am79C970A
1-663
PRELIMINARY Transmit buffer read: (TMD1, current transmit descriptor. on-going network transmission terminated orderly sequence. Receive buffer write: (RMD1, last receive descriptor associated with frame. Terminating on-going network transmission orderly sequence means that less than bits have been transmitted onto network, transmission will terminated immediately, generating runt packet. bits more have been transmitted, message will have current inverted appended next byte boundary guarantee error detected receiving station. APERREN does affect reporting address parity errors data parity errors that occur when PCnet-PCI controller target transfer.
error nothing happened. network activity continues. Advanced Parity Error Handling cycles, PCnet-PCI controller provides second, more advanced level parity error handling. This mode enabled setting APERREN (BCR20, ONE. When APERREN ONE, bits (RMD1 TMD1, used indicate parity error data transfers receive transmit buffers. Note that since advanced parity error handling uses additional descriptor, SWSTYLE (BCR20, bits 7-0) must ONE, THREE program PCnet-PCI controller 32-bit software structures. PCnet-PCI controller will react following when data parity error occurs: Initialization block read: STOP (CSR0, causes STOP_RESET device. Descriptor ring read: on-going network activity terminated orderly sequence then STOP (CSR0, cause STOP_RESET device. Descriptor ring write: on-going network activity terminated orderly sequence then STOP (CSR0, cause STOP_RESET device.
1-664
Am79C970A
Initialization Block Transfers
During execution PCnet-PCI controller master initialization procedure, PCnet-PCI controller microcode will repeatedly request transfers from BIU. During each these initialization block transfers, will perform data transfer cycles reading DWord transfer then will relinquish bus. When SSIZE32 (BCR20, (i.e. initialization block organized 32-bit software structures), there DWords transfer during master initialization procedure, four mastership periods needed order complete initialization sequence. Note that last DWord transfer last mastership period initialization sequence accesses unneeded location. Data from this transfer discarded internally. When SSIZE32 cleared ZERO (i.e. initialization block
organized 16-bit software structures), then three mastership periods needed complete initialization sequence. PCnet-PCI controller supports transfer modes reading initialization block: non-burst burst mode; with burst mode being preferred mode when PCnet-PCI controller used application. When BREADE cleared ZERO (BCR18, initialization block read transfers will executed non-burst mode. There address phase every data phase. FRAME will dropped between transfers. phases within mastership period will have addresses ascending contiguous order.
FRAME
IADDi
DATA
IADDi+4
DATA
C/BE
0110
0000
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
19436C-27
Figure Initialization Block Read Non-Burst Mode
Am79C970A
1-665
PRELIMINARY mode. AD[1:0] will ZERO during address phase indicating linear burst order.
When BREADE (BCR18, initialization block read transfers will executed burst
FRAME IADDi 0110
DATA
DATA
C/BE
0000
IRDY TRDY DEVSEL DEVSEL sampled
19436C-28
Figure Initialization Block Read Burst Mode
1-666
Am79C970A
Table Descriptor Read Sequence
Descriptor Transfers
PCnet-PCI controller microcode will determine when descriptor access required. descriptor read will consist data transfers. descriptor write will consist data transfers. descriptor transfers within single mastership period will always same type (either read write). During descriptor read accesses, byte enable signals will indicate that byte lanes active. Should some bytes needed, then PCnet-PCI controller will internally discard extraneous information that gathered during such read. settings SWSTYLE (BCR20, bits 7-0) BREADE (BCR18, affect PCnet-PCI controller performs descriptor read operations. When SWSTYLE ZERO, TWO, descriptor read operations performed non-burst mode. setting BREADE effect this configuration. When SWSTYLE THREE, descriptor entries ordered allow burst transfers. PCnet-PCI controller will perform descriptor read operations burst mode, BREADE ONE.
SWSTYLE BREADE BCR18[6] BCR20[7:0]
Sequence Address XXXX XX00h Turn around cycle Data MD1[31:24], MD0[23:0] Idle Address XXXX XX04h Turn around cycle Data MD2[15:0], MD1[15:0] Address XXXX XX04h Turn around cycle Data MD1[31:0] Idle Address XXXX XX00h Turn around cycle Data MD0[31:0] Address XXXX XX04h Turn around cycle Data MD1[31:0] Idle Address XXXX XX08h Turn around cycle Data MD0[31:0] Address XXXX XX04h Turn around cycle Data MD1[31:0] Data MD0[31:0]
Am79C970A
1-667
FRAME
DATA
DATA
C/BE
0110
0000
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
19436C-29
Figure Descriptor Ring Read Non-Burst Mode
During descriptor write accesses, only byte lanes which need written enabled. buffer chaining used, accesses descriptors intermediate buffers consist only data transfer return ownership buffer system. When SWSTYLE (BCR20, bits 7-0) cleared ZERO (i.e. descriptor entries organized 16-bit software structures), descriptor access will write single byte. When SWSTYLE (BCR20, bits 7-0) ONE,
THREE (i.e. descriptor entries organized 32-bit software structures), descriptor access will write single word. single buffer transmit receive descriptors, well last buffer chain, writes descriptor consist data transfers. first writing DWord containing status information. second data transfer writing byte (SWSTYLE cleared ZERO) otherwise word containing additional status ownership (i.e. MD1[31]).
1-668
Am79C970A
FRAME
DATA
DATA
C/BE
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
19436C-30
Figure Descriptor Ring Read Burst Mode settings SWSTYLE (BCR20, bits 7-0) BWRITE (BCR18, affect PCnet-PCI controller performs descriptor write operations. When SWSTYLE ZERO, TWO, descriptor write operations performed non-burst mode. setting BWRITE effect this configuration. When SWSTYLE THREE, descriptor entries ordered allow burst transfers. PCnet-PCI controller will perform descriptor write operations burst mode, BWRITE ONE. write transaction descriptor ring entries only case where PCnet-PCI controller inserts wait state when being master. Every data phase non-burst burst mode extended clock cycle, during which IRDY deasserted. Table Descriptor Write Sequence
SWSTYLE BWRITE BCR20[7:0] BCR18[5] Sequence Address XXXX XX04h Data MD2[15:0], MD1[15:0] Idle Address XXXX XX00h Data MD1[31:24] Address XXXX XX08h Data MD2[31:0] Idle Address XXXX XX04h Data MD1[31:16] Address XXXX XX00h Data MD2[31:0] Idle Address XXXX XX04h Data MD1[31:16] Address XXXX XX00h Data MD2[31:0] Data MD1[31:16]
Am79C970A
1-669
PRELIMINARY enable signals second data transfer would 0111b, device programmed 16-bit software structures (SWSTYLE
Note that figure below assumes that PCnet-PCI controller programmed 32-bit software structures (SWSTYLE byte
FRAME
DATA
DATA
C/BE
0111
0000
0111
0011
IRDY
TRDY
DEVSEL
DEVSEL sampled
19436C-31
Figure Descriptor Ring Write Non-Burst Mode
1-670
Am79C970A
FRAME
DATA
DATA
C/BE
0110
0000
0011
IRDY
TRDY
DEVSEL
DEVSEL sampled
19436C-32
Figure Descriptor Ring Write Burst Mode
FIFO Transfers
PCnet-PCI controller microcode will determine when FIFO transfer required. This transfer mode will used transfers data from PCnet-PCI controller FIFOs. Once PCnet-PCI controller been granted mastership, will perform series consecutive transfer cycles before relinquishing bus. transfers within master cycle will either read write cycles, transfers will contiguous, ascending addresses. Both nonburst burst cycles used, with burst mode being preferred mode when device used application. Non-Burst FIFO Transfers default mode PCnet-PCI controller uses non-burst transfers read write data when accessing FIFOs. Each non-burst transfer will performed sequentially, with issue address, transfer corresponding data with appropriate output signals indicate selection active data bytes during transfer. FRAME will deasserted
after every address phase. number data transfer cycles contained within single mastership period general dependent programming DMAPLUS option (CSR4, 14). Several other factors will also affect length mastership period. possibilities follows: DMAPLUS cleared ZERO, maximum transfers will performed default. This default value changed writing Transfer Counter (CSR80). Note that DMAPLUS merely sets maximum value. minimum number transfers mastership period will determined following variables: settings FIFO watermarks (CSR80), conditions FIFOs, value Transfer Counter (CSR80), value Timer (CSR82), occurrence preemption that takes place during mastership period. DMAPLUS ONE, cycles will continue until transmit FIFO filled high threshold (read transfers) receive FIFO emptied 1-671
Am79C970A
PRELIMINARY Note that Latency Timer significant during non-burst transfers. Burst FIFO Transfers Bursting only performed PCnet-PCI controller BREADE and/or BWRITE bits BCR18 set. These bits individually enable/disable ability PCnet-PCI controller perform burst accesses during master read operations master write operations, respectively. burst transaction will start with address phase, followed more data phases. AD[1:0] will always ZERO during address phase indicating linear burst order. During FIFO read operations, byte lanes will always active. PCnet-PCI controller will internally discard unused bytes. During first last data phases FIFO burst write operation, more byte enable signals inactive. other data phases will always write complete DWord.
threshold (write transfers), until Activity Timer (CSR82) expired. exact number total transfer cycles mastership period dependent following variables: settings FIFO watermarks, conditions FIFOs, latency system PCnet-PCI controller's request, speed operation preemption events. Transfer Counter disabled when DMAPLUS ONE. TRDY response time memory device will also affect number transfers, since speed accesses will affect state FIFO. During accesses, FIFO filling emptying network end. example, receive operation, slower TRDY response will allow additional data accumulate inside FIFO. accesses slow enough, complete DWord become available before mastership period thereby increase number transfers that period. general rule that longer Grant latency, slower transfer operations, slower clock speed, higher transmit watermark lower receive watermark, longer mastership period will
1-672
Am79C970A
PRELIMINARY following figure shows beginning FIFO write with beginning buffer aligned DWord boundary. PCnet-PCI controller starts writing only three bytes during first data phase.
This operation aligns address other data transfers 32-bit boundary that PCnet-PCI controller continue bursting full DWords.
FRAME
DATA
DATA
DATA
C/BE
0111
0001
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
19436C-33
Figure FIFO Burst Write Start Unaligned Buffer
Am79C970A
1-673
PRELIMINARY even when there less then four bytes write. example, there only byte left current receive frame, PCnet-PCI controller will write full DWord, containing last byte receive frame least significant byte position (BSWP cleared ZERO, CSR3, content other three bytes undefined. message byte count receive descriptor always reflects exact length received frame.
receive buffer does DWord boundary, PCnet-PCI controller will perform non-DWord write last transfer buffer. following figure shows final three FIFO transfers receive buffer. Since there were only nine bytes space left receive buffer, PCnet-PCI controller burst three data phases. first data phases write full DWord, last only writes single byte. Note that PCnet-PCI controller will always perform DWord transfer long owns buffer space,
FRAME
DATA
DATA
DATA
C/BE
0111
0000
1110
IRDY
TRDY
DEVSEL
DEVSEL sampled
19436C-34
Figure FIFO Burst Write Unaligned Buffer
application PCnet-PCI controller should have length mastership period controlled only Latency Timer. Timer (CSR4, should remain default value ZERO that Activity Timer (CSR82) enabled. Transfer Counter (CSR80) should disabled setting DMAPLUS (CSR4, ONE. this mode, PCnet-PCI controller will continue transferring FIFO data until 1-674
transmit FIFO filled high threshold (read transfers) receive FIFO emptied threshold (write transfers), PCnet-PCI controller preempted, Latency Timer expired. host should values MIN_GNT MAX_LAT registers determine value Latency Timer.
Am79C970A
PRELIMINARY applications that don't Latency Timer that don't support preemption following rules apply limit time PCnet-PCI controller takes bus. DMAPLUS cleared ZERO, maximum transfers will performed default. This default value changed writing Transfer Counter (CSR80). Note that DMAPLUS merely sets maximum value. minimum number transfers mastership period will determined following variables: settings FIFO watermarks (CSR80), conditions FIFOs, value Transfer Counter (CSR80) value Activity Timer (CSR82). DMAPLUS ONE, bursting will continue until transmit FIFO filled high threshold (read transfers) receive FIFO emptied threshold (write transfers), until Activity Timer (CSR82) expired. exact number total transfer cycles mastership period dependent following variables: settings FIFO watermarks, conditions FIFOs, latency system PCnet-PCI controller's request, speed operation. Transfer Counter disabled when DMAPLUS ONE. TRDY response time memory device will also affect number transfers, since speed accesses will affect state FIFO. During accesses, FIFO filling emptying network end. example, receive operation, slower TRDY response will allow additional data accumulate inside FIFO. accesses slow enough, complete DWord become available before mastership period thereby increase number transfers that period. general rule that longer Grant latency, slower transfer operations, slower clock speed, higher transmit watermark lower receive watermark, longer total burst length will When FIFO burst operation preempted, PCnet-PCI controller will relinquish ownership until Latency Timer expires. Transfer Counter will freeze current value while PCnet-PCI controller waiting regain ownership. will continue counting when FIFO burst operation restarts. Activity Timer will reset starting value when PCnet-PCI controller regains ownership. Latency Timer cannot disabled. Systems that support preemption that want control duration PCnet-PCI controller mastership period with Transfer Counter Activity Timer must program Latency Timer with high value that does expire before other registers
BUFFER MANAGEMENT UNIT
Buffer Management Unit (BMU) microcoded state machine which implements initialization procedure manages descriptors buffers. buffer management unit operates half speed input.
Initialization
PCnet-PCI controller initialization includes reading initialization block memory obtain operating parameters. initialization block organized ways. When SSIZE32 (BCR20, default value ZERO, initialization block entries logically 16-bits wide backwards compatible with Am79C90 C-LANCE Am79C96x PCnet-ISA family. When SSIZE32 (BCR20, ONE, initialization block entries logically 32-bits wide. Note that PCnet-PCI controller always performs 32-bit transfers read initialization block entries. initialization block read when INIT CSR0 set. INIT should before concurrent with STRT insure correct operation. Once initialization block been completely read internal registers have been updated, IDON will CSR0, generating interrupt IENA set). PCnet-PCI controller obtains start address initialization block from contents CSR1 (least significant bits address) CSR2 (most significant bits address). host must write CSR1 CSR2 before setting INIT bit. initialization block contains user defined conditions PCnet-PCI controller operation, together with base addresses length information transmit receive descriptor rings. There alternate method initialize PCnet-PCI controller. Instead initialization initialization block memory, data written directly into appropriate registers. Either method combination used discretion programmer. Please refer Appendix details this alternate method.
Re-Initialization
transmitter receiver sections PCnet-PCI controller turned initialization block (DTX, DRX, CSR15, bits 1-0). states transmitter receiver monitored host through CSR0 (RXON, TXON bits). PCnet-PCI controller should re-initialized transmitter and/or receiver were turned during original initialization, subsequently required activate them either section shut detection error condition (MERR, UFLO, BUFF error). Re-initialization done initialization block setting STOP CSR0, followed writing 1-675
Am79C970A
PRELIMINARY (SWSTYLE, BCR20, bits 7-0) affects descriptor rings their entries arranged. When SWSTYLE default value ZERO, descriptor rings backwards compatible with Am79C90 C-LANCE Am79C96x PCnet-ISA family. descriptor ring base addresses must aligned 8-byte boundary maximum ring entries allowed when ring length through TLEN RLEN fields initialization block. Each ring entry contains subset three 32-bit transmit receive message descriptors (TMD, RMD) that organized four 16-bit structures (SSIZE (BCR20, ZERO). Note that even though PCnet-PCI controller treats descriptor entries 16-bit structures, will always perform 32-bit transfers access descriptor entries. value CSR2, bits 15-8 used upper 8-bits memory addresses during master transfers. When SWSTYLE ONE, THREE, descriptor ring base addresses must aligned 16-byte boundary maximum ring entries allowed when ring length through TLEN RLEN fields initialization block. Each ring entry organized three 32-bit message descriptors (SSIZE32 (BCR20, ONE). fourth DWord reserved. When SWSTYLE THREE, order message descriptors optimized allow read write access burst mode. software style, ring lengths beyond this range 65535) writing transmit receive ring length registers (CSR76, CSR78) directly. Each ring entry contains following information: address actual message data buffer user host memory length message buffer Status information indicating condition buffer permit queuing de-queuing message buffers, ownership each buffer allocated either PCnet-PCI controller host. within descriptor status information, either RMD, used this purpose. When ONE, signifies that PCnet-PCI controller currently ownership this ring descriptor associated buffer. Only owner permitted relinquish ownership write field descriptor entry. device that current owner descriptor entry cannot assume ownership change field entry. device may, however, read from descriptor that does currently own. Software should always read descriptor entries sequential order. When software finds that current descriptor owned PCnet-PCI
CSR15, then setting START CSR0. Note that this form restart will perform same PCnet-PCI controller CLANCE. particular, upon restart, PCnet-PCI controller reloads transmit receive descriptor pointers with their respective base addresses. This means that software must clear descriptor bits reset descriptor ring pointers before restarting PCnet-PCI controller. reload descriptor base addresses performed CLANCE only after initialization, restart CLANCE without initialization leaves CLANCE pointing same descriptor locations before restart.
Suspend
PCnet-PCI controller offers suspend mode that allows easy updating registers without going through full re-initialization device. suspend mode also allows stopping device with orderly termination network activity. host requests PCnet-PCI controller enter suspend mode setting SPND (CSR5, ONE. When host sets SPND ONE, PCnet-PCI controller first finishes on-going transmit activity updates corresponding transmit descriptor entries. then finishes on-going receive activity updates corresponding receive descriptor entries. then sets read-version SPND enters suspend mode. host must poll SPND until reads back determine that PCnet-PCI controller entered suspend mode. suspend mode, registers accessible. long PCnet-PCI controller reset while suspend mode H_RESET, S_RESET setting STOP bit), re-initialization device required after device comes suspend mode. When host clears SPND, PCnet-PCI controller will leave suspend mode will continue transmit receive descriptor ring locations, where left off.
Buffer Management
Buffer management accomplished through message descriptor entries organized ring structures memory. There descriptor rings, transmit receive. Each descriptor describes single buffer. frame occupy more buffers. multiple buffers used, this referred buffer chaining.
Descriptor Rings
Each descriptor ring must occupy contiguous area memory. During initialization user-defined base address transmit receive descriptor rings, well number entries contained descriptor rings programming software style
1-676
Am79C970A
PRELIMINARY controller, then software must read ahead next descriptor. software should wait descriptor does until PCnet-PCI controller sets ZERO release ownership software. (When LAPPEN (CSR3, ONE, this rule modified. LAPPEN description.) initialization, PCnet-PCI controller reads base address both transmit receive descriptor rings into CSRs PCnet-PCI controller during subsequent operations.
following figure illustrates relationship between initialization base address, initialization block, receive transmit descriptor ring base addresses, receive transmit descriptors receive transmit data buffers, when SSIZE32 cleared ZERO. Note that value CSR2, bits 15-8 used upper 8-bits memory addresses during master transfers.
Descriptor Ring
CSR2 IADR[31:16] CSR1 IADR[15:0] RMD0 RMD0 desc. start desc.
Initialization Block PADR[15:0] PADR[31:16] PADR[47:32] LADRF[15:0] LADRF[31:16] LADRF[47:32] LADRF[63:48] RDRA[15:0] RDRA[23:16] TDRA[15:0] TDRA[23:16]
Buffers
Data Buffer
Data Buffer
Data Buffer
Descriptor Ring
desc. start desc.
Buffers
Data Buffer
Data Buffer
Data Buffer
19436C-35
Figure 16-Bit Software Model
Am79C970A
1-677
PRELIMINARY addresses, receive transmit descriptors receive transmit data buffers, when SSIZE32 ONE.
following figure illustrates relationship between initialization base address, initialization block, receive transmit descriptor ring base
CSR2
IADR[31:16]
CSR1
IADR[15:0]
desc. start
Descriptor Ring
desc. start
Initialization Block
MODE PADR[31:0] PADR[47:32] LADRF[31:0] LADRF[63:32] RDRA[31:0] TDRA[31:0]
Buff
Data Buffer
Data Buffer
Data Buffer
desc. start
Descriptor Ring
desc. start
TMD0
TMD0 TMD1 TMD2 TMD3
Buff
Data Buffer
Data Buffer
Data Buffer
19436C-36
Figure 32-bit Software Model
Polling
there network channel activity there pre- post-receive pre- post-transmit activity being performed PCnet-PCI controller, then PCnet-PCI controller will periodically poll current receive transmit descriptor entries order ascertain their ownership. DPOLL CSR4 set, then transmit polling function disabled. typical polling operation consists following: PCnet-PCI controller will current receive descriptor address stored internally vector
appropriate Receive Descriptor Table Entry (RDTE). will then current transmit descriptor address (stored internally) vector appropriate Transmit Descriptor Table Entry (TDTE). accesses will made following order: RMD1, then RMD0 current RDTE during arbitration, after that, TMD1, then TMD0 current TDTE during second arbitration. information collected during polling activity will stored internally appropriate CSRs, set. (i.e. CSR18, CSR19, CSR20, CSR21, CSR40, CSR42, CSR50, CSR52).
1-678
Am79C970A
PRELIMINARY typical receive poll following conditions: product
PCnet-PCI controller does current poll time elapsed RXON (CSR0, PCnet-PCI controller does next RDTE there more than receive descriptor ring poll time elapsed RXON RXON cleared ZERO, PCnet-PCI controller will never poll RDTE locations. order avoid missing frames system should have least RDTE available. minimize poll activity RDTEs should available. this case, poll operation will only consist check status current TDTE. typical transmit poll product following conditions: PCnet-PCI controller does current TDTE DPOLL (CSR4, TXON (CSR0, poll time elapsed, PCnet-PCI controller does current TDTE DPOLL TXON frame just been received, PCnet-PCI controller does current TDTE DPOLL TXON frame just been transmitted. Setting TDMD CSR0 will cause microcode controller exit poll counting code immediately perform polling operation. RDTE ownership been previously established, then RDTE poll will performed ahead TDTE poll. microcode executing poll counting code when TDMD set, then demanded poll TDTE will delayed until microcode returns poll counting code. user change poll time value from default 65,536 clock periods modifying value Polling Interval register (CSR47).
chain buffers.) After resetting this descriptor, PCnet-PCI controller will again immediately request order access next TDTE location ring. buffer length will cleared. C-LANCE buffer length interpreted 4096-byte buffer. zero length buffers acceptable long last buffer chain (STP set, then microcode control proceeds routine that will enable transmit data transfers FIFO. PCnet-PCI controller will look ahead next transmit descriptor after performed least transmit data transfer from first buffer. PCnet-PCI controller does next TDTE (i.e. second TDTE this frame), will complete transmission current buffer update status current (first) TDTE with BUFF UFLO bits being set. DXSUFLO (CSR3, cleared ZERO, underflow error will cause transmitter disabled (CSR0, TXON PCnet-PCI controller will have re-initialized restore transmit function. Setting DXSUFLO enables PCnet-PCI controller gracefully recover from underflow error. device will scan transmit descriptor ring until finds either start frame TDTE does own. avoid underflow situation chained buffer transmission, system should always transmit chain descriptor bits reverse order. PCnet-PCI controller does second TDTE chain, will gradually empty contents first buffer bytes needed transmit operation), perform single-cycle transfer update status first descriptor (clear TMD1), then perform data access second buffer chain before executing another lookahead operation. (i.e. lookahead third descriptor.) imperative that host system never reads TDTE bits order. PCnet-PCI controller normally clears bits strict FIFO order. However, PCnet-PCI controller queue frames transmit FIFO. When second frame uses buffer chaining, PCnet-PCI controller might return ownership normal FIFO order. last (and maybe only) buffer first frame cleared until transmission completed. During transmission PCnet-PCI controller will read buffers next frame clear their bits last one. first intermediate buffers second frame have their bits cleared before
Transmit Descriptor Table Entry
after Transmit Descriptor Table Entry (TDTE) access, PCnet-PCI controller finds that that TDTE set, PCnet-PCI controller resumes poll time count re-examines same TDTE next expiration poll time count. TDTE set, Start Packet (STP) set, PCnet-PCI controller will immediately request order clear this descriptor. (This condition would normally found following late collision (LCOL) retry (RTRY) error that occurred middle transmit frame
Am79C970A
1-679
PRELIMINARY PCnet-PCI controller retains ownership current next RDTE. When receive activity present channel, PCnet-PCI controller waits complete address message arrive. then decides whether accept reject frame based active addressing schemes. frame accepted PCnet-PCI controller checks current receive buffer status register CRST (CSR41) determine ownership current buffer. ownership lacking, PCnet-PCI controller will immediately perform final poll current RDTE. ownership still denied, PCnet-PCI controller buffer which store incoming message. MISS will CSR0 Missed Frame Counter (CSR112) will incremented. interrupt will generated IENA (CSR0, MISSM (CSR3, cleared ZERO. Another poll current RDTE will occur until frame finished. PCnet-PCI controller sees that last poll (either normal poll, final effort described above paragraph) current RDTE shows valid ownership, proceeds poll next RDTE. Following this poll, regardless outcome this poll, transfers receive data from FIFO begin. Regardless ownership second receive descriptor, PCnet-PCI controller will continue perform receive data transfers first buffer. frame length exceeds length first buffer, PCnet-PCI controller does second buffer, ownership current descriptor will passed back system writing ZERO RMD1 status will written indicating buffer (BUFF possibly overflow (OFLO errors. frame length exceeds length first (current) buffer, PCnet-PCI controller does second (next) buffer, ownership will passed back system writing ZERO RMD1 when first buffer full. only modified descriptor. Receive data transfers second buffer occur before PCnet-PCI controller proceeds look ahead ownership third buffer. Such action will depend upon state FIFO when been updated first descriptor. case, lookahead will performed third buffer information gathered will stored chip, regardless state ownership bit. This activity continues until PCnet-PCI controller recognizes completion frame (the last byte this receive message been removed from FIFO). PCnet-PCI controller will subsequently
PCnet-PCI controller returns ownership last buffer first frame. error occurs transmission before bytes current buffer have been transferred, transmit status current buffer will immediately updated. buffer does contain packet, PCnet-PCI controller will skip over rest frame which experienced error. This done returning polling microcode where PCnet-PCI controller will clear descriptors with continue like manner until descriptor with more transmit frames ring) (the first buffer frame) reached. transmit operation, whether successful with errors, immediately following completion descriptor updates, PCnet-PCI controller will always perform another polling operation. described earlier, this polling operation will begin with check current RDTE, unless PCnet-PCI controller already owns that descriptor. Then PCnet-PCI controller will poll next TDTE. transmit descriptor ZERO value, PCnet-PCI controller will resume incrementing poll time counter. transmit descriptor value ONE, PCnet-PCI controller will begin filling FIFO with transmit data initiate transmission. This end-ofoperation poll coupled with TDTE lookahead operation allows PCnet-PCI controller avoid inserting poll time counts between successive transmit frames. default, whenever PCnet-PCI controller completes transmit frame (either with without error) writes statu
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