PSoC Designer Version Service Pack Release Date: October 2006 Tha

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PSoC Designer Version Service Pack Release Date: October 2006 Tha

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PSoC Designer Version Service Pack
Release Date: October 2006 Thank your interest PSoC DesignerVersion Service Pack information this document lists installation requirements describes software updates changes.
System Requirements Recommendations System Requirement PSoC Designer Version Windows® 2000, (SP1) Microsoft Internet Explorer (SP1) Adobe Reader (For Viewing .PDF Documentation) Processor Speed Free Hard Drive Space Screen Resolution Port, preferably Open Host Controller Universal CD-ROM Drive Parallel Port (Supported, Recommended) Minimum Recommended
1024x768
1280x1024
Updates Check latest downloads software documentation. NOTE: Service Packs cannot separately uninstalled removed This service pack requires PSoC Designer installed, once service pack installed, only remove uninstall PSoC Designer v4.3 later re-install PSoC Designer v4.3.
Service Pack User Module datasheets include links example projects Cypress site. Currently, Cypress developing testing over PSoC Designer user module example projects PSoC Express driver-based example projects. will updated incrementally through December 2006 with these example projects. example project looking today, feel free contact Applications Support phone number listed below, create customer support case. Applications group able provide early BETA version prioritize completion your requested design example. 1.800.669.0557 ext. 4814 (US, Canada) +1.425.787.4814 (International)
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Defects Repaired Service Pack file flashblock.asm updated provide support CY8C20x34, CY8C21x34 CY8C21x23 devices below CapSense wizard updated correctly generate firmware when more buttons selected. user module "update baseline" function updated correctly generate baselines multiple sensor groups. user module updated support maximum sensors CY8C21x34 CY8C24x94). extended temperature devices CY8C24x23-12PVXE were updated boot time frequency 12MHz. possible condition that PSoC Designer into infinite loop when updating design using wizard corrected. user module updated shadow registers that support large memory model (LMM). user module function "GetCentroid" updated return zero there active sensors slider diplexed.
PSoC Designer Version Release Notes (provided convenience) Attention: CapSense Project Designers This release includes significant updates User Module, with numerous improvements, including extension user module CY8C24x94 family PSoC devices. Projects generated with PSoC Designer will require "Update" function when first opened. Note Slider Projects: Projects incorporating slider will additionally require wizard re-run, which happens right-mouse clicking icon choosing "CSR Wizard." data needs changed re-entered, just select "OK" allow tables rebuilt project update complete.
Inclusion PSoC Designer service packs (SP1, SP2, SP3). User Module support added CY8C24x94 family. Added support CY8C24894 device. efficient math library routines that reduce Flash size improve performance. math library documented PSoC Designer: Libraries User Guide. PSoC Power Estimator tool added CY8C24x94 family. Improved Filter Design Wizard User Modules.
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Design Rule Check (DRC) that block power when block placed. Design Rule Checks (DRCs) enabled default. PSoC Designer used from non-administrative account. Extensibility support enables future service packs extension packs incrementally installed removed. Defects Repaired Corrected code generation error that caused I2CCFG register reset when I2CHW EZI2C User Module unplaced deleted. Corrected code generation errors with dynamic reconfiguration that could leave register bank setting Bank instead Bank Corrected code generation errors that prevented generation psocgpioint.h psocgpioint.inc when names were entered user GPIO interrupt sources were enabled. Corrected code generation PRT5IE register CY8C24x94 CY7C64215 devices. Updated CY7C63300/m8c.h, CY7C63800/m8c.h, CY7C63900/m8c.h. defines TCAPINTE TCAPINTS have been given same name TMRCR. Updated boot.tpl CY7C603xx devices remove conditional code since these devices operate 2.4-3.6V. Updated boot.tpl CY8C29xxx devices decimator into full algorithm mode start boot sequence. This saves power consumption decimator used application. Updated boot.tpl CY8C24x94 ACB00CR0/ACB01CR0 preferred default state. Previously, entry character allowed grid names. Some special characters caused compiler/assembler errors. Those characters restricted. Compiler License Agreement Dialog works properly most non-English Languages. Updates Enhancements User Modules Data sheets most user modules updated correct documentation errors clarify user module characteristics. Several defects repaired USBFS: USBFS passed (USB Spec.) Chapter Chapter testing. USBFS: Updated ReadOUTEndpt() function change Clock when extracting data from Endpoint buffers. USBFS: Data sheet updated with information about user supposed vendor-specific device requests. USBFS: Data toggle handling corrected. USBFS: Corrected failure Vendor Specific Control Read length response. AMPINV: Changed default RTapMux values R15_1 gain R14_2 gain.
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I2CHW: Fixed file definition I2C_TX. I2CM: Prevent assignment same pin.
User Modules Details following user modules available PSoC Designer Device Editor User Module Selection View. User Modules supporting PSoC devices: Segment (LED7SEG) Light Emitting Diode (LED)
Updates That Affect Previous Projects Floating-Point Math floating-point implementation completely rewritten. Except feature, version implements IEEE-754 standard floating-point numbers (single precision). omission that denormalized numbers truncated `0'. Because implementation adhere IEEE standard, calculations using implementation necessarily binary identical calculations using implementation. User Module CY8C21x34 This updated; Projects generated with version will require "Update" function when first opened. Projects incorporating slider will additionally require wizard re-run, which happens right-mouse clicking icon choosing "CSR Wizard." data needs changed re-entered, just select "OK" allow tables rebuilt project update complete. Analog Comparator Update Before PSoC Designer when using dynamic reconfiguration, analog comparators stayed connected from configuration configuration. manual overwrite required remove connection when moving from configuration another. PSoC Designer clears analog comparator connections between configurations. Analog Comparators Disconnected Projects used analog comparators projects created before PSoC Designer 4.3, aware that PSoC Designer disconnects connected analog comparators configurations except base configuration. Check comparator connections configurations reconnect comparators that became disconnected when upgrading PSoC Designer 4.3. Protect Project from Unintentional Alteration version 4.3, setting been added Project Settings Device Editor lock-down device configuration prevent device user module updates. This check labeled "Lock device configuration." manually choose this automatically select "Cancel" "Revert" from "Project Update" dialog box. Project Cloning Causes "Project Update" Dialog Appear
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best thing choose "Update." choose "Cancel" "Revert," "Lock device configuration" check set. regenerate configuration, must Project Settings Device Editor uncheck "Lock device configuration." Unlocking Project Allow Regeneration "Project Update" dialog comes choose "Cancel," project setting will occur that prevents "Generate Application" from executing (the selection grayed-out). reenable "Generate Application," Project Settings Device Editor uncheck "Lock device configuration" check box.
PSoC Designer Project Migration Compatibility dialog boxes encountered when opening project from older release: first "Old Version" dialog box. notifies user about necessity update current project order comply with current version PSoC Designer gives option perform project update immediately postpone until later. changes made boot.tpl, such added jumps interrupt vector table, must migrated boot.tpl. second dialog "Outdated User Modules" dialog box. This dialog provides users with list outdated User Modules. update process happens automatically during source generation. When source generated, files added project file moved backup directory. interrupt files contain start markers user code. User code placed within user code markers automatically carried into file. migration, make sure that user code between user code markers following first "Generate Application" invocation after upgrading 4.2. need modify source code manually after first application generation avoid compilation errors. must generate source before closing updated project dialog order update take effect. source generated, files remain project out-of-date status lost. updated file generated your project time. Right click file source tree select Remove from Project. When source generated, file added project file moved backup directory. When migrating projects CY8C29x66 using cloning, compiler linker default using small memory model (SMM). Project Settings, Compiler "Enable paging" large memory model (LMM). When migrating projects CY8C29x66 using assembly language: Additional code required manage pages. small number User Module function calls need changing. AN2218 PSoC Large Memory Model Programming details. Reference Application Note AN2218 PSoC Large Memory Model Programming under .\Program Files\Cypress MicroSystems\PSoC Designer\Documentation http://www.cypress.com guidance. Projects from previous PSoC Designer releases have projectname_globalparams.inc projectnameapi.h under Library Source folder. These files were replaced with globalparams.inc psocapi.h manually removed right clicking file icon selecting Remove from Project.
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Documentation User guides documents located \Documentation subdirectory PSoC Designer installation directory. default location C:\Program Files\Cypress MicroSystems\PSoC Designer\Documentation. This directory accessed within PSoC Designer under Help Documentation. documents .PDF files require Adobe Reader viewing. Documents include: PSoC Designer: Integrated Development Environment User Guide PSoC Designer: Assembly Language User Guide PSoC Designer: Language Compiler User Guide PSoC Designer: ICE-4000 Adapter Installation Guide PSoC Designer: Connection Troubleshooting Guide PSoC Designer: PSoC Programmer User Guide PSoC Designer: Libraries User Guide CY8C29x66 PSoC Mixed-Signal Array Data Sheet CY8C27x43 PSoC Mixed-Signal Array Data Sheet CY8C25-26xxx PSoC Device Family Data Sheet CY8C24x94 PSoC Mixed-Signal Array Data Sheet CY8C24x23A PSoC Mixed-Signal Array Data Sheet CY8C24x23 PSoC Mixed-Signal Array Data Sheet CY8C22x13 PSoC Mixed-Signal Array Data Sheet CY8C21x34 PSoC Mixed-Signal Array Data Sheet CY8C21x23 PSoC Mixed-Signal Array Data Sheet CY8C26xxx_Master.pdf Interface Diagram/Worksheet PSoC Technical Reference Manual (TRM) Large Memory Programming Migrating Large Memory Model PSoC Devices PSoC Compatibility Guide PSoC Device Selector Guide AN2209 Supporting documents PSoC Designer's public-domain functionality, such "Find Files" text search (grep.pdf) build utility (make.pdf sed.pdf), located .\Program Files\Cypress MicroSystems\PSoC Documents. Tele-Training recommend that first time users attend Module Introductory Module TeleTraining program. following Tele-Training modules available: PSoC Pre-Recorded Video Module Introductory Module PSoC Pre-Recorded Video Module Getting Started Designing PSoC Pre-Recorded Video Module Getting Started Debugging PSoC Pre-Recorded Video Module Dynamic Re-configuration PSoC Module Advanced Analog Design PSoC Pre-Recorded Video Module Introduction PSoC Express PSoC Pre-Recorded Video Module CY3210-ExpressDK PSoC Express Development PSoC Pre-Recorded Video Module Hands PSoC Express Capacitive Touch Sensing with PSoC
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Jazz-up your user interface with PSoC-enabled Capacitive Touch Sensing details. Example Projects instructive user view test Example Projects. They located three directories product family: .\Program Files\Cypress MicroSystems\PSoC Designer\Examples\CY8C24, .\CY8C27, .\CY8C29, respectively. (This default installation path PSoC Designer.) Example projects include: Examples CY8C24x23A, CY8C27x43, CY8C29x66 parts: ASM_Example_ADC_UART_LCD ASM_Example_Blink_LED ASM_Example_DAC_ADC ASM_Example_Dynamic_PWM_PRS ASM_Example_LED_Logic C_Example_ADC_UART_LCD
Installation Issues Considerations have trouble connecting ICE-4000 Adapter ICE-Cube, Debugger Subsystem Debugger Error Messages PSoC Designer Help System PSoC Designer: Troubleshooting Guide more details. problems persist, contact Cypress MicroSystems. want assist with connection. information PSoC Designer Help System PSoC Designer: Troubleshooting Guide sufficient resolve issues, please following resources: TightLink Email Support System enter support request this system with guaranteed response-time four hours: Support Forums View participate discussion threads about wide variety PSoC device topics: http://www.cypress.com/forums/. Open Host Controller Interface (OHCI) allows communication with operate faster than Universal Host Controller Interface (UHCI). This improves download debugging speed. find which interface using, "Device Manager," look under "Universal Serial controllers" heading. these three Host Controllers: Universal, Open, Enhanced. Based port which connected, Adapter will default either Universal Open. Typically, Intel motherboards have UHCI. Most hubs OHCI.
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Note: recommended connection method; following section maintained completeness. Parallel Port Considerations Proper installation PSoC Designer Windows NT/2000/XP requires user have local Administrator permission. Windows Active Desktop supported. PSoC Designer function correctly Windows Active Desktop enabled. Windows compatibility mode causes problems PSoC Designer's debugging with parallel port. enable compatibility mode. Upgrading from Windows 95/98/Me Windows NT/2000/XP requires uninstalling PSoC Designer before upgrade reinstalling PSoC Designer after Windows upgrade. this done, PSoC Designer's parallel port drivers updated match operating system. Windows logging cause problems with parallel port connections ICE. This fixed following these steps: Open Start Menu Select Settings Open Control Panel Open Administrative Tools Open Local Security Policy (may available Windows Home Edition) Open Local Policies Open Security Options Disable "Strengthen default permissions internal system objects" setting Reboot PSoC ICE-4000 provides significant debugging functionality that requires full twoway communication over ICE-4000 operate. There several steps connection process, including both setting hardware, making communications connection software. Making software connection often requires changes BIOS settings port. Some recent laptops support Bidirectional modes BIOS needed full two-way communication over ICE4000. relatively easy method that bypasses need changing BIOS settings install parallel port card. This added benefit providing dedicated port without potential conflicts with other applications printers user have their computer. PSoC Designer: Troubleshooting Guide details parallel port cards both desktops laptops that were tested compliance with ICE-4000. mode operation parallel port affected when some laptops return from sleep. Often, connection cannot resumed. Restarting system rectifies this situation. Hardware Note: ICE-4000 only supports CY8C24x23 CY8C27x43 families. older in-circuit emulator ICE-4000 does support PSoC families. recommend that purchase newer ICE-Cube (which sold called CY3215DK) best results.
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Rev. Pods required emulation CY8C22x13, CY8C24x23, CY8C27x43, CY8C29x66 parts. Rev. Pods, later, required CY8C25xxx/26xxx family devices. ICECube in-circuit emulator does support CY8C25/26xxx family. ICE-4000 continues support this family PSoC devices. YProgrammer boards required programming CY8C22x13, CY8C24x23, CY8C24x23A, CY8C25xxx/26xxx, CY8C27x43, CY8C29x66 family devices using ICE-4000. ICE-Cube, with attached ISSP cable, enables programming without YProgrammer.
Device Editor Subsystem Notes Errata Device Editor, general, allows settings combinations that supported underlying hardware. some cases, this means mutually-exclusive settings (such selections output bus) allowed Device Editor. Whenever suitable, mutually-exclusive settings prevented Device Editor, hardware support them, user's program make these settings. Device Editor does prevent choosing that require more pins than device that selected. This design allows design migrated between available parts long internal resources support Cloning from PSoC device PSoC device which number analog resources reduced (i.e., From CY8C24xxx CY8C22xxx) stop placement more analog user modules. necessary delete analog user module then same user module back into project. Clock global resource setting PSoC devices that have SLIMO feature displays Clock frequency "SysClk/N" where 256). customers updating CY8C29x66 CY8C24x23 PSoC devices, Clock setting defaults "SysClk/8" MHz) when opening project first time this release. This because change. Changing value then saving project restores correct Clock global resource. Acer TravelMate Notebook (with MOBILITY RADEON 9000 Graphics Adapter) cause schematic area Interconnect View blank when Navigation Help window appears. Closing Navigation Help window causes Interconnect View window divider move. Debugger Subsystem/ICE Errata Debugger does detect Flash size limits during emulation. parts that have less than Flash, exercise caution that designs work within memory limits. complex sequential breakpoints offered Events feature Debugger subsystem provide means detecting stack memory overflows during development. Analog register display scrambled when Successive Approximation Register (SAR) operation enabled. Enabling operation (i.e., count Analog Synchronization Register (ASY_CR) scrambles Debugger register Bank analog register displays. Enabling stalls until analog register data ready, does stall on-chip Debugger interface used PSoC Designer. result, analog register contents displayed PSoC Designer incorrect. programs that read registers still correct data. This only affects analog block registers.
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some machines, unplugging from result inability reconnect. this occurs, power cycling required. Adding Flash watch variable will default address. correct this, reselect FLASH memory space Flash Watch Variable's property dialog box. cannot watch variables with values greater than 0x7FFFFFFF. Debugger program counter will three setps vbehind program counter pipelining.
Debugger Subsystem/ICE Notes Debugger switches operation when halted. status shows user-selected speed while halted on-chip digital PSoC blocks running with SysClk MHz. This affect external hardware. System clock-jitter target circuit board cause emulation fail when mode enabled. failure symptom usually Invalid Memory Reference. Debugger cannot halt immediately after instruction that puts into sleep mode. This means that cannot step over sleep, breakpoint immediately after sleep, halt event point immediately after sleep. Placing breakpoint further away from sleep instruction recommended. Clicking Halt icon exit sleep okay, assuming that sleep interrupt been enabled. sleep interrupt been enabled part goes into sleep, disconnects when halt executed. Occasionally, with Adapter, disconnects when debugging with sleep. breakpoint instruction immediately following SSC_Action macro does halt debugger. breakpoint halts second instruction after SSC_Action macro. When CY8C29xxx/27xxx/24xxx/22xxx parts debugging, enables sysclk (doubler). False event triggers occur. Setting event break Instruction Register (IR) with (opcode 0x40) triggers event following "go" from reset. Setting event break when Program Counter (PC) above user code causes halt occur following "go" from reset.
Compiler/Assembler/Build System Errata Code compression settings (found Project Settings Compiler tab) currently compatible with dynamic reconfiguration. certain corner case input values (close zero infinity), following functions found math.h known return incorrect results: sinh(), cosh(), tanh(), atan2(). Internal references prevent elimination from removing certain parts functions that need removal.
Compiler/Assembler/Build System Notes "TOP" area reserved boot code (boot.asm) special linker implications. create code within "TOP" area declared another source file, other than boot.asm.
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total size arrays structures limited bytes, even large memory model. code compressor makes debugging very difficult when more blocks code combined into single "subroutine." problem that debugger does know which chunk associated source code display. This partially mitigated using step assembly necessary when possible, turning code compression off.
Library Notes low-level arithmetic library routines provided. They called from well assembly language. routines faster more compact than previous implementation. routines documented PSoC Designer: Libraries User Guide.
User Module Errata ADCINCVR iGetData result data skewing interrupt occurs between handling. work around flag check mismatched data between MSB. assistance http://www.cypress.com choose "Technical Support" from left side menu, contact Application Team 425.787.4814.
Silicon Errata most up-to-date versions silicon errata available site following link navigating Errata Update upper-right corner PSoC Mixed-Signal Array http://www.cypress.com/psoc.
Cypress Semiconductor 2700 162nd Street Building Lynnwood, 98087 Phone: 425.787.4400 Fax: 425.787.4641 Application Support Hotline: 425.787.4814 http://www.cypress.com/
Copyright 2006 Cypress Semiconductor Corporation. rights reserved. PSoC registered trademark Cypress Semiconductor Corp. "Programmable System-on-Chip," PSoC Designer, PSoC Express trademarks Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property their respective owners. information contained herein subject change without notice. Made U.S.A.
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PSoC Designer Version Service Pack Release Date: October 2006 Tha

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