LC2MOS Dual 12-Bit Serial DACPORT AD7249 AD7249 REFOUT

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LC2MOS Dual 12-Bit Serial DACPORT AD7249 AD7249 REFOUT

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FEATURES 12-Bit CMOS Channels with On-Chip Voltage Reference Output Amplifiers Three Selectable Output Ranges Channel Serial Interface Update Rate Small Size: 16-Pin SOIC Power Dissipation APPLICATIONS Process Control Industrial Automation Digital Signal Processing Systems Input/Output Ports
LC2MOS Dual 12-Bit Serial DACPORT AD7249
AD7249
REFOUT
ROFSA
REFIN
12-BIT
VOUTA
ROFSB AGND 12-BIT DGND INPUT SHIFT REGISTER VOUTB
GENERAL DESCRIPTION
AD7249 DACPORT® contains pair 12-bit, voltageoutput, digital-to-analog converters with output amplifiers Zener voltage reference monolithic CMOS chip. external trims required achieve full specified performance. output amplifiers capable developing across load. output voltage ranges with single supply operation while additional bipolar output range available with dual supplies. ranges selected using internal gain resistor. Interfacing AD7249 serial, minimizing count allowing small package size. Standard control signals allow interfacing most processors microcontrollers. data stream consists bits, DB15 DB13 don't care bits, 13th (DB12) used channel select remaining bits (DB11 DB0) contain data update DAC. 16-bit data word clocked into input register each falling SCLK edge. data format natural binary both unipolar ranges, while either offset binary twos complement format selected bipolar range. function provided which sets output both unipolar ranges twos complement bipolar range, while with offset binary data format, output -REFIN. This function useful power-on reset allows outputs known voltage level.
DACPORT registered trademark Analog Devices, Inc.
SCLK
SDIN
SYNC BIN/COMP
LDAC
AD7249 features serial interface which allows easy connection both microcomputers 16-bit digital signal processors with serial ports. serial data applied rates allowing update rate kHz. AD7249 fabricated linear compatible CMOS (LC2MOS), advanced, mixed technology process. packaged 16-pin 16-pin SOIC packages.
PRODUCT HIGHLIGHTS
complete 12-bit DACPORTs AD7249 contains complete voltage output, 12-bit DACs both 16-lead SOIC packages. Single dual supply operation Minimum 3-wire interface most processors update rate-125
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7249-SPECIFICATIONS AGND DGND REFIN AGND. specifications unless otherwise noted.)
Parameter STATIC PERFORMANCE Resolution Relative Accuracy3 Differential Nonlinearity3 Unipolar Offset Error3 Bipolar Zero Error3 Full-Scale Error3, Full-Scale Temperature Coefficient REFERENCE OUTPUT REFOUT Reference Temperature Coefficient Reference Load Change (VREFOUT REFERENCE INPUT Reference Input Range, REFIN Input Current DIGITAL INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current Input Capacitance5 ANALOG OUTPUTS Output Range Resistor, ROFSA ROFSB Output Voltage Ranges6 Output Voltage Ranges6 Output Impedance CHARACTERISTICS5 Voltage Output Settling-Time Positive Full-Scale Change Negative Full-Scale Change Digital-to-Analog Glitch Impulse3 Digital Feedthrough3 Digital Crosstalk3 POWER REQUIREMENTS Range Range (Dual Supplies) (Dual Supplies)
Version2 4.95/5.05
Version2 4.95/5.05
Version2 4.95/5.05
Units Bits FSR/°C min/V ppm/°C
Test Conditions/Comments
Guaranteed Monotonic Latch Contents Latch Contents
Reference Load Current (IL) Change µA-100
4.95/5.05
4.95/5.05
4.95/5.05
min/V
15/30 +10,
15/30 +10,
15/30 +10,
min/
Single Supply; Dual Supply;
+10.8/+16.5 -10.8/-16.5
secs secs secs
Settling Time Within Final Value Typically Typically Latch Contents Toggled Between
+11.4/+15.75 +11.4/+15.75 min/V -11.4/-15.75 -11.4/-15.75 min/V
Specified Performance Unless Otherwise Stated Specified Performance Unless Otherwise Stated Output Unloaded; Typically Output Unloaded; Typically
NOTES Power supply tolerance, Version: 10%; Versions: Temperature ranges follows: Versions: -40°C +85°C; Version: -55°C +125°C. Terminology. Measured with respect REFIN includes unipolar/bipolar offset error. Guaranteed design production tested. output range available only with 14.25 Specifications subject change without notice.
REV.
AD7249 TIMING CHARACTERISTICS
Parameter Limit (All Versions)
(VDD AGND DGND
specifications TMIN TMAX unless otherwise noted.)
Units
Limit TMIN TMAX (All Versions)
Conditions/Comments SCLK Cycle Time SYNC SCLK Falling Edge Setup Time SYNC SCLK Hold Time Data Setup Time Data Hold Time SYNC High LDAC LDAC Pulse Width LDAC High SYNC Pulse Width SYNC High Time
NOTES Timing specifications guaranteed design production tested. input signals specified with (10% timed from voltage level Figure Power supply tolerance, Version: 10%; Versions: SCLK Mark/Space Ratio range 45/55 55/45.
ABSOLUTE MAXIMUM RATINGS
+25°C unless otherwise noted)
AGND, DGND -0.3 AGND, DGND +0.3 AGND DGND -0.3 VOUTA, AGND REFOUT AGND REFIN AGND -0.3 Digital Inputs DGND -0.3 Operating Temperature Range Industrial Versions) -40°C +85°C Extended Version) -55°C +125°C Junction Temperature +150°C Storage Temperature Range -65°C +150°C Power Dissipation Plastic Thermal Impedance +117°C/W Lead Temperature (Soldering, secs) +300°C
Power Dissipation, Cerdip Thermal Impedance Lead Temperature (Soldering, secs) Power Dissipation, SOIC Thermal Impedance Lead Temperature (Soldering) Vapor Phase secs) Infrared secs)
76°C/W +300°C 75°C/W +215°C +220°C
NOTES Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Only Absolute Maximum Rating applied time. outputs shorted voltages this range provided power dissipation package exceeded.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7249 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD7249
FUNCTION DESCRIPTION (DIP SOIC NUMBERS)
Mnemonic REFOUT REFIN ROFSB VOUTB AGND
Description Voltage Reference Output. internal analog reference provided this pin. operate part using internal reference, REFOUT should connected REFIN. Voltage Reference Input. internally buffered before being applied both DACs. nominal reference voltage specified operation AD7249 Output Offset Resistor amplifier connected VOUTB range, AGND range REFIN range. Analog Output Voltage This buffer amplifier output voltage. Three different output voltage ranges chosen: Analog Ground. Ground reference analog circuitry. Clear, Logic Input. Taking this input clears both DACs. sets VOUTA VOUTB both unipolar ranges twos complement bipolar range -REFIN offset binary bipolar range. Logic Input. This input selects data format either binary twos complement. both unipolar ranges natural binary format selected connecting this input Logic "0". bipolar configuration offset binary format selected with Logic while Logic selects twos complement. Digital Ground. Ground reference digital circuitry. Serial Data Logic Input. 16-bit serial data word applied this input. Load DAC, Logic Input. Updates both outputs. outputs updated falling edge this signal alternatively this line permanently low, automatic update mode selected whereby both DACs updated 16th falling SCLK pulse. Serial Clock, Logic Input. Data clocked into input register each falling SCLK edge. Data Synchronization Pulse, Logic Input. Taking this input initializes internal logic readiness data word. Positive Power Supply. Analog Output Voltage This buffer amplifier output voltage. Three different output voltage ranges chosen: Negative Power Supply (used output amplifier only) connected single supply operation dual supplies. Output Offset Resistor amplifier connected VOUTA range, AGND range REFIN range.
BIN/COMP
DGND SDIN LDAC
SCLK SYNC VOUTA ROFSA
CONFIGURATIONS (DIP SOIC)
REFOUT REFIN ROFSB VOUTB AGND ROFSA VOUTA SYNC SCLK LDAC SDIN
ORDERING GUIDE
Model AD7249AN AD7249BN AD7249AR AD7249BR AD7249SQ1
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C
Relative Accuracy
Package Option N-16 N-16 R-16 R-16 Q-16
AD7249
VIEW (Not Scale)
BIN/COMP DGND
NOTE Available /883B processing only. Contact your local sales office military data sheet.
REV.
AD7249
TERMINOLOGY Bipolar Zero Error
Bipolar Zero Error voltage measured VOUT when configured bipolar output loaded with (Twos Complement Coding) with 1000 0000 0000 (Offset Binary Coding). combination offset errors DAC, amplifier mismatch between internal gain resistors around amplifier.
Full-Scale Error
This "knee" offset effect, linearity error, transfer function would have followed dotted line output voltage could have gone negative. Normally, linearity measured between zero (all input code) full scale (all input code) after offset full scale have been adjusted allowed for, this possible single supply operation offset negative, knee transfer function. Instead, linearity AD7249 unipolar mode measured between full scale lowest code which guaranteed produce positive output voltage. This code calculated from maximum specification negative offset. versions, linearity measured between Codes 4095. grade, linearity measured between Code Code 4095.
Differential Nonlinearity
Full-Scale Error measure output error when amplifier output full scale (for bipolar output range full scale either positive negative full scale). measured with respect reference input voltage includes offset errors.
Digital-to-Analog Glitch Impulse
This voltage spike that appears VOUT when digital code Latch changes, before output settles final value. energy glitch specified secs, measured codes change from 0000 0000 0000 1111 1111 1111.
Digital Feedthrough
Differential Nonlinearity difference between measured change ideal change between adjacent codes. specified differential nonlinearity less over operating temperature range ensures monotonicity.
Unipolar Offset Error
This measure voltage spike that appears VOUT result feedthrough from digital inputs AD7249. measured with LDAC held high.
Relative Accuracy (Linearity)
Unipolar Offset Error measured output voltage from VOUT with zeros loaded into latch, when configured unipolar output. combination offset errors output amplifier.
CIRCUIT INFORMATION Section
Relative Accuracy, endpoint linearity, measure maximum deviation transfer function from straight line passing through endpoints transfer function. measured after allowing zero full-scale errors expressed LSBs percentage full-scale reading.
Single Supply Linearity Gain Error
output amplifier AD7249 have true negative offsets even when part operated from single supply. However, because negative supply rail (VSS) output cannot actually negative. Instead, when output offset voltage negative, output voltage sits resulting transfer function shown Figure
AD7249 contains 12-bit voltage-mode converters consisting highly stable thin film resistors high-speed NMOS single-pole, double-throw switches. simplified circuit diagram section shown Figure output voltage from converter same polarity reference voltage, REFIN, allowing single supply operation.
VOUT
OUTPUT VOLTAGE
REFIN* AGND SHOWN
*BUFFERED REFIN VOLTAGE
NEGATIVE OFFSET
Figure Simplified Circuit Diagram
CODE
Figure Effect Negative Offset (Single Supply)
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AD7249
Internal Reference Section
AD7249 on-chip temperature compensated buried Zener reference which factory trimmed reference voltage provided REFOUT pin. This reference used provide reference voltage converter connecting REFOUT REFIN pin. reference voltage also used reference other components capable providing external load. maximum recommended capacitance REFOUT normal operation reference output required drive capacitive load greater than then resistor should placed series with capacitive load. Figure shows suggested decoupling scheme, resistor parallel combination tantalum ceramic capacitor. This decoupling scheme reduces noise spectral density reference.
output voltage-mode converter buffered noninverting CMOS amplifier. ROFS input allows three output voltage ranges selected. buffer amplifier capable developing across load AGND. output amplifier operated from single supply tying amplifier also operated from dual supplies allow additional bipolar output range Dual supplies necessary bipolar output range also used unipolar ranges give faster settling time voltages near allow full sink capability over entire output range eliminate effects negative offsets transfer characteristic (outlined previously). plot output sink capability amplifier shown Figure
REFOUT 10µF 0.1µF
ISINK
LOAD
-15V
Figure Reference Decoupling Scheme
External Reference
some applications, user require system reference some other external reference drive AD7249. References such AD586 provide ideal external reference source (See Figure 10). REFIN voltage internally buffered unity gain amplifier before being applied converter. converter scaled reference device tested with applied REFIN. Other reference voltages used with degraded performance. Figure shows degradation linearity REFIN.
+15V -15V 25°C
OUTPUT VOLTAGE Volts
Figure Amplifier Sink Current
+15V +25°C REFERENCE DECOUPLING) REFERENCE (DECOUPLED*) OUTPUT WITH
LINEARITY ERROR LSBs
REFIN Volts
100k FREQUENCY *REFERENCE DECOUPLING COMPONENTS RESISTOR SERIES WITH PARALLEL COMBINATION 10µF 0.1µF GND.
Figure Linearity REFIN Voltage
Figure Noise Spectral Density Frequency
REV.
AD7249
DIGITAL INTERFACE
AD7249 contains input serial parallel shift register latch both simplified diagram input loading circuitry shown Figure Serial data SDIN input loaded input register under control SYNC SCLK. SYNC input provides frame synchronization signal which tells AD7249 that valid serial data SDIN input will available next falling edges SCLK. internal counter/decoder circuit provides gating signal that only data bits clocked into input shift register. After SCLK pulses internal gating signal goes inactive (high) thus locking further clock pulses. Therefore either continuous clock burst clock source used clock data. SYNC input taken high after complete 16-bit word loaded selection accomplished using thirteenth (DB12) serial data input stream. zero DB12 will select while this position selects Although bits data clocked into input register, only bits transferred into latch. relevant latch determined value thirteenth first three bits 16-bit stream don't cares. Therefore, data format three don't cares followed selection 12-bit data word with last serial stream.
There ways which latches hence analog outputs updated. status LDAC input examined after SYNC taken low. Depending status, update modes selected. LDAC then automatic update mode selected. this mode latch analog output updated automatically when last serial data stream clocked update thus takes place sixteenth falling SCLK edge. LDAC then automatic update disabled both latches updated taking LDAC time after 16-bit data transfer complete. update occurs falling edge LDAC. Note that LDAC input must taken back high again before next data transfer initiated. When complete word held shift register then loaded into latch under control LDAC.
Clear Function (CLR)
clear function clears contents input shift register loads both latches with activated taking low. ranges except Offset Binary bipolar range output voltage reset offset binary bipolar range output -REFIN. clear function especially useful power-up enables output reset known state.
SYNC RESET COUNTER/ DECODER GATING SIGNAL SHIFT REGISTER DECODER SDATA SDIN SHIFT REGISTER AUTO-UPDATE CIRCUITRY LDAC SELECT LATCH (12-BITS) LATCH (12-BITS)
SCLK
Figure Simplified Loading Structure
REV.
AD7249
SCLK
SYNC
SDIN DB15 DON'T CARE DB14 DON'T CARE DB13 DB12 DB11 DB15 DON'T CARE DB14 DON'T CARE DB13 DON'T CARE DB12 DB11
DON'T CARE SELECT
SELECT
LDAC
Figure Timing Diagram
TRANSFER FUNCTION
internal scaling resistors provided AD7249 allow several output voltage ranges. part produce unipolar output ranges bipolar output range Connections various ranges outlined below. Since each ROFS input DACs different output ranges.
Unipolar Configuration
restricted this range order maintain sufficient amplifier headroom. Dual supplies used improve settling time give increased current sink capability amplifier. Figure shows connection diagram unipolar operation AD7249. Table shows digital code analog output this configuration.
Unipolar Configuration
first configurations provides output voltage range This achieved connecting output offset resistor ROFSA, ROFSB (Pin AGND. Natural Binary data format selected connecting BIN/COMP (Pin DGND. this configuration, AD7249 operated using either single dual supplies. Note that supply
REFOUT ROFSA
output voltage range achieved tying ROFSA VOUTA ROFSB VOUTB. Once again, AD7249 operated using either single dual supplies. table output voltage versus digital code Table with 2REFIN replaced REFIN. Note, this range, REFIN (2-12) (REFIN/4096).
Table Unipolar Code Table Range)
Input Data Word XXXY 1111 1111 1111 XXXY 1000 0000 0001
Analog Output, VOUT +2REFIN (4095/4096) +2REFIN (2049/4096) +2REFIN (2048/4096) +REFIN +2REFIN (2047/4096) +2REFIN (1/4096)
12-BIT REFIN
VOUTA ROFSB
XXXY 1000 0000 0000 XXXY 0111 1111 1111 XXXY 0000 0000 0001 XXXY 0000 0000 0000
AD7249*
12-BIT
VOUTB
Don't Care. Select Bit, Note: 2REFIN/4096.
AGND
DGND
BIN/COMP
*ADDITIONAL PINS OMITTED CLARITY.
Figure Unipolar Configuration
REV.
AD7249
Bipolar Configuration Bipolar Operation (Offset Binary Data Format)
bipolar configuration AD7249, which gives output range achieved connecting ROFSA, ROFSB VREFIN. AD7249 must operated from dual supplies achieve this output voltage range. Either offset binary twos complement coding selected. Figure shows connection diagram bipolar operation. AD586 provides reference voltage this could provided on-chip reference connecting REFOUT REFIN.
+VIN ROFSA VOUTA AD586 VOUT REFIN 12-BIT ROFSB
AD7249 configured Offset Binary data format connecting BIN/COMP (Pin low. analog output digital code obtained inverting Table
APPLYING AD7249
Good printed circuit board layout important overall circuit design itself achieving high speed converter performance. AD7249 works size 2.44 unipolar range bipolar range, when using unipolar range size 1.22 Therefore designer must conscious minimizing noise both converter itself surrounding circuitry. Switching mode power supplies recommended switching spikes feedthrough on-chip amplifier. Other causes concern ground loops feedthrough from microprocessors. These factors which influence high performance converter, proper printed circuit board layout which minimizes these effects essential obtain high performance.
LAYOUT HINTS
AD7249*
12-BIT
VOUTB
AGND
DGND
BIN/COMP
*ADDITIONAL PINS OMITTED CLARITY.
Figure Bipolar Configuration with External Reference
Bipolar Operation (Twos Complement Data Format)
AD7249 configured twos complement data format connecting BIN/COMP (Pin high. analog output digital code shown Table
Table Twos Complement Bipolar Code Table
Ensure that layout digital analog tracks separated much possible. Take care digital track alongside analog signal track. Establish single point analog ground separate from logic system ground. Place this star ground close possible AD7249. Connect analog grounds this star point also connect AD7249 DGND this point. connect other digital grounds this analog ground point. impedance analog digital power supply common returns essential noise operation high performance converters. accomplish this track widths should kept wide possible also ground planes minimizes impedance paths also guards analog circuitry from digital noise.
NOISE
Input Data Word XXXY 0111 1111 1111 XXXY 0000 0000 0001 XXXY 0000 0000 0000 XXXY 1111 1111 1111 XXXY 1000 0000 0001 XXXY 1000 0000 0000
Analog Output, VOUT +REFIN (2047/2048) +REFIN (1/2048) -REFIN (1/2048) -REFIN (2047/2048) -REFIN (2048/2048) -REFIN
Keep signal leads VOUTA VOUTB signals signal return leads AGND short possible minimize noise coupling. applications where this possible shielded cable between outputs their destination. Reduce ground circuit impedance much possible since potential difference grounds between destination device appears error voltage series with output.
Power Supply Decoupling
Don't Care. Select Bit, Note: REFIN/2048.
achieve optimum performance when using AD7249, lines should decoupled AGND using capacitors. noisy environments recommended that capacitors connected parallel with capacitors.
REV.
AD7249
MICROPROCESSOR INTERFACING
Microprocessor interfacing AD7249 serial which uses standard protocol compatible with processors microcontrollers. communications channel requires three-wire interface consisting clock signal, data signal synchronization signal. AD7249 requires 16-bit data word with data valid falling edge SCLK. interfaces, update done automatically when data clocked done under control LDAC. Figures show AD7249 configured interfacing number popular processors microcontrollers.
AD7249-ADSP-2101/ADSP-2102 Interface
DSP56000 applied AD7249 SCLK input. Data from DSP56000 valid falling edge SCK. output provides framing pulse valid data. This line must inverted before being applied SYNC input AD7249.
TIMER
DSP56000
AD7249*
LDAC
SCLK SDIN SYNC
Figure shows serial interface between AD7249 ADSP-2101/ ADSP-2102 processor. ADSP-2101/ ADSP-2102 contains serial ports either port used interface. data transfer initiated going low. Data from ADSP-2101/ADSP-2102 clocked into AD7249 falling edge SCLK. DB12 16-bit serial data stream selects updated. Both DACs updated holding LDAC high while performing write cycles DAC. must taken high after each write cycle. LDAC brought second cycle both outputs updated together. interface shown updated using external timer
TIMER
*ADDITIONAL PINS OMITTED CLARITY.
Figure AD7249-DSP5600 Interface
this interface external LDAC pulse generated from external timer used update outputs DACs. This update also produced using programmable control line from DSP56000.
AD7249-TMS32020 Interface
ADSP-2101/ ADSP-2102*
AD7249*
LDAC SCLK SDIN SYNC
Figure shows serial interface between AD7249 TMS32020 processor. this interface, CLKX signals TMS32020 should generated using external clock/timer circuitry. TMS32020 must configured input. Data from TMS32020 valid falling edge CLKX. clock/timer circuitry generates LDAC signal AD7249 synchronize update output with serial transmission. Alternatively, automatic update mode selected connecting LDAC DGND.
CLOCK/ TIMER LDAC TMS32020
SCLK
*ADDITIONAL PINS OMITTED CLARITY.
Figure AD7249-ADSP-2101/ADSP-2102 Interface
which generates LDAC pulse. This could also done using control decoded address line from processor. Alternatively, LDAC input hardwired output update takes place automatically 16th falling edge SCLK.
AD7249-DSP56000 Interface
AD7249*
CLKX SYNC SCLK SDIN SDIN
serial interface between AD7249 DSP56000 shown Figure DSP56000 configured Normal Mode Asynchronous operation with Gated Clock. also 16-bit word with outputs control "0." internally generated
*ADDITIONAL PINS OMITTED CLARITY.
Figure AD7249-TMS32020 Interface
-10-
REV.
AD7249
AD7249-68HC11 Interface
Figure shows serial interface between AD7249 68HC11 microcontroller. 68HC11 drives SCLK AD7249 while MOSI output drives serial data line AD7249. SYNC signal derived from port line (PC0 shown). correct operation this interface, 68HC11 should configured such that CPOL CPHA When data transmitted part, taken low. When 68HC11 configured like this, data MOSI valid falling edge SCK. 68HC11 transmits serial data 8-bit bytes with only eight falling clock edges occurring transmit cycle. load data AD7249, left after first eight bits transferred second byte data then transferred serially AD7249. When second serial transfer complete, line taken high. Figure shows LDAC input AD7249 being driven from another programmable port line (PC1). result, both DACs updated simultaneously taking LDAC after both DACs latches have updated.
AD7249*
first eight bits transferred, second byte data then transferred serially AD7249 with DB12 used select appropriate register. When second serial transfer complete, P3.3 line taken high then taken again start loading sequence second (see timing diagram Figure Figure shows LDAC input AD7249 driven from programmable port line P3.2. result, both outputs updated simultaneously taking LDAC line following completion write cycle second DAC. Alternatively LDAC could hardwired analog output will updated sixteenth falling edge after SYNC signal gone low.
AD7249*
P3.2 P3.3 LDAC SYNC SCLK SDIN SDIN
87C51*
68HC11* MOSI
*ADDITIONAL PINS OMITTED CLARITY. LDAC SYNC SDIN SCLK SDIN
Figure AD7249-87C51 Interface
APPLICATIONS
OPTO-ISOLATED INTERFACE
*ADDITIONAL PINS OMITTED CLARITY.
Figure AD7249-68HC11 Interface
AD7249-87C51 Interface
serial interface between AD7249 87C51 microcontroller shown Figure 87C51 drives SCLK AD7249 while drives serial data line part. SYNC signal derived from port line P3.3 LDAC line driven port line P3.2. 87C51 provides SBUF register first serial data stream. Therefore, user will have ensure that data SBUF register arranged correctly that don't care bits first transmitted AD7249 last sent word loaded AD7249. When data transmitted part, P3.3 taken low. Data valid falling edge TXD. 87C51 transmits serial data 8-bit bytes with only eight falling clock edges occurring transmit cycle. load data AD7249, P3.3 left after
many process control type applications necessary provide isolation barrier between controller unit being controlled. Opto-isolators provide voltage isolation excess serial loading structure AD7249 makes ideal opto-isolated interfaces number interface lines kept minimum. Figure shows 2-channel isolated interface using AD7249. sequence events program output channels follows. Take SYNC line low. Transmit 16-bit word data word selects DAC, DB12 select bring SYNC line high after bits have been transmitted. Bring SYNC line again transmit bits bring SYNC back high transmission. Pulse LDAC line low. This updates both output channels simultaneously falling edge LDAC.
REV.
-11-
AD7249
DATA SDIN CLOCK CONTROLLER SYNC LDAC VOUTB VOUTB SCLK VOUTA VOUTA
AD7249*
SYNC
CONTROL *ADDITIONAL PINS OMITTED CLARITY
QUAD OPTO-COUPLER
Figure Opto-Isolated Interface
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
Plastic (N-16)
0.840 (21.33) 0.745 (18.93) 0.210 (5.33) 0.200 (5.05) 0.125 (3.18) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.280 (7.11) 0.240 (6.10)
0.150 (3.81)
0.015 (0.381) 0.008 (0.204)
0.022 (0.558) 0.014 (0.356)
0.100 (2.54)
0.070 (1.77) 0.045 (1.15)
SEATING PLANE
Wide Body SOIC (R-16)
Cerdip (Q-16)
0.299 (7.60) 0.291 (7.40) 0.419 (10.65) 0.404 (10.26)
0.271 (6.89) 0.240 (6.09)
0.780 (19.81)
0.300 (7.62) 0.163 (4.14) 0.133 (3.378)
0.413 (10.50) 0.348 (10.10)
0.107 (2.72) 0.089 (2.26)
0.364 (9.246) 0.344 (8.738)
0.125 (3.17) 0.02 (0.5) 0.016 (0.406) 0.11 (2.79) 0.099 (2.28) 0.06 (1.52) 0.05 (1.27)
0.21 (5.33) 0.15 (3.81)
0.012 (0.305) 0.008 (0.203)
SEATING PLANE
0.010 (0.25) 0.004 (0.10)
0.050 (1.27)
0.018 (0.46) 0.014 (0.36)
0.015 (0.38) 0.007 (1.18)
0.045 (1.15) 0.020 (0.50)
-12-
REV.
PRINTED U.S.A.
C1785-18-4/93

LC2MOS Dual 12-Bit Serial DACPORT AD7249 AD7249 REFOUT

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