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Am79C440 Spread Spectrum (SS) PhoX Controller Digital Cordless Telephones
Version
1998 Advanced Micro Devices, Inc. rights reserved. Advanced Micro Devices, Inc. ("AMD") reserves right make changes products without notice order improve design performance characteristics.
information this publication believed accurate time publication, makes representations warranties with respect accuracy completeness contents this publication information contained herein, reserves right make changes time, without notice. disclaims responsibility consequences resulting from information included this publication. This publication neither states implies representations warranties kind, including limited warranty merchantability fitness particular purpose. products authorized critical components life support devices systems without AMD's written approval. assumes liability whatsoever claims associated with sale (including engineering samples) products except provided AMD's Terms Conditions Sale such products.
Trademarks
PhoX, AMD, logo, combinations thereof trademarks Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.
TABLE CONTENTS
Chapter
OVERVIEW General Description Protocol Functions Audio Functions 1.3.1 Codec 1.3.2 Audio Front 1.3.3 Tone Ringer. 1.3.4 Biasing 1.3.5 DTMF Generator System Control Functions 1.4.1 Microcontroller 1.4.2 Synchronous Serial Port 1.4.3 Peripheral Ports 1.4.4 Battery Level Detector 1.4.5 Watchdog Timer 1.4.6 Wakeup Timer. 1.4.7 Interrupt Controller 1.4.8 Clock Generator 1.4.9 Address Decoder Connection Diagrams Descriptions. Ordering Information FUNCTIONAL DESCRIPTION Operating Modes Power Management Functions. 2.1.1 Reset. 2.1.2 Operating Mode 2.1.3 System Clock 2.1.4 Clock Enables Shutdown Mode 2.1.5 Watchdog Timer 2.1.6 Battery Monitor 2.1.7 Wakeup Timer. Microprocessor Core Peripheral Ports 2.2.1 80C32T2 Microcontroller. 2.2.2 Interrupt Controller 2.2.3 Synchronous Serial Port 2-11 2.2.4 Parallel Ports. 2-13 Formatter 2-14 2.3.1 Communications System Block Diagram 2-14 2.3.2 Theory Operation 2-15 2.3.3 Framing Format. 2-17 2.3.4 Channel Access 2-18 2.3.5 Baseband Transmitter 2-19 2.3.6 Baseband Receiver. 2-23 2.3.7 Channel Operation 2-35 2.3.8 System Synchronization 2-37 2.3.9 Crystal Trimming 2-38 2.3.10 Link Quality Assessment Subsystem 2-39 2.3.11 Free Channel Scanning 2-40 Table Contents
Chapter
Chapter
2.3.12 Parameter Configuration Calibration Mode 2-40 Audio Functions 2-41 Development Modes 2-46
REGISTER SUMMARY Memory Index Reserved Register Bits 3.3. Address Decoder 3.3.1 ADRDEC. Chip Information 3.4.1 CHIPINFO. Parallel Port 3.5.1 P1SRC0 3.5.2 P1SRC1 3.5.3 P1SRC2 3.5.4 P1MASK 3.5.5 P1TRIG 3.5.6 PORT4 3.5.7 PORT5 3.5.8 XISTAT0 3.5.9 XISTAT1 3.5.10 XISTAT2 3.5.11 GPOCTR0. 3.5.12 BDMUX 3-10 Serial Port 3-12 3.6.1 SIOTB 3-12 3.6.2 SIORB. 3-12 3.6.3 SIOCFG 3-13 3.6.4 SIOSTAT 3-14 3.6.5 SIOMASK 3-14 3.6.6 SPTMG 3-14 Audio 3-15 3.7.1 AOMUX 3-15 3.7.2 AINCTR. 3-16 3.7.3 STCTR 3-17 Tone Ringer 3-18 3.8.1 TRFR 3-18 Wakeup Timer 3-21 3.9.1 WAKEUP. 3-21 3.10 Battery Detect 3-22 3.10.1 BATLEV. 3-22 3.11 Dual-Tone Generator 3-23 3.11.1 T1FR1-3, T2FR1-3 (Dual-Tone Frequency) 3-23 3.11.2 T1AR, T2AR (Dual-Tone Amplitude) 3-24 3.11.3 TTAR, RTAR (Dual-Tone Path Attenuation). 3-26 3.12 Codec 3-27 3.12.1 TXATTN 3-27 3.12.2 RXATTN 3-27 3.12.3 DSPCTR 3-27 3.12.4 STROBEN. 3-28 3.13 Noise Suppression. 3-29 3.13.1 NSCTR 3-29 3.13.2 MUTE 3-30 3.14 Formatter 3-31 3.14.1 RXBUF0-5 3-31 3.14.2 TXBUF0-5 3-31 3.14.3 SYNC_CTRL. 3-32 3.14.4 QUALITY. 3-32 Table Contents
3.14.5 RSSI 3-33 3.14.6 BASELINE 3-33 3.14.7 TIMING_LOOP 3-34 3.14.8 TXMODE. 3-35 3.14.9 RXMODE 3-36 3.14.10 BSYNC 3-37 3.14.11 RSSI_DELAY 3-38 3.14.12 IF_DELAY 3-39 3.14.13 TXEN_CNFG 3-40 3.14.14 RXEN_CNFG 3-41 3.14.15 PAENB_CNFG 3-42 3.14.16 SCRAMBLE 3-42 3.14.17 3-43 3.14.18 XTALDAC 3-44 3.14.19 SYNC0 3-44 3.14.20 SYNC1 3-44 3.14.21 DCHSTAT 3-45 3.14.22 SYNCSRC 3-46 3.14.23 SYNCMASK 3-46 3.14.24 IFLOOPA. 3-47 3.14.25 IFLOOPB 3-48 3.14.26 IFLOOPC 3-49 3.14.27 DCOMSB 3-50 3.14.28 DCOLSB 3-50 3.14.29 INTMSB 3-50 3.14.30 INTLSB 3-50 3.15 Interrupt Controller. 3-51 3.15.1 MISRC0 3-51 3.15.2 MISRC1 3-52 3.15.3 MIMSK0 3-54 3.15.4 MIMSK1 3-55 3.16 Clock Generator (Power Management) 3-56 3.16.1 UCCCTR. 3-56 3.16.2 UCCCP 3-57 3.16.3 MECTR0 3-58 3.16.4 MECTR1 3-59 3.17 Watchdog Timer. 3-59 3.17.1 WDTKEY. 3-59 Chapter HARDWARE APPLICATIONS EEPROM Interface Handset Loudspeaker Interface PSTN Interface Scanner Interface A-Law/µ-Law Interface Battery Superheterodyne Radio Architecture. Development Modes 4.8.1 Unidirectional, Non-TDD Mode 4.8.2 Bidirectional, Mode Channels 4.8.3 Test/Development Signals.
Table Contents
Chapter
SOFTWARE APPLICATIONS Shutdown Mode Scanner Operation Timer/Counters. Interrupts Serial Port Service PACKAGE DIMENSIONS
Chapter
Table Contents
LIST FIGURES
Figure Block Diagram Figure Reset Circuit Structure Figure Battery Detector Function Diagram. Figure Interrupt Tree. Figure Transfer Format CLOCK EDGE Equals Zero 2-12 Figure Transfer Format CLOCK EDGE Equals 2-12 Figure Communications System Block Diagram 2-14 Figure Mathematical Model Transmission Path 2-15 Figure Timing Structure 2-17 Figure Frame Format 2-18 Figure 2-10 Heterodyne Channel Spacing 2-18 Figure 2-11 Baseband Transmitter Block Diagram 2-19 Figure 2-12 Scrambler Architecture 2-21 Figure 2-13 Differential QPSK Line Coder 2-21 Figure 2-14 Output Constellation (Nondifferential) 2-22 Figure 2-15 Subchannel Format 2-23 Figure 2-16 Baseband Receiver Block Diagram. 2-23 Figure 2-17 RSSI Timing Diagram 2-27 Figure 2-18 Baseband Receiver Front 2-28 Figure 2-19 Matched Filter Block Diagram 2-32 Figure 2-20 Frame Synchronization State Machine 2-34 Figure 2-21 Packet Structure 2-35 Figure 2-22 Master/Slave Timing Implementation 2-38 Figure 2-23 Audio Front 2-41 Figure 2-24 Codec Block Diagram 2-42 Figure 2-25 Noise Suppression Muting Sequence 2-44 Figure 2-26 Dual-Tone Generator Block Diagram 2-45 Figure Figure Figure Figure Figure Interface Synthesizer Serial Access EEPROM Interface Handset Loudspeaker Interface Public Switched Telephone Network Interface Keypad Matrix. A-Law/µ-Law Interface
Figure Example Scanner Flow Diagram
Table Contents
LIST TABLES
Table Table Table Table Table Table Table Table Table Table 2-10 Table 2-11 Table 2-12 Table 2-13 Table Table Table Table Table Table Table Table Table Table 3-10 Table 3-11 Table Establishing Basic Operating Mode Battery Detection Levels Battery Detector Relative Parameters. Program Memory Data Memory Map. Additions 8032 INT0 Interrupt Sources. 2-10 8032 INT1 Interrupt Sources 2-10 Parallel Port Description 2-13 Radio Interface Signals 2-20 DQPSK Coding Summary. 2-20 Radio Interface Signals 2-24 Recovery Circuit Parameters 2-29 External Data Space Address Select Multifunction Configuration 3-11 Gain Codes 3-16 Sidetone Gain Codes 3-17 Tone Ringer Frequency Codes, Ordered Frequency 3-19 Tone Ringer Frequency Codes, Ordered Code 3-20 Battery Detect Adjust Value Codes 3-22 DTMF Frequency Short-Form Table 3-23 Attenuation Codes. 3-25 Sequence Codes 3-43 8032 Speed Codes. 3-57 Test/Development Signals.
viii
Table Contents
CHAPTER
OVERVIEW
GENERAL DESCRIPTION
Am79C440 PhoX Controller baseband processor direct sequence spread spectrum, residential digital cordless telephones that operate Canadian band. device used either handset base station point-to-point operation. Figure indicates principal functional blocks within Am79C440.
PROTOCOL FUNCTIONS
protocol block conducts signal voice channel transmit receive directions.
1.3.1 1.3.2 1.3.3
AUDIO FUNCTIONS Codec
codec trancodes analog voice signals Kbit/s ADPCM data.
Audio Front
audio front connects analog voice pins codec.
Tone Ringer
tone ringer produces digital square-wave ringing tone signals output RINGER pin.
1.3.4
Biasing
biasing circuits establish precision voltage current references support analog operations audio battery detection.
1.3.5
DTMF Generator
DTMF generator produces digitally-generated tones DTMF dialing call progress tones.
Overview
Figure
Block Diagram
Protocol Functions PAENB RXEN TXEN RSSI RSSI_REF RXIF1 RXIF2 XTALDAC DSSS Frame Formatter
Audio Functions Biasing
IREF CFILT
ADPCM CODEC DTMF Generator
Audio Front
Digital Ringer
RINGER
System Control Functions P4[4:0] P5[4:0] BDP0 BDP1 BDP2 BDP3 WAKEUP SDIN Parallel Ports Interrupt Controller Synchronous Serial Port SDOUT SCLK XINT0 XINT1 XINT2
Wakeup Timer
RESET
Watchdog Timer
BATMON
Battery Detect 80C32T2 Microcontroller ROM: Kbytes RAM: bytes
MCLK1 MCLK2 OSCENA
Clock Generator
PSEN P0[7:0] P2[7:0] P3[7:6] P1[7:0] P3[1:0] MODE0 MODE1
Kbyte
Mode Select
Note: 100-pin package only
Overview
1.4.1
SYSTEM CONTROL FUNCTIONS Microcontroller
80C32T2 microcontroller core executes program software controls protocol logic other hardware configurations. 80C32T2 provides asynchronous serial port. PhoX Controller includes Kbytes addition byte internal microcontroller. optional Kbyte, mask-programmable also available.
1.4.2
Synchronous Serial Port
synchronous serial port provides synchronous serial link devices such synthesizers, TAD, serial EEPROMs, etc.
1.4.3
Peripheral Ports
peripheral ports general purpose functions. support key-scanning function, port specifically designed such that change state generates interrupt; this interrupt automatically bring PhoX Controller Shutdown mode.
1.4.4
Battery Level Detector
battery level detector reports battery condition prevent misoperations while batteries low. sends dead battery control signal that used hold PhoX Controller disabled, low-power state. addition, battery level detector used high-level detection battery charging control.
1.4.5
Watchdog Timer
watchdog timer protects system from errant operations issuing RESET signal unless periodically serviced software.
1.4.6
Wakeup Timer
wakeup timer multivibrator that controlled external passive components. used call detection sending periodic wakeup signal while PhoX Controller low-power state.
1.4.7
Interrupt Controller
interrupt controller structures various interrupts manageable service microcontroller.
1.4.8
Clock Generator
internal clock generator creates required internal timing signals from external 21.4 clock input.
1.4.9
Address Decoder
address decoder generates strobes access selected address spaces within PhoX Controller.
Overview
CONNECTION DIAGRAMS
XTALDAC BATMON AVCC2 AVCC3 AVSS2 AVSS3
RXIF1
RXIF2
CFILT
AVSS
IREF AVCC P2.7 MODE0 P2.6 MODE1 P2.5 P2.4 P5.0 P5.1 P5.2 P5.3 P5.4 P2.3 P4.0 P2.2 P2.1 P4.1 P2.0 P3.7 P4.2 P3.6 P4.3 P4.4 RESETIOX
RSSI_IN RSSIGND AVCC4 TXEN RXEN PAENB AVSS4 MCLK1 MCLK2 OSCENA SCLK SDOUT SDIN P0.0 P0.1 P0.2 RINGER P0.3 P0.4 WAKEUP P0.5 P0.6 P0.7
100-Pin PQFP
PSEN
VSSB
XINT0
XINT1
VCCB
Overview
XINT2
P3.1
P3.0
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
BDP3
BDP2
BDP1
BDP0
P1.7
CONNECTION DIAGRAMS (continued)
AVCC3 XTALDAC AVSS2 BATMON AVCC2 AVSS3
RXIF1
IREF AVCC MODE0 MODE1 P5.0 P5.1 P5.2 P5.3 P5.4 P4.0 P4.1 P4.2 P4.3 P4.4 RESETI0X BDP0 P3.1 P3.0 P1.5 P1.6 P1.7 XINT2 BDP3 BDP2 BDP1 P1.0 P1.1 P1.2 P1.3 P1.4 RSSI1 RSSI2 AVCC4 TXEN RXEN PAENB AVSS4 MCLK1 MCLK2 OSCENA SCLK SDOUT SDIN RINGER WAKEUP
68-Pin PLCC
DESCRIPTIONS
signals CMOS levels unless otherwise stated.
Overview
RXIF2
CFILT
AVSS
1.7.1
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. ordering number (valid combination) formed combination elements below:
Am79C440
OPTIONAL PROCESSING Blank standard processing
TEMPERATURE RANGE Commercial (0°C +70°C)
PACKAGE TYPE 100-pin plastic quad flat-pack (PQFP) 68-pin plastic leaded chip carrier (PLCC)
DEVICE NAME/DESCRIPTION Am79C440 Spread Spectrum (SS) PhoX Controller Digital Cordless Telephones
Valid Combinations Valid Combinations Valid combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations, check newly released valid combinations.
Am79C440
Overview
CHAPTER
2.1.1
FUNCTIONAL DESCRIPTION
OPERATING MODES POWER MANAGEMENT FUNCTIONS Reset
PhoX reset active Low, level-sensitive that resets chip default state when driven Low. chip drives reset under conditions: when battery detector indicates dead battery described Section 2.1.6) when watchdog timer expires described section 2.1.5). Figure shows wired-OR configuration reset circuit structure. battery detector output BAT.DEAD ordinarily inactive (Low). p-channel (MP1 Figure 2-1) sources current into resistive/capacitive load, keeping voltage reset High forming resistor divider across internal pull-up external load When watchdog timer expires, turns n-channel (MN2), discharging stored charge load capacitance ground pulling reset node Low. time constant discharge, formed components nF), approximately times smaller than active drive time watchdog timer. battery monitor output affects reset same watchdog timer output, turning pull reset node down dissipate charge stored ground. pull-up path broken MP1. When actual level drops driver transistors function, circuit dominated external pull-down load resistance. Diodes provide electrostatic discharge protection. also safely discharges load capacitance event sudden drop level. reset output defeated selecting suitably strong external pull-up RDEFEAT reset pin.
Functional Description
Figure
Reset Circuit Structure Reset sequence complete
RESET(H) (internal) PhoX External
Reset Latch Watchdog Timer
RDEFEAT
SHUTDOWN
RESET
Battery Monitor
BAT.DEAD
OSCENA Analog
MCLK1 MCLK2 OSCENA Oscillator
21.4
Series drive Resistance, Watchdog Timer Series drive Resistance, Battery Detector Internal Pull-up Resistance,
nominal nominal nominal
2.1.2
Operating Mode
basic operating mode defined level MODE0 MODE1 pins, shown Table 2-1.
Table
Establishing Basic Operating Mode MODE1 High High MODE0 High High Processor Internal Internal External Configuration Internal Kbytes optional external External only Kbytes) External only Kbytes) 100-Pin Both 100-pin 100-pin
Basic Operating Mode Normal, Internal Normal, External Reserved (Test) Emulation, External
Normal mode typical chip applications uses embedded 80C32T2 processor (code user-supplied), well additional external ROM, required. External mode bypasses internal ROM, mapping that space external ROM. Emulation mode code development with 8051 in-circuit emulator. Test mode factory test only.
Functional Description
2.1.3
System Clock
master timing source external 21.4 clock. internal generates 18.432 clock, which used microcontroller other blocks. internal 18.432 clock responsive three conditions: OSCILLATOR DISABLE SHUTDOWN BAT.DEAD RESET where SHUTDOWN represents latch normal completion shutdown sequence programmed UCCCTR register cleared enabled interrupt reset. When device Shutdown mode, OSCEN signal goes Low. BAT.DEAD represents condition where battery detector determined that battery level below minimum value. RESET reset level. Therefore, internal clock runs during reset, except when inhibited battery condition, shown Figure 2-1. internal clock disabled battery condition defeated test mode well low-voltage device testing.
2.1.4
Clock Enables Shutdown Mode
power management features PhoX chip centralized clock generator block. Each functional block chip individually enabled disabled programming appropriate MECTR0 MECTR1 register. 80C32T2 clock rate programmable UCCCTR register reduced power consumption. clock rate control mechanism includes automatic speedup feature, which allows enabled interrupt immediately increase clock rate maximum speed fast interrupt service. When enabled, auto speedup responds interrupts processor INT0 INT1 interrupts. These interrupts internal chip driven interrupt controller. UCCCTR also controls entry into low-power Shutdown mode. Shutdown mode, circuits held static minimum power consumption. PhoX device enters Shutdown mode between 3.56 after UCCCTR[7] set, software 3.56 perform necessary housekeeping tasks before clocks chip stop analog circuits power down. These tasks include disabling codec analog interfaces programming 80C32T2 Idle mode. enabled interrupt occurring during sequence causes abort. enabled interrupt awakens chip from Shutdown mode. wake-up sequence takes 3.56 returns chip condition before shutdown. Analog circuits take approximately reactivate stabilize. battery level detector controls entry into Dead Battery mode, which further detailed Figure 2-1. When battery level falls below dead battery threshold, detector asserts BAT.DEAD signal that disables oscillator resets chip. microcontroller remains static undetermined state. PSEN pins pulled Inactive state.
Functional Description
2.1.5
Watchdog Timer
PhoX chip drives reset watchdog timer expiration software reset. Software must perform watchdog timer (WDT) sequence uninterrupted least once every Failure correctly perform sequence results 1.80 output pulse reset returns chip default condition. sequence write WDTKEY write WDTKEY hex. Software induce software reset writing WDTKEY fact, value written WDTKEY other than those listed sequence, reset results. Reset also occurs sequence incorrectly performed. Because watchdog clocked from clock input, counter frozen Shutdown mode.
2.1.6
Battery Monitor
battery monitor detects battery supply voltage ensure proper system reset when battery low. Because latch-up considerations, BATMON voltage allowed exceed chip Vcc, BATMON level scaled version actual battery level. recommended scaling network resistors producing voltage that 17.06% Vcc. detection circuit consists three comparators, which compare resistor-divided battery level BATMON three internally-generated voltage references derived from single bandgap reference. three references dead-battery, low-battery, high-battery thresholds. Detector outputs called BAT.DEAD, BAT.LOW, BAT.HIGH. Table summarizes thresholds outputs, reflecting hysteresis decision thresholds. Further detail provided Chapter Electrical Characteristics. BAT.DEAD True when battery level drops below dead battery threshold, remains True until BATMON voltage exceeds low-battery threshold. When BAT.DEAD True, hardware drives RESET Low, causing chip reset oscillator disabled. Figure shows interaction battery monitor reset circuit. BAT.LOW BAT.HIGH indicators present BATLEV register polling. BAT.LOW True when level drops below low-battery threshold. BAT.HIGH True when level exceeds high-battery threshold. device includes three-bit, user-programmable adjustment field lower three bits BATLEV register that used null device external resistor errors. BATLEV register responsive activity RESET pin. Instead, adjustment field returns default value whenever below approximately
Table
Battery Detection Levels Condition Target Battery Voltage, Battery Voltage Falling Cells BAT.DEAD BAT.LOW BAT.HIGH <3.12 <3.48 >4.168 Cell <1.04 <1.16 >1.348 Target Battery Voltage, Battery Voltage Rising Cells <3.515 <3.515 >4.250 Cell <1.172 <1.172 >1.375
Functional Description
Table
Battery Detector Relative Parameters
Parameter HYSTDEAD Description Difference between dead battery trip point rising falling battery conditions.* Difference between battery trip point rising falling battery conditions. Target Difference between high battery trip point rising falling battery conditions. Target Test Conditions Measured BATMON Referred target battery Measured BATMON Referred target battery 62.3 67.3 72.3 Measured BATMON Referred target battery 10.8 13.8 16.8 Unit
HYSTLOW
HYSTHIGH
Note: Detector uses battery trip point battery rises.
Figure
Battery Detector Function Diagram
Falling battery voltage Rising battery voltage
HYSTHIGH VHIR VHIF VLOR VLOF VDEAD
Volts
HYSTLOW HYSTDEAD
BAT.HIGH
time
BAT.LOW BAT.DEAD RESET
2.1.7
Wakeup Timer
wakeup timer external RC-controlled monostable multivibrator. WAKEUP load intended capacitor tied ground resistor tied Vcc, creating time constant approximately device drives WAKEUP then releases Each time level crosses threshold upward direction, input level detector increments counter then drives again. counter terminal count 8191, which decoded cause interrupt intended awaken device from Shutdown mode. counter free-running repeats after terminal count reached. interrupt reported MISRC1[7] maskable MIMSK1[7]. interrupt becomes non-maskable when chip Shutdown mode. interrupt cleared only reading WAKEUP register.
Functional Description
WAKEUP register enables timer. defaults enabled state. When disabled, output disabled (high impedance) counter cleared. timer automatically enabled when chip Shutdown mode. Software write control then clear restart counter.
2.2.1
MICROPROCESSOR CORE PERIPHERAL PORTS 80C32T2 Microcontroller
microcontroller PhoX chip member 8051 family microcontrollers, with standard 8051-family architecture instruction set. microcontroller referred throughout this manual 80C32T2 simply 8032). feature 80C32T2 dual data pointer. Appendices 80C32T2 Appendices, PhoXController Digital Cordless Telephones define architecture, programming requirements, instruction 8032.
2.2.1.1
Memory
Table Table identify separate program data spaces 8032. Data space further divided into internal external spaces, which accessed different means.
Table
Program Memory Program Space Normal Mode Internal Reserved Expansion External Emulation Mode External Address Range 0000-5FFE 5FFF 6000-FFFF 0000-FFFF Size Kbytes byte Kbytes Kbytes
Table
Data Memory 8032 Internal Data Space Internal RAM, direct/indirect access Internal RAM, indirect access only Special Function Registers (SFRs), direct access only Address Range 00-7F 80-FF 80-FF Size bytes bytes bytes
8032 External Data Space (Access Movx) Internal ADRDEC[7])
Address Range 0000-03FF 0000-EFFF 0400-EFFF F000-F3FF F400-F7FF F800-FEFF FF00-FFFF
Size Kbyte Kbytes Kbytes Kbyte Kbyte Kbytes bytes
ADRDEC[7]) ADRDEC[7])
(Unmapped) PhoX Chip Memory Mapped Registers
Functional Description
2.2.1.2
Port Interrupts
standard 8032 port been modified generate maskable interrupts transition events pins. Although directly accessible 8032 space, controls interrupt function located PhoX memory-mapped register space. transition event either positive negative transition pin, programmed P1TRIG register. Bits individually masked P1MASK register, masked groups MIMSK1 register. Events reported P1SRC0, P1SRC1, P1SRC2 registers. Interrupts masked while changing edge sensitivity P1TRIG, because change cause interrupt.
2.2.1.3 Upper Order Address Port,
During access external data memory using MOVX @DPTR instruction, uses strong pullups when emitting held weakly High during reset Shutdown mode, high impedance Emulation mode. bits have weak pullups that individually disabled.
2.2.1.4 Clock Input
microcontroller clock supplied internal signal called CPUCLK, which derived from external 21.4 clock input appears when Emulation mode. frequency CPUCLK programmable from 9.216 UCCCTR register. programming UCCCTR Shutdown mode, CPUCLK stops entirely. Automatic Speedup mode enables hardware immediately increase CPUCLK speed maximum when triggered interrupt either 8032 external interrupts, INT0 INT1. auto speedup feature does respond 8032 timer/counter serial port interrupts. clock doubling control doubles microprocessor effective clock rate, maximum 18.432 MHz. clock rates shown Table 3-11.
2.2.1.5 Reset
reset input active Low, unlike standard 8051-family microcontroller reset inputs.
2.2.1.6
Note: This does exist 68-pin 100-pin configuration.
PhoX chip external address select (EA) pin, which present standard 8051-family microcontrollers. Internal external selected with MODE1 pin. Section 2.1.2.
2.2.1.7 Microcontroller Port Modifications
PhoX microcontroller ports support CMOS levels. When device Normal mode executing from internal ROM, Port pins driven weakly High PSEN inactive. Port pins reflect movx data transactions. When controller Normal mode executing from external expansion ROM, PSEN ports behave External Program mode. External Program mode, PhoX device drives higher order address conducts multiplexed lower order address data PSEN active during instruction fetches. When device Emulation mode, ports assume high impedance state. eliminate spurious glitches during reset, ports driven "float high" condition.
Functional Description
minimize power consumption, Port buffers capable disabling weak pull-ups software control Port Control Register special function registers.
2.2.1.8 Additions
special function registers listed Table added standard 8032 disable microcontroller port weak pull-ups. SFRs marked with asterisk accessible only when PCFIG[0] High.
Table
Additions Name PCFIG P1PCRB P2PCRB P3PCRB Address 90H* A0H* B0H* Default After Reset
These SFRs accessed only when PCFIG[0] been High.
Each PxPCRB (Port [1,2,3] Port Control Register Bit) contains bits corresponding bits each ports. When PxPCRB cleared, associated port behaves standard 8032 port, where internal weak pull-up applied port driving Setting PxPCRB disables weak pull-up respective port bit, making high impedance input port when port programmed Notice that PxPCRB SFRs share same address port SFRs. PCFIG 1-bit register PCFIG[0] selects access either port PxPCRB SFR. PCFIG[0] must access PxPCRB registers must cleared access port SFRs.
2.2.1.9 PSEN Modifications
reduce power consumption during instruction fetches from external program ROM, CPUCLK clock signal less than 9.216 reduce PSEN pulse width.
2.2.1.10 Interrupt Modifications
INT0 (P3.2) INT1 (P3.3) interrupt inputs driven internally. interrupt sources PhoX chip, reported MISRC0 MISRC1 registers, fundamentally level-sensitive nature. Therefore, TCON[2,0] 8032 should programmed proper interrupt response. 8032 Idle mode (PCON[0]) supports low-power Shutdown mode such that controller clock stopped indefinitely. avoid entering Idle mode with interrupts disabled therefore being incapable awakening without full reset, 8032 ignores interrupt mask bits TCON[7,2,0] when Idle mode. interrupt types enabled TCON bits themselves unchanged. software development purposes in-circuit emulator environment, software always enables interrupts TCON before programming Idle mode bit, because wakeup safeguard present standard 8051-family emulators.
2.2.1.11
(P3.4) (P3.5) signals appear pins PhoX chip. They internally tied clock source enabled MECTR0 register, located external data space.
Functional Description
When using counter functions, care must taken with regard clock inputs CPUCLK rate. Counter mode, 8032 samples inputs once machine cycle increments counter only negative transitions sampled counter input; therefore, counter function works normally only CPUCLK rates greater than (i.e., 9.216 MHz).
2.2.2
Interrupt Controller
centralized interrupt controller incorporates interrupts generated various on-chip functions into INT0 INT1 interrupts recognized 8032 microcontroller. Software controls masking MIMSK0 MIMSK1 registers determines interrupt sources reading status registers MISRC0 MISRC1. Figure shows interrupt tree. proper response interrupts, program 8032 level-sensitive interrupts. Table Table list interrupt sources service requirements. unmasked interrupt causes PhoX device shutdown awaken. Port wakeup timer interrupts automatically enabled during shutdown system viability, their masks automatically returned their previous condition after system awakens recognizes interrupt source.
Figure
Interrupt Tree
MIMSK0
MISRC0
DRXFULL RXENINT DTXEMPTY
INT0
EXTINT0
EXTINT1
MUTETRIG
MIMSK1
EXTINT2 PORT5 SYNC
MISRC1
INT1
P1INT0
P1INT1 P1INT2
WAKEUP
Functional Description
Table
8032 INT0 Interrupt Sources MISRC0 Interrupt Mnemonic DRXFULL RXENINT DTXEMPTY EXTINT0 EXTINT1 MUTETRIG Reserved Reserved Source Formatter Formatter Formatter External External Noise Suppression Reserved Reserved Description channel receive buffer full. Cleared reading RXBUF5. RXEN transition occurred. Cleared reading RXEN_CFNG. channel transmit buffer empty. Cleared writing TXBUF5 buffer. XINT0 changed state. Cleared reading XISTAT0. XINT1 changed state. Cleared reading XISTAT1. Receive Channel check-field errors exceed programmed thresholds. Cleared reading NSCTR. Reserved, used Reserved, used
Table
8032 INT1 Interrupt Sources MISRC1 Interrupt Mnemonic EXTINT2 PORT5 Source External Serial Port Description XINT2 changed state. Cleared reading XISTAT2. Activity (keypad) pins. Cleared reading Non-maskable shutdown mode. Transmit buffer empty receive data available. Cleared writing transmit buffer reading SIOSTAT. SYNC interrupt occurred, reflected SYNCSRC register. Cleared reading SYNCSRC. unmasked event occurred P1[1:0]. Cleared reading P1SRC0. unmasked event occurred P1[3:2]. Cleared reading P1SRC1. unmasked event occurred P1[7:4]. Cleared reading P1SRC2. Terminal count wakeup timer. Cleared reading WAKEUP register. Non-maskable shutdown mode.
SYNC P1INT0 P1INT1 P1INT2 WAKEUP
Formatter Parallel Port Parallel Port Parallel Port Wakeup Timer
2-10
Functional Description
2.2.3
Synchronous Serial Port
serial port compatible with master-only serial peripheral interface which SDIN, SDOUT, SCLK pins bussed external peripherals. SCLK will output only will control shifting data external peripherals, which selected separate general purpose pins tied peripheral chip select.
2.2.3.1
General Description Synchronous Serial Port Interface
During transfer, data always simultaneously transmitted received. only want transfer data, ignore data being shifted into SDIN input. only want receive data, write transmit data buffer automatically start SCLK output received data; written data also transmitted SDOUT pin. single SCLK synchronizes shifting sampling information serial data lines out) simultaneously. Another view simultaneous transfer through character shift register master shift register equal length slave, which linked together. When transfer occurs, this distributed shift register shifted together characters master slave effectively exchanged. serial port transmit buffer length changed configuration register (SIOCFG) from bits. When data that written into transmit buffer (SIOTB) sent out, SCLK stops programmed idle level waits next load SIOTB before starting transmission. Software select four combinations serial clock (SCLK) phase polarity using bits. clock polarity selected CLOCK LEVEL SELECT control bit, SIOMODE register. This selects active high active clock effect transfer format, does select idle level clock when transmission occurs. RECEIVE CLOCK EDGE selects fundamentally different transfer formats. this equal zero, data sampled leading edge clock pulse. this equal one, data sampled trailing edge clock pulse. These clock control bits have been moved SIOCFG register. timing diagrams below (Figure Figure 2-5) indicate effect changing CLOCK EDGE bit. clock phase polarity edge select should identical slave peripheral device which data being exchanged. some cases, polarity clock edge select changed between transfers allow communication with different peripheral slaves having different requirements. Depending upon maximum communication rate external device, clock frequency peripheral change between transfers (i.e., while external peripheral chip select active). serial port single buffered transmit side double buffered receive side. data transmission cannot written buffer while previous data being transferred. However, want read data buffer during transmission, contents transfer corrupted last data value read correctly. Because received data transferred into parallel read data buffer, shifter free accept second serial character immediately. long first character read read data buffer before third character written transmit buffer, overrun condition occurs.
Functional Description
2-11
Figure
Transfer Format CLOCK EDGE Equals Zero
Sample Time (CLOCKLEVEL SELECT (CLOCKLEVEL SELECT
SCLK SCLK
SDOUT SDIN
Figure
Transfer Format CLOCK EDGE Equals
Sample Time (CLOCKLEVEL SELECT (CLOCKLEVEL SELECT
SCLK SCLK
SDOUT SDIN
2-12
Functional Description
2.2.4
Parallel Ports
parallel ports include ports which reside PhoX memory mapped register space. Ports reserved microcontroller. Port 5-bit output port with weak logic drive strong logic drive. output level given programmable through PORT4 register, which resides PhoX memory mapped register space. Outputs default reset. Port 5-bit input port, with interrupt generation change state keypad detection. interrupt maskable MIMSK1 register, becomes non-maskable Shutdown mode. value pins read from PORT5 register, PhoX memory mapped register space. Each port weak internal pull-up.
Table
Parallel Port Descriptions Name P1.7-P1.0 Type Model Description Port 8-bit port with internal pull-ups. Port pins written pulled high internal pull-ups used inputs. inputs, Port pins externally pulled source current because pull-ups. Port pins programmed generate interrupts response changes state. When driving high, ports actively drive only cycles, after which they weakly held high. drive levels always actively driven. P1[7:0] held weakly high during reset retain their programmed values Shutdown mode. They high impedance Emulation mode. pull-up associated with each individually disabled. Port weak pull-up, strong pull-down output port that drives value programmed PORT4 register retains that value when chip goes into Shutdown mode. Outputs default reset. Port input port with internal weak pull-up that read PORT5 register. change pins generates keyscan interrupt.
P4.4-P4.0
P5.4-P5.0
Functional Description
2-13
2.3.1
FORMATTER Communications System Block Diagram
Figure shows application Am79C440 PhoX Controller communications system. frame formatter prepares routes user data [consisting voice channel) control channel)], along with transmit radio controls time-division duplex (TDD) power level adjustment, radio transmitter. radio channel selection synthesizer configured synchronous serial port. voice data stream from radio receiver routed codec voice processing, while control data stream routed microcontroller control processing. frame formatter receives commands from microcontroller returns status information both polling interrupt forms. frame formatter obtains timing input from clock generator.
Figure
Communications System Block Diagram PhoX Controller
Data CODEC
Voice Data Channel)
Radio Control
Radio Transmitter
Microcontroller
Control Data Channel) Command Status
Frame Formatter
Data RSSI Radio Control Radio Receiver
Interrupt Controller
Status
Clock Generator
Master Timing
Synchronous Serial Port
Synthesizer Configuration
Synthesizer
2-14
Functional Description
2.3.2
Theory Operation
Figure complex baseband mathematical model transceiver that includes both baseband radio components.
Figure
Mathematical Model Transmission Path
Transmitter
spreading mixer X(t)
Diff Encode
X(t) pn(t)
S(t)
g(t)
ejct
Channel R(t) S(t) b(t) U(t) despreading mixer V(t)
Receiver W(t) f(t)e
X(t)
I.D.
Z(t) Diff Decode Slicer
Limiter
N(t)
e-j(ci)t
g(t)
pn(t
e-jit
Complex Limiter
Z(kT)
{Ak} complex-valued random symbol sequence representing input data stream, with elements differential symbols defined Ak-1. symbols conducted continuous-time complex baseband information signal x(t), where X(kTs) symbol period, 1/64 kHz). spectrum X(t) QPSK spectrum with nulls n/Ts. spreading mixer multiplies X(t) filtered version spreading signal pn(t). spectrum S(t), modulated carrier, periodic nulls n/Tc chip rate) strongly attenuated sidelobes filter g(t). Considering isolated differential symbol transmitted output Sk(t) train impulse responses, each separated written
complete output S(t) modulated differential symbols Sk(t) processed sequence,
S(t)
this analysis, channel response b(t) innocuous, signal receiver
R(t) N(t) Functional Description 2-15
where N(t) noise. purposes this model signal path, receive band filters approximated ideal bandpass filters, with effect signal other than linear phase shift. V(t) result despreading downconversion.
Expanding terms, V(t) written
V(t)
represents phase offset timing recovery; ideally, V(t) made (nearly) constant-envelope data-bearing portion attributable time-varying scaling factor dependent upon correlation
approximated short-term average power signal, which maximized timing recovery circuit operates RSSI power input steer zero, resulting V(t) optimally-high receive power. Because pulse shape g(t) imposed each chip, V(t) amplitude modulation chipping rate that rejected filter f(t). f(t) also attenuates noise outside narrowband signal bandwidth, leaving
limiter provides significant signal gain effect de-emphasizing noise when input high enhancing noise when very low. Ideally, output complex valued square wave (i.e., values with radian frequency phase time-varying symbol rate. limiter output then correlated against locally-generated reference using integrate/dump correlators determine signal content each these signal space vectors. data elements differential nature, phase difference between pairs consecutive symbols taken differential decoder result sliced.
2.3.2.1 Treatment Additive White Gaussian Noise (AWGN)
white character AWGN, added changed first bandwidth) bandpass filter that characterized band-limited white noise. despreading operation convolves this ideally rectangular noise power spectrum with MHz-bandwidth despreading spectrum, aliasing power noise over bandwidth. This results small reduction noise in-band. signal bandwidth significantly reduced, increasing within narrow signal bandwidth (realization processing gain) second filter. reasonably high SNR, limiter acts decision element reject low-level noise. effect AWGN constellation sliced circularly symmetric; therefore, standard probability-of-error estimates based function applicable. Noise manifested slicer constellation ways: symmetrically spreading constellation points circle away from ideal constellation point; drawing constellation points circle which they ideally toward origin.
2-16
Functional Description
2.3.2.2
Treatment Interferers
tone interferers, despreading resultant includes discrete spectral lines that receiver fooling RSSI optimization circuit, drawing-off recovery circuit, simply causing symbol errors. spectral lines occur intervals repetition rate sequence, this case kHz. Because narrow filter bandwidth approximately kHz, only spectral lines pass unattenuated limiter. amount interferers' energy represented those spectral lines depends precise location interfering tone with respect signal center frequency; therefore, performance varies with interfering tone frequency with selection sequence phasing.
2.3.3
Framing Format
frame time division duplex (TDD), with frame period place power surge noise (typically coupled from antenna microphone On-Off Keying) below voice band while minimizing audio path delay. timing structure shown Figure 2-8. time symbol periods provided allow time radio switch between Transmit Receive modes.
Figure
Timing Structure
Frame Symbols, 6-Symbol Time
TX_DATA
Transmit Frame Symbols
Transmitter Off-Time Symbols
RX_DATA
Receiver Off-Time Symbols
Receive Frame Symbols
frame format includes four logical channels: transparent voice channel error-controlled, packetized control channel framing synchronization channel (SYNC) preamble structure frame shown Figure 2-9. preamble provides settling time transients recovery circuit allows resolution ambiguity symbol-rate differential decoder.
Functional Description
2-17
Figure Symbols:
Bits:
Frame Format
SYNC
Frame Characteristics Symbol rate rate Frame rate Total channel transfer rate Effective channel transfer rate Total channel transfer rate Effective channel transfer rate
Rate Kbaud Kbit/s frame/s Kbit/s Kbit/s Kbit/s Kbit/s
2.3.4
Channel Access
Channel access TDD, frequency division multiple access (FDMA). frame rate FDMA spacing 902~928 band 1/Tc MHz. transmit-shaping filter radio reduces sidelobes allow second adjacent channel, directly-adjacent channel adjoining geographical areas supported. Figure 2-10 shows channel spacing. Channel center frequencies calculated
903.84
where
Figure 2-10
Heterodyne Channel Spacing
Second Adjacent Channel Adjacent Channel Channel Interest
2/Tc Fc(n-2) Fc(n) Fc(n+2)
2-18
Functional Description
2.3.5
2.3.5.1
Baseband Transmitter
Transmitter Block Diagram
Figure 2-11 block diagram baseband transmitter. Frame Timing generates frame timing, timing, chip timing. timing master, frame timing derived from master clock that referenced chip main clock input. timing slave, frame timing derived from long-term averaged slave clock receive frame synchronization pulse generated receiver. There four parallel-processing paths. Sequence Generator creates sequence, which synchronized frame timing. SYNC Channel Transmitter generates frame synchronization patterns. Channel Transmitter serializes nibbles from Channel FIFO calculates channel check field. Channel Transmitter sends packet data over channel. Scrambler applies scrambling code channels improve randomization. DQPSK line coder differentially encodes data. spreader applies sequence complex data stream. filters perform pulse shaping. DACs drive analog complex baseband pair TXI, well unmodulated sequence.
Figure 2-11
Clock Referenced MCLK Input
Baseband Transmitter Block Diagram
TXEN Clock Frame Sync TXMODE, TXEN_CFG Registers Frame Timing PAENB
Word Register
Sequence Generator
Filter Filter Spreader Filter
8051 Processor Data DTXEMPTY
TXBUF0-5 Channel Buffer
Transmitter
DQPSK Line Coder
SYNC0 SYNC1 Registers
SYNC, Preamble Transmitter
Scramble Register CODEC ADPCM FIFO
Scrambler
Channel Transmitter
Functional Description
2-19
2.3.5.2
Frame Timing
Frame Timing block multiplexes various subchannels into serial framed data provides timing basis transmit radio control signals. begin transmission TXMODE[7] register must set. Master Slave timing modes established with timing mode field TXMODE register. Master mode, Frame Timing block sources timing from master clock source that based clock input PhoX Controller. master clock divided produce (128-symbol), free-running frame. Radio Slave mode, Frame Timing block sources timing from clock frame rate sync signal that derived from receiver clock. start transmit frame after receive frame advanced relative ideal timing (which assumes zero path delay) symbol periods account symbol detection delays. This operation effect approximately evening intervals radio interface. transmit frame enabled only when receiver frame-locked timing master. synchronization mode allows synchronization timing master common frame synchronization signal. Additionally, there non-TDD timing mode development test.
2.3.5.3 Radio Interface Signals
transmitter block drives signals Table 2-10. also drives signal used receiver discussed Section 2.3.6.
Table 2-10
Radio Interface Signals Signal Description
TXI, DQPSK symbols represented complex baseband form. symbols internally spread digitally filtered through linear-phase, low-pass filter reduce sidelobes then converted into analog form before being presented single-ended outputs. They require single-pole external reconstruction filter eliminate sampling images multiples 15.36 MHz. TXEN Transmit power-on, active High Low. Programmable timing TXEN_CNFG enables: Active state eight symbol increments before data transmission begins. Inactive state eight symbol increments after data transmission ends.
PAENB
2.3.5.4
Transmit Generator
Generator produces 15-chip sequence synchronously with data symbol boundaries. sequence specified register.
2.3.5.5 Scrambler
frame-synchronized Scrambler created XORing output 7-bit maximal length shift register, shown Figure 2-12. principle function whiten data sequence. maximal length code produced feeding back result from terms back into term code restarted each transmit frame loading
2-20 Functional Description
user programmable seed value. scrambling code applied Preamble SYNC field. secondary function scrambler security: each frame, programmable seed reloaded from SCRAMBLE register, allowing different time-shifted versions sequence superimposed data sequence. Turn scrambler programming seed lockout code
Figure 2-12
Scrambler Architecture
Seed (SCRAMBLE Register)
Scramble Sequence
2.3.5.6
Line Coder
DQPSK line-coder encodes data differentially avoid requiring absolute phase reference receiver. DQPSK Encoder state machine shown Figure 2-13. Two-bit data symbols encoded phase difference between successive symbols. this figure, input bits noted arcs output DQPSK symbol represented state. output state summarized Table 2-9. symbols Gray-coded that error rate receiver half symbol error rate.
Figure 2-13
Differential QPSK Line Coder
Functional Description
2-21
Table 2-11
DQPSK Coding Summary Input Data Differential Phase Shift
Figure 2-14 shows transmitted constellation, phase-referenced local carrier. Constellation points correspond states state diagram. code located -135° allow amplitudes balanced represent mapping from logic levels normalized voltages: Logic -0.5 Logic +0.5
Figure 2-14
Output Constellation (Nondifferential)
PHASE REVERSE control TXMODE register swaps final output waveforms, effecting phase reversal compensate phase reversal that might occur radio selection high-side low-side mixing various upconversions downconversions. PHASE REVERSE control RSSI_DELAY register complementary function receiver.
2.3.5.7 SYNC Channel Preamble Transmitter
16-bit SYNC Channel transmitted every frame. contents defined SYNC1 SYNC0 registers, serializing SYNC1 first SYNC0 last. special measures protect against software changing SYNC1 SYNC0 fields during this operation. Preamble transmitter sends symbol sequence resulting transmission consecutive symbols 180° differential phase shifts.
2.3.5.8 Transmit Channel
Section 2.3.7.2, Channel Transmit Operation.
2-22
Functional Description
2.3.5.9
Transmit Channel
transmit channel path channels ADPCM-encoded voice from codec radio interface. path includes FIFO storage, check word calculation, timeslot assignment. When enable channel TXMODE register, channel output hexadecimal transmit FIFO stores ADPCM nibbles sampled rate from codec. Output burst-mode, with burst transmit frame. Each burst timeslot formatted shown Figure 2-15. figure, each ADPCM nibble identified separately.
Figure 2-15
Subchannel Format Bits QPSK Symbols
ADPCM transmission first. Parity calculated each pair ADPCM nibbles such that modulo-2 nibbles parity
2.3.6
Baseband Receiver
Figure 2-16 block diagram baseband receiver. Timing Recovery block uses part-time early-late algorithm chip timing recovery, based received correlation measured RSSI input. Initial synchronization done using maximum-likelihood detector. timing drives Sequence Generator, which shared transmitter.
Figure 2-16
Frame Sync Master
Baseband Receiver Block Diagram
Frame Sync Slave
Frame Timing
RXEN
Radio Control Timing
Channel Buffer Bytes) Sync Channel Receiver Descrambler
DATA
Buffer Full Interrupt/Status (DRXFULL) Sync Status
RX_IF1 RX_IF2
Baseband Receiver Front
Symbol Clock Clock
Channel Receiver
FIFO
FIFO
ADPCM CODEC
Error
RSSI
Timing Recovery
Channel Receiver
Error
RSSI_REF
Sequence Generator
Functional Description
2-23
Baseband Receiver Front demodulates RX_IF input, extracts timing information, decodes data bits. Front accepts narrowband (despread) data from limiter DQPSK format 10.7 center frequency. Radio Control Timing block generates control signal RXEN enabling receiver. Descrambler removes scrambling pattern routes descrambled signal channel receivers. SYNC Channel Receiver establishes validates recovered frame timing evaluating SYNC Channel contents. reports link synchronization status microcontroller initiates Frame Timing reference. Channel Receiver recovers channel nibbles from serial incoming stream evaluates check fields channel errors. FIFO adapts serial rate connection codec. Channel Receiver identifies packet headers, recovers channel packet from serial incoming stream, validates CRC. errors reported microcontroller. packet contents loaded Channel Buffer, which reports status microcontroller when becomes full. Frame Timing block demultiplexes received frame into SYNC, channels. case slave device, output receive frame synchronization pulse initiates transmit frame.
2.3.6.1 Radio Interface Signals
radio interface signals associated with receiver listed Table 2-12.
Table 2-12
Radio Interface Signals Signal Description During receive portion frame, this single-ended, balanced signal conducts sequence reception. requires external reconstruction filter eliminate sampling images that multiples 15.36 MHz. Receive power-on, active High Low. Programmable timing RXEN_CNFG enables: Active state eight symbol increments before expected receive frame begins. Inactive state eight symbol increments after expected receive frame ends. Receive signal from external limiter. signal levels expected differentially, with center frequency nominally 10.7 MHz, with tolerance. Receive signal strength indicator analog input recovering spreading code synchronization.
RXEN
RX_IF1, RX_IF2 RSSI
RSSI_REF Input RSSI ground reference. This signal used sense ground noise RSSI circuit.
2-24
Functional Description
2.3.6.2
Chip (PN) Synchronization
Clock Recovery block estimates frequency phase remote unit's chip timing, based upon correlation peaks detected Receive Signal Strength Indicator (RSSI).
2.3.6.2.1 Timing Slave Acquisition
phase acquisition state machine uses maximum likelihood (ML) algorithm determine within chip relative phasing remote local generators. detector optimizes recovery speed system. pure sliding-correlator threshold-crossing technique risks false correlations strictly onset transmissions. timing uncertainty remote transmitter necessitates multiple samples over window each candidate phase. specific implementation sequence three times through each candidate phases, dwelling symbol periods. During each dwell, timing loop takes arithmetic average three 9-bit samples, sample symbol. each dwell interval, averaged dwell sample compared initially-cleared peak hold register, larger values stored peak hold register. value phase candidate corresponding measured peak also stored. third dwell sequence, registers contain greatest measured RSSI level associated phase. sequence timing then driven with this best candidate timing until either SYNC pattern detected hardware timer expires. hardware timer indicates that detection output longer valid considering crystal reference differences between local remote units. SYNC pattern detected, timing recovery state machine advances from acquire fast track state. Expiration hardware timer causes state machine restart acquisition procedure. timing master begin transmission during course slave's acquisition routine, which case slave sample RSSI optimum phase. most cases, frame synchronization state machine prevents false frame lock suboptimal phase because requires confirmed repetition frame sync pattern. frame synchronization machine also locks enters slow tracking state, software compares RSSI BASELINE registers, which represent correlation values in-phase out-of-phase signals, respectively. small negative difference between RSSI BASELINE registers indicates false lock uncorrelated interferer in-band.
2.3.6.2.2 Timing Master Acquisition
timing master advantage having rough approximation timing incoming signal, although knowledge sequence timing known. timing master sequences through 1/2-chip phase candidates once over course frames, dwelling symbol periods each candidate. determination made second frame state machines progresses fast tracking state. signal present, SYNC detected frame synchronization state machine locks. SYNC detected, acquisition process repeats subsequent frames until SYNC finally found. anticipated delay link setup time from slave master acquisition.
Functional Description
2-25
total expected link setup budget calculated follows:
Slave wakeup/scan interval sync slave master Frame sync slave master Slave transmitter response time sync master slave Frame sync master slave Total Tscan 4.125 0.2-2 Tslv_tx Tscan Tslv_tx 12.125
2.3.6.2.3
Timing Loop
tracking loop premised fact that remote local sequence generators operating system clocks that accurate within nominal crystal reference. resulting possible end-to-end offset translates ns/frame, approximately 3.9% chip frame. timing loop attempts track incoming sequence timing using modes (fast slow). Both modes used timing master timing slave device receivers. Fast Tracking Mode: Fast tracking designed correct ±1/2 chip offset resulting from coarse decision. timing slave device, Fast Track mode runs exactly frames after frame synchronization detected. During those frames, separate evaluations made relative correlation advanced retarded phases, each followed single adjustment Each evaluation average RSSI measurement made four consecutive symbols. size early/late step (±1/16 ±1/4 chip) programmed user register. Slow Tracking Mode: Slow tracking designed long-term synchronization maintenance differs master slave devices. consists short-term error-proportional loop long-term integrated error loop capable sustaining synchronization within ±1/2 chip assuming maximum frequency difference between remote local generators. slave device, long-term integrated error loop compensates frequency offset between master slave internal reference clocks. master, disabled. error integrator measures long-term frequency offset remote local generators accumulating direct error term over course frames ms). integrated value then applied during subsequent period. absence noise multipath, operation integrator causes direct error term converge toward zero. integrator output applied during interval avoid complications interaction with timing direct error feedback path. integrator itself saturates counts, which applied over course frames, thereby limiting long-term response ±20.3 ppm. decoder distributes adjustments fairly uniform fashion over 32-frame interval. proportional error term allows loop track optimal RSSI without inducing undue jitter accommodates shifts impinging multipath signals. slave, error calculated acted upon once frame, using relative RSSI levels corresponding early late versions sequence that tested beginning frame. Each timing modification calculation made from samples each early late timing. loop responds with adjustment only samples consistent within measurement, implemented with divide-by-15/16/17 counter from
2-26
Functional Description
15.36 reference clock. Thus, direct error path loop allows adjustment frame ppm). facilitate fade detection detection in-band interferers, slow track mode evaluates (Measurement) field using sequence timing that chip intervals phase with desired timing. Thus, field desirable function dynamically maintaining measurement uncorrelated noise, allowing detection loss synchronization well in-band interferers range-limited SNR. measured RSSI values SYNC fields updated each frame RSSI BASELINE registers, respectively, software detection response. early/late timing loop software-configured through TIMING_LOOP registers, which allow selection early/late step size visibility control over timing acquisition state. RSSI register reports most recent RSSI level, which useful during free channel scanning.
2.3.6.2.4 RSSI Subsystem
RSSI subsystem includes sample/hold circuit, 9-bit A/D, sample-timing control unit. timing interface shown Figure 2-17.
Figure 2-17
RSSI Timing Diagram
RX_EPOCH
RSSI_DELAY
RSSI_SH
RSSI Diagram
RX_EPOCH symbol-rate signal that times beginning sequence receiver. RSSI_SH active-low sample-hold control (low track); timing rising edge programmable software RSSI_DELAY register. Sample/Hold Circuit: RSSI input buffer high-impedance voltage input that feeds internal track/hold circuit. input voltage range 0.2~2.2 with supply. track/hold period 15.625 Input expected DC-coupled. symbol-rate-sampled RSSI feeds input.
Functional Description
2-27
2.3.6.2.5
Chip-Rate Filter
chip-rate filter applied TXI, TXQ, received signals. PN-spreading sequence output filtered Shape final transmitted spectrum, allowing FDMA usage band consistent with channel access plan. Reject out-of-channel signals receiver. circuit filters sequence, which toggling kHz, with 8th-order Bessel low-pass characteristic with 3-dB frequency kHz. Bessel filter (maximally linear phase) utilized desirable time-domain characteristics. filter implemented with direct digital synthesis (DDS) because allows faithful duplication waveform each link. When disabled inactive, filter outputs approach approximately VCC/2.
2.3.6.3 Receiver Front
Baseband Receiver Front shown Figure 2-18. receiver includes 10.7 MHz-460 downconverter carrier recovery circuit, which tracks time-varying carrier. matched filter implemented pair correlators followed symbol-rate integrate/dump circuits. Detection differentially coherent, meaning that recovered symbol phase difference between consecutive received phases. Even recovered carrier offset disturbed fade link initialization, differentially coherent receiver continues receive data, although noise margin degraded.
Figure 2-18
Baseband Receiver Front
10.24
Carrier Recovery
RX_IF Down-Convert RDATA
10.7
Matched Filter
Differential Decoder
Slicer
Clock Epoch
Symbol/Bit Clock Timing
Symbol Clock
RBITCLK
2.3.6.3.1
Carrier Recovery
carrier recovery block tracks incoming generates quadrature carrier square waveforms correlation with received feedback term includes integrator such that error output phase detector converges zero frequency offset compensated. integrator also allows operating frequency held constant through transmit portion frame timing. integrator value read written microcontroller. analog-domain transfer function loop filter
2-28
Functional Description
which represents unity-gain, second-order low-pass filter with zero kOkDkI/kOkDkP. following gain constants above equation, normalized phase detector gain degrees:
radians
following table lists, combinations natural frequency (n), damping factor lock-in range (L). lock-in time (TL), pull-in time (TP) frequency step kHz. Note that lock-in time defined damping factors greater than equal unity. Optimal combinations based damping factors close 0.707 highlighted bold. equations various parameters shown below. They based theory described Phased-Locked Loops: Theory, Design, Applications, Edition Roland Best.
Table 2-13
Recovery Circuit Parameters log2(kI) log2(kP) (rod/s) 8.87e+04 6.27e+04 4.43e+04 3.14e+04 2.22e+04 1.57e+04 1.11e+04 7.84e+03 1.35e+00 1.91e+00 2.71e+00 3.83e+00 5.41e+00 7.65e+00 1.08e+01 1.53e+01 (rod/s) 2.40e+05 2.40e+05 2.40e+05 2.40e+05 2.40e+05 2.40e+05 2.40e+05 2.40e+05 TL(s)
2.58e-06 5.16e-06 1.03e-05 2.06e-05 4.13e-05 8.26e-05 1.65e-04 3.30e-04
8.87e+04 6.27e+04 4.43e+04 3.14e+04 2.22e+04 1.57e+04 1.11e+04 7.84e+03
6.77e-01 9.57e-01 1.35e+00 1.91e+00 2.71e+00 3.83e+00 5.41e+00 7.65e+00
1.20e+05 1.20e+05 1.20e+05 1.20e+05 1.20e+05 1.20e+05 1.20e+05 1.20e+05
7.09e-05 1.00e-04
5.16e-06 1.03e-05 2.06e-05 4.13e-05 8.26e-05 1.65e-04 3.30e-04 6.61e-04
Functional Description
2-29
Table 2-13
Recovery Circuit Parameters (continued) log2(kI) log2(kP) (rod/s) (rod/s) TL(s)
8.87e+04 6.27e+04 4.43e+04 3.14e+04 2.22e+04 1.57e+04 1.11e+04 7.84e+03
3.38e-01 4.78e-01 6.77e-01 9.57e-01 1.35e+00 1.91e+00 2.71e+00 3.83e+00
6.00e+04 6.00e+04 6.00e+04 6.00e+04 6.00e+04 6.00e+04 6.00e+04 6.00e+04
7.09e-05 1.00e-04 1.42e-04 2.00e-04
1.03e-05 2.06e-05 4.13e-05 8.26e-05 1.65e-04 3.30e-04 6.61e-04 1.32e-03
8.87e+04 6.27e+04 4.43e+04 3.14e+04 2.22e+04 1.57e+04 1.11e+04 7.84e+03
1.69e-01 2.39e-01 3.38e-01 4.78e-01 6.77e-01 9.57e-01 1.35e+00 1.91e+00
3.00e+04 3.00e+04 3.00e+04 3.00e+04 3.00e+04 3.00e+04 3.00e+04 3.00e+04
7.09e-05 1.00e-04 1.42e-04 2.00e-04 2.83e-04 4.01e-04
2.06e-05 4.13e-05 8.26e-05 1.65e-04 3.30e-04 6.61e-04 1.32e-03 2.64e-03
8.87e+04 6.27e+04 4.43e+04 3.14e+04 2.22e+04 1.57e+04 1.11e+04 7.84e+03
8.46e-02 1.20e-01 1.69e-01 2.39e-01 3.38e-01 4.78e-01 6.77e-01 9.57e-01
1.50e+04 1.50e+04 1.50e+04 1.50e+04 1.50e+04 1.50e+04 1.50e+04 1.50e+04
7.09e-05 1.00e-04 1.42e-04 2.00e-04 2.83e-04 4.01e-04 5.67e-04 8.02e-04
4.13e-05 8.26e-05 1.65e-04 3.30e-04 6.61e-04 1.32e-03 2.64e-03 5.28e-03
8.87e+04 6.27e+04 4.43e+04 3.14e+04 2.22e+04 1.57e+04 1.11e+04
4.23e-02 5.98e-02 8.46e-02 1.20e-01 1.69e-01 2.39e-01 3.38e-01
7.50e+03 7.50e+03 7.50e+03 7.50e+03 7.50e+03 7.50e+03 7.50e+03
7.09e-05 1.00e-04 1.42e-04 2.00e-04 2.83e-04 4.01e-04 5.67e-04
8.26e-05 1.65e-04 3.30e-04 6.61e-04 1.32e-03 2.64e-03 5.28e-03
2-30
Functional Description
Table 2-13
Recovery Circuit Parameters (continued) log2(kI) log2(kP) (rod/s) 7.84e+03 4.78e-01 (rod/s) 7.50e+03 TL(s) 8.02e-04
1.06e-02
8.87e+04 6.27e+04 4.43e+04 3.14e+04 2.22e+04 1.57e+04 1.11e+04 7.84e+03
2.11e-02 2.99e-02 4.23e-02 5.98e-02 8.46e-02 1.20e-01 1.69e-01 2.39e-01
3.75e+03 3.75e+03 3.75e+03 3.75e+03 3.75e+03 3.75e+03 3.75e+03 3.75e+03
7.09e-05 1.00e-04 1.42e-04 2.00e-04 2.83e-04 4.01e-04 5.67e-04 8.02e-04
1.65e-04 3.30e-04 6.61e-04 1.32e-03 2.64e-03 5.28e-03 1.06e-02 2.11e-02
Implementation discrete time, discrete-valued arithmetic. three operating modes: Acquisition, Tracking, Hold. Recovery circuit does require calibration mode fully digital implementation phase detector, loop filter, digitally-controlled oscillator. Acquisition mode entered each time device acquires lock exits Tracking mode when recovered frequency sufficiently close actual input frequency, such that SYNC channel code been detected consecutive receive frames. Acquisition need initiated every attempt link re-establishment. circuit allows most recent frequency compensation information used re-establishment after fade. Acquisition mode, low-pass response input frequency change, with characteristics determined values loaded into KPF[2:0] KISF[2:0] fields IFLOOPA register. Tracking mode, utilizes values loaded into KPS[2:0] KISS[2:0] fields IFLOOPB register determine tracking response. Generally, wider bandwidth selected Acquisition mode, while narrower bandwidth selected Tracking mode. Hold mode, which controlled software, input error code allowed adapt, that continues produce last known frequency sustain fades. testing purpose, circuit supports software forcing loop filter into state writes DCOMSB DCOLSB registers.
Functional Description
2-31
2.3.6.4
Matched Filter
complex-valued matched filter implemented pair correlators integrate/dump circuits shown Figure 2-19. symbol paths windowed time allow integration over integral number cycles orthogonality exclude symbol transition intervals during which noise capture limiter degrading symbol correlation. width time window programmable IF_DELAY register. Dump timing related sequence timing programmable parameter IF_DELAY register.
Figure 2-19
Matched Filter Block Diagram
REF(Q) REF(I) DUMP
Integrate/ Dump
Input Symbol Eval Window
MF_I Complex Output
Integrate/ Dump
MF_Q
2.3.6.4.1
Differential Decoder
differential decoder allows modest receiver phase constellation rotation frequency offsets between remote local references expense noise margin degradation. drawback doubling noise variance slicer input, resulting loss about calculations comparison optimal coherent receiver. differential decoder calculates phase difference between current sample previous sample.
2.3.6.4.2 Slicer
slicer quantizes recovered differential symbol into four two-bit codes. phase reversal realized setting Phase Reverse RSSI_DELAY register.
2.3.6.4.3 Symbol Quality Measurement
most significant bits decision margin slicer reported QUALITY register. value reported unsigned magnitude representing margin decision quantize most recent symbol into given quadrant. Small erratic numbers indicate least following conditions: Presence interfering noise range Loss synchronization recovery circuit Poor configuration IF_DELAY register (for more information, refer Section 2.3.6.4.4, Symbol Clock Timing) Mismatched sequence programming either link
2-32
Functional Description
2.3.6.4.4
Symbol Clock Timing
transmitter, epoch aligned time with baseband symbols. baseband symbol paths undergo identical delay until they diverge despreading mixer receiver. After despreading mixer, removed narrowband signal passes through single greatest delay element system: narrowband filter. After filter subsequent limiter, symbol boundaries limited signal delayed from receive epoch, delay value fixed dominated filter. receive symbol clock drives dump timing matched filters. relationship receive epoch programmed INTEGRATE/DUMP DELAY field IF_DELAY register matched delay narrowband filter strip. appropriate value determined empirically setting transmit/receive pair non-TDD test mode configuring TXMODE RXMODE registers, observing relationship between symbol boundaries apparent output narrowband filter MF_WINDOW calibration output BPD0 when BDPMUX register configured calibration mode. Adjust MF_WINDOW center time around symbol boundaries. Given rough approximation INTEGRATE/DUMP DELAY, further refinement made desired with automatic calibration routine maximize average value reported QUALITY register over values delay around original approximation, given controlled input conditions. minimum, receiver non-TDD mode, input high, input valid QPSK modulation.
2.3.6.5 Frame Synchronization
Frame synchronization acquired recognition SYNC channel code word. procedure occurs each time chip timing lost, example, upon link initialization link reestablishment. Frame synchronization monitored hardware validate frame synchronization during link. frame synchronization state machine initially reset ACQUIRE state. SYNC occurrence counter also cleared. timing slave, serial data compared SYNC pattern. Upon first occurrence valid SYNC pattern data stream, counter incremented receive frame timing associated radio timing set. timing master initiating link expecting response, only serial data within broad window around expected location SYNC pattern evaluated. When SYNC pattern recognized within that window, counter incremented receive frame timing associated radio timing set. state machine then enters TRACK state. When TRACK state, frame sync circuit compares each subsequent SYNC channel expected SYNC pattern either increments counter matches decrements mismatches. counter saturates maximum minimum timing slave, when counter saturates state machine enters LOCKED state. timing master, machine skips TRACK state enters directly into LOCKED state. When LOCKED state, receiver remains that state until software clears state machine. assist deciding when reestablish after link drops, FLAG SYNCSTAT register goes High whenever center value falls minimum, LOCKED state. Software expected this short-term status FLAG distinguish between temporary irrecoverable dropouts.
Functional Description
2-33
violations measured timing master only occurrence expected SYNC timing moving beyond time-limited window, location which upon initial acquisition width which fixed bits. window allows some drift fades, multipath, range variations. receive Channel operational TRACK LOCKED states. receive Channel operational only LOCKED state. master, transmit channels unaffected receiver state. slave, however, transmitter enabled only LOCKED state. frame synchronization state machine interacts with recovery state machine such that software involvement minimized link establishment. master, frame synchronization state machine fails identify SYNC pattern acquisition state, entire link acquisition process automatically restarted; i.e., repeats every until either link established software halts slave, frame sync state machine fails find SYNC pattern confirm subsequent frames before expiration hardware timer ms), entire link acquisition process also automatically restarted.
Figure 2-20
Frame Synchronization State Machine Acquire
(SLAVE, From state (RESET RESYNC)/Clear (Master, 1)/Set
Violation
FLAG (Master VIOL)/Clear
Track
Locked
Notation: (input, input,.input/output, .output) Frame sync counter
2.3.6.6
Descrambler
descrambler applies inverting signal received frame-locked data stream, driven same maximal length shift register used transmitter. descrambling pattern applied SYNC timeslot. descrambler operates TRACK LOCKED frame synchronization modes only. When receiver frame synchronization ACQUIRE mode, descrambling applied. scrambler also disabled modes.
2.3.6.7 Receive Channel
Channel Receiver performs parity checks received ADPCM nibbles well conditional muting, passes data receive FIFO. Output receive FIFO read regular rate codec. When enable RXMODE register, Channel output hexadecimal
2-34
Functional Description
code inserted when parity errors detected B-channel error blanking feature enabled RXMODE register. most recently received nibbles buffered that they both zeroed should parity error detected. three more parity errors detected frame, channel error flag becomes active QUALITY register, rest frame muted forcing ADPCM words Subsequent frames muted until frame received with zero error. When channel error blanking feature disabled, channel error flag functions, voice data passed codec without change.
2.3.7
Channel Operation
Channel packet-data transport channel. Outgoing packets initialized software. When there packets sent, channel filled with idle code.
2.3.7.1
Packet Structure
Channel packet, shown Figure 2-21, requires baseband frames ms). includes 16-bit new-packet identifier (SYNCD) 64-bit code word (comprising 48-bit information field 16-bit check field). transmission order each information byte least-significant first.
Figure 2-21
Packet Structure Order Transmission Time Frame Frame Frame Frame Frame Frame Frame Frame Frame Frame SYNCD SYNCD Byte Byte Byte Byte Byte Byte DRXFULL, DRXERR, DRXOVF DTXEMPTY Transmitter Interrupt Status Receiver Interrupt Status
2.3.7.1.1
SYNCD
16-bit SYNCD pattern prefixes every channel message. inserted automatically transmitter serves beginning-of-message indicator receiver. SYNCD pattern 1100 0100 1101 0111, chronological order.
2.3.7.1.2 Information Bytes
information bytes loaded software into transmit buffer TXBUF read software from receive buffer RXBUF.
Functional Description 2-35
2.3.7.1.3
Parity
Error control channel done application cyclic redundancy check (CRC) each packet software-driven retransmission request upon error detection. DRXERR DCHSTAT register identifies when packet received with error. generator polynomial code
g(x)
coded transmitted packet systematic consists information bits loaded transmit buffer followed 15-bit field. field calculated first associating information bits coefficients polynomial then multiplying that polynomial X15. resultant divided generator polynomial 15-bit remainder, with last (associated with inverted, field. single parity bit, calculated that 64-bit final coded packet even Hamming weight, appended coded packet catch odd-weight error-patterns. software development, transmit calculation disabled intentionally generate error faults receiver. feature controlled TXMODE register, bits [6,4].
2.3.7.1.4 IDLE_D
When channel packets being transmitted, channel contains continuous stream zeros.
2.3.7.2 Channel Transmit Operation
When packet transmitted, software loads transmit buffer with bytes code word. Writing byte starts transmission, provided ENABLE control (TXMODE[7]) been previously set. transmitter first drives SYNCD pattern begins transmission data bytes contained buffer. When code-word bytes have been sent, transmitter sends field appends parity bit. channel transmitter drives IDLE_D after transmission been initiated transmit buffer been emptied. transmit buffer cannot programmed transmit IDLE_D because automatic generation. When transmit buffer been emptied, formatter propagates DTXEMPTY interrupt central interrupt controller through MISCR0 register, which subject masking MIMSK0 register. DTXEMPTY status reported DCHSTAT register occurs when last buffer byte read from buffer into serializing shift register, approximately before packet transmission. consecutive code words transmitted without intervening frames IDLE_D bits (i.e., maximum throughput condition), next code word must written within DTXEMPTY interrupt. After first code word packet transmitted, transmitter continues transmission buffer been reloaded, transmitter sends IDLE_D after check field parity bit.
2.3.7.3 Channel Receive Operation
Am79C440 PhoX Controller acquires channel synchronization locating SYNCD channel stream. hardware clears channel synchronization whenever frame synchronization state machine enters ACQUIRE state. channel synchronization begins only when frame synchronization enters TRACK LOCK state. After recognizing SYNCD pattern, receiver starts collecting following bytes channel data that make code word. channel information bytes loaded receive buffer. next bits parity routed CRC/Parity check circuit, which generates DRXERR flag error detected. check field reception, DRXFULL interrupt notifies
2-36 Functional Description
software that receive buffer contains code word. check field, however, loaded into receive buffer. DRXERR DRXFULL flags reported DCHSTAT register, DRXFULL forwarded interrupt controller interrupt MISRC0 register, which masked MIMSK0 register. Upon complete reception packet, hardware automatically clears channel synchronization begins seeking next SYNCD. software fails read buffer contents before arrival Byte 0[0] next packet, overflow flag (DRXOF) generated packet reported DCHSTAT. packet allowed overwrite previous packet stored buffer. read timing restriction implies maximum allowable software read latency 2.39 assuming maximum packet arrival rate, i.e., minimum delay zero frames between packets bits frame SYNC bits).
2.3.8
System Synchronization
system synchronization provides robust behavior conditions fading, variable range, variable propagation delay component tolerance allows either handset-to-base handset-to-handset communication. transmitter either timing master slave, depending system requirements. master transmits data rate based baseband clock input frequency, which tied radio crystal with 10-ppm tolerance. receiver always recovers timing phase-locking remote unit. receiver link initiation timing slave device. receive timing driven recovered clock based RSSI measurements frame synchronization. slave conducts transmission that timed recovered long-term averaged receive clock. This recovered receive clock does jitter during transmission, adjust much receive frame. initialization frame synchronization, master receives SYNC channel pattern within time-limited window (-2/+4 symbol periods) around expected timing, which makes allowances various radio architectures round-trip propagation delays. implementation master/slave timing control shown Figure 2-22. control register TXMODE[1:0] determines whether device master slave. selects either recovered clock (radio slave) free-running source based crystal reference (master) transmitter clock. applications that require multiple base station transmissions synchronized, mode register also allows master device synchronize with frame clock input (not shown) rather than free running source.
Functional Description
2-37
Figure 2-22
Master/Slave Timing Implementation
Unit (Master) Transmitter Channel
Receiver Slave
Unit (Slave)
Free-Running Source
TXMODE[1:0] "SLV"
TXMODE[1:0] "MAS"
Free-Running Source
Receiver Slave
Transmitter
Channel
2.3.9
Crystal Trimming
voltage output 6-bit driving XTALDAC programmed XTALDAC register intended drive varactor purpose tuning local oscillator frequency best performance radio baseband receiver. general, tuning algorithm does following: Reads recovery registers INTMSB INTLSB, which reflect frequency received downconverted (nominal), referenced local crystal, Changes voltage, shift received toward Consider whether high-side low-side mixing used determine direction voltage change. Also, notice characteristics pulling operation when designing algorithm. example, with wide loop bandwidth allows transients settle quickly that receive frame, frequency carrier (approximately kHz) reflects actual frequency remote transmitter, referenced local crystal. remote crystal higher frequency both transmitter receiver low-side mixing, resulting higher transmit center frequency higher receive kHz, then changing increase local crystal frequency reduces frequency Repeated measurements changes made until measured frequency matches locally generated recovered natural frequency 457.265 kHz, indicated convergence INTMSB INTLSB registers toward zero. second example, narrow loop bandwidth, that transients significantly decay during course frame. this case, absolute center frequency transmission determined effects transmitter's crystal frequency time-varying effect pulling. possible receiver recovery circuit separate effects crystal offset pulling, convergence INTMSB INTLSB toward zero appropriate algorithm.
2-38
Functional Description
2.3.10
2.3.10.1
Link Quality Assessment Subsystem
RSSI/Correlation Indicators
Current RSSI samples baseline available polling RSSI BASELINE registers. Both registers retain most recent sample value taken during receive subframe. When difference between RSSI BASELINE values decreases, either strong interference, loss synchronization, deep fade indicated. Further inference made absolute values registers. small RSSI value indicates fade, whereas large RSSI value with small RSSI-BASELINE difference indicates strong interferer loss synchronization.
2.3.10.2 Energy Indicators
slicer margin field QUALITY register reflects decision margin data slicer receiver.
2.3.10.3 Violation Indicator
When frame synchronization locked, received SYNC channel position timing master receiver wanders outside window expectation (usually phase-lock loss remote timing slave), SYNC channel receiver leaves LOCKED state goes VIOLATION state, which reported SYNC_CNTRL register FLAG bit. remains this state until software clears condition resynchronizing terminating link.
2.3.10.4 SYNC Channel Indicators
SYNC channel receiver state available polling SYNC_CNTRL register. Additionally, FLAG interrupt generated when SYNC channel state machine detects consistent loss pattern detection.
2.3.10.5 Channel Indicators
three more channel parity errors detected single frame, Channel Error Indicator flag QUALITY register.
2.3.10.6 Channel Indicators
channel CRC/Parity errors reported DCHSTAT register.
2.3.10.7 Voice Channel Blanking Muting
hardware capable detecting single errors given subchannel ADPCM nibbles parity) blanking (zero-stuffing) those ADPCM samples. software must configure RXMODE enable channel error blanking utilize this feature. Muting occurs when three more parity error found frame. remainder channel frame 1-stuffed (ADPCM zero signal code), subsequent frames until frame with fewer errors received. muting feature enabled when error blanking RXMODE register. software must determine, basis various link quality assessment registers, when apply longer mutes. Mutes realized either disabling receive channel RXMODE register attenuating voice signal codec RXATTN register.
2.3.10.8 Automatic Resynchronization
device automatically restarts synchronization upon failure initial synchronization. Acquisition been successfully made, however, software responsible resynchronizing terminating. master, restarts occur intervals. slave, restarts occur intervals.
Functional Description 2-39
2.3.11
Free Channel Scanning
perform free channel scanning, checking whether given channel occupied before beginning transmission ENABLE SCAN TIMING_LOOP register place receiver non-TDD slave mode. ENABLE SCAN keeps tracking loop idle allows continuous conversions RSSI signal identify occupied channels rapidly. RSSI register average four consecutive RSSI conversion values updated during scan. BASELINE register, representing unfiltered RSSI output, updated during scan. non-TDD slave mode forces receiver state machine remain locked state with receiver enabled. detected receive data ignored.
2.3.12
Parameter Configuration Calibration Mode
initialize radio link, configure several parameters, most them receiver. calibration mode, programmed BDMUX register, allows several timing signals driven pins order facilitate parameter configuration. following steps configure parameters using transmitting PhoX radio receiving PhoX radio. Table configuration calibration signal pinout. Configure transmitter non-TDD BERT mode enable transmission setting TXMODE register Configure BDMUX register Debug that BDP0 drives EPOCH signal. Configure receiving (slave) device non-TDD BERT mode enable reception setting RXMODE register TXMODE[1:0] default register programming both ends link. slave, configure BDMUX[7:5] Debug mode. EPOCH signal appears BDP1 pin. Validate sequence tracking observing EPOCH kHz) synchronization master EPOCH kHz). slave EPOCH tracking master EPOCH, there fundamental problem, such very large difference crystal frequencies broken transmission RSSI path. master, reconfigure BDP[3:0] pins programming BDPMUX[7:5] BERT mode. sequence generator clocked TBERCLK output (BDP0 pin), driving TBERDATA input (BDP1 pin). slave, configure BDMUX[7:5] Calibration mode. RSSI_SH signal appears BDP2 pin. Given that epochs tracking Step above, observe relationship between RSSI signal eye-diagram RSSI_SH signal. Adjust RSSI_DELAY register move rising edge RSSI_SH near peak RSSI eye. slave, RSSI DELAY inhibit inversion operation, which balances receive signal. This inversion obstruct visibility symbol boundaries before calibration made. despreader temporarily degraded content signal. Observe timing relationship between WINDOW output BDP0 symbol boundaries apparent narrowband 10.7 receive before limiting. Adjust INTEGRATE/DUMP DELAY field IF_DELAY register until high portion WINDOW signal centered over middle symbol portion centered over symbol transitions. Adjust WINDOW pulse width reject noisy symbol boundaries. Performance best high time WINDOW approximately multiple carrier period 2.17 Revert RSSI DELAY zero normal, DC-balance operation despreader.
2-40
Functional Description
slave, reconfigure BDPMUX register bits [7:5] BERT mode observe outputs RBERCLK RBERDATA. RBERDATA identical transmitted pattern TBERDATA. repeating pattern such 01001111 01001111 validate QPSK phase inversion selection. this pattern comes 10001111 10001111 10110110 10110110 there inversion data phase, attributable some selection high-side low-side mixing. this, change configuration either PHASE REVERSE RSSI_DELAY register slave PHASE REVERSE TXMODE register master. Calibration parameters complete. Configure these parameters both master slave devices before connection mode.
2.4.1
AUDIO FUNCTIONS Audio Front
Figure 2-23 shows audio front end. Because internal nodes limited ±0.5 swing, gain configuration should carefully considered. possible saturate summing point addition more large signals, resulting clipping distortion. input typically used microphone PSTN input enabled programming AINCTR register, [7]. input must coupled followed gain stage programmable either AINCTR register. maximum internal signal level gain stage output ±0.5 therefore, maximum input level 0.36 gain. AOP/AON differential output pair normally used handset earpiece base station PSTN driver. drives differential load minimum ±2.0 (differential). Capacitance from either ground must exceed pins enabled AOMUX[7] connected codec D/A, well sidetone path (AIN) under control AOMUX[4]. Sidetone gain independently controlled STCTR register.
Figure 2-23
Audio Front
AINCTR +3dB, +18dB, coupled, +/-0.36 peak Sidetone STCTR -12dB, -18dB, AOMUX[7] 0.5V peak
2.0V diff, peak R(load) Ohms
AOMUX[4] AOMUX[0]
0.5V peak
Functional Description
2-41
2.4.2
ADPCM Codec
codec, shown Figure 2-24, performs kbps ADPCM conversion accordance with CCITT G.721. codec enabled setting MECTR0[6] timed frame clock enabled MECTR1[4]. codec will function this frame clock disabled. codec DTMF generator registers, except DSPCTR, default unknown values must initialized before enabling codec. dual tone generator discussed separately. Attenuations transmit receive voice paths programmed TXATTN RXATTN registers. codec acts ADPCM transcoder DSPCTR configured transcoder mode. Data conducted through MON0-MON3 pins, which must further configured TST1 TST0 pins.
Figure 2-24
Codec Block Diagram
Noise Suppression
Noise Suppression Trigger from Formatter Receiver kbps ADPCM Input from Formatter Receiver kbps Output MON2 ADPCM decoder
mute Analog Output Audio Front
Attenuation (RXATTN)
Interpolator
A-Law Output Port Dual Tone Generator Transmit Dual Tone (DTMF)
Receive Dual Tone (DTMF)
kbps Input from MON3 kbps ADPCM Output Formatter Transmitter
A-Law Input Port
ADPCM encoder
Attenuation HPF, LPF, (TXATTN) Reject
Decimator
Analog Input from Audio Front
DSPCTR Register
Note: External filtering recommended remove sampling images drop output noise levels, particularly around kHz. This filtering part ordinary hybrid interface. Part function interpolator shape output noise that noise energy shifted frequency from voice band toward kHz, allowing simple external filtering. interpolator exhibits undesirable limit cycle when data been processed input stream becomes zeroes (e.g. RXATTN programmed state). converter 7-bit converter noise shaper affects least significant bit. characteristics limit cycle that operates least significant that results data dependent. some cases, limit cycle output nearly random, creating uniform noise floor, others limit cycle output more periodic nature, creating harmonics below full scale 30-90 range. Harmonic peaks below approximately (max) below full scale.
2-42
Functional Description
2.4.3
Noise Suppression
Noise suppression feature that recognizes noise ADPCM receive data stream mutes receive path response. When codec enabled normal mode, DSPCTR[7] enables noise suppression.
2.4.3.1
Muting Trigger
muting trigger (MUTETRIG) generated Formatter receiver response Channel parity errors. occurrence trigger sets status NSCTR[7] causes interrupt MISRC0[5].
2.4.3.2 Muting Response
NSCTR[1:0] defines algorithm responds noise indicators, shown Figure 2-25. bits control number size attenuation steps applied receive data muting sequence. Noise generally arrives bursts, four columns Figure 2-25 show response noise suppression algorithm multiple consecutive noise events (triggers), expressed function mute sequence, NSCTR[1:0]. Each trigger causes increased muting until maximum muting given programmed mute sequence reached. MUTE register controls length each attenuation step during recovery. each trigger, mute length counter restarted, counter reaches programmed endpoint, attenuation step removed. Figure 2-25 assumes that noise triggers occur near beginning sequence, that none occur during recovery phase. trigger occurs during recovery phase, muting again increases step event until maximum muting reached mute length counter restarted.
Functional Description
2-43
Figure 2-25
Noise Suppression Muting Sequence
trigger Full Mute Full Mute triggers Full Mute triggers Full Mute Full Mute triggers more
Mute sequence
Mute sequence
Full Mute
Full Mute
Full Mute
Mute sequence
Full Mute
Full Mute
Full Mute
Full Mute
Mute sequence
Full Mute
Full Mute
Full Mute
Full Mute
2.4.4
Dual Tone Generator
dual tone generator codec feature generating (single frequency), DTMF (dual tone multi-frequency) alert tones. requires codec enabled MECTR0[6] supplied with frame clock MECTR1[4]. Figure 2-26 block diagram dual tone generator. Each tones programmable frequency amplitude. frequency tone programmed T1FR1, T1FR2, T1FR3 amplitude, relative digital full scale, programmed T1AR. Likewise, tone defined T2FR1, T2FR2, T2FR3, T2AR. tones summed form dual tone signal. Care should taken when programming amplitudes T1AR T2AR ensure that summed signal does overflow digital full scale, resulting clipping distortion. example, tone amplitude (0.5 full scale) tone amplitude (0.707 full scale), peak summed value 1.207 full scale, which will clipped. Therefore, amplitudes must adjusted down avoid distortion. tones added transmit receive paths codec, with independent gain adjustment each path. Again, digital overflow should avoided summing points consideration expected voice levels transmit receive paths programmed transmit receive tone levels. TTAR programmed loss applied summed dual tone signal before summed with transmit audio data. RTAR loss applied summed dual tone signal before added receive audio data.
2-44
Functional Description
Programming Notes: dual-tone generator registers must initialized before codec enabled. Writes dual-tone generator registers buffered such that possible update locations simultaneously. Dual-tone registers, loaded software, advanced into digital signal processor until RTAR address written. Therefore, write dual tone register must accompanied write RTAR, which must occur DTMF register write sequence.
Figure 2-26 Dual-Tone Generator Block Diagram
Tone Frequency T1FR1 T1FR2 T1FR3 Tone Amplitude Receive Tone Attenuation
T1AR
Tone
RTAR
codec receive path summer
Tone Frequency Tone Amplitude T2FR1 T2FR2 T2FR3
Dual Tone Waveform
TTAR T2AR Tone Transmit Tone Attenuation
codec transmit path summer
2.4.5
Tone Ringer
tone ringer generates digital square wave programmable frequency RING pin, enabled MECTR0[3]. When MECTR0[3] low, RING held low. ringer frequency programmed TRFR register, which must initialized valid value before ringer enabled. ringer smoothly switches from programmed frequency newly programmed value with irregular pulses.
2.4.6
Biasing
biases various PhoX analog blocks determined internal bandgap reference. IREF current reference, must tied analog ground through temperature stable 61.9 resistor. IREF high impedance when PhoX Shutdown mode. Because high input impedance, IREF susceptible noise. Therefore, external components connected should located close possible away from noisy signal traces. CFILT filters internal analog reference voltage. capacitors, frequency parallel with high frequency, must tied from CFILT analog ground. bias network performs rapid charge acquisition procedure after reset bring analog circuits their approximate bias point, after which CFILT provides single pole low-pass filter rejection, which affected PhoX Shutdown mode. internal references automatically powered down when PhoX Shutdown mode. Upon exit from Shutdown mode, approximately stabilization time required.
Functional Description 2-45
DEVELOPMENT MODES
PhoX spread spectrum protocol supports several development debug modes. wirelink mode, configured RSSI DELAY register, allows 4-wire baseband interconnection between PhoX devices software development before availability radio hardware. pinout interface described Table (see BDMUX register). Cross-connect EPOCH EPOCH signals between devices, cross connect TXDATA SCRAMRDATA between devices. wirelink mode bypasses receive despreader symbol recovery, thereby ignoring RSSI receive inputs. There bit-error rate (BER) test modes, uni-directional, non-TDD operation, bi-directional operation. Configuration bits TXMODE RXMODE registers. 4-wire interface appears BDP[3:0] pins, which must configured function BDMUX register. interface includes output transmit clock, input transmit data, output receive clock, output transmit data. uni-directional, non-TDD mode, channel transparent. mode, channels transparent, Preamble, SYNC, channels operate normally sustain link. Error Generation feature, enabled simultaneously setting bits TXMODE register while operation, inhibits generation correct CRCs transmit channel, allowing software designers stimulate code written error handling. Clear Enable Baseband Spreading TXMODE register narrowband transmission.
2-46
Functional Description
CHAPTER
REGISTER SUMMARY
MEMORY INDEX
user registers reside Kbyte external data space 8032, shown Table 3-1. controller also internal data space that includes bytes special function registers, which described 80C32T2 Appendices, PhoXController Digital Cordless Telephones. Table 3-1, following conventions apply: register described numerical sequence Table default value unknown reserved unused applicable
Table
Data Space Data Address Decoder
External Data Space Address
Register Mnemonic Address 0000-03FF 0000-03FF 0400-EFFF F000-F3FF F400-F7FF Reserved ADRDEC Reserved CHIPINFO P1SRC0 P1SRC1 P1SRC2 P1MASK P1TRIG PORT4 PORT5 XISTAT0 XISTAT1 XISTAT2 Reserved GPOCTR0 BDMUX FF00-FF0E FF0F FF10-FF1F FF2D FF20 FF21 FF22 FF23 FF24 FF25 FF26 FF27 FF28 FF29 FF2A FF2B FF2C FF2D FF2E FF2F Access xxxx xxxx 0xxx 0xxx xxxx xxxx xxx0 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxx0 0000 xxxx xxxx 0000 000x 0000 000x 0000 000x xxxx xxxx 0000 0000 0000 0000 Default xxxx xxxx xxxx xxxx Description On-chip RAM, ADRDEC[7] I/O, ADRDEC[7] Emulation mode I/O, Emulation mode I/O, Emulation mode I/O, Emulation mode Address decoder Chip information interrupt source interrupt source interrupt source interrupt mask interrupt trigger control Port Port External interrupt status External interrupt status External interrupt status (See Codec) General purpose output control (See Chip Information) (See Noise Suppression) channel routing Page 3-10
Chip Information Parallel Port
Register Summary
Data Space Serial Port
Register Mnemonic SIOTB SIORB SIOCFG Reserved SIOSTAT SIOMASK Reserved SPTMG Reserved AOMUX Reserved AINCTR STCTR Reserved TRFR WAKEUP Reserved BATLEV Reserved T1FR1 T1FR2 T1FR3 T1AR TTAR T2FR1 T2FR2 T2FR3 T2AR RTAR TXATTN RXATTN DSPCTR STROBEN NSCTR Reserved MUTE Reserved
Address FF31 FF32 FF33 FF34-FF36 FF37 FF38 FF3A-FF3F FFED FF40-FF41 FF42 FF43 FF44 FF45 FF46-FF4A FF4B FF4C FF4D FF4E FF4F FF50 FF51 FF52 FF53 FF54 FF55 FF56 FF57 FF58 FF59 FF5A FF5B FF5C FF2A FF2E FF5D FF5E FF5F-FFBF
Access
Default xxxx xxxx x000 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx x000 xxxx xxxx 0xx0 xxx0 xxxx xxxx 0xx0 0000 xxxx 0000 xxxx xxxx xxxx xxxx xxxx xxx1 xxxx xxxx xxxx x100 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xx0x x0xx xxx0 0000 xxxx 0000 xxxx xxxx xxxx xxxx xxxx xxxx
Description Serial port transmit buffer Serial port receive buffer Serial port configuration Serial port interrupt status Serial port interrupt mask Serial port timing control Analog output control control Sidetone control Tone ringer frequency Wakeup timer Battery level Tone frequency Tone frequency Tone frequency Tone amplitude Transmit tone attenuation Tone frequency Tone frequency Tone frequency Tone amplitude Receive tone attenuation Transmit attenuation Receive attenuation Codec mode control Uniform port control Noise suppression control Noise suppress mute length
Page 3-12 3-12 3-13 3-14 3-14 3-14 3-15 3-16 3-17 3-18 3-21 3-22 3-23 3-23 3-23 3-24 3-26 3-23 3-23 3-23 3-24 3-26 3-27 3-27 3-27 3-28 3-29 3-30
Audio
Tone Ringer Wakeup Timer Battery Detect Dual-Tone Generator
Codec
Noise Suppression
Register Summary
Data Space Formatter
Register Mnemonic RXBUF0-5 TXBUF0-5 SYNC_CNTRL QUALITY RSSI BASELINE INTLSB INTMSB TIMING_LOOP DCOLSB DCOMSB TXMODE RXMODE BSYNC IFLOOPB RSSI_DELAY IF_DELAY IFLOOPC TXEN_CNFG RXEN_CNFG PAENB_CNFG SCRAMBLE IFLOOPA XTALDAC SYNC0 SYNC1 DCHSTAT SYNCSRC SYNCMASK MISRC0 MISRC1 MIMSK0 MIMSK1 Reserved UCCCTR UCCCP MECTR0 MECTR1 Reserved WDTKEY Reserved
Address FFC0-FFC5 FFC0-FFC5 FFC6 FFC7 FFC8 FFC9 FFCB FFCC FFCD FFCE FFCF FFD0 FFD1 FFD2 FFD3 FFD4 FFD5 FFD6 FFD7 FFD8 FFD9 FFDA FFDB FFDC FFDD FFDE FFDF FFE4 FFE5 FFE6 FFE0 FFE1 FFE2 FFE3 FFE4-FFE6 FFE7-FFE8 FFE9 FFEA FFEB FFEC FFED FFEE FFEF FFF0-FFFF
Access
Default xxxx xxxx 0x0x xx00 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 xx00 0x11 0000 0000 0000 0000 0000 0000 0000 00x0 000x xxxx 0011 0000 0000 0000 0110 0001 0000 0000 1010 1110 0100 0010 1010 1110 0000 0001 0101 0100 0100 1100 0010 0000 0100 1101 1010 0011 0000 0100 0000 0x0x xxxx 0x0x 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx 00xx 0000 x000 0x00 xxx0 00xx xxxx xxxx xxxx xxxx
Description Receive buffers Transmit buffers Link sync control/status Link quality indicator Current RSSI level RSSI baseline level recov loop integrator recov loop integrator Timing loop control Digitally-controlled Digitally-controlled Transmitter mode Receiver mode Burst synchronization loop control Receiver RSSI delay Receiver symbol delay loop control TXEN configuration RXEN configuration PAENB configuration Baseband scramble code loop control sequence seed XTAL code word SYNC channel, byte SYNC channel, high byte channel source Sync interrupt source Sync interrupt mask Main interrupt source Main interrupt source Main interrupt mask Main interrupt mask (See Formatter) Shutdown/µc clock control Shutdown/µc clock ctrl protect Module enable control Module enable control (see Serial Port)
Page 3-31 3-31 3-32 3-32 3-33 3-33 3-50 3-50 3-34 3-50 3-50 3-35 3-36 3-37 3-48 3-38 3-39 3-49 3-40 3-41 3-41 3-42 3-47 3-43 3-44 3-44 3-44 3-45 3-46 3-46 3-51 3-52 3-54 3-55 3-56 3-57 3-58 3-59 3-59
Interrupt Controller
Clock Generator
Watchdog Timer
Register Summary
RESERVED REGISTER BITS
Many registers contain data fields that reserved feature enhancement future silicon revisions. features will enabled programming reserved bits High, software compatibility with future silicon revisions, writes reserved data fields must write zeroes. Except where noted, reads reserved data fields return unknown values. Read-modify-write operations may, general, write back reserved field value read. Exceptions noted individual register descriptions.
3.3.1
ADDRESS DECODER ADRDEC
Full name: Address Decoder Control Register Address: FF0F Default: Access:
Data Disable
0xxx 0xxx Read/Write
Reserved
Quiet Mode
Reserved
Data Disable Enable on-chip 1024 byte address space 0000-03FF. decodes address range 0400-EFFF. Disable on-chip 1024 byte RAM. decodes address range 0000-EFFF.
Bits
Reserved. Reads return unknown values. Quiet Mode Enable (Noise reduction feature when operating from on-chip memory). This must programmed before external memory accessed. Quiet mode disabled PhoX device configured MODE0 MODE1 pins access external ROM. Microcontroller operates normally, even while accessinginternal memory. Disables accessing external memory. held weakly High held Low. Reserved. Reads return unknown values.
Bits
Register Summary
3.4.1
CHIP INFORMATION CHIPINFO
Full name: Chip Information Register Address: FF2D Default: Access:
Reserved
xxx0 0100 Read Only
PACKAGE
PRODUCT CODE
Reserved Package Type 100-pin package 68-pin package
Bits
Product Code This field indicates product revision.
3.5.1
PARALLEL PORT P1SRC0
Full name: Interrupt Source Register Address: FF20 Default: Access: 0000 0000 Read Only
P1SRC0 latches occurrences unmasked transitions port pins P1.0 P1.1 generates interrupt reported MISRC1[4]. Each transition associated P1MASK set. polarity transition defined P1TRIG register. Cleared reading P1SRC0 applying reset.
P1.1 INTRUPT FLAG
P1.0 INTRUPT FLAG
Reserved
Bits
Reserved. Reads return zeroes. Subject change future silicon revisions. P1.1 Interrupt Flag P1.0 Interrupt Flag
Register Summary
3.5.2
P1SRC1
Full name: Interrupt Source Register Address: FF21 Default: Access: 0000 0000 Read Only
P1SRC1 latches occurrences unmasked transitions port pins P1.2 P1.3 generates interrupt reported MISRC1[5]. Each transition associated P1MASK set. polarity transition defined P1TRIG register. Cleared reading P1SRC1 applying reset.
P1.3 INTRUPT FLAG
P1.2 INTRUPT FLAG
Reserved
Bits
Reserved. Reads return zeroes. Subject change future silicon revisions. P1.3 Interrupt Flag P1.2 Interrupt Flag
3.5.3
P1SRC2
Full name: Interrupt Source Register Address: FF22 Default: Access: 0000 0000 Read Only
P1SRC2 latches occurrences unmasked transitions port pins P1.7-P1.4 generates interrupt reported MISRC1[6]. Each transition associated P1MASK set. polarity transition defined P1TRIG register. Cleared reading P1SRC2 applying reset.
P1.7 INTRUPT FLAG
P1.6 INTRUPT FLAG
P1.5 INTRUPT FLAG
P1.4 INTRUPT FLAG
Reserved
Bits
Reserved. Reads return zeroes. Subject change future silicon revisions. P1.7 Interrupt Flag P1.6 Interrupt Flag P1.5 Interrupt Flag P1.4 Interrupt Flag
Register Summary
3.5.4
P1MASK
Full name: Interrupt Mask Register Address: FF23 Default: Access:
P1.7 MASK
0000 0000 Read/Write
P1.6 MASK
P1.5 MASK
P1.4 MASK
P1.3 MASK
P1.2 MASK
P1.1 MASK
P1.0 MASK
P1MASK individually masks transitions bits affecting P1SRC2-P1SRC0. bits: Disable interrupt source clear corresponding source bit. Enable corresponding interrupt source.
3.5.5
P1TRIG
Full name: Interrupt Trigger Register Address: FF24 Default: Access:
P1.7 TRIG SELECT
0000 0000 Read/Write
P1.6 TRIG SELECT
P1.5 TRIG SELECT
P1.4 TRIG SELECT
P1.3 TRIG SELECT
P1.2 TRIG SELECT
P1.1 TRIG SELECT
P1.0 TRIG SELECT
P1TRIG defines polarity transitions individual bits, causing interrupts latched P1SRC2-P1SRC0 registers. bits: High-to-Low transitions cause interrupts. Low-to-High transitions cause interrupts.
3.5.6
PORT4
Full name: Port Register Address: FF25 Default: Access: xxx0 0000 Write Only
PORT4 defines drive level P4.4-P4.0 pins. Setting configures corresponding pull High. Clearing drives corresponding Low.
Reserved
P4.4
P4.3
P4.2
P4.1
P4.0
Bits Bits
Reserved Level
Register Summary
3.5.7
PORT5
Full name: Port Register Address: FF26 Default: Access: xxxx xxxx Read Only
PORT5 read-only access input port pins P5.4-P5.0.
Reserved
P5.4
P5.3
P5.2
P5.1
P5.0
Bits Bits
Reserved Level
3.5.8
XISTAT0
Full name: External Interrupt Status Register Address: FF27 Default: Access: 0000 000x Read Only
XISTAT0 reports current logic level XINT0 pin.
Reserved
XINT0
Bits
Reserved. current silicon revision returns zeroes, subject change future revisions. XINT0 Level XINT0 XINT0 High
3.5.9
XISTAT1
Full name: External Interrupt Status Register Address: FF28 Default: Access: 0000 000x Read Only
XISTAT1 reports current logic level XINT1 pin.
Reserved
XINT1
Bits
Reserved. current silicon revision returns zeroes, subject change future revisions. XINT1 Level XINT1 XINT1 High
Register Summary
3.5.10
XISTAT2
Full name: External Interrupt Status Register Address: FF29 Default: Access: 0000 000x Read Only
XISTAT2 reports current logic level XINT2 pin.
Reserved
XINT2
Bits
Reserved. current silicon revision returns zeroes, subject change future revisions. XINT2 Level XINT2 XINT2 High
3.5.11
GPOCTR0
Full name: General Purpose Output Control Register Address: FF2C Default: Access: 0000 0000 Read/Write
GPOCTR0 controls general-purpose outputs OUT0-OUT3, which outputs multifunction pins BDP0-BDP3 configured writing BDMUX[7:5] 001. Values written GPOCTR0 internally latched regardless whether pins configured operation driven pins only when pins appropriately configured.
Reserved
OUT3
OUT2
OUT1
OUT0
Bits Bits
Reserved. current silicon revision returns zeroes, subject change future revisions. OUT# OUT# drives OUT# drives High
Register Summary
3.5.12
BDMUX
Full name: Channel Port Multiplexer Control Register Address: FF2F Default: Access:
0000 0000 Read/Write
SELECT
PORT
CHANNEL SOURCE
ADPCM SOURCE
Select SELECT[2:0] controls configuration four multifunction pins, described Table 3-2. Channel Data Output Source 32-Kbit/s channel output (BCHOUT) BDP0 follows codec transmit ADPCM output BDMUX[7:5]=000. BCHOUT follows unscrambled received channel BDMUX[7:5]=000.
Bits
Channel Source Transmit Channel Source identifies channel data transmitted. Codec transmit ADPCM output BCHIN BDP1 BDMUX[7:5]=000. BDMUX[7:5] 000, operation unpredictable. Unscrambled received channel (i.e., Loopback Reserved, should driven
Bits
ADPCM Receiver Source Unscrambled receive channel BCHIN BDP1 BDMUX[7:5]=000. BDMUX[7:5] 000, operation unpredictable. Codec transmit ADPCM output (i.e., Loopback Hexadecimal
3-10
Register Summary
Table Desc
Select Multifunction Configuration BDMUX [7:5]
Other Condition(s)
DSPCTR[2:0]= BSYNC[5]=0 DSPCTR[2:0]= BSYNC[5]=1 DSPCTR[2:0]= BSYNC[5]=0 TMODE[6]=0
BDP0
ALAWOUT (Output) BCHOUT (Output) BCHOUT (Output) OUT0
BDP1
ALAWIN (Input) BCHIN (Input) BCHIN (Input) OUT1
BDP2
ALAWCLK (Output) BCLK (Output) BCLK (Output) OUT2
BDP3
CLK8K (Output) CLK8K (Input) CLK8K (Output) OUT3
Section
A-law Port External Protocol Channel
Purpose Outputs Master Port Reserved BERT Mode Calibration Debug Recov Debug
DSPCTR[3:0]= 0001 x100
PCMOUT (Output) TBERCLK (Output) Window (Output) TXPNEPO (Output) REF_I (Output)
PCMIN (Input) TBERDATA (Input) RXIF460 (Output) RXPNEPO (Output) RXIF460 (Output)
PCMCLK (Input) RBERCLK (Output) RSSH_SH (Output) PNACQD (Output) RBERCLK (Output)
STROBE (Output) RBERData (Output) ScramRData (Output) ScramRData (Output) RBERData (Output)
2.3.12 2.3.12 2.3.12 2.3.6.3.1
Register Summary
3-11
3.6.1
SERIAL PORT SIOTB
Full name: Serial Port Transmit Buffer ch
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