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Am79C30A / 32A

Digital Subscriber Controller (DSCTM) Circuit

FINAL
Am79C30A / 32A
Digital Subscriber Controller (DSCTM) Circuit
DISTINCTIVE CHARACTERISTICS
s Combines CCITT I.430 S / T-Interface Transceiver, D-Channel LAPD Processor, Audio s Processor (DSC device only), and IOM-2 Interface in a single chip s Special operating modes allow realization of CCITT I.430 power-compliant terminal equipment s S- or T-Interface Transceiver - Level 1 Physical Layer Controller - Supports point-to-point, short and extended passive bus configurations - Provides multiframe support s Certified protocol software support available s CMOS technology, TTL compatible s D-channel processing capability - Flag generation / detection - CRC generation / checking - Zero insertion / deletion - Four 2-byte address detectors - 32-byte receive and 16-byte transmit FIFOs
BLOCK DIAGRAM
SBP / IOM-2 Interface CAP1 CAP2 SBIN SCLK BCL / CH2STRB SBIOUT SFS
AINA AREF AINB EAR1 EAR2 LS1 LS2
Audio Interface
Main Audio Processor (MAP) (Am79C30A Only)
Peripheral Port (PP)
S / T Line Interface Unit (LIU) D Channel B1
LOUT1 LOUT2 LIN1 LIN2
B-channel Multiplexer (MUX)
B2 D-Channel Data Link Controller (DLC)
XTAL1 XTAL2 MCLK
Oscillator (OSC) Bb Bc
D Channel Microprocessor Interface (MUX) RESET
D7 D6 D5 D4 D3 D2 D1 D0 INT A2 Microprocessor Interface
A1 A0 09893H-1
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 09893 Rev: H Amendment / 0 Issue Date: November 1997
S / T Interface
DISTINCTIVE CHARACTERISTICS (continued)
s Audio processing capability (DSC circuit only) - Registers for implementation of software-based speaker phone algorithms - Dual audio inputs - Earpiece and loudspeaker drivers - Codec / filter with A / µ selection - Programmable gain and equalization filters - Programmable sidetone level - Programmable DTMF, single tone, progress tone, and ringer tone generation - Programmable on-chip microphone amplifier s Pin and software compatible with the Am79C32A ISDN Data Controller (IDCTM) Circuit. The Am79C32A is used in data-only applications.
GENERAL DESCRIPTION
Am79C30A / 32A Data Sheet
CONNECTION DIAGRAMS Top View
44-Pin PLCC AREF EAR2 EAR1 HSW 40 39 38 37 36 35 Am79C30A 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 AVSS AINB AINA LIN1 42 LIN2 41 LS2 LS1 44
CAP1 CAP2 AVCC DVCC RESET CS RD WR DVSS A2 A1
LOUT1 LOUT2 AVSS DVSS INT XTAL1 XTAL2 MCLK SFS SCLK SBOUT
44-Pin PLCC RSRVD RSRVD RSRVD RSRVD RSRVD AREF HSW 40 39 38 37 36 35 Am79C32A 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 LIN1 42 LIN2 41 LS2 LS1
BCL / CH2STRB
RSRVD RSRVD AVCC DVCC RESET CS RD WR DVSS A2 A1
LOUT1 LOUT2 AVSS DVSS INT XTAL1 XTAL2 MCLK SFS SCLK SBOUT
Note: 1. Pin 1 is marked for orientation purposes.
Am79C30A / 32A Data Sheet
BCL / CH2STRB
CONNECTION DIAGRAMS (continued) Top View
44-Pin TQFP AREF EAR2 EAR1 HSW 34 AVSS AINB AINA LIN1 36 LIN2 35 LS2 39 LS1 38
CAP1 CAP2 AVCC DVCC RESET CS RD WR DVSS A2 A1
LOUT1 LOUT2 AVSS DVSS INT XTAL1 XTAL2 MCLK SFS SCLK SBOUT
44-Pin TQFP RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD HSW 34 33 32 31 30 29 Am79C32A 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 LIN1 36 LIN2 35 LS2 LS1
BCL / CH2STRB
RSRVD RSRVD AVCC DVCC RESET CS RD WR DVSS A2 A1
LOUT1 LOUT2 AVSS DVSS INT XTAL1 XTAL2 MCLK SFS SCLK SBOUT
Note: Pin 1 is marked for orientation purposes.
Am79C30A / 32A Data Sheet
BCL / CH2STRB
ORDERING INFORMATION Standard Products
AMD® standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
AM79C30A / 32A
SPEED OPTION Not Applicable DEVICE NAME / DESCRIPTION Am79C30A / 32A Digital Subscriber Controller (DSC) device ISDN Data Controller (IDC) device
Valid Combinations AM79C30A AM79C32A JC, VC JC, VC
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Reference Appendix C, Figures 1 & 2, for specific mechanical dimensions of the two packages.
Am79C30A / 32A Data Sheet
PIN DESCRIPTION Line Interface Unit (LIU)
HSW Hook-Switch (Input) The HSW signal indicates if the hook-switch is on or off hook. This signal may be generated with a mechanical switch wired to ground with a pull-up resistor to VCC. Any change in the HSW state causes an interrupt. LIN1, LIN2 Subscriber Line Input (Differential Inputs) The LIN1 and LIN2 inputs interface to the subscriber (S reference point) via an isolation transformer. LIN2 is the positive input LIN1 is the negative input. These pins are not TTL compatible. LOUT1, LOUT2 Subscriber Line Output (Differential Outputs) The LOUT1 and LOUT2 line driver output signals interface to the subscriber line at the S reference point via an isolation transformer and resistors. LOUT2 is the positive S-interface driver (sources current during a High mark), and LOUT1 is the negative S-interface driver (sources current during Low mark). For multi-point applications, all TEs must maintain the same polarity on the S Interface. These pins are not TTL compatible.
EAR1, EAR2 Earpiece Interface (Differential Outputs) EAR1 and EAR2 are the outputs from the receive path of the codec / filter. These differential outputs can directly drive a minimum load of 130 ohms. LS1, LS2 Loudspeaker Interface (Differential Outputs) LS1 and LS2 are push-pull outputs which can directly drive a minimum load of 40 ohms.
Microprocessor Interface (MPI)
A2-A0 Address Line (Inputs) A2, A1, and A0 signals select source and destination registers for read and write operations on the data bus. CS Chip Select (Input) CS must be Low to read or write to the Am79C30A / 32A. Data transfer occurs over the bidirectional data lines (D7-D0). D7-D0 Data Bus (Bidirectional with High-Impedance State) The eight bidirectional data bus lines are used to exchange information with the microprocessor. D0 is the least significant bit (LSB) and D7 is the most significant bit (MSB). A High on the data bus line corresponds to a logic 1, and Low corresponds to a logic 0. These lines act as inputs when both WR and CS are active and as outputs when both RD and CS are active. When CS is inactive or both RD and WR are inactive, the D7-D0 pins are in a high-impedance state. INT Interrupt (Output) An active Low output on the INT pin informs the external microprocessor that the Am79C30A / 32A needs interrupt service. INT is updated once every 125 µs. The INT pin remains active until the Interrupt Register (IR) is read or the Am79C30A / 32A is reset. RESET Reset (Input) Reset is an active High signal which causes the Am79C30A / 32A to immediately terminate its present activity and initialize to the reset condition. When reset returns Low, the Am79C30A / 32A enters the Idle mode. The MCLK output remains active while RESET is held High.
Main Audio Processor (MAP)
All MAP pins are analog, and therefore are not TTL compatible. AINA, AINB Analog (Inputs) These analog inputs allow for two separate analog (audio) inputs to the transmit path of the codec / filter.Input signals on either of these pins must be referenced to AREF. AREF Analog Reference (Output) This is a nominal 2.25-V reference voltage output for biasing the analog inputs. When the MAP is disabled, this pin is high impedance. CAP1, CAP2 Capacitor / Resistor (CAP1, Input CAP2, Output) An external resistor and capacitor are connected in series between these pins. These components are needed for the integrator in the Analog-to-Digital Converter (ADC).
Note: All signal levels are TTL compatible unless otherwise stated.
Am79C30A / 32A Data Sheet
RD Read (Input) The active Low read signal is conditioned by CS and indicates that internal information is to be transferred onto the data bus. A number of internal registers are user accessible. The contents of the accessed register are transferred onto the data bus after the High to Low transition of the RD input. WR Write (Input) The active Low write signal is conditioned by CS and indicates that external information on the data bus is to be transferred to an internal register. The contents of the data bus are loaded on the Low to High transition of the WR input.
When the Peripheral Port is programmed to IOM-2 mode, SBOUT functions as the data output except in the special case of IOM-2 Slave mode when it becomes an input during part or all of the IOM-2 frame. SCLK Serial Data Clock (Input / Output) When the PP is programmed to SBP mode, SCLK outputs a 192-kHz data clock, which may be inverted under software control. When the PP is programmed to IOM-2 Master mode, SCLK outputs a 1.536-MHz 2X data clock. In IOM-2 Slave mode, SCLK functions as the clock input. The SCLK pin defaults to a high-impedance state upon reset, but becomes active after any MUX connection is made or if the PP is programmed to IOM-2 Master mode. SFS Serial Frame Sync (Input / Output) In SBP mode, SFS outputs an 8-kHz frame synchronization signal. SFS is an output in IOM-2 Master mode, and an input in IOM-2 Slave mode. As an output, SFS is active for 8-bit periods. The SFS pin defaults to a high-impedance state upon reset, but becomes active after any MUX connection is made or if the PP is programmed to IOM-2 Master mode. For SBP mode, the active signal state is Low during Idle and 8 kHz in Active Data Only and Active Voice and Data modes. BCL / CH2STRB Bit Clock / SBP Channel 2 Strobe (Output, Three-state) In SBP mode, this pin provides a strobe during the 8-bit times of the second 64-kbit / s data channel. In IOM-2 Master mode, this pin provides a 768-kHz bit clock to aid in the connection of non-IOM-2 devices to the port. In IOM-2 Slave mode, this pin is high-impedance.
Oscillator (OSC)
Peripheral Port (PP)
SBIN Serial Data (Input / Output) When the Peripheral Port is programmed to SBP mode, SBIN operates as an input for serial data. When the Peripheral Port is programmed to IOM-2 mode, SBIN functions as the data input except in the special case of IOM-2 Slave mode, when it becomes an open-drain output during part or all of the IOM-2 frame, or when deactivated. SBOUT Serial Data (Input / Output) When the Peripheral Port is programmed to SBP mode, SBOUT operates as an output for serial data.
Power Supply Pins
Note: For best performance, decoupling capacitors should be installed between VCC and VSS as close to the chip as possible. Do not use separate supplies for analog and digital power and ground connections.
Am79C30A / 32A Data Sheet
OPERATIONAL DESCRIPTION Overview of Power Modes
The minimization of power consumption is a key factor in the design of Terminal Equipment for the ISDN, and the DSC / IDC circuit employs two basic approaches to power management: 1. The power consumption of the DSC / IDC circuit itself is managed by using four basic power modes which allow unused functional blocks to be disabled. The INIT register may be programmed to select Active Voice and Data, Active Data Only, Idle, or Power-Down mode, depending upon which DSC / IDC device resources are required at the time. 2. The power consumption of the controlling micro-processor system may be controlled by driving the processor clock with the DSC / IDC circuit MCLK output. A wide range of MCLK operating frequencies may be selected, and a special Clock Speed-Up function is provided which increases the speed of MCLK upon the occurrence of a key event, without processor intervention. Control of MCLK frequency and Clock Speed-up is accomplished by programming the INIT and INIT2 registers, as described later.
Idle mode reduces DSC / IDC circuit power consumption by disabling the MUX, DLC, and MAP functional blocks. The Peripheral Port is also disabled, except that an IOM-2 activation request interrupt is possible, and the SFS and SCLK outputs may still be activated. The SFS and SCLK outputs are high impedance upon RESET, but become active after any MUX connection is programmed. The DLC read-only registers are cleared when the DSC / IDC circuit enters the Idle mode.
Power-Down Mode
Power-Down mode consumes the least power of all the DSC / IDC power options, and differs from Idle mode in that all clocks, including the XTAL oscillator, are stopped. Most functional blocks are disabled, except for those required to recognize key external events that will force the DSC / IDC circuit to return to Idle mode. The Power-Down mode is not available unless the Power-Down Enable bit is set in the INIT2 register see the INIT2 register description for further details. Entering the Power-Down Mode The Power-Down mode is entered by appropriate programming of the INIT and INIT2 registers. Selection of the Power-Down mode causes the DSC / IDCcircuit to begin an internal countdown of at least 250 MCLK cycles after which the MCLK and XTAL1 outputs are both stopped and held High, and the XTAL2input will be disregarded. The purpose of this countdown cycle is to allow the microprocessor time for housekeeping operations before its clock is stopped. If an interrupt causes the DSC INT pin to go Low during the countdown, the Power-Down mode bits in the INIT register will be reset and the countdown will be canceled. If the LIU is enabled and in any state other than F3 at the end of the countdown, MCLK is stopped but the oscillator continues to run. This allows the LIU to identify the incoming signal and either (1) generate an interrupt and force the DSC / IDC circuit to Idle mode when activation is complete, or (2) move to the F3 state and stop the oscillator once the line goes idle. Exiting the Power-Down Mode The DSC / IDC circuit will exit the Power-Down mode and enter the Idle mode if any of the following events occur: s The DSC / IDC circuit receives a hardware reset via the RESET pin. s The CS and WR pins are both pulled Low at the same time, as would occur during a normal write operation from the microprocessor to the DSC circuit. No data will be transferred by this operation.
Active Voice and Data Mode
In Active Voice and Data mode all functional blocks of the DSC / IDC circuit are available. Device registers may be accessed through the MPI, the LIU and DLC are available, the OSC is running, the Peripheral Port is available, MUX connections may be made, the Secondary Tone Ringer may be activated, and the MAP is operational (DSC circuit only).
Active Data Only Mode
Active Data Only mode is similar to Active Voice and Data mode, except that the MAP (DSC circuit only) is disabled to reduce system power consumption. This increases the amount of power available for the Secondary Tone Ringer or microprocessor system during the phases of call setup and teardown, or during a data-only telephone call.
Idle Mode
Idle mode is the RESET default mode of DSC / IDCcircuit operation, and represents an operational state in which power consumption is reduced, yet the microprocessor system is operational to program DSC / IDC circuit registers or perform other required background tasks. Idle mode may also be entered by appropriate programming of the INIT register. In Idle mode, the MCLK output is available to drive the microprocessor system, the MPI is available for programming of DSC / IDC registers, and the LIU is available to initiate or respond to S / T interface activity. The HSW hookswitch interrupt is also available in Idle mode. 8
Am79C30A / 32A Data Sheet
s The HSW hookswitch pin changes state, and the hookswitch interrupt is enabled. s The LIU receiver is enabled, detects an incoming signal on the S / T Interface, and achieves activation as indicated by a transition to state F7. Both the INT pin and the F7 transition interrupt must be enabled for Power-Down mode to be exited. If the LIU is enabled, it may restart the oscillator so that it can identify the activity on the interface. If the activity is determined to be noise, the LIU will stop the oscillator and continue to monitor the line without an interrupt or returning to Idle mode. s The IOM-2 Interface is enabled as a clock master and the SBIN input pin goes Low. This indicates that a slave device wants to activate the IOM-2 Interface and communicate with the DSC circuit. Both the INT pin and the IOM-2 timing request interrupts must be enabled for Power-Down mode to be exited. s The IOM-2 Interface is enabled as a clock slave and the SCLK input pin goes High. This indicates that the master device is activating the IOM-2 Interface and the DSC circuit must wake up in order to monitor the data. Both the INT pin and the IOM-2 timing request interrupts must be enabled for Power-Down mode to be exited. If the DSC / IDC circuit is awakened by any condition other than RESET, the MCLK output will be restored to its previously programmed frequency, and will not generate any shortened or spurious output cycles. If the DSC / IDC circuit is revived by RESET, MCLK will default to its normal 6.144-MHz rate. The DSC / IDC circuit provides a minimum of two MCLK cycles prior to activating the interrupt pin when exiting Power-Down mode.
There are two events that will trigger the clock speed-up function: 1. The DLC receive FIFO threshold has been reached or, 2. a second packet begins to be received while data from a prior packet is still in the receive FIFO. The second packet case requires provision of an interrupt see the DLC register section for further information. The clock speed-up function allows the user to program a very slow MCLK frequency using INIT2 when D-channel activity is minimal. If a burst of activity is seen on the D channel and it exceeds the programmed threshold of the receive FIFO or threatens to overrun the receive FIFO status buffers, MCLK will instantly toggle back to the higher frequency programmed in the INIT register. This eliminates the latency incurred if an interrupt has to be serviced to change the clock speed, and allows the overall system power to be reduced during typical voice connections. Note that automatic clock speed-up will not function unless at least one of the associated interrupts are enabled so the processor can be informed that the clock speed has been altered.
Global Register Functions
Bit 7 6 5 4 3 2 1 0 Function 0 Idle mode 1 Active Voice and Data mode 0 Active Data Only mode 1 Power-Down mode
INIT Register
MCLK Frequency Control
The MCLK frequency selection bits in the INIT register are unchanged from Revision D. However, additional MCLK frequencies are available by programming bits in the INIT2 register. No shortened or spurious clock pulses that might disrupt the external microprocessor will result when the MCLK frequency is changed. In order to reduce the probability of errant software disrupting system operation, the INIT2 register requires two consecutive writes before the value will be entered into the register. Note that there will be no MCLK countdown as is the case for entering Power-Down mode if INIT2 is programmed to cause MCLK to STOP, and there will be no shortened or spurious MCLK pulses.
MCLK Clock Speed-up Function
A programmable automatic MCLK speed-up option is provided that will force a hardware reset of INIT2 bits 3-0, which will cause the MCLK frequency to be restored to the value programmed in the INIT register.
X X X X X X DLC receiver abort disabled X X X X X X DLC receiver abort enabled X X X X X X DLC transmitter abort disabled X X X X X X DLC transmitter abort enabled
Am79C30A / 32A Data Sheet
RESET Operation
The Am79C30A / 32A can be reset by driving the RESET pin High. When power is first supplied to the DSC / IDC circuit, a reset must be performed. This initializes the DSC / IDC circuit to its default condition as defined in Table 3. Table 3.
Pin Name D7-D0 MCLK INT SBOUT SFS SCLK LS1, LS2 EAR1 EAR2 AREF LOUT1 LOUT2
Reset Pin Conditions
State Following RESET High Impedance 6.144 MHz Logical 1 High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance
X X X X X X Reserved, must be written to 0 READs are undefined 0 X X X X X Power-Down disabled writing 11 to the INIT Register will put the DSC / IDC circuit into Idle mode 1 X X X X X Power-Down enabled writing 11 to the INIT Register will put the DSC / IDC circuit into Power-Down mode X 0 X X X X Multiframe Interrupt filter disabled X 1 X X X X Multiframe Interrupt filter enabled (see LIU section for detailed description) X X X 0 X X Clock speed-up option disabled X X X 1 X X Clock speed-up option enabled if set, this register bit will be cleared when the DLC FIFO receive threshold or second packet received interrupt is triggered X X X 0 0 X X X 0 0 X X X 0 1 X X X 0 1 X X X 1 0 X X X 1 0 X X X 1 1 X X X 1 1 0 MCLK frequency determined by INIT Register 1 MCLK frequency is 1.536 MHz 0 MCLK frequency is 768 kHz 1 MCLK frequency is 384 kHz 0 MCLK stopped in High state 1 Reserved 0 Reserved 1 Reserved
Receive and Transmit Abort Commands
The microprocessor has the option via INIT Register bits 6 and 7 to abort the receive and transmit D-channel packets. When the microprocessor sets one of these bits, the Am79C30A / 32A aborts the respective operation. The frame abort sequence is defined in greater detail later. (See the Data Link Controller section on page 36.)
Interrupt Handling
Am79C30A / 32A Data Sheet
Bc buffers must be accessed within 122.4 µs. This is to prevent erroneous data transfers. Only one interrupt is used to signal accessibility for both B channels of the S Interface. Since the data transfer must occur synchronously to the S Interface, any data access to either Bb or Bc or both must be made within the122.4 µs limit. Note that even though only a single interrupt is issued, either or both S-Interface B channels must be serviced. IR bits 2, 3, 5, 6, and 7, if set, indicate that a bit has been set in the associated status or error register. All of the interrupts generated by the Am79C30A / 32A can be
individually disabled. In the case of IR bit 7, the interrupt can also be masked by setting PPIER bit 7 to 0. DMR1, DMR2, DMR3, LMR2, MCR4, and MF control the mask conditions that affect the INT pin. The INT pin is activated only by interrupts that are not disabled. The Interrupt Register reflects the status of enabled interrupts. The INT pin can be disabled by setting INIT Register bit 2 to a logical 1. The Am79C30A / 32A has facilities that allow the microprocessor to read the status registers (status update is inhibited during status read) or the IR at any time during functional operation.
Am79C30A / 32A Data Sheet
Table 4. Format of the Interrupt Register (IR), Read Only
Bit 0 1 2 Interrupt Generated / Action Required D-channel transmit threshold interrupt / load D-channel Transmit buffer D-channel receive threshold interrupt / read D-channel Receive buffer D-channel status interrupt / read DSR1 Source DSR1 bit 0 DSR1 bit 1 DSR1 bit 6 3 Source DER bit 0 DER bit 1 DER bit 2 DER bit 3 DER bit 4 DER bit 5 DER bit 6 DER bit 7 DSR2 bit 2 4 5 Cause Valid Address (VA) or End of Address (EOA) When a closing flag is received or a receive error occurs When a closing flag is transmitted DMR3 bit 1 Cause Current received packet has been aborted Non-integer number of bytes received Collision abort detected FCS error Overflow error Underflow error Overrun error Underrun error Receive packet lost DMR2 bit 0 DMR2 bit 1 DMR2 bit 2 DMR2 bit 3 DMR2 bit 4 DMR2 bit 5 DMR2 bit 6 DMR2 bit 7 DMR3 bit 6 MCR4 bit 3 DMR3 bit 0 DMR1 bit 3 DMR3 bit 1 Interrupt Mask DMR1 bit 0 DMR1 bit 1
D-channel error interrupt / read DER and DSR2 bit 2
Bb or Bc byte available or buffer empty interrupt / read or write Bb or Bc buffers LIU status interrupt / read LSR Source LSR bit 3 LSR bit 4 LSR bit 5 LSR bit 7 Cause Change of state to F3 Change of state from / to F7 Change of state from / to F8 HSW change of state Cause Last byte of received packet Receive byte available Last byte transmitted Transmit buffer available Start of second packet Cause S-data available Q-bit buffer empty Multiframe change of state (in / out of sync) Monitor receive, data available Monitor transmit, buffer available Monitor EOM received Monitor abort received C / I channel 0, data change C / I channel 1, data change IOM-2 timing request
LMR2 bit 3 LMR2 bit 6 LMR2 bit 4 LMR2 bit 5
D-channel status interrupt / read DSR2 Source DSR2 bit 0 DSR2 bit 1 DSR2 bit 3 DSR2 bit 4 DSR2 bit 7 DMR3 bit 2 DMR3 bit 3 DMR3 bit 4 DMR3 bit 5 EFCR bit 1
Multiframe or PP interrupt / read MFSB and PPSR Source MFSB bit 5 MFSB bit 6 MFSB bit 7 PPSR bit 0 PPSR bit 1 PPSR bit 2 PPSR bit 3 PPSR bit 4 PPSR bit 5 PPSR bit 6 MF bit 1 MF bit 2 MF bit 3 PPIER bit 0 PPIER bit 1 PPIER bit 2 PPIER bit 3 PPIER bit 4 PPIER bit 5 PPIER bit 6
Am79C30A / 32A Data Sheet
FUNCTIONAL DESCRIPTION Microprocessor Interface (MPI)
The Am79C30A / 32A can be connected to any general purpose 8-bit microprocessor via the MPI. The MCLK from the Am79C30A / 32A can be used as the clock for the microprocessor. The MPI is an interrupt-driven interface containing all the circuitry necessary for access to the internal programmable registers, status registers, coefficient RAM, and transmit / receive buffers. MPI External Interface External connections to the MPI are shown in Table 5. Table 5. MPI External Interface
Name D7-D0 A2-A0 RD WR CS RESET INT Direction Bidirectional Inputs Input Input Input Input Output Function Data Bus Address Line Read Enable Write Enable Chip Select Initialization Interrupt
Direct Registers
Access to the Direct Registers of the Am79C30A / 32A is controlled by the state of the CS, RD, WR, A2, A1, and A0 input pins, as defined below by Table 6.
Indirect Registers
To read from or write to any of the Indirect Registers, an indirect address command is first written to the Command Register (CR). One or more data bytes may then be transferred to or from the selected register through the Data Register (DR). Registers within certain groups can be accessed quickly by using internal circuitry which automatically increments the indirect value. In Table 7, the bytes transferred numbers are the number of bytes which are read or written to the DR after the CR has been loaded. Whenever the CR is loaded, any previous commands are automatically terminated.
Table 6. Direct Register Access Guide
Note: The RD and WR signals must never both be Low under normal operating conditions.
Am79C30A / 32A Data Sheet
Table 7.
Operation Block Register INIT INIT LIU LIU LIU LIU LIU LIU LIU LIU MUX MUX MUX MUX MUX MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP MAP DLC DLC DLC DLC DLC Initialization Register Initialization Register 2 LIU Status Register LIU Priority Register LIU Mode Register 1 LIU Mode Register 2 - Multiframe Register Multiframe S-bit / Status Register Multiframe Q-bit buffer MUX Control Register 1 MUX Control Register 2 MUX Control Register 3 MUX Control Register 4 - X filter Coefficient Register R filter Coefficient Register GX Gain Coefficient Register GR Gain Coefficient Register GER Gain Coefficient Register Sidetone Gain Coefficient Register Frequency Tone Generator Register 1, 2 Amplitude Tone Generator Register 1, 2 MAP Mode Register 1 MAP Mode Register 2 - MAP Mode Register 3 Secondary Tone Ringer Amplitude Secondary Tone Ringer Frequency Transmit Peak Register Receive Peak Register - First Received Byte Address Registers 1, 2, 3 Second Received Byte Address Registers 1, 2, 3 Transmit Address Register D-channel Receive Byte Limit Register D-channel Transmit Byte Count Register
Indirect Register Access Guide
Register Number 1 2 1 2 3 4 5 6 7 8 1 2 3 4 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 Indirect Name INIT INIT2 LSR LPR LMR1 LMR2 Perform 2-4 MF MFSB MFQB MCR1 MCR2 MCR3 MCR4 Perform 1-4 X Coeff. R Coeff. GX Coeff. GR Coeff. GER Coeff. STG Coeff. FTGR1, FTGR2 ATGR1, ATGR2 MMR1 MMR2 Perform 1-10 MMR3 STRA STRF PEAKX PEAKR Perform 15-16 FRAR 1, 2, 3 SRAR1, 2, 3 TAR DRLR DTCR Mode Address R / W R / W R R / W R / W R / W - R / W R W R / W R / W R / W R / W - R / W R / W R / W R / W R / W R / W R / W R / W R / W R / W - R / W R / W R / W R R R R / W R / W R / W R / W R / W 21H 20H A1H A2H A3H A4H A5H A6H A7H A8H 41H 42H 43H 44H 45H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 70H 71H 72H 81H 82H 83H 84H 85H One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred MCR1, 2, 3, 4 h0 LSB, h0 MSB..h7 MSB h0 LSB, h0 MSB..h7 MSB LSB, MSB LSB, MSB LSB, MSB LSB, MSB FTGR1, 2 ATGR1, 2 One byte transferred One byte transferred 46 bytes loaded 1-10 One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred FRAR1, 2 SRAR1, 2 LSB, MSB LSB, MSB LSB, MSB Byte Sequence One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred
Am79C30A / 32A Data Sheet
Table 7.
Operation Block Register DLC DLC DLC DLC DLC DLC DLC DLC DLC DLC DLC DLC DLC PP PP PP PP PP PP PP PP PP PP PP D-channel Mode Register 1 D-channel Mode Register 2 -
Indirect Register Access Guide (Continued)
Register Number 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 Indirect Name DMR1 DMR2 Perform 1-7 DRCR RNGR1 (LSB) RNGR2 (MSB) FRAR4 SRAR4 DMR3 DMR4 Perform 12-15 ASR EFCR PPCR1 PPSR PPIER MTDR MRDR CITDR0 CIRDR0 CITDR1 CIRDR1 PPCR2 PPCR3 Mode Address R / W R / W - R R / W R / W R / W R / W R / W R / W - R R / W R / W R R / W W R W R W R R / W R / W 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H C0H C1H C2H C3H C3H C4H C4H C5H C5H C8H C9H Byte Sequence One byte transferred One byte transferred 4 bytes loaded 1-7 LSB, MSB One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred FRAR4, SRAR4, DMR3, DMR4 One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred One byte transferred
D-channel Receive Byte Count Register Random Number Generator Register Random Number Generator Register First Received Byte Address Register 4 Second Received Byte Address Register 4 D-channel Mode Register 3 D-channel Mode Register 4 - Address Status Register Extended FIFO Control Register Peripheral Port Control Register 1 Peripheral Port Status Register Peripheral Port Interrupt Enable Register Monitor Transmit Data Register Monitor Receive Data Register C / I Transmit Data Register 0 C / I Receive Data Register 0 C / I Transmit Data Register 1 C / I Receive Data Register 1 Peripheral Port Control Register 2 Peripheral Port Control Register 3
Line Interface Unit (LIU)
The LIU connects to the four-wire S Interface through a pair of isolation transformers, one for the transmit and one for the receive direction, as shown in Figure 1. The receiver section of the LIU consists of a differential receiver, circuitry for bit timing recovery, circuitry for detecting High and Low marks, and a frame recovery circuit for frame synchronization. The receiver converts the received pseudo-ternary coded signals to binary before delivering them to the other blocks of the Am79C30A / 32A. It also performs collision detection (Eand D-bit comparison) per the CCITT recommenda-
tions so several TEs can be connected to the same S Interface. The transmitter consists of a binary to pseudo-ternary encoder and a differential line driver which meets the CCITT recommendations for the S Interface. The Am79C30A / 32A can establish multiframe synchronization, receive S bits, and transmit Q bits synchronized to the received frame. External Interface The LIU can be connected to both point-to-point and point-to-multipoint configurations at the CCITT S reference point. The point-to-point configuration consists of one TE connected to the NT or PABX linecard. The
Am79C30A / 32A Data Sheet
point-to-multipoint configuration can have multiple TEs connected to one NT. Line Code Pseudo-ternary coding is used for both transmitting and receiving over the S Interface. In this type of coding, a binary 1 is represented by a space (zero voltage), and a binary 0 is represented by a High mark or a Low mark. Two consecutive binary 0s are represented by alternate marks to reduce DC offset on the line. A mark followed, either immediately or separated by spaces, by a mark of the same polarity, is defined as a code violation. Code violations are used to identify the boundaries of the frame.
Note: The DSC defines "Any Signal" as any frame with at least three marks above receive threshold.
(bit 7 of the Multiframe Register) and multiframe change of state bit (bit 7 of the Multiframe S bit / Status buffer) are set. Note that S-bit data is received, compiled, and transferred to the user after attaining synchronization at the start of the next multiframe. S-Bit Reception The default operation of the DSC / IDC circuit is that the LIU will receive and pass multiframe data to the user in 5-bit increments four times per multiframe, regardless of the value of the data. After multiframe synchronization has been requested and established the microprocessor can read the Multiframe S bit / Status buffer (MFSB) once the S-bit available bit (MFSB bit 5) is set. The S-data available bit is set to a logical 1 when the Am79C30A / 32A has received five S bits (one S bit per S-interface frame) synchronized to the setting of the FA -bit to a logical 1 and transferred them into the MFSB. Once the S-bit available bit is set, the MFSB must be accessed within 1.25 ms or succeeding S data will be lost. Subsequent to the original definition of the DSC / IDC circuit, the CCITT has defined a structure for the 20 multiframe bits, which specifies five 4-bit channels. Furthermore, the idle code for these channels has been defined as 0000. An enhanced mode of multiframe reception has been included, which may be enabled by setting INIT2 bit 4 to a 1. This enhanced mode reduces processor overhead by generating an interrupt only upon the reception of a non-zero S-channel word. INIT2 bit 4 will be automatically cleared by hardware when the five received data bits in the MFSB are not all 0s, as long as MF bit 1 (interrupt enable) is set. This allows subsequent valid all-zero words to be received. Furthermore, when the first five S bits of the multiframe are loaded into the MFSB, bit 4 of the MF register will be set, which allows identification of the position of received words within the multiframe.
Frame Structures In both transmit and receive directions, the bits are grouped into frames of 48 bits each. The frame structure is identical for both point-to-point and point-to-multipoint configurations. Each frame transmitted at 4 kHz consists of several groups of bits. Multiframing If multiframing is enabled, the Am79C30A / 32A recognizes and establishes multiframe synchronization based on the monitoring of the FA (Q-bit control) and M (M-bit control) bits. The Am79C30A / 32A also receives and compiles S bits, and transmits Q bits synchronized to the received frame. Establishment of Multiframe Synchronization When the enable multiframe synchronization bit (bit 0 of the Multiframe Register) is set and the LIU is in either state F6 or F7, the LIU monitors the FA (Q-bit control) and M (M-bit control) bits. When three consecutive multiframes with the M bits and FA bits set as defined in Table 8 are received, the multiframe synchronized bit
Line Drivers Binary to Pseudo-ternary Coder
To MUX and DLC Decoder
Frame Recovery
Slicer Timing Recovery Balanced Receiver
09893H-2
Figure 1. 16
LIU Block Diagram
Am79C30A / 32A Data Sheet
Table 8.
Multiframing Structures
NT-to-TE M Bit (M) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 NT-to-TE S Bit (S) SC11 SC21 SC31 SC41 SC51 SC12 SC22 SC32 SC42 SC52 SC13 SC23 SC33 SC43 SC53 SC14 SC24 SC34 SC44 SC54 SC11 SC21 TE-to-NT FA Bit (Q Bit) Q1 0 0 0 0 Q2 0 0 0 0 Q3 0 0 0 0 Q4 0 0 0 0 Q1 0
Transmission of Q bits The microprocessor can load the Multiframe Q-bit buffer (MFQB) once the Q-bit buffer empty bit (bit 6 of the Multiframe S bit / Status buffer) is set. The Q-bit buffer empty bit is set to a logical 1 at reset or when data that has been written to the Multiframe Q-bit buffer is transferred to the LIU. The Q-bit buffer empty bit is cleared to a logical 0 when the Multiframe S-bit / Status buffer is read. After multiframing has been requested and established, the Am79C30A / 32A transfers the data written into the Q-bit Register to the LIU, synchronized to the multiframe, irrespective of the receipt of valid Q-control bits. If the microprocessor does not reload the Q-bit Register for retransmissions, the Q-bit pattern is repeated in the next multiframe. If multiframing is enabled but multiframe synchronization is not established, the LIU transmits the value loaded in MFQB bit 4 in all Q bits. The default value of MFQB bit 4 is a logical 0 which satisfies the CCITT recommendations. When synchronization is achieved, the contents of MFQB bits 3 to 0 are transmitted according to Table 8.
Loss of Multiframe Synchronization The Am79C30A / 32A continuously monitors the FA (Q-bit control) and the M bits to ensure multiframe synchronization. Once multiframe synchronization is established, multiframe synchronization is lost if three consecutive invalid multiframes are received, or the LIU is no longer in state F6 or F7, or multiframing is disabled. When loss of multiframe synchronization occurs, bit 7 of the Multiframe Register is set to a logical 0, and bit 7 of the Multiframe S bit / Status buffer is set to a logical 1. The Am79C30A / 32A also terminates the reception of S bits and transmission of Q bits until multiframing synchronization is re-established.
The hookswitch circuitry on the DSC circuit provides the attached microprocessor with a way of converting an external mechanical hookswitch into a software status condition capable of generating an interrupt. Debounce and glitch rejection are provided internal to the DSC circuit. The logic rejects glitches less than 162 ns and provides debounce of 16 ms. HSW status reporting is disabled after RESET. It is enabled by any of the following: taking the device out of Idle mode, a write to a MUX Control Register (MCR3-MCR1), or unmasking the HSW interrupt.
Am79C30A / 32A Data Sheet
LIU Registers The LIU contains the registers shown in Table 9. Table 9. LIU Registers
Registers LIU Status Register LIU Priority Register LIU Mode Registers Multiframe Register Multiframe S-bit / Status Register Multiframe Q-bit buffer No. / Registers Mnemonic 1 1 2 1 1 1 LSR LPR LMR1, LMR2 MF MFSB MFQB
as 1, F4 as 2, and so on, where bit 0 is the LSB. The LIU interrupts the microprocessor via bit 4 of the LSR when activation has been achieved (that is, when the LIU moves to state F7 upon receipt of INFO 4). During reset the LSR is 0. Even though the LIU Status Register (LSR) is read-only, no default value upon power-up is given due to the uncertain state of bit 6 (Hookswitch State). Following RESET, the LIU State is F2 and the HSW bit reflects the HSW pin, producing a power-up value of either 00H or 40H. LIU D-Channel Priority Register (LPR), Read / Write The LPR contains the priority level for D-channel access. Its default value after reset is 0. The D-channel access procedure of the Am79C30A / 32A uses the priority level programmed in the LPR. The priority mechanism defined by the CCITT I-series recommendations is fully implemented if the LPR is programmed via the microprocessor to conform to the priority class of the Layer-2 frame to be transmitted.The LPR has 16 possible programmable priority levels. The priority levels are numbered 0-15. Priority Level 0 corresponds to counting eight 1s in the echo channel, priority Level 1 corresponds to counting ten 1s in the echo channel, priority Level 2 corresponds to counting twelve 1s, etc. The DSC circuit automatically handles transitions between the programmed priority level n and the associated odd value n + 1. The priority is incremented following a successfully transmitted packet, and decremented when the higher count has been satisfied. The LPR format is shown in Table 11. Table 11.
LIU Priority Register
Description
When the microprocessor reads the LSR, bits 3, 4, 5, and 7 are cleared. The other bits retain the current status of the LIU. bits 0 to 2 are defined such that state F2 (see CCITT I.430 state matrix tables) is coded as 0, F3
D-channel access priority level bit 0 is LSB Reserved, reads logical 0
Am79C30A / 32A Data Sheet
Bit 0 1 2 3 4 5 6 7 Logical 1 Enable B1 transmit Enable B2 transmit Disable F transmit Disable FA transmit Activation request Go from F8 to F3 Enable receiver / transmitter Reserved must be set to logical 0 Logical 0 (default value) Disable B1 transmit Disable B2 transmit Enable F transmit Enable FA transmit No activation request No transition Disable receiver / transmitter Reserved must be set to logical 0
Notes: The F and FA bits in LMR1 (bits 2 and 3) should be enabled during the activation procedure so the Am79C30A / 32A can respond with INFO 3. LMR1 bit 4 is used to transfer the signals PH-AR and Expiry of Timer from the microprocessor to the LIU (see CCITT I.430 state diagram-activation request). PH-AR is defined as bit 4 being a logical 1 and Expiry of Timer is defined as the transition of bit 4 from a logical 1 to a logical 0. This bit must not be set until the LIU, as reflected in the LSR, is in state F3, F6, or F7 and the receiver has been enabled for a minimum of 250 µs. LMR1 bit 6 is primarily used to disable the receiver when the terminal does not require access to the S Interface signals. This bit is cleared by reset and must be written to logical 1 in order to receive activation from the S Interface, or to request activation.
Bit 0 1 2 3 4 5 6 7 Logical 1 D-channel loopback at Am79C30A / 32A enable D-channel loopback at LIU enable D-channel back-off disable F3 change of state interrupt enable F8 change of state interrupt enable HSW interrupt enable F7 change of state interrupt enable Reserved must be set to logical 0 Logical 0 (Default Value) D-channel loopback at Am79C30A / 32A disable D-channel loopback at LIU disable D-channel back-off enable F3 change of state interrupt disable F8 change of state interrupt disable HSW interrupt disable F7 change of state interrupt disable Reserved must be set to logical 0
Am79C30A / 32A Data Sheet
The three D-channel loopback controls defined in LMR2 bits 0, 1, and 2 are explained below: Bit 0, D-channel loopback at Am79C30A / 32A enable:
Bit 1, D-channel loopback at LIU enable: Am79C30A D S D NT / PABX
Am79C30A
NT / PABX MPI
This local loopback is provided for local testing. Data on the incoming D channel is ignored. The data from the microprocessor is processed by the DLC and then looped back to the microprocessor. Bit 2, D-channel back-off disable:
Am79C30A
NT / PABX
Bit 0 1 2 3 4 5, 6 7 Logical 1 Enable Multiframe sync Enable S-data available interrupt Enable Q-bit buffer empty interrupt Enable Multiframe change of state interrupt First subframe Not used, reads logical 0 Multiframe synchronized (read only) Logical 0 (Default Value) Disable Multiframe sync Disable interrupt Disable interrupt Disable interrupt Not first subframe Not used, reads logical 0 Multiframe not synchronized (read only)
Am79C30A / 32A Data Sheet
Code 0000 0001 0010 Channel No connection (default value) B1 (LIU) B2 (LIU) Ba (MAP) Bb (MPI) Bc (MPI) Bd (PP channel 1) Be (PP channel 2) Bf (PP channel 3)
Multiframe Q-Bit Buffer
Multiplexer (MUX)
The MUX contains the registers found in Table 17. Table 17.
Register MUX Control Registers
MUX Registers
Mnemonic MCR1, MCR2, MCR3, MCR4
No. / Registers 4
The Multiplexer is used to selectively route 64-Kbit / s full-duplex B channels between the LIU (Line Interface Unit), MAP (Main Audio Processor), MPI (Microprocessor Interface), and the PP (Peripheral Port).
For example, to connect B1(LIU) with Bb (MPI) and B2 (LIU) with Ba (MAP), the contents of the MCRs would be: Port 1 Port 2
Register 7 6 5 4 3 2 1 0 Channel Connection MCR1 MCR2 MCR3 0 0 0 1 0 1 0 0 B1 (LIU) 0 0 1 0 0 0 1 1 B2 (LIU) 0 0 0 0 0 0 0 0 No connect Bb (MPI) Ba (MAP) No connect
Am79C30A / 32A Data Sheet
Peripheral Port Bd Be Bf
Bb MPI Bc B-channel MUX
B1 LIU B2
Ba MAP
09893H-3
Figure 2. MUX Logical Channels Therefore, in this example, MCR1 provides a data link from the S Interface and MCR2 sets up a voice connection across the S Interface. To loopback a channel, the same channel code is used for port 1 and port 2. For example, to loopback B1, B2, and Ba, the MCRs would be:
Port 1 Port 2
MCR will overwrite the data from the connecting port in the lower priority MCR, for example:
Port 1 Port 2
Register 7 6 5 4 3 2 1 0 Channel Connection MCR1 MCR2 MCR3 0 0 0 0 0 0 0 0 No connect 0 0 0 1 0 1 0 0 B1 (LIU) 0 1 0 0 0 0 1 1 Bb (MPI) Bb (MPI) Ba (MAP)
Register 7 6 5 4 3 2 1 0 Channel Connection MCR1 MCR2 MCR3 0 0 0 1 0 0 0 1 B1 (LIU) Loopback 0 0 1 0 0 0 1 0 B2 (LIU) Loopback 0 0 1 1 0 0 1 1 Ba (MAP) Loopback
The final data transfers are: B1 (LIU) receives Bb (MPI), Ba (MAP) receives Bb (MPI), Bb (MPI) receives Ba (MAP). Therefore, the data transfer from B1 (LIU) to Bb (MPI) is lost in the arrangement proposed in MCR2.
MCR3 has higher priority than MCR2. MCR2 has higher priority than MCR1. If multiple connections are made to the same port, the data from the connecting ports in the highest priority
Am79C30A / 32A Data Sheet
Bit 0-2 3 4 5 6 7 Logical 1 Reserved, must be set to logical 0
MUX Control Register 4
Logical 0 (Default Value) Reserved, must be set to logical 0
Enable Bb- or Bc-channel byte available interrupt (IR Bit 4) Disable interrupt Reverse bit order of Bb (LSB transmitted / received first) Reverse bit order of Bc (LSB transmitted / received first) Reserved, must be set to logical 0 Reserved, must be set to logical 0 No Bb bit reversal (MSB transmitted / received first) No Bc bit reversal (MSB transmitted / received first) Reserved, must be set to logical 0 Reserved, must be set to logical 0
Am79C30A / 32A Data Sheet
Main Audio Processor (MAP)
(Am79C30A only) Overview The MAP, as illustrated in Figure 3, implements audio-band analog-to-digital (ADC) and digital-to-analog (DAC) conversions together with a wide variety of audio support functions. Analog interfaces are provided for a handset earpiece, a handset mouthpiece, a microphone, and a loudspeaker. A programmable analog preamplifier is included in front of the A / D converter. The codec and filter functions are implemented using digital signal processing (DSP) techniques to provide operational stability and programmable features. There is one programmable digital gain stage in the transmit path and two in the receive path to allow precise signal level control. Sidetone attenuation is programmable, and programmable equalization filters are present in both the receive and transmit paths in order to modify the frequency response of either or both paths. Tone generation capability is included to allow generation of ringing signals, DTMF tones, and call progress signals. MAP operation is described in detail in the following sections. CAP1 CAP2 AINA AINB AREF Analog Sidetone Gain EAR1 EAR2 DAC LS1 LS2
Notes: Minimum GX GER GR STG GA ASTG 0 dB -10 dB -12 dB -18 dB 0 dB -27 dB Default 0 dB 0 dB 0 dB -18 dB 0 dB 8 Maximum 12 dB 18 dB 0 dB 0 dB 24 dB -6 dB
Audio Inputs The audio input port consists of two inputs (AINA and AINB) which are selectable, one at a time, by register programming. Signals applied to these inputs must be AC-coupled. Earpiece and Loudspeaker Drivers The earpiece and loudspeaker drivers each consist of amplifiers with differential, low-impedance outputs. The MAP receive path signal may be routed to either of these outputs, or to both outputs simultaneously. Alternatively, the MAP receive path may be routed to the EAR outputs while the Secondary Tone Ringer (STR) is routed to the LS outputs. The EAR drivers can drive loads S130 ohms between the EAR1 and EAR2 pins, while the LS drivers can drive loads S40 ohms between the LS1 and LS2 pins. The maximum capacitive-loading between EAR1 and EAR2 or between LS1 and LS2 is 100 pF. The EAR outputs are high-impedance when the MAP is disabled. The LS outputs are high impedance when both the MAP and the Secondary Tone Ringer are disabled.
PEAKX GA ADC Decimators, BPF Digital Loopback 1 (A) DTMF GEN. Sidetone Gain X GX COMP Ba channel to MUX
Transmitter Receiver
Digital Loopback 2 Interpolators, LPF R GER + GR
Ba channel from EXP MUX
STR (C)
Step 0.5 dB 0.5 dB 0.5 dB 0.5 dB 6.0 dB 1.5 dB
PEAKR Tone Ringer Tone Gen. (B)
Programmable These registers can also be programmed for infinite attenuation to break the signal path if desired.
09893H-4
Figure 3. Main Audio Processor Block Diagram 24 Am79C30A / 32A Data Sheet
Programmable Analog Preamplifier A programmable analog preamplifier GA is included in front of the A / D converter and is adjustable in 6-dB increments from 0 dB to +24 dB. The existing GX gain stage in the transmit path may be used for finer adjustment of transmit gain. This preamplifier eliminates the need for an external operational amplifier when interfacing electret-type handsets to the DSC circuit. Analog Sidetone Analog sidetone takes the analog input to the transmitter ADC and sums it into the single-ended input of the EAR output buffer. The summing point is after the output selection switch. The analog sidetone path has programmable attenuation between -6 and -27 dB, plus infinity (off). Default is infinity. Programming is via four bits in the Extended FIFO Control Register, EFCR.6-3. The programming values are given in Table 20. Table 20. Analog Sidetone
Receiver
The receiver performs a series of operations described as follows: 1. An expander converts the input A- or µ-law data to digital linear data. The most significant bit is transferred from the MUX first. The default value is µ-law. 2. The GR filter is a programmable gain filter that allows the user to program a gain of -12 to 0 dB in 0.5-dB steps. The default value of GR is 0 dB. 3. The GER and Sidetone Gain (STG) are programmable constant multipliers which allow the user to program a gain of -10 to +18 dB in 0.5-dB steps (default value 0 dB) and -18 to 0 dB in 0.5-dB steps (default value -18 dB) respectively. The GER provides volume control (for the hearing impaired) and should be programmed to 0 dB for normal operation. The sidetone gain path provides feedback from the transmitter. 4. The R filter is provided to correct for speaker attenuation distortion and is a user-programmable filter similar to the X filter in the transmitter. 5. A series of interpolators increases the sampling frequency. 6. A DAC converts the digital signal to the analog audio output signal. PEAK Hold Registers Logic in the form of two microprocessor accessible peak hold registers will be provided to allow for support of a software based speaker phone solution. These registers, one in the transmit path (PEAKX) and one in the receive path (PEAKR), will provide the compressed maximum (peak) absolute value of the data in the path since the register was last read. With appropriate software, this can be used to implement a hands-free function. Refer to the MAP block diagram for the location of these registers in the processing path. The following assumptions are made: 1. The GX and GR blocks are used as gain / attenuators, without modification to their range or resolution. 2. The data is presented in compressed A-law format, without the alternate bit inversion. The sign bit is not presented. 3. The data extraction point for the transmit path is after the X filter. 4. The data extraction point for the receive path is immediately following the expander. 5. The compressed data from the transmit and receive paths is presented using the same compression algorithm.
Signal Processing
Transmitter
The transmitter performs a series of operations as described below. 1. An ADC converts the incoming analog signal at a sampling rate of 512 kHz. 2. The Band Pass filter and a series of decimators reject DC and 50- to 60-Hz line frequencies while reducing the sampling rate to 8 kHz. 3. The X filter is an 8-tap user-programmable filter for tuning the microphone. The default is flat with unity gain. 4. The GX filter is a programmable gain filter that allows the user to program a gain of 0 to +12 dB in 0.5-dB steps. The default value is 0 dB. 5. The µ-law or A-law digital compression algorithm converts the linear output of the GX filter to µ- or A-law code. The default algorithm is µ-law code. The MSB (sign bit) is transferred first to (or from) the MUX.
Am79C30A / 32A Data Sheet
The DTMF generator may be used to generate single frequency outputs. To obtain a single frequency out of the DTMF generator, load a zero code into one of the two frequency registers.
Tone Generation
This generator provides call progress tones to the receive path, where it is added to the incoming speech (Figure 3, Block B).
Tone Ringer
This generator provides tone alert signals output through the receive path to the loudspeaker or earpiece (Figure 3, Block C). To program the DTMF tone generators, two frequency values and two amplitude values must be written to the two 8-bit Frequency Tone Generator Registers (FTGR1, FTGR2) and the two 8-bit Amplitude Tone Generator Registers (ATGR1, ATGR2), respectively. The Tone Generator and the Tone Ringer use the frequency programmed in FTGR1. The Tone Generator uses the amplitude programmed in ATGR1 while the Tone Ringer uses the amplitude programmed in ATGR2. Common frequency values are listed in Table 22. The FTGR codes to obtain DTMF dialing output frequencies are listed in Table 21.
DTMF Generator
Table 21. DTMF Codes
FTGR 2 or 1 HEX REG VALUE FTGR 1 or 2 5AH 63H 6EH 79H FREQ 697 770 852 941 9BH 1209 1 4 7 ABH 1336 2 5 8 0 BFH 1477 3 6 9 # D3H 1633 A B C D
Am79C30A / 32A Data Sheet
The output frequency of the DTMF tone generator approximately equals:
The ATGR registers allow the user to program a gain of -18 dB to 0 dB in 2-dB steps. Example ATGR codes to obtain amplitude gains are listed in Table 23. 0 dB implies a level of +3 dBm0. The gain values are rounded off to the nearest 1 dB. Table 23. Amplitude Gain Coefficients
Gain (dB) -18 Hex Code 37 32 31 27 22 21 20 12 11 10
where i is the decimal equivalent of value programmed into the FTGR register. This allows the DTMF generator to supply common dual tone call progress signals such as Busy or Dial tones. Table 22. Tone Ringer and Tone Generator Frequency Coefficients
Hex Code AB 81 67 56 4A 41 39 34 2F 2B 28 25 23 21 1F 1D 1B 1A 19 18 17 16 15
Frequency (Hz) 2666 2000 1600 1333 1142 1000 889 800 727 667 615 571 533 500 471 444 421 400 381 364 348 333 320
Secondary Tone Ringer
A Secondary Tone Ringer is included, which is able to ring the phone using the LS outputs while a voice conversation is in progress on the EAR outputs. The STR is louder than the Tone Generator, and may be used with or without enabling the MAP in order to provide flexible control of system power consumption. The STR is not available if the INIT register is programmed to Idle or Power-Down mode. The amplitude and frequency of the STR square-wave output waveform is programmable via the STRA and STRF registers, respectively. If both the LS outputs from the MAP receive path and the STR are simultaneously enabled, priority is given to the STR connection. The STR is available for both the DSC and IDC circuits. A legal value must be programmed in the STRF register before the STR is enabled.
Note: These coefficients do not apply to the DTMF generator.
Am79C30A / 32A Data Sheet
Programmable Gain Coefficients The GER, GR, GX, and Sidetone gain coefficients are each 16 bits in length. Two consecutive register locations correspond to one gain coefficient. The LSB is transferred first to (or from) the microprocessor. Sample coefficients for the GER filter are listed in Table 24. The gain values are rounded off to the nearest 0.1 dB. Table 24. GER Gain Coefficients
Hex Code Gain (dB) -10 -9.5 -9.0 -8.5 -8.0 -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 MSB AA 9B 79 09 41 31 9C 9D 74 54 6A AB AB 74 64 6A 2A BE 5C 75 00 55 43 33 52 77 55 41 LSB AA BB AC 9A 99 99 DE EF 9C 9D AE CD DF 29 AB FF BD EF CE CD 99 4C DD DD EF 1B 42 DD Gain (dB) 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.4 14.0 14.5 15.0 15.5 15.9 16.6 16.9 17.5 18.0 MSB 31 44 43 33 40 11 44 41 31 55 10 42 41 11 60 00 42 40 11 22 72 42 21 10 22 11 00 21 00 Hex Code LSB DD 1F 1F 1F DD DD 0F 1F 1F 20 DD 11 0F 1F 0B DD 10 0F 0F 10 00 00 10 0F 00 10 0B 00 0F
Note: The coefficient 0008 provides an attenuation of infinity when GER gain is enabled.
Am79C30A / 32A Data Sheet
Example coefficients for the GR, GX, and STG filters are listed in Tables 25, 26, and 27. The gain values are rounded off to the nearest 0.1 dB. Table 25. GX Gain Coefficients
Hex Code Gain (dB) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 MSB 08 4C 3D 2A 25 22 21 1F 12 12 11 0B 10 03 02 02 01 01 01 00 00 00 00 00 00 LSB 08 B2 AC E5 33 22 22 D3 A2 1B 3B C3 F2 BA CA 1D 5A 22 12 EC 32 21 13 11 0E
Table 26. GR Gain Coefficients
Hex Code Gain (dB) -11.5 -11.0 -10.5 -10.0 -9.5 -9.0 -8.5 -8.0 -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 MSB 91 91 92 91 92 92 92 92 93 93 94 9F 9C 9B 9A 9A A2 A2 A6 AA B2 BB CB 08 LSB C5 B6 12 A4 22 32 FB AA 27 B3 B3 91 EA F9 AC 4A 22 A2 8D A3 42 52 B2 08
Am79C30A / 32A Data Sheet
Table 27.
Gain (dB) -18.0 -17.5 -17.0 -16.5 -16.0 -15.5 -15.0 -14.5 -14.0 -13.5 -13.0 -12.5 -12.0 -11.5 -11.0 -10.5 -10.0 -9.5 -9.0 -8.5 -8.0 -7.5 -7.0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0
STG Gain Coefficients
Hex Code MSB 8B 8B 8B 8B 8B 8B 91 91 91 91 91 91 91 91 91 92 91 92 92 92 92 93 93 94 9F 9C 9B 9A 9A A2 A2 A6 AA B2 BB CB 08 LSB 7C 44 35 2A 24 22 23 2E 2A 32 3B 4B F9 C5 B6 12 A4 22 32 FB AA 27 B3 B3 91 EA F9 AC 4A 22 A2 8D A3 42 52 B2 08
Note: The coefficient 9008 provides an attenuation of infinity when GR, GX, and / or STG are enabled.
Am79C30A / 32A Data Sheet
Table 28. Recommended Ranges
Recommended and guaranteed GX GER GR STG 0 to +12 dB plus infinite in 0.5 dB steps -10 to +18 dB plus infinite in 0.5 dB steps -12 to 0 dB plus infinite in 0.5 dB steps -18 to 0 dB plus infinite in 0.5 dB steps
where each hj Coefficient Register pair has the following format:
Byte LSB MSB 7 S1 S3 654 M1 M3 3 S0 S2 210 M0 M2
Limits by design GX GER GR STG -84.3 to 14.0 dB plus infinite in 0.1 dB steps over most of the range -24.1 to 24.1 dB plus infinite in 0.1 dB steps over most of the range -84.3 to 14.0 dB plus infinite in 0.1 dB steps over most of the range -84.3 to 14.0 dB plus infinite in 0.1 dB steps over most of the range
Design Ranges
The X and R filter coefficients are programmed using a 16-byte transfer with the format shown in Table 30. Table 30. X / R Filter Format
Byte 0 1 2 4 5 6 7 8 9 10 11 12 13 14 15 Value h0 LSB h0 MSB h1 LSB h2 LSB h2 MSB h3 LSB h3 MSB h4 LSB h4 MSB h5 LSB h5 MSB h6 LSB h6 MSB h7 LSB h7 MSB
As an example, in a hands-free application using an electret requiring 24 dB of gain in the transmit path for optimum performance. The typical implementation would use 18 dB of GA and 6 dB of GX gain. The user would then have a programmable range of +6 dB to -66 dB utilizing GX. Selection of these gain points is of course, application specific, and will depend on the performance requirements of the system. Listings of the optimized programming values for various levels are included in Appendix A. Values listed in the recommended tables are still correct and will perform as stated. There is no need to convert to the extended values unless greater resolution is required. Programmable Filter Coefficients and Equations The frequency domain transfer function equation for the X and R filters is:
Note: AmMAP software, which calculates X and R filter coefficients, is available from Advanced Micro Devices. Contact your local AMD Sales Office for more information.
Test Facilities Three capabilities are provided for MAP operation verification.
MAP Analog Loopback
Signals sent in on AINA or AINB may be sent back out to EAR1 / EAR2 or LS1 / LS2 by looping the MAP path in the MUX. The MUX should be set up for Ba-to-Ba loopback by writing 33H to MCR1, MCR2, or MCR3. No other MUX connections overriding Ba-to-Ba should be programmed. This test allows the MAP analog and digital to be tested using a local signal source.
MAP Digital Loopback 1
This loopback mode connects the interpolator output to the decimator input in place of the ADC output. This mode allows verification from the S Interface or micro-
Am79C30A / 32A Data Sheet
processor that the MAP digital circuitry is functional. Note that the digital patterns received after loopback will not be identical to the transmitted patterns. The D-D gain is approximately 2.5 dB.
MAP Digital Loopback 2
This loopback mode connects the analog D / A output path to the analog A / D input path, internal to the DSC circuit. The EAR and LS outputs and both AIN inputs will be disabled. This mode allows verification from the S Interface or microprocessor that the MAP analog and digital circuitry are functional. The digital patterns received after loopback will not be identical to the transmitted patterns. The bits in the MAP mode Register define the enable / disable options for the various MAP configurations as follows. MAP Registers The MAP contains the programmable registers found in Table 31. Table 31. Map Registers
MAP Register X-filter Coefficient Register R-filter Coefficient Register GX-Gain Coefficient Register GR-Gain Coefficient Register GER-Gain Coefficient Register Sidetone-Gain Coefficient Register Frequency Tone Generator Register Amplitude Tone Generator Register MAP mode Registers (3) Secondary Tone Ringer Amplitude Reg Secondary Tone Ringer Frequency Reg Transmit Peak Register Receive Peak Register Bytes 16 16 2 2 2 2 2 2 1 1 1 1 1 Mnemonic X R GX GR GER STGR FTGR ATGR MMR STRA STRF PEAKX PEAKR
Following reset, the MAP registers FTGR, MMR1, MMR2, MMR3, STRA, and STRF all default to 00 hex. All other MAP registers are not affected by reset and must be programmed by the microprocessor before being enabled. When the registers are disabled, or after reset, the MAP will have the response shown in Table 32. Table 32. Default Values
Filter X filter R filter GX filter GR filter GER filter Sidetone gain Default Response Disabled (0 dB, Flat) Disabled (0 dB, Flat) Disabled (0 dB, Gain) Disabled (0 dB, Gain) Disabled (0 dB, Gain) Disabled (-18 dB, Gain)
Note: It is necessary to complete any transfers to the multi-byte MAP registers. For instance, a total of 16 bytes must be transferred to update the X filter.
Am79C30A / 32A Data Sheet
Note: To remove the sidetone path completely, it is necessary to enable the STG function by setting MMR1 bit 6 to 1, and program the STGR coefficient to 9008 (hex).34
Bit 0 1 2 3 4 5 6 7 Logical 1 AINB selected LS1 / LS2 selected DTMF enabled Tone generator enabled Tone ringer enabled High pass filter disabled ADC auto-zero function disabled Reserved, must be Logical 0 Logical 0 (Default Mode) AINA selected EAR1 / EAR2 selected DTMF disabled Tone generator disabled Tone ringer disabled High pass filter enabled ADC auto-zero function enabled Reserved, must be Logical 0
Note: For most applications, MMR2 bits 5 and 6 should always be written to logical 0. This enables the 50-60 Hz rejection filter and the internal offset cancellation circuits to operate normally. They can both be disabled when system or test conditions require the transmission of DC or low frequency signals.
Am79C30A / 32A Data Sheet
Map Mode Register 3 - (MMR3) - Read / Write Address Indirect 6CH Table 35. Map Mode Register 3
Bit 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 X 0 0 0 0 1 1 1 1 X X X X X X X X 5 X 0 0 1 1 0 0 1 1 X X X X X X X X 4 X 0 1 0 1 0 1 0 1 X X X X X X X X 3 X X X X X X X X X 1 0 X X X X X X 2 X X X X X X X X X X X 1 0 X X X X 1 X X X X X X X X X X X X X 1 0 X X 0 Function X Bit 7 Reserved, must be written to 0 X 0-dB pre-amplifier gain, 1.250-V maximum peak input voltage X +6-dB pre-amplifier gain, 0.625-V maximum peak input voltage X +12-dB pre-amplifier gain, 0.312-V maximum peak input voltage X +18-dB pre-amplifier gain, 0.156-V maximum peak input voltage X +24-dB pre-amplifier gain, 0.078-V maximum peak input voltage X Reserved undefined X Reserved undefined X Reserved undefined X MUTE ON, AINA and AINB inputs disabled X MUTE OFF, AINA or AINB enabled X Digital Loopback 2 enabled D / A output looped to A / D input EAR, LS, and AIN pin disabled X Digital Loopback 2 disabled X EAR and LS simultaneously enabled X EAR or LS enabled by MMR2 bit 1 1 0 Secondary Tone Ringer enabled Secondary Tone Ringer disabled
Am79C30A / 32A Data Sheet
Counter Value 3F 1F 0F 87 43 A1 D0 E8 F4 7A 3D 1E 8F C7 63 B1 58 2C 16 0B 05 02 01 80 40 20 10 88 C4 E2 71 38 1C 8E 47 23 91 48 A4 D2 E9 74 3A 1D 0E 07 03 81 C0 60 30 98 4C 26 93 49 Frequency (Hz) Reserved Reserved 12000.0 9600.0 8000.0 6857.1 6000.0 5333.3 4800.0 4363.6 4000.0 3692.3 3428.6 3200.0 3000.0 2823.5 2666.7 2526.3 2400.0 2285.7 2181.8 2087.0 2000.0 1920.0 1846.2 1777.8 1714.3 1655.2 1600.0 1548.4 1500.0 1454.6 1411.8 1371.4 1333.3 1297.3 1263.2 1230.8 1200.0 1170.7 1142.9 1116.3 1090.9 1066.7 1043.5 1021.3 1000.0 979.6 960.0 941.2 923.1 905.7 888.9 872.7 857.1 842.1 Counter Value 3B 9D 4E 27 13 09 04 82 41 A0 50 A8 D4 6A B5 DA 6D B6 5B AD D6 6B 35 9A 4D A6 D3 69 34 1A 0D 86 C3 E1 F0 F8 7C BE DF 6F B7 DB ED F6 7B BD 5E AF D7 EB 75 BA 5D 2E 17 8B Frequency (Hz) 727.3 716.4 705.9 695.7 685.7 676.1 666.7 657.5 648.7 640.0 631.6 623.4 615.4 607.6 600.0 592.6 585.4 578.3 571.4 564.7 558.1 551.7 545.5 539.3 533.3 527.5 521.7 516.1 510.6 505.3 500.0 494.9 489.8 484.9 480.0 475.3 470.6 466.0 461.5 457.1 452.8 448.6 444.4 440.4 436.4 432.4 428.6 424.8 421.1 417.4 413.8 410.3 406.8 403.4 400.0 396.7 Counter Value D8 6C 36 1B 8D C6 E3 F1 78 3C 9E CF E7 73 39 9C CE 67 33 19 8C 46 A3 D1 68 B4 5A 2D 96 4B 25 12 89 44 A2 51 28 94 4A A5 52 A9 54 2A 95 CA E5 72 B9 DC EE 77 BB DD 6E 37 Frequency (Hz) 369.2 366.4 363.6 360.9 358.2 355.6 352.9 350.4 347.8 345.3 342.9 340.4 338.0 335.7 333.3 331.0 328.8 326.5 324.3 322.2 320.0 317.9 315.8 313.7 311.7 308.7 307.7 305.7 303.8 301.9 300.0 298.1 296.3 294.5 292.7 290.9 289.2 287.4 285.7 284.0 282.4 280.7 279.1 277.5 275.9 274.3 272.7 271.2 269.7 268.2 266.7 265.2 263.7 262.3 260.9 259.5 Counter Value F7 FB FD 7E BF 5F 2F 97 CB 65 32 99 CC 66 B3 59 AC 56 2B 15 8A C5 62 31 18 0C 06 83 C1 E0 70 B8 5C AE 57 AB 55 AA D5 EA F5 FA 7D 3E 9F 4F A7 53 29 14 0A 85 42 21 90 C8 Frequency (Hz) 247.4 246.2 244.9 243.7 242.4 241.2 240.0 238.8 237.6 236.5 235.3 234.2 233.0 231.9 230.8 229.7 228.6 227.5 226.4 225.4 224.3 223.3 222.2 221.2 220.2 219.2 218.2 217.2 216.2 215.3 214.3 213.3 212.4 211.5 210.5 209.6 208.7 207.8 206.9 206.0 205.1 204.3 203.4 202.5 201.7 200.8 200.0 199.2 198.4 197.5 196.7 195.9 195.1 194.3 193.6 192.8
Am79C30A / 32A Data Sheet
Table 37. Frequencies for Secondary Tone Ringer (Continued)
Counter Value 24 92 C9 64 B2 D9 EC 76 Frequency (Hz) 827.6 813.6 800.0 786.9 774.2 761.9 150.0 738.5 Counter Value 45 22 11 0-8 84 C2 61 B0 Frequency (Hz) 393.4 390.2 387.1 384.0 381.0 378.0 375.0 372.1 Counter Value 9B CD E6 F3 79 BC DE EF Frequency (Hz) 258.1 256.7 255.3 254.0 252.6 251.3 250.0 248.7 Counter Value E4 F2 F9 FC FE FF Frequency (Hz) 192.0 191.2 190.5 189.7 189.0 188.2
Data Link Controller (DLC)
Overview A 16-Kbit / s D-channel is time-multiplexed within the frame structure of the S Interface. The data carried by the D channel is encoded using the Link Access Protocol D-channel (LAPD) format shown in Figure 4. The D channel can be used to carry either end-to-end signaling or low-speed packet data. Further information concerning LAPD protocol can be found in the CCITT recommendations. The LIU controls the multiplexing and demultiplexing of the D-channel data between the S Interface and the DLC. The DLC performs processing of Level-1 and partial Level-2 LAPD protocol, including flag detection and generation, zero deletion and insertion, Frame Check Sequence (FCS) processing for error detection, and some addressing capability. High level protocol processing is done by the external microprocessor. The microprocessor may process the address field in the LAPD frame depending on the programmed state of the DLC. The status of the DLC is held in the status registers and relevant interrupts are generated under user program control. In addition to transmit and receive data FIFOs, the DLC contains a 16-bit pseudo-random number generator (RNG) used in the CCITT D-channel address allocation procedure.
last byte of the aborted packet is read from the D-channel Receive buffer. The Receive-Abort interrupt can be masked by setting DMR2 bit 0 to a logical 0. With the exception of the Packet-Reception-in-Progress bit, no other bits associated with packet reception are updated after a receive packet abort. The receive frame can be aborted at any time by setting INIT bit 6 to logical 1. Similarly, the transmit frame can be aborted by setting INIT bit 7 to a logical 1. When the transmit frame is aborted, seven consecutive 1s are transmitted on the S Interface followed by a logical 0, and DSR1 bit 7 is set to a logical 1. Seven consecutive 1s followed by a 0 will continue to be transmitted as long as INIT bit 7 is set to 1. DSR1 bit 7 will be set after each sequence of seven consecutive 1s followed by 0. Level-2 Frame Structure The D-channel Level-2 frame structure conforms to one of the formats shown in Figure 4. All frames start and end with the flag sequence consisting of one 0 followed by six 1s followed by one 0. A packet consists of a Level-2 frame minus the flag bytes. The LSB is transmitted first for all bytes except the FCS. The flag preceding a packet is defined as the opening flag. Therefore, the byte following an opening flag, by definition, cannot be an abort or another flag. A closing flag is defined as a flag that terminates a packet. This flag can be followed by another flag(s), interframe fill consisting of all 1s or flags, or the address field of the next packet. In the latter case, the closing flag of one packet is the opening flag of the next packet. The DLC receiver can recognize interframe fill consisting of logical 1s or flags. The DLC transmitter follows the closing flag with interframe fill consisting of all 1s (mark Idle) if DMR4 bit 4 is set to a logical 0, or all 0s (flag Idle) if DMR4 bit 4 is set to a logical 1. CCITT I-series D-channel access protocol specifies use of mark Idle. When a collision is detected (mismatch of a D and E bit), a complete frame must be retransmitted. For transfer across the S Interface, the S-Interface frame structure is impressed upon the D-channel frame structure (LAPD). Zero Insertion / Deletion When transmitting, the DLC examines the frame content between the opening and closing flags. To ensure
D-channel Processing
Random Number Generator (RNG) The RNG is accessible by the microprocessor and operates in the following manner. On the Low-to-High transition of the reset signal, the RNG is cleared, then started. The RNG stops when the LSB or MSB of the 16-bit counter is read by the microprocessor, or when the MSB is loaded by the microprocessor. Writing to the MSB of the counter loads this byte but does not start the RNG. The RNG starts when the LSB of the counter is loaded by the microprocessor. Frame Abort The DLC aborts an incoming D-channel frame when seven contiguous logical 1s are received. When this occurs, an End-of-Receive-Packet interrupt is issued to the processor. DER bit 0 is set to a logical 1 when the
Am79C30A / 32A Data Sheet
that a flag sequence is not repeated within the flag boundaries of the frame, a logical 0 bit is automatically inserted after each sequence of five contiguous logical 1s. When receiving, the DLC examines the frame content between the opening and closing flags and automatically discards the first logical 0 which directly follows five contiguous logical 1s. D-Channel Address Recognition The address field, shown in Figure 4, allows for three types of addresses: 1. 1-byte address signified by the LSB of the first address byte being set to a logical 1 2. 2-byte address signified by the LSB of the first address byte being set to a logical 0, and the LSB of the second address byte being set to a logical 1 3. More than 2-byte address signified by the LSB of both the first and second address bytes being set to a logical 0
In the case of the LAPD operating environments, the address is a 2-byte address where the first byte is analogous to the Service Access Point Identifier (SAPI) and the second byte is analogous to the Terminal Endpoint Identifier (TEI) as defined by the CCITT recommendations. The DLC is able to recognize D-channel addresses of all of the three types outlined above. Note that only the first two bytes of a more than 2-byte address can be checked by the DLC. There are four First Received Byte Address Registers (FRARs) which hold the values used to match against the first byte of the incoming address. Similarly, there are four Second Received Byte Address Registers (SRARs) which hold the values used to match against the second byte of the incoming address. FRAR4 defaults to FE hex SRAR4 defaults to FF hex. This default is analogous to the broadcast address defined by the CCITT recommendations. The type of address recognition which is enabled is shown in Table 38
8 OCTET 2
OCTET 3
FLAG 01111110 OCTET FLAG 01111110 OCTET 1 1
ADDRESS 16 bits 2, 3 ADDRESS 16 bits 2, 3
CONTROL 8 bits 4
FCS 16 bits 5, 6
FLAG 01111110 7 FCS 16 bits N-1 FLAG 01111110 N
09893H-4
Minimum Packet
CONTROL 8 bits 4
INFORMATION N bits 5..
General
Figure 4.
Level-2 Frame Structure Formats
Am79C30A / 32A Data Sheet
Table 38. .Address Recognition
DMR4 Bit 7 0 Bit 5 1 7 X X 1 1 1 X X X 1 X 0 X X X 1 X X 0 6 X 1 X X X 1 X X X 1 X 0 DMR1 Bits 5 X X X X 1 X X X 1 X X 0 4 1 X X 1 X X X 1 X X X 0 FRAR1 FRAR3 FRAR4 SRAR1 SRAR2 SRAR3 SRAR4 FRAR1:SRAR1 FRAR2:SRAR2 FRAR3:SRAR3 FRAR4:SRAR4 Address recognition disabled 2-byte address Second received byte-only address Type of address recognition First received byte-only address
If DMR4 bit 6 is set to a logical 0, bit 1 of the FRARs is ignored when matching the first incoming address byte. If DMR4 bit 6 is set to a logical 1, all bits of the FRARs are used when matching the first incoming address byte. FRAR bit 1 is analogous to the C / R bit defined by the CCITT recommendations. The address recognition mechanism for the four FRAR / SRAR addresses can be individually enabled / disabled via DMR1 bits 4-7. First Received Byte-Only Address Recognition If DMR4 bit 5 is set to a logical 1 and DMR4 bit 7 is set to a logical 0, only the first byte of the incoming address is compared with the values stored in the enabled FRARs. An interrupt is generated if there is an address match and the Valid Address interrupt is enabled. If the address matches, the packet will be received. Second Received Byte-Only Address Recognition If DMR4 bits 5 and 7 are set to a logical 1, the DLC compares only the value in the second byte of the incoming address with values stored in the enabled SRARs. An interrupt is generated if there is an address match and the Valid Address interrupt is enabled. If the address matches, the packet will be received. 2-Byte Address Recognition If DMR4 bit 5 is set to a logical 0, the first byte of the incoming address is compared with the values stored in the enabled FRARs, and the second byte of the incoming address is compared with the value stored in the corresponding SRAR. An interrupt is generated if a match is found for both incoming address bytes with a FRAR / SRAR pair and the Valid Address interrupt is enabled. If the address matches, the packet will be received. Disabling Address Recognition If DMR1 bits 4, 5, 6, and 7 are all set to logical 0, all address recognition is disabled and all addresses are rec38
ognized and received. In this case, the Am79C30A / 32A receives the first two bytes following the opening flag (the incoming address), and then issues an End of Address interrupt if the End of Address interrupt is enabled.
DLC Operation
DLC Transmit and Receive FIFOs The DLC Transmit and Receive FIFOs may be configured to the Normal or Extended mode of operation.Normal mode is fully backwards compatible with the Revision D or prior DSC circuit, and is activated upon RESET or if EFCR bit 0 is programmed to logical 0. In Normal mode the Transmit and Receive FIFOs are each 8 bytes in length. The Extended mode of FIFO operation may be activated by programming EFCR bit 0 to a logical 1, increasing the depth of the Transmit and Receive FIFOs to 16 bytes and 32 bytes, respectively. The setting of EFCR bit 0 to logical 1 also alters the available programmable FIFO threshold values set by DMR4 bits 2 and 3. Receiving D-Channel Packets The receiver controls the flow of D-channel data to the D-channel Receive buffer and the termination of a receive packet. Up to two packets can be contained in the D-channel Receive buffer. After receiving an opening flag (a bit sequence of 01111110) and one byte of data which is not an abort or flag on the D channel, the DLC sets the Packet-Reception-in-Progress status bit (bit 2) in D-channel Status Register 1 (DSR1). The DLC then receives the first two bytes (the two address bytes). If address recognition is enabled, the Am79C30A / 32A issues a Valid Address interrupt if a match between the programmed values and the received address is detected. If no match is detected and address recognition is enabled, the DLC ignores the packet. If address recognition is
Am79C30A / 32A Data Sheet
D-Channel Receive and Transmit Errors
Non-Integer Number of Bytes
A non-integer number of bytes occurs when the number of D-channel bits received between opening and closing flags is not divisible by eight. If a received packet consists of a non-integer number of bytes, the DLC sets bit 1 in the D-channel Error Register (DER) to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer.
Underflow
If a received D-channel (including FCS) packet is less than 5 bytes for a 2-byte address packet, an underflow error condition occurs, and the DLC sets DER bit 5 to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer.
Overrun
A D-channel overrun error occurs when the receiver buffer is full, and another byte is received. This can happen if the D-channel Receive buffer fills, and is not read within 425 µs. When this error occurs, the DLC sets DER bit 6 to a logical 1 and terminates the packet.
Frame Check Sequence Error
If a received packet, including its 16-bit Frame Check Sequence, is not received perfectly, the DLC sets DER bit 3 to a logical 1 when the last byte of the associated packet is read from the Receive buffer.
Underrun
A D-channel underrun error occurs when an empty D-channel buffer is transmitted. This can happen if the D-channel Transmit buffer is not loaded within 375 µs of the D-channel Transmit buffer Empty interrupt being asserted (IR bit 0). When this error occurs, the DLC sets DER bit 7 to a logical 1 and terminates the packet.
Receive Packet Abort
If seven contiguous 1s are received while receiving a packet, the packet will be terminated. DER bit 0 will be set to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer.
Overflow
Overflow occurs when the total number of D-channel bytes within a packet (including, only when enabled, the Frame Check Sequence bytes) exceeds the limit contained in the D-channel Receive Byte Limit Register. (See Receiving D-channel Packets section.) When overflow occurs, the DLC terminates the packet, and sets DER bit 4 to a logical 1 when the last byte of the associated packet is read from the D-channel Receive buffer.
Receive Packet Lost
Receive Packet Lost occurs when two outstanding packets have been received and not serviced (the microp