Single port 10/100 Fast Ethernet Transceiver 10/100Mbps Full-dupl

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Single port 10/100 Fast Ethernet Transceiver 10/100Mbps Full-dupl

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IP101A
Single port 10/100 Fast Ethernet Transceiver
10/100Mbps Full-duplex half-duplex Supports Auto MDI/MDIX function Fully compliant with IEEE 802.3/802.3u Supports IEEE 802.3u auto-negotiation Supports RMII interface IEEE 802.3 full duplex control specification Supports Automatic Power Saving mode Supports BaseLine Wander (BLW) compensation Supports Interrupt function Supports repeater mode Single 3.3V power supply with built-in 2.5V regulator DSP-based Transceiver technology Using either 25MHz crystal/oscillator 50MHz oscillator REF_CLK clock source Flexible display speed, duplex, link, activity collision Supports flow control communicate with other through MDIO 0.25u, CMOS technology 48-pin LQFP Support Lead Free package (Please refer Order Information)
General Description
IP101A IEEE 802.3/802.3u compliant single-port Fast Ethernet Transceiver both 100Mbps 10Mbps operations. supports Auto MDI/MDIX function simplify network installation reduce system maintenance cost. improve system performance, IP101A provides hardware interrupt indicate link, speed duplex status change. IP101A also provides Media Independent Interface (MII) Serial Network Interface (SNI) Reduced Media Independent Interface (RMII) connect with different types 10/100Mb Media Access Controller (MAC). IP101A designed category unshielded twisted-pair cable connecting other devices. IP101A Transceiver fabricated with advanced CMOS technology, which chip only requires 3.3V power supply consumes very power Auto Power Saving mode. IP101A implemented Network Interface Adapter with RJ-45 twisted-pair connection. also easily implemented into HUB, Switch, Router, Access Point.
1/39 Copyright 2004, Plus Corp.
July 2005 IP101A LF-DS-R06
IP101A
Table Contents
Features General Description Table Contents. Revision History. Transmit Receive Data Path Block Diagram Assignments Descriptions Register Descriptions. Functional Description Crystal Specifications. Layout Guideline Circuit Diagram interface with RMII interface with connection 6.2.1 Clock Source. 6.2.2 Clock from IP101A Electrical Characteristics D.C. Characteristic 7.1.1 Absolute Maximum Rating. 7.1.2 Power Dissipation 7.1.3 Operating Condition. 7.1.4 Supply Voltage A.C. Characteristic. 7.2.1 Timing 7.2.2 RMII Timing. Order Information. Package Mechanical Specification
Revision History
Revision IP101A LF-DS-R01 IP101A LF-DS-R02 IP101A LF-DS-R03 IP101A LF-DS-R04 IP101A LF-DS-R05 IP101A LF-DS-R06 Change Description Initial release. Crystal Specification Timing. Modify 7.1.2 Power Dissipation page Modify register 5.11 page order information lead free package. Revise general description modify application diagram.
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July 2005 IP101A LF-DS-R06
IP101A
Transmit Receive Data Path Block Diagram
100M
II/SNI/RM Interface
100M
4B/5B Encoder
4B/5B Decoder
Serial Parallel
100M
Registers
100M
Descram bler Scram bler
100M
achester/N Decoder
100M
AutoNegotiation
Serial Parallel
100M
Clock Recovery
100M
Clock Recovery
Parallel Serial Parallel Serial
100M
100M
LT3/NRZI Decoder
100M
Squelch
NRZI/M LT-3 Encoder
NRZ/M anchest Encoder
100M
Engine
100M
Line Driver
RJ-45 Connector
Figure Flow chart IP101A
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IP101A
Assignments
TEST_ON REGOUT
AVDD33
MDI_RN
MDI_RP
MDI_TN
MDI_TP
RTSET
AGND
AGND
MDIO
AN_ENA DPLX RPTR RESET_N ISOL MII_SNIB DGND INTR
RX_ER /LEDMOD RX_DV /CRS_DV RXD0 RXD1
IP101A
Fast Ethernet Single Transceiver Chip pins LQFP package
RXD2 RXD3 DGND RX_CLK/ C50M_O LED4/ PHYAD4 DVDD33 LED3/ PHYAD3
LED1/ PHYAD1
Figure IP101A pins assignment
4/39 Copyright 2004, Plus Corp.
LED2/ PHYAD2
TX_CLK/ REF_CLK
LED0/ PHYAD0
DGND
TX_EN
REGIN
TXD3
TXD2
TXD1
TXD0
/RMII
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IP101A
Descriptions
Type Description Latched Input power reset Bi-directional input output Input Output Label Type Type Description Internal Pull-Down Internal Pull-Up Power Open Drain Description
Interface Management Interface Pins Management Data Interface Clock: This provides clock reference MDIO. clock rate 10MHz. MDIO Management Data interface Input/Output: function this transfer management information between MAC.
Interface Media Independent Interface (MII) Pins TX_EN Transmit Enable: This active high input. high status, (PD) indicates nibble data TXD[3:0] valid. TX_CLK Transmit Clock: This provides continuous 25MHz clock 100BT 2.5Mbps 10BT timing reference TXD[3:0] TX_EN when chip operates under MII. Transmit Data: When TX_EN high, will transmit data through these lines which transmission synchronizing with TX_CLK. Receive Data Valid: high status stands data flow present within RXD[0:3] lines means data exchange occurred. Receive Clock: This provides 25MHz 100BT 2.5Mhz 10BT RX_DV uses this reference under MII. Receive Data: These data lines transmission path send data they synchronizing with RX_CLK.
TXD[3:0]
RX_DV
RX_CLK RXD[3:0]
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IP101A
Descriptions (continued)
Label Type Description Interface Media Independent Interface (MII) Pins RX_ER Receive error: This outputs high status when errors (PD) occurred decoded data reception. (Notice: This pulled down internally) COL/RMII O/LI (PD) Collision Detected: When this outputs high status signal means collision detected. RMII Mode: During power reset, this status latched arranged with MII/SNIB (pin44) determine interface RMII MII/SNIB RMII Interface Interface SNII Interface (Notice: This pulled down internally) Carrier Sense: When signal output from this high indicates transmission reception process status means line idle state. LEDMOD: During power reset, this status latched determine which mode operate, please refer pins description. (Notice: This pulled down internally)
CRS/LEDMOD
(PD)
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IP101A
Descriptions (continued)
Label Type Description Reference Clock: This input operates 50MHz reference clock (REF_CLK) RMII mode. Please refer clock source description page24. Reference Clock out: This could configured 50MHz clock output RMII mode. With 25MHz crystal/oscillator, IP101A could generate 50MHz output RMII mode. Please refer clock source description page24. Transmit Enable: indicate transmit operation Transmit two-bit Data Receive Error Carrier Sense Receive Data Valid RMII (Reduced MII) REF_CLK
C50M_O
TX_EN TXD[1:0] RX_ER CRS_DV RXD[1:0]
(PD)
Received two-bit Data (Serial Network Interface): 10Mbps only TX_EN Transmit Enable: Indicate transmit operation (PD) TX_CLK TXD0 RX_CLK RXD0 Transmit Clock: 10MHz, clock generated Transmit Serial Data Receive Clock: 10MHz, clock recovery from received data Received Serial Data Collision Detect Carrier Sense Transmit Output Pair: Differential pair shared 100Base-TX 10Base-T modes. When configured 100Base-TX, output MLT-3 encoded waveform. When configured 10Base-TX, output Manchester code. Receive Input Pair: Differential pair shared 100Base-TX 10Base-T modes.
Cable Transmission Interface MDI_TP MDI_TN
MDI_RP MDI_RN
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July 2005 IP101A LF-DS-R06
IP101A
Descriptions (continued)
Label Type (PD) Description high this will isolate IP101A from other MAC. This action will also isolate MDC/MDIO management interface. power usage minimum when this activated. This directly connected VCC. internal weak pulled-down used inactive default) Enable this high will IP101A into repeater mode. This directly connected VCC. internal weak pulled-down used inactive default) This latched input during power reset condition. high IP101A into 100Mbps operation. This directly connected VCC. internal weak pulled-up used 100Mbps default) This latched input during power reset condition. high enable full duplex. This directly connected VCC. internal weak pulled-up used full duplex default) This latched input during power reset condition. high enable auto-negotiation mode, force mode. This directly connected VCC. internal weak pulled-up used enable Auto-Negotiation default) high IP101A into mode. This directly connected VCC. Please refer page25 power down modes description more information. internal weak pulled-up used enable mode default) This latched input during power reset condition. Pull high IP101A into mode operation. mode. This directly connected VCC. internal weak pulled-up used mode default) Configuration Options ISOL
RPTR
(PD) LI/O (PU)
DPLX
LI/O (PU)
AN_ENA
LI/O (PU)
(PU)
MII_SNIB
LI/O (PU)
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IP101A
Descriptions (continued)
Label Type Description Address Configuration These five pins latched into IP101A during reset configure address [4:0] used management register interface. then, normal operation after initial reset, they used driving pins status indication LED. driving polarity, active active high, determined each latched status address [4:0] during reset. latched status high then will active low, latched status then will active high. Moreover, IP101A provides operation modes. mode selected pulling CRS, only LEDs needed status indication. Default first mode. mode LINK FULL DUPLEX 10BT /ACT(blinking) 100BT /ACT(blinking) LI/O mode LINK /ACT(blinking) FULL DUPLEX /COL(blinking) 10BT 100BT Reserved
LED0 LED1 LED2 LED3 LED4 PHYAD0/ LED0
Address Status: Mode1: Active when linked. Mode2: Active when linked blinking when transmitting receiving data. Address Status: Mode1: Active when Full Duplex operation. Mode2: Active when Full Duplex operation blinking when collisions occur. Address Status: Mode1: Active when linked 10Base-T mode, blinking when transmitting receiving data. Mode2: Active when linked 10Base-T mode. Address Status: Mode1: Active when linked 100Base-TX blinking when transmitting receiving data. Mode2: Active when linked 100Base-TX mode. Address Status: Mode1: Active when collisions occur. Mode2: Reserved.
PHYAD1/ LED1
LI/O
PHYAD2/ LED2
LI/O
PHYAD3/ LED3
LI/O
PHYAD4/ LED4
LI/O
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IP101A
Descriptions (continued)
Label Type Description Clock Miscellaneous Crystal Input/Output Pins 25MHz Crystal Output: Connects crystal provide 25MHz output. must left open when driven with external 25MHz oscillator. 25MHz Crystal Input: Connects crystal provide 25MHz crystal input. 25MHz oscillator used, connect oscillator's output. input voltage this should exceed 2.75v. voltage divider formed resistors recommended output voltage oscillator over 2.75v. Please refer application circuit. 50MHz clock applied pin7, should connected 2.5v VDD. Please refer clock source description.
Clock Miscellaneous Miscellaneous Pins RESET_N RESET_N: Enable status signal will reset chip. complete reset function. 25MHz clock (x1) must active minimum clock cycles before rising edge RESET_N. Chip will able operate after 2.5ms delay rising edge RESET_N. 2.5ms extention ensure stability system power. INTR Interrupt Pin: When register 17:<15> high, this (OD) used interrupt (Notice: this open drain output, external pulled-up resistor needed) TEST_ON (PD) Test Enable: this high enable test mode, while normal operation, this does need connected. internal weak pulled-down used disable test mode default) ISET Transmit Bias Resistor Connection: This should connected 6.2K (1%) resistor define driving current transmit DAC.
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IP101A
Descriptions (continued)
Label Type Description Regulator Power Output: This regulator power output IP101A digital circuitry. 3.3V Analog power input: This 3.3V power supply analog circuitry, should decoupled carefully. Analog Ground: These pins should connect motherboard's GND. Regulator Power Input: This regulator power input from Pin32. external regulator needed. 3.3V Digital Power input: This 3.3V power supply digital circuitry. Digital Ground: These pins should connect motherboard's GND. Power Ground REGOUT 29,35 11,17,45 AVDD33 AGND REGIN DVDD33 DGND
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IP101A
Register Descriptions
Name Description/Usage Default value (h): 3100
Register Control Register Reset When set, this action will bring both status control registers default state. This self-clearing. Software reset Normal operation This enables loop-back transmit data receive data path, i.e., RXD. IP101A requires least 512us link after programming this bit. TX/RX packets should activated after 512us. enable loop-back normal operation This sets speed transmission. 100Mbps 10Mbps This determines auto-negotiation function. enable auto-negotiation; bits will ignored. disable auto-negotiation; bits 0:<8> will determine link speed data transfer mode, under this condition. Auto-MDIX function should disabled (set Reg16.11=1) this been "0". Please refer section Auto-MDIX function description details. This will turn down power chip internal crystal oscillator circuit this enabled. MDIO still activated accessing MAC. power down normal operation 1=electrically Isolate from isolate MDIO 0=normal operation This allows auto-negotiation function reset. restart auto-negotiation normal operation This sets duplex mode auto-negotiation disabled (bit 12=0) full duplex half duplex After completing auto-negotiation, this will reflect duplex status.(1: Full duplex, Half duplex) 1=enable signal test 0=disable signal test
Loop-back
Speed Selection
AutoNegotiation Enable
(TP)
Power Down
Isolate
0,RW
Restart AutoNegotiation Duplex Mode
Collision Test Reserved
0,RW
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IP101A
Register Descriptions (continued)
Name Description/Usage Default value (h): 7849 IP101A will accept management frames with preamble suppressed. IP101A accepts management frames without preamble. Minimum preamble bits required first read/write transaction after reset. idle required between management transactions IEEE802.3u specifications auto-negotiation process completed auto-negotiation process completed remote fault condition detected (cleared read) remote fault condition detected Link been experienced fail state Link been experienced fail state valid link established valid link established jabber condition detected jabber condition detected extended register capability basic register capability only
Register Status Register 100Base-T4 enable 100Base-T4 support suppress 100Base-T4 support 10:7 100Base-TX Full Duplex 100BASE-TX Half Duplex 10Base-T Full Duplex 10_Base-T Half Duplex Reserved Preamble Suppression enable 100Base-TX full duplex support suppress 100Base-TX full duplex support enable 100Base-TX half duplex support suppress 100Base-TX half duplex support enable 10Base-T full duplex support suppress 10Base-T full duplex support enable 10Base-T half duplex support suppress 10Base-T half duplex support
AutoNegotiation Complete Remote Fault AutoNegotiation Link Status Jabber Detect Extended Capability
RO/LH RO/LL RO/LH
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Register Descriptions (continued)
Name Description/Usage Default value (h): 0243 0X0243, Default value (h): 0C50 0X0C50,
Register Identifier Register 15:0 PHYID1 identifier software recognize IP101A
Name
Description/Usage
Register Identifier Register 15:0 PHYID2 identifier software recognize
Note Register register identifier registers altogether consist Vender model, model revision number Organizationally Unique identifier (OUI) information. Total bits allocate these registers they return zeroes bits desired. Register contains OUI's most significant bits OUI's lest significant bits, Vender model, Model revision number allocated register
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IP101A
Register Descriptions (continued)
Register lists advertised abilities during auto-negotiation what will transmitted IP101A LF's Link Partner. Name Description/Usage Default value (h): 0001
Register Auto-Negotiation Advertisement Register Next Page bit. transmitting primary capability data page transmitting protocol specific data page Reserved Reserved Asymmetric. Pause Pause Full Duplex Full Duplex Selector asymmetric flow control supported local node asymmetric flow control supported local node flow control supported local node flow control supported local node 100Base-T4 supported local node 100Base-T4 supported local node 100Base-TX full duplex supported local node 100Base-TX full duplex supported local node 100Base-TX supported local node 100Base-TX supported local node 10Base-T full duplex supported local node 10Base-T full duplex supported local node 10Base-T supported local node 10Base-T supported local node Binary encoded selector supported this node. Currently only CSMA/CD <00001> specified. other protocols supported. advertise remote fault detection capability advertise remote fault detection capability
<00001>,
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IP101A
Register Descriptions (continued)
This register contains advertised abilities Link Partner received during Auto-negotiation. content changes after successful Auto-negotiation Next-pages supported. Name Description/Usage Default value (h): 0000
Register Auto-Negotiation Link Partner Ability Register (ANLPAR) Next Page Next Page bit. transmitting primary capability data page transmitting protocol specific data page Acknowledge link partner acknowledges reception local node's capability data word acknowledgement link partner indicating remote fault link partner does indicate remote fault asymmetric flow control supported link partner asymmetric flow control supported link partner flow control supported Link partner flow control supported Link partner 100Base-T4 supported link partner 100Base-T4 supported link partner 100Base-TX full duplex supported link partner 100Base-TX full duplex supported link partner 100Base-TX supported link partner 100Base-TX supported link partner This will also after link 100Base established parallel detection. 10Base-T full duplex supported link partner 10Base-T full duplex supported link partner 10Base-T supported link partner 10Base-T supported link partner This will also after link 10Base established parallel detection. Link Partner's binary encoded node selector Currently only CSMA/CD <00001> specified
Remote Fault Reserved Asymmetric. Pause Pause TXFD 100BASE-TX
10FD 10Base-T
Selector
<00000>,
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IP101A
Register Descriptions (continued)
Register defines more auto-negotiation registers meet requirement. Name Description/Usage Default value (h): 0000
Register Auto-Negotiation Expansion Register 15:5 Reserved This always This status indicates multiple link fault occurred. fault occurred fault occurred This status indicates link partner supports Next Page negotiation. supported supported This indicates device able send additional Next Pages. This will link code word page been received. cleared automatically after auto-negotiation link partner's ability register (register read management. link partner supports auto-negotiation.
LP_NP_ABLE
NP_ABLE PAGE_RX
LP_NW_ABLE
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Register Descriptions (continued)
Name Description/Usage Default value (h): 0000
Register Spec. Control Register Debug Mode IP101A operates normal mode IP101A operates debug mode (Notice functionalities 16:<14>, 16:<13>, 16:<12>, 16:<4:0> depend setting this 16:<15> 14:12 Reserved Auto MDIX high disable automatic switch MDI-X modes. disabled setting pin37=0 during power this will (Auto-MDIX off) automatically. Setting Reg0.12=1 will re-activate this case, user needs Auto-MDIX function, this should details, please refer section Auto-MDIX function description. Heart beat function enable 10Base-T Jabber function enable 10Base-T enable disable functionality Far-End Fault Mode Enable Disable 100Base-TX high disable power saving during auto-negotiation
Heart Beat Enable Jabber Enable Far-End Fault Enable/Disable Analog Power Saving Disable Reserved Bypass reset Reserved Repeater Mode Mode Analog
high bypass reset mechanism sub-layer high IP101A into repeater mode high enable Auto Power Saving mode high power down analog transceiver
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IP101A
Register Descriptions (continued)
Name Description/Usage Default value (h): 0E00 When this high, changes events will cause interrupt When this high, changes speed mode will cause interrupt When this high, changes duplex mode will cause interrupt When this high, changes link status will cause interrupt When this low, changes Auto-Negotiation arbiter state machine will cause interrupt Flag indicate Auto-Negotiation arbiter change interrupt
Register Interrupt Ctrl/Status Register INTR used high enable pin48 interrupt pin. Pin48 will high impedance this low. 14:12 Reserved Mask Speed Mask Duplex Mask Link Mask Arbiter State Enable Arbiter State Change Reserved Link Status Change Speed Change Duplex Change
Flag indicate link status change interrupt Flag indicate speed change interrupt Flag indicate duplex change interrupt
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July 2005 IP101A LF-DS-R06
IP101A
Functional Description
IP101A 10/100Mbps Ethernet Transceiver integrates Base-TX Base-T modules into single chip. IP101A acts interface between physical signaling Media Access Controller (MAC). IP101A several major functions: layer (Physical Coding Sub-Layer): This function contains transmit, receive carrier sense functional circuitries. Management interface: Media Independent Interface (MII) Reduced Management Interface (RMII) registers contains information communication with other MAC. Auto-Negotiation: Communication conditions between transceivers. IP101A advertise ability also detects corresponding operational mode from other party, eventually both sides will come agreement their optimized transmission mode. IP101A LF's major features included: Flow Control ability configuration access Operation modes both full half duplex (Auto Power Saving) mode Base Line Wander (BLW) compensation Auto MDI/MDIX function Interrupt function Repeater Mode Flexible clock source
Major Functional Block Description functional blocks diagram referred Figure 4B/5B encoder: Base-X transmissions require converting 4-bit nibble data into 5-bit wide data code-word format. Transmitting data packaged codes start packet codes packet 4B/5B block. When transmit error occurred during transmitting process, error code will sent. idle code sent between packets. 4B/5B Decoder: decoder performs 5B/4B decoding from received code-groups. bits (5B) data decoded into four bits nibble data. decoded (4B) data then forwarded through repeater, switch device. then converted into nibbles IDLE Codes replaced nibbles data. decoded data driven onto corresponding port shared port. Receiving invalid code group will cause assert RXER signal. Scrambler/Descrambler: Repetitive patterns exist 4B/5B encoded data which result large spectrum peaks keep system from being approved regulatory agencies. peak radiated signal reduced significantly scrambling transmitted signal. Scrambler adds random generator data signal output. resulting signal with fewer repetitive data patterns. scrambled data stream descrambled receiver adding another random generator output. receiver's random generator same function transmitter's random generator. Scrambler operation dictated 100Base-X TP_FDDI standards. NRZI/MLT-3(Manchester) Encoder Decoder: Base-TX Transmission requires encode data into format again converted into MLT-3 signal, while Base-T will convert into Manchester form after coding. This helps remove high frequency noise generated twisted pair cables. receiving end, coding reversed from MLT-3 (Manchester) signal back
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IP101A
format. Clock Recovery: receiver circuit recovers data from input stream regenerating clocking information embedded serial stream. clock recovery block extracts RXCLK from transition received Engine: This block includes Adaptive equalizer Base Line Wander correction function.
Transmission Description 10Mbps Transmit flow path: Parallel Serial NRZI/Manchester Encoder line driver After passes data bits nibbles, data serialized parallel serial converter. converter outputs NRZI coded data which data then mapped Manchester code within Manchester Encoder. Before transmitting physical medium, Manchester coded data shaped converter physical medium. 10Mbps Receive: Squelch Clock Recovery Manchester/NRZ Decoder Serial Parallel squelch block determines valid data from both timing amplitude measurement. When valid data present medium, squelch block will generate signal indicate data received. data receive coded Manchester form, decoded Manchester Decoder. Then data mapped bits nibbles transmitted onto interface. 100Mbps Transmit: 4B/5B Encoder Scrambler NRZI/MLT-3 Encoder line driver major differences between 10Mbps transmission 100Mbps transmission that 100Mbps transmission requires coded from 4-bit wide nibbles bits wide data coding, after that data scrambled through scrambler reduce radiated energy generated 4B/5B conversion. Then data converted into NRZI form again from NRZI coded form into MLT-3 form. MLT-3 data form into converter shaped physical medium transmission. 100Mbps Receive: Serial Parallel Descrambler 4B/5B Decoder received data first through engines which includes adaptive equalizer base-line wander correction mechanism. adaptive equalizer will compensate loss signals during transmission, while base-line wander monitors corrects equalization process. valid data detected then data parallelized Serial Parallel block, which converts NRZI coded data form back scrambled data. scrambled data descrambled converted back bits-wide format data then feed into MAC. Management Control Interface Media Independent Interface (MII) described clause IEEE 802.3u standard. main function this interface provide communication path between MAC/Repeater. operate either 10Mb 100Mb environment, operate 2.5MHz frequency 10Mb clock data rate 25MHz frequency 100Mb data rate transmission. consists wide data path both transmit receive. transmission pins consists TXD[3:0], TX_EN TXC, receiving pins have RXD[3:0], RXER, RX_DV RXC. Management control pins include MDIO. MDC, Management Data Clock, provides management data clock maximum 10MHz reference MDIO, Management Data Input/Output. CRS, Carrier Sense, used signaling data transmission
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IP101A
process while COL, Collision, used signaling occurrence collision during transmission. Transmitting packet, will first assert TX_EN convert information into wide data then pass data IP101A IP101A will sample data according TX_CLK until TX_EN low. While receiving packet, IP101A asserts RX_DV high when data present medium through RXD[3:0] lines. IP101A samples received data according RX_CLK until medium back idle state.
RMII Interface Reduced Media Independent Interface (RMII) defined provide fewer pins data transmission condition. management interface, MDIO, identical defined IEEE 802.3. RMII supports 10/100Mb data rates clock source provided single 50MHz clock from either external within IP101A This clock used reference transmit, receive control. RMII provides independent wide transmit receive data path, i.e., TXD[1:0] RXD[1:0]. CRS_DV asserted when receive medium idle de-asserted when medium idle. Before transmission occurs, CRS_DV should de-asserted value "00" should present both TXD[1:0] RXD[1:0]. When transmission begins, IP101A will send "01" (TXD[1:0] preamble indicate SFD, also assert TX_EN synchronous with first nibble preamble. TX_EN should de-asserted until data transmission. receiving mechanism, receiving "01" means valid data available. False carrier detected, RXD[1:0] shall "10" until transmission. 10Mbps mode, every 10th cycle REF_CLK will sampled RXD[1:0] TXD[1:], because REF_CLK frequency times faster than data rate 10Mbps.
Interface IP101A also provides serial-network interface legacy MACs, when chip operates 10BASE-T either Auto-Negotiation resolved result forced mode. setup this mode operation, pull both MII/SNIB COL/RMII pins low. transaction protocol interface almost identical that interface, except data width clock rate. This interface consists 10Mbps transmit receive clock generated PHY's digital phase-locked loop (DPLL), 10Mbps transmit receive serial data, transmit enable, collision detect, carry sense signals.
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July 2005 IP101A LF-DS-R06
IP101A
Auto-Negotiation Related Information IP101A supports clause IEEE 802.3u standard. IP101A operated either 10Mbps/100Mbps half/full duplex transmission mode. IP101A also supports flow control mechanism prevent collision network. other does support Auto-Negotiation function, IP101A will link half duplex mode enter parallel detection. beginning auto-negotiation, IP101A will advertise ability sending waveform other also listening signals from other end. IP101A will place itself into correct connection speed depends received signals. signal replied from other end, IP101A will enter 10Mbps, while active idle pulses (unique 100Mbps pattern) IP101A will 100Mbps mode instead. Once negotiation completed with other party, IP101A will configure itself desired connection mode, i.e., 10/100Mbps Half/Full duplex modes. there detection link pulses within 1200ms~1500mS, IP101A will enter Link Fail State restart auto-negotiation procedure. auto-negotiation information stored IP101A LF's registers. These registers modified monitor IP101A LF's Auto-Negotiation status. reset auto-negotiation register registers time restart auto-negotiation. flow control ability also included IP101A chip. supports flow control condition, then flow control will enabled setting (Pause) Register (AN_ENA), (DLPX), (SPD) configured manually IP101A LF's transmission ability. Enabling (set high) will IP101A Auto-Negotiation mode, will IP101A into forced mode. will configure Duplex ability IP101A high, IP101A Full-Duplex will IP101A enter half duplex mode. determines speed connection. pulled high, IP101A 100Mbps, while will make IP101A connect 10Mbps speed. AN_ENA (Pin DLPX (Pin38) (Pin39) Operation Auto-Negotiation enable, ability field does support 100Mbps full duplex mode operation Auto-Negotiation enable, ability field does support 100Mbps operation Auto-Negotiation enable, ability field does support full duplex mode operation Default setup, auto-negotiation enable, IP101A will support 10BT/100BT, half/full duplex mode operation Auto-Negotiation disable, force IP101A into 10BT half duplex mode. Auto-Negotiation disable, force IP101A into 10BT full duplex mode. Auto-Negotiation disable, force IP101A into 100BT half duplex mode. Auto-Negotiation disable, force IP101A into 100BT full duplex mode.
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July 2005 IP101A LF-DS-R06
IP101A
Auto MDIX function IP101A will keep sensing incoming signal pair, incoming signal detected, IP101A will switch pairs automatically trying establish connection. IP101A supports this function both Auto-Negotiation mode force mode.
Configuration IP101A provides operation modes, Mode (default): LED0 LED1 LED2 LED3 LED4 Function Link status: Active indicates link established Duplex operation: Active indicates full duplex 10BT/ACT: Active indicates 10Mbps connection established, blinking while TX/RX events occur. 100BT/ACT: Active indicates 100Mbps connection established, blinking while TX/RX events occur. Collision detect: Active indicates Collision occurred
Mode (could pulling with 4.7K resistor): LED0 LED1 LED2 LED3 LED4 Function Link/ACT: Active indicates link established, blinking while TX/RX events occur. Duplex/COL: Active indicates full duplex, blinking while collision events occur. 10BT: Active indicates 10Mbps connection established 100BT: Active indicates 100Mbps connection established
pins also include information address, default address 00001b (01h). address modified changing circuitry. modification arranged follow:
VDD33
5.1k
5.1k LEDx {X=0:4}
LEDx {X=0:4}
Figure address Configuration left diagram will enable specific address connected VDD33. diagram right shows configuration setting address when circuit connected ground. setting either bits according diagram will allow modify addresses from PHYAD0 PHYAD4.
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IP101A
Flexible Clock Source Pin1 COL/RMII Pin44 MII/SNIB Function RMII, pin7 RMII, crystal from X1,X2; pin16. (Please refer following figure recommened application circuit.) MII, crystal from X1,X2 SNI, crystal from X1,X2
While pin1=1 pin44=0 been selected, clock will provided IP101A RMII mode. suggest application circuit following
CPU/Switch/MAC
50MHz colck
Other
Buffer
Pin16 Pin7
IP101A
Pin46 Pin47
this configuration, RMII reference clock IP101A from pin7. Clock skew could eliminated adding external buffer placing equal trace lengths between buffer outputs each chip.
25/39 Copyright 2004, Plus Corp.
July 2005 IP101A LF-DS-R06
IP101A
Power-Down Modes IP101A power-down methods. These methods follow: Power Down Register Enable this will disconnect power IP101A also internal clock, MDIO still activated. mode Register high this will into power saving mode(APS sleeping mode) while link down, MDIO kept activated. IP101A will send every 64ms during sleeping mode. Analog Register Enable this will IP101A analog state. This will power down analog functions internal 25MHz operating clock active, MDIO also activated. ISOL (pin 43): high will isolate IP101A from disable management interface (MDC MDIO). power usage minimum when this activated.
Repeater Modes enter Repeater mode, either (RPTR) high Register will allow IP101A enter Repeater mode. IP101A used repeater, will high process receiving packets, while IP101A used network interface card, will generated both transmitting receiving packets.
Miscellaneous ISET (pin should connected 6.2k resistor with accuracy ensure correct driving current transmit DAC. REST_N, least 10ms will reset functions available IP101A Register will into default status.
Interrupt IP101A provides kinds interrupt function: speed change, duplex change, link change arbiter state change. Interrupt masks could selected active interrupt will sent from pin48 when event occurs.
26/39 Copyright 2004, Plus Corp.
July 2005 IP101A LF-DS-R06
IP101A
Crystal Specifications
Item Parameter Nominal Frequency Oscillation Mode Frequency Tolerance Temperature Characteristics Operating Temperature Range Equivalent Series Resistance Drive Level Load Capacitance Shunt Capacitance Insulation Resistance Aging Rate Year 25.000 Fundamental Mode Max. 100W Mega Min./DC 100V ppm/year Range
27/39 Copyright 2004, Plus Corp.
July 2005 IP101A LF-DS-R06
IP101A
Layout Guideline
General Layout Guideline Best performance depends good layout. following recommendation steps will help customer gain maximum performance. Create good power source minimize noise from switching power source. components qualified, especially high noise component, such clock component. bulk capacitors between power plane ground plane layers board, signals trace component bottom side, power plane third layer, ground layer second layer. decoupling capacitors decouple high frequency noise between chip's power ground, must close possible IP101A clock trace length IP101A must equal clock trace length MAC. guard traces protect clock traces possible Avoid signals path parallel clock signals path, because clock signals will interference with other parallel signals, degrading signal quality, such X1signals. clock must jitter with less than 0.5ns 25/50/125Mhz 100ppm. Avoid highly speed signal across ground prevent large effect. Keep ground region continuous unbroken plane. Place between system chassis grounds. ground loop exists chassis ground.
Twisted Pair recommendation When routing TD+/- signal traces from IP101A transformer, traces should short possible, termination resistors should close possible output TD+/- pair IP101A Center primary winding these transformers must connected analog 2.5V respectively. recommended that RD+/- trace pair route such that space between others three times space, which separate individual traces from another. recommended that offers chassis ground area between transformer media connector (RJ-45 port), this isolates analog signals from external noise sources reduces effect. Note usage vias, best place anywhere other than close proximity device, order minimize impedance variations given signal trace.
28/39 Copyright 2004, Plus Corp.
July 2005 IP101A LF-DS-R06
IP101A
Circuit Diagram
There suggested applications IP101A
interface with
VDD33 5.1K MDIO TXD0 TXD1 TXD2 TXD3 TX_EN TX_CLK RX_DV RXD0 RXD1 RXD2 RXD3 RX_CLK CRS/LEDMOD RX_ER/FIBMOD PHYAD0/LED0 PHYAD1/LED1 PHYAD2/LED2 PHYAD3/LED3 PHYAD4/LED4 REGIN VDD33 5.1k MDIO TXD0 TXD1 TXD2 TXD3 TX_EN TX_CLK RX_DV RXD0 RXD1 RXD2 RXD3 RX_CLK CRS/LEDMOD RX_ER/FIBMOD PHYAD0/LED0 PHYAD1/LED1 PHYAD2/LED2 PHYAD3/LED3 PHYAD4/LED4 REGIN DVDD33 INTR/FIB_DIS DGND DGND DGND IP101A LQFP48 0.1U RESET_N VDD33 RESET_N REGOUT AVDD33 AGND AGND REGOUT AVDD33
Chip Diagram
VDD33
5.1K
CRS/LEDMOD
mode
IP101A
TEST_ON
Floating pull-low
MDI_RP MDI_RN MDI_TN MDI_TP
MDI_RP MDI_RN MDI_TN MDI_TP ISET ISOL RPTR DPLX AN_ENA RESET_N
C25M
25.000Mhz
"C25M" with 3.3V output swing
crystal
ISOL RPTR DPLX AN_ENA
6.2K
Floating pull-high
BANDGAP REGISTER
Default setting
Optional ,but recommended Pin48 could short VDD33 interrupt funtion used.
5.1K
0.1U
RESET Circuitry
Title
IP101A Chip Circuit Diagram
Size Document Number Custom Date: 2004
Sheet
<RevCode>
Transformer
0.1U
Optional ,but recommended
50(1%) 50(1%) MDI_RP MDI_RN MDI_TN MDI_TP RDCT TDCT 16PT8515 RXTXCMT
CH_GND
supression
TXRX+ RXN/C RJ8-45 CH_GND 0.1U 0.1U
50(1%)
50(1%)
0.1U REGOUT
Only resister needed transformer have been shorted inside.
REGOUT CH_GND
(CONNECT CHASSIS GND)
0.01U/3KV
0.01U
0.1U
0.1U Title
0.01U
IP101A Chip Circuit Diagram
Size Document Number Custom Date: 2004
Sheet
<RevCode>
29/39 Copyright 2004, Plus Corp.
July 2005 IP101A LF-DS-R06
IP101A
interface with (continued)
address Configuration Power: 3.3V
VCC5V
LM1117 VDD33
This schematic sets address 00001b.
5.1K VDD33
INPUT OUTPUT ADJ/GND
P0PHYAD0/LED0
P0PHYAD1/LED1 P0PHYAD2/LED2 P0PHYAD3/LED3 P0PHYAD4/LED4
5.1K
REGOUT REGIN connection Analog Digital 3.3V connection
REGOUT REGOUT BEAD REGIN
5.1K
5.1K
0.1U
0.01U
0.1U
5.1K
Optional ,but recommended
Hardwire Configuration network:
This configuration shows Enable: Auto negotiation, Full duplex, 100Mbps, Link Down Power Saving, interface Disable: Isolate, Repeater mode These senven configuration pins could connected directly.
VDD33
BEAD
AVDD33 0.1U
LED0 Link
LED1 Dupx
LED2 10Act
LED3 100Act
LED4
Title
IP101A Chip Circuit Diagram
Size Date: Document Number
2004 Sheet
<RevCode>
30/39 Copyright 2004, Plus Corp.
July 2005 IP101A LF-DS-R06
IP101A
6.2.1
RMII interface with connection
Clock Source
VDD33 5.1K MDIO P0TXD0 P0TXD1 P0TX_EN REF_CLK P0CRS_DV P0RXD0 P0RXD1 MDIO TXD0 TXD1 TXD2 TXD3 TX_EN TX_CLK/REF_CLK CRS_DV RXD0 RXD1 RXD2 RXD3 RX_CLK COL/RMII RX_ER/FIBMOD PHYAD0/LED0 PHYAD1/LED1 PHYAD2/LED2 PHYAD3/LED3 PHYAD4/LED4 REGIN DVDD33 INTR/FIB_DIS DGND DGND DGND IP101A LQFP48 RESET_N REGOUT AVDD33 AGND AGND REGOUT AVDD33 0.1U
Chip Diagram
VDD33 5.1k P0COL
TEST_ON
MDI_RP MDI_RN MDI_TN MDI_TP ISET ISOL RPTR DPLX AN_ENA RESET_N
MDI_RP MDI_RN MDI_TN MDI_TP
P0RX_ER/FIBMOD
Note1. Could also pulled down
5.1k
P0PHYAD0/LED0 P0PHYAD1/LED1 P0PHYAD2/LED2 P0PHYAD3/LED3 P0PHYAD4/LED4 REGIN VDD33 P0INT 5.1k
P0ISO P0RPTR P0SPD P0DPLX P0AN_ENA P0APS P0MII_SNIB 6.2K (1%)
Optional ,but recommended
BAND REGISTER
RESET_N 0.1U VDD33
5.1K
0.1U
RESET Circuitry
Title
IP101A Chip Circuit Diagram
Size Document Number Custom Date: 2004
RMII
Sheet
<RevCode>
Transformer
0.1U
Optional ,but recommended
50(1%) 50(1%) MDI_RP MDI_RN MDI_TN MDI_TP RDCT TDCT 16PT8515 RXTXCMT
CH_GND
supression
TXRX+ RXN/C RJ8-45 CH_GND 0.1U 0.1U
50(1%)
50(1%)
0.1U REGOUT
Only resister needed transformer have been shorted inside.
REGOUT 0.1U CH_GND
(CONNECT CHASSIS GND)
0.01U/3KV
0.01U
0.1U
0.01U
Title
IP101A Chip Circuit Diagram
Size Document Number Custom Date: 2004
RMII
Sheet
<RevCode>
31/39 Copyright 2004, Plus Corp.
July 2005 IP101A LF-DS-R06
IP101A
address Configuration
This schematic sets address 00001b.
P0PHYAD0/LED0 5.1K VDD33 50MHZ (HALF)
CLOCK
0.1UF 4.7UF CHOKE 10UF VDD33
REF_CLK
RER_CLK
P0PHYAD1/LED1 P0PHYAD2/LED2 P0PHYAD3/LED3 P0PHYAD4/LED4
5.1K
Oscillator's clock MUST same distance from chipsets. REGOUT REGIN connection
REGOUT REGOUT BEAD REGIN
5.1K
Analog Digital 3.3V connection
BEAD
0.1U
0.01U
0.1U VDD33 AVDD33 0.1U
5.1K
Optional ,but recommended Hardwire Configuration network:
This configuration shows Enable: Auto negotiation, Full duplex, 100Mbps, Link Down Power Saving, interface Disable: Isolate, Repeater mode These senven configuration pins could connected directly.
5.1K
LED0 Link
LED1 Dupx
LED2 10Act
LED3 100Act
LED4
Title
IP101A Chip Circuit Diagram
Size Document Number Custom Date: 2004
RMII
Sheet
<RevCode>
32/39 Copyright 2004, Plus Corp.
July 2005 IP101A LF-DS-R06
IP101A
6.2.2 Clock from IP101A
VDD33 5.1K P0TX_EN REFCLK_IP101A P0CRS_DV P0RXD0 P0RXD1 P0RX_ER/FIBMOD P0PHYAD0/LED0 P0PHYAD1/LED1 P0PHYAD2/LED2 P0PHYAD3/LED3 P0PHYAD4/LED4 REGIN VDD33 P0INT 5.1k MDIO P0TXD0 P0TXD1 MDIO TXD0 TXD1 TXD2 TXD3 TX_EN TX_CLK/REF_CLK CRS_DV RXD0 RXD1 RXD2 RXD3 RX_CLK COL/RMII RX_ER/FIBMOD PHYAD0/LED0 PHYAD1/LED1 PHYAD2/LED2 PHYAD3/LED3 PHYAD4/LED4 REGIN DVDD33 INTR/FIB_DIS DGND DGND DGND IP101A LQFP48 RESET_N REGOUT AVDD33 AGND AGND REGOUT AVDD33 0.1U
Chip Diagram
VDD33 5.1k
50MHZ CLOCK Generate IP101A
50MHz_CLKOUT
TEST_ON
P0COL 25Mhz
MDI_RP MDI_RN MDI_TN MDI_TP ISET ISOL RPTR DPLX AN_ENA RESET_N
MDI_RP MDI_RN MDI_TN MDI_TP
P0ISO P0RPTR P0SPD P0DPLX P0AN_ENA P0APS P0MII_SNIB 6.2K (1%)
Optional ,but recommended
BAND REGISTER
RESET_N 0.1U VDD33
5.1K
0.1U
RESET Circuitry
Title
IP101A Chip Circuit Diagram
Size Document Number Custom Date: 2004
RMII
Sheet
<RevCode>
Transformer
0.1U
Optional ,but recommended
50(1%) 50(1%) MDI_RP MDI_RN MDI_TN MDI_TP RDCT TDCT 16PT8515 RXTXCMT
CH_GND
supression
TXRX+ RXN/C RJ8-45 CH_GND 0.1U 0.1U
50(1%)
50(1%)
0.1U REGOUT
Only resister needed transformer have been shorted inside.
REGOUT 0.1U CH_GND
(CONNECT CHASSIS GND)
0.01U/3KV
0.01U
0.1U
0.01U
Title
IP101A Chip Circuit Diagram
Size Document Number Custom Date: 2004
RMII
Sheet
<RevCode>
33/39 Copyright 2004, Plus Corp.
July 2005 IP101A LF-DS-R06
IP101A
address Configuration
CLOCK generate IP101A
50MHz_CLKOUT VCC33 REFCLK_IP101A
This schematic sets address 00001b.
5.1K VDD33
REFCLK_OUT
P0PHYAD0/LED0
74LV244
There could more than output REFCLK(50MHz) when using buffer 74LV244.
P0PHYAD1/LED1 P0PHYAD2/LED2 P0PHYAD3/LED3 P0PHYAD4/LED4
5.1K
REGOUT REGIN connection
REGOUT REGOUT BEAD REGIN
5.1K
Analog Digital 3.3V connection
0.1U
0.01U
0.1U
5.1K
VDD33
BEAD
AVDD33 0.1U
Optional ,but recommended Hardwire Configuration network:
This configuration shows Enable: Auto negotiation, Full duplex, 100Mbps, Link Down Power Saving, interface Disable: Isolate, Repeater mode These senven configuration pins could connected directly.
5.1K
LED0 Link
LED1 Dupx
LED2 10Act
LED3 100Act
LED4
Title
IP101A Chip Circuit Diagram
Size Document Number Custom Date: 2004
RMII
Sheet
<RevCode>
34/39 Copyright 2004, Plus Corp.
July 2005 IP101A LF-DS-R06
IP101A
7.1.1
Electrical Characteristics
D.C. Characteristic
Absolute Maximum Rating Symbol Conditions Minimum -55°C Typical 3.3V Maximum 3.6V 125°C
Supply Voltage Storage Temp
7.1.2
Power Dissipation Symbol IP101A 41mA 17mA 11mA 11mA 138mA 137mA 148mA 147mA 145mA 147mA 95mA
Auto Power Saving Mode Analog Mode Power Down Mode Isolate Mode Full Half Full Half Transmit Receive IDLE 7.1.3 Operating Condition
Symbol
Conditions 3.3V Supply voltage Operating Temperature
Minimum
Typical 3.3V
Maximum 3.6V 70°C
7.1.4
Supply Voltage Specific Name Input High Vol. Input Vol. Output High Vol. Output Vol. Tri-state Leakage Input Current Average Operating Supply Current PECL Input High PECL Input Vol. PECL Output High Vol. PECL Output Vol.
35/39
Symbol
Condition
0.5*Vcc -0.5V 0.9*Vcc
Vcc+0.5V 0.3*Vcc 0.1*Vcc
Vout=Vcc Vin=Vcc Iout=0mA Vdd-1.16V Vdd-1.81V Vdd-1.02V Vdd-1.62V
July 2005 IP101A LF-DS-R06
200mA Vdd-0.88V Vdd-1.47V
PECL PECL PECL PECL
Copyright 2004, Plus Corp.
IP101A
7.2.1
A.C. Characteristic
Timing Reset Clock output timing relationship Symbol Tdelay Description Delay time after reset clock output
Tdelay RESET_N MII_TXCLK MII_RXCLK
Min.
Typ.
Max.
Unit
Transmit Timing Requirements Symbol TTxClk TTxClk TsTxClk ThTxClk Description Transmit clock period 100M Transmit clock period TXEN, MII_TXCLK setup time TXEN, MII_TXCLK hold time
Min.
Typ.
Max.
Unit
II_T [3:0]
Receive Timing Symbol TRxClk TRxClk TdRxClk Description Receive clock period 100M Receive clock period MII_RXCLK falling edge RXDV,
RxClk
Min.
Typ.
Max.
Unit
MII_RXCLK dRxClk RXDV, RXD[3:0]
36/39 Copyright 2004, Plus Corp.
July 2005 IP101A LF-DS-R06
IP101A
7.2.2 RMII Timing Reset Clock output timing relationship been configured 50MHz output Description Delay time after reset clock output
Tdelay RESET_N C50M_O
Symbol Tdelay
Min.
Typ.
Max.
Unit
Clock Timing RMII Symbol TR_CLKRMII TF_CLKRMII TP_CLKRMII TH_CLKRMII TL_CLKRMII Description REFCLK Rise time REFCLK Fall time REFCLK Period REFCLK High REFCLK
H_CLKRMII
Notes (max) (min) (min) (max)
Units
20.0 10.0 10.0 12.0 12.0
P_CLKRMII
L_CLKRMII
REFCLK
R_CLKRMII
F_CLKRMII
Figure Clock Timing RMII
RMII Receive Timing Symbol TDLY_RXD Description REFCLK rising edge RXD[1:0], RX_ER CRS_DV delay RXD[1:0], RX_ER, CRS_DV Rise time RXD[1:0], RX_ER, CRS_DV Fall time Notes Initial rising edge CRS_DV asynchronous REFCLK (max) (min) (min) (max) 12.0 15.0 Units
TR_RXD TF_RXD
37/39 Copyright 2004, Plus Corp.
July 2005 IP101A LF-DS-R06
IP101A
REFCLK RXD[1:0] RX_ER CRS_DV
DLY_RXD
Figure Receive Delay
RXD[1:0] RX_ER CRS_DV
R_RXD
IH_DIG(MAX)
IL_DIG(MAX)
F_RXD
Figure RMII Rise Fall Times
RMII Transmit Timing Symbol TSU_TXD_RMII THD_TXD_RMII Parameter TXD[1:0], TX_EN, Data Setup REFCLK rising edge TXD[1:0], TX_EN, Data Hold from REFCLK rising edge Units
REFCLK TX[1:0] TX_EN
SU_TXD_RMII
Valid Data
HD_TXD_RMII
Figure RMII Transmit Timing
Order Information
Part IP101A IP101A Package 48-PIN LQFP 48-PIN LQFP Notice Lead free
38/39 Copyright 2004, Plus Corp.
July 2005 IP101A LF-DS-R06
IP101A
Package Mechanical Specification
GAUGE PLANE DETAIL Symbol unit 1.600MAX. 0.050~0.150 1.400 0.05 0.200TYP 0.127TYP 7.000 0.100 7.000 0.100
SEATING PLANE
0.254
inch 0.0630MAX. 0.0020~0.0059 0.0551 0.0020 0.0078TYP 0.0050TYP 0.2756 0.0039 0.2756 0.0039
0.500TYP 9.000 0.250 9.000 0.250 0.600 0.150 1.000REF 0.100MAX. 0"~7"
0.0196TYP 0.3543 0.0098 0.3543 0.0098 0.0236 0.006 0.0393REF 0.0039MAX. 0"~7"
Notes: DIMENSION INCLUDE MOLD FLASH PROTRUSION. DIMENSION DOES INCLUDE DAMBAR PROTRUSION INTRUSION. MAX. FLASH 0.15MM. MAX. DAMBAR PROTRUSION 0.13MM. GENERAL APPEARANCE SPEC SHOULD BASED FINAL VISUAL INSPECTION SPEC.
Plus Corp. Headquarters
10F, No.47, Lane Kwang-Fu Road, Sec. Hsin-Chu City, Taiwan 300, R.O.C. 886-3-575-0275 886-3-575-0475 Website www.icplus.com.tw
Sales Office
106, Hsin-Tai-Wu Road, Sec.1, Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C. 886-2-2696-1669 886-2-2696-2220
39/39 Copyright 2004, Plus Corp.
July 2005 IP101A LF-DS-R06

Single port 10/100 Fast Ethernet Transceiver 10/100Mbps Full-dupl

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