INSIDER GUIDE Planning XC166 Family Designs Engineers Introductio
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Insider Guide
INSIDER GUIDE Planning XC166 Family Designs
Engineers Introduction XC166 Family
Microcontrollers
Insiders Guide Planning XC166 Family Designs
Copyright Hitex (UK) Ltd. 19/12/2005
Edition 2006-02-22 Published Infineon Technologies 81726 Germany Rights Reserved. Attention please! information herein given describe certain components shall considered guarantee characteristics. Terms delivery rights technical change reserved. hereby disclaim warranties, including limited warranties noninfringement, regarding circuits, descriptions charts stated herein. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
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Credits Authors: Editor: Michael Beach David Greenhill Alison Wenlock
Acknowledgements authors would like thank Karl Smith, Mike Copeland Manfred Choutka Infineon Technologies plus Joachim Klein Hitex Development Tools GmbH. their contributions this book.
Preface This guide contains basic information that useful when doing your first XC166 family design. There many simple facts which, they known outset, save time money. Overall, intended complement user manuals putting things into practical context. Some material found XC166 family databooks most simply result practical experience only found here. topics covered those that obvious often missed out. Where user manuals provide satisfactory explanation, will referred back them, rather than duplicating information here. This means complete reference work additional information found Infineon website. Note: While every effort been made ensure accuracy information contained within this guide, Hitex cannot held responsible consequences errors contained therein. subjective anecdotal information presented necessarily official view either Hitex Development Tools Ltd. Infineon Technologies
Prepared Michael Beach David Greenhill With additional material from: Karl Smith, Infineon Technologies Joachim Klein, Hitex Development Tools
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Contents
1.2.1 1.3.1 1.3.2 1.3.3 1.3.4 1.4.1 2.1.1 2.1.2 2.1.3 2.2.1 2.3.1 2.3.2 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 3.1.1 3.2.1 3.2.2 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 RISC Architectures Embedded Applications Introduction Behind C166S V2's Near-RISC Core Conventional CISC Bottle-necks.12 RISC Architecture Embedded Control.13 Interface.13 RISC Interrupt Response.14 Registers Multi-Tasking Coping With RISC Instruction (Apparent) Omissions RISC Real World Peripherals RISC Benefits Embedded Applications.19 Traditional RISC RISC Getting Started With XC166 Basic Considerations Family Overview Fundamental Design Factors.23 Setting Hardware Configuration Options.23 Calculating Pull-Down Resistor Values.25 Pull-Up Resistor Calculations Start-Up Configuration Internal Start Configuration External Start Configuration.28 Reset Control.30 Clock Speeds Sources Start External Start.32 Internal Start.33 Choice Clock Speed Choosing PLLCON Values Generating Clock.37 Designing Clock Circuits Oscillator Modules Designing Crystal Oscillator Circuits.38 Crystal Oscillator Components Test Procedure Laying Clock Circuits.41 Symptoms Poor Clock Real Time Clock Oscillator.42 Further Information Oscillator Design Modes Timings Flexible Interface Integral Chip Selects.43 Setting Mode On-Chip Boot External Boot Setting Overall Addressing Capabilities.45 External Memory Access Times Calculating Timing Parameters Multiplexed Bus.46 Calculating Timing Demultiplexed Tool Calculating Timing Parameters.49 Settings Commonly-Used Memory Devices
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4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7 5.2.1 5.3.1 5.3.2 5.4.1 5.4.2 5.4.3 5.5.1 5.6.1 5.10 5.11 5.12 5.13 6.1.1 6.1.2 6.1.3 6.2.1 6.2.2
Interfacing External Memory Devices Using 16-Bit Memory Devices.52 Using Byte-Wide Memory Devices 16-bit XC166 Systems Using XC166 With Byte-Wide Memories #BHE Using DRAM With XC166 Family Using FLASH Memory Cards With XC166 Cheap Gigabyte Storage Using CompactFLASH Cards XC166 Program Updates Interfacing SD/Multimedia Cards Interfacing CompactFLASH Managing Large FLASH Cards.60 File System Embedded Programs.61 Resources Implement File System XC166.61 In-Circuit Reprogrammable FLASH EPROM Introduction Internal FLASH Layout FLASH Identification FLASH Reliability.65 Dynamic Error Correction FLASH Endurance.66 Managing FLASH Under Extreme Conditions.66 When Manage FLASH.66 Dynamic Recovery From Double Errors Predicting Future FLASH Failures Tools Programming FLASH.69 Programming XC166 FLASH Production.69 Introduction Bootstrap Loader Programs XC166 Serial Bootstrap Loader Testing FLASH Programmers Under IEC61508 Other Standards.71 Bootstrap Mode Debugging Problems With JTAG.71 Bootstrap Mode Debugging Using In-Circuit Emulator Hardware Aspects In-Circuit FLASH Programming In-Circuit FLASH Programming Bootstrap Mode In-Circuit FLASH Programming SSC0 Bootstrap Mode.74 In-Situ FLASH Programming Without Bootstrap Mode Planning Memory Understanding DPPs Fast DPP-Based Data Access Accessing Large Data Objects.77 Data Addressing Impact C/C++ Compilers Planning Memory Configuring Compiler. Using DPPs Using PSRAM.78 External Factors Internal FLASH External Implications Mode/Trading Port Pins Power Consumption Reducing Power Consumption Optimising Clock Speed Comparing Current Consumptions Supply Voltage.84
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8.1.1 8.1.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.4.2 8.6.1 8.6.2 8.6.3 8.7.1 8.7.2
System Programming Serial Port Baud Rates Synchronous Serial Ports Module Adding Communications XC166 Family.87 XC166 Link Hardware Issues.87 XC166 Software.88 Software.88 Getting Started With Interrupt Performance.89 Interrupt Latencies Software Interrupts Hardware Traps Interrupt Structure.90 Interrupt System Usage Notes.90 Event-Driven Data Transfers System.92 Extending Address Ranges Sizes Above XC166 Family Stacks XC166 Co-Processor Adding DSPs Microcontrollers Compiler Handling Infineon Libraries Special Module Possibilities Time Triggered Using TwinCAN Module.97 Loop-Back Mode
Allocating Pins/Port Pins Your Application General Points About Parallel Ports.99 Allocating Port Pins Your Application Port 9.3.1 Port Allocations:.100 Port .100 Port .100 9.5.1 CAPCOM Units.100 9.5.2 Time-Processor Unit Versus CAPCOM .101 9.5.3 32-bit Period Measurements.101 9.5.4 Generating With XC166 CAPCOM Unit .101 9.5.5 Sinewave Synthesis Using CAPCOM.102 9.5.6 CAPCOM6E Motor Drive Peripheral.102 9.5.7 Automotive Applications CAPCOM1 .105 9.5.8 Digital Analog Conversion Using CAPCOM Unit .105 9.5.9 Multiple Independent Timebase Generation .106 9.5.10 Software UARTs .106 Port .107 9.6.1 Using GPT1 .107 9.6.2 Using GPT2 .108 9.6.3 Combining CAPCOM, GPT1 GPT2 Crank Synchronisation.108 Port .110 9.7.1 Interfacing Networks .110 Port .113 9.8.1 XC166 Analog Digital Converter.113 9.8.2 Basic Conversion Clock .114 9.8.3 Calibration .114
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9.8.4 9.8.5 9.8.6 9.9.1 9.9.2 9.9.3 9.10 9.10.1 9.10.2 9.10.3 9.10.4 9.11 9.12 9.13 9.14 9.15 9.15.1
Over-Voltage Protected Analog Inputs .114 Matching Inputs Signal Sources .115 Analog Reference Voltage.117 Board Design Issues.117 Component Placement .117 Power Supply.117 Ground Planes.117 Connecting Signal Sources.118 Ratiometric Mode.118 Fixed Precision Reference.119 Corrected Conversion Mode .120 Interfacing Analog Voltages Greater Than 5v.121 Port .122 Port .122 Port .122 Port .122 Summary Port Interrupt Capabilities .123 Interrupts From Port Pins.123
Typical XC166 Family Applications 10.1 Automotive Applications.125 10.2 Industrial Control Applications .126 10.3 Telecommunications Applications.126 10.3.1 Transport Applications .126 10.4 Consumer Applications .127 10.5 Instrumentation Applications.127 10.6 High Integrity, Aerospace, Medical .127 12.1 12.1.1 12.2 12.2.1 12.2.2 12.3 12.3.1 12.3.2 12.3.3 12.3.4 12.3.5 12.4 12.4.1 12.4.2 13.1 13.1.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 XC166 Compatibility With Other Architectures
Mounting XC166 Family Devices PCB's Package Types .131 Table Common XC166 Derivatives.131 Connecting Emulators XC166 Family Devices .131 Socketed Devices .131 Debugging Family Applications.132 Connecting In-Circuit Emulator.133 QuadConnect .133 Yamaichi Socket .134 Solder-In Stack .134 Emulating Soldered-Down CPU's .134 "PressOn" Emulation Adaptors .135 XC166 Family PCBs .136 Grounding Arrangements.136 Electromagnetic Compatibility (EMC) .136 Getting Boards Up-And-Running Useful Equipment .138 (Almost) Free TantinoXC JTAG Debugger .138 Before Applying Power.139 Testing Board .139 External Start Applications.139 Using Serial Bootstrap Mode MINIMON Test Boards .140 Using JTAG Testing Boards.142 Common External Problems.145
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13.4 13.5 20.1 20.2 20.3
Internal Start Designs .145 Testing System.145 Conclusion Acknowledgements Feedback Further Reading Contact Addresses Appendix Infineon XC166 Family Part Numbers
Appendix Pinout Common XC166 Derivatives XC167CI Pinout .152 XC161CJ Pinout .153 XC164Cx Pinout .154
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RISC Architectures Embedded Applications
Introduction
RISC microcontrollers becoming increasingly popular. C166S core used XC166 series makes extensive Reduced Instruction Computer (RISC) concepts achieve blend very high performance modest cost. understand RISC techniques especially suited high-speed real time embedded systems, useful examine detail they grew traditional Complex Instruction Computers (CISC) that reached their peak late 1980's 1990's. However despite many inherent advantages RISC microcontroller applications, RISC microcontrollers fully exploit them legacy reasons. This section examines some critical issues.
Behind C166S V2's Near-RISC Core
quest ever-greater throughput been reason behind abandonment traditional Complex Instruction Computers (CISC). demands workstations involved tasks latterly, advanced video games, have been real driving force behind this. Traditionally, microprocessors have been designed with assembler instruction sets that have been geared towards making assembler programmer's life easier through extensive microcode produce ever more powerful instructions. providing single assembler instructions that perform, instance, three-operand multiplication, assembler programmer (and compiler writer) been relieved achieving same result with simpler instructions. needs able recognize (decode) many hundreds different instructions, requires complex silicon many clock cycles. greater silicon area, greater cost device power consumed. With physical limitations acting restrict achievable clock speeds silicon devices, number cycles instruction obviously very significant gaining higher performance. RISCs tend shift burden programming from microcoder assembler programmers compiler writers. Work within academia commercial manufacturers proved that suitably-programmed RISC machine achieve higher throughput than CISC given clock speed. Strangely, mid-range embedded world been slow question suitability CISC-based microcontroller. very end, RSIC devices such ARM9, MIPS Hyperstone provide stiff competition conventional CISC PowerPC Pentium more commonplace embedded tasks, RISC still relatively uncommon. With increasing complexity modern control algorithms, need greater processing power become issue anything simplest applications. addition, here more than workstation world, worst-case response time non-deterministic events crucial, area where CISCs especially poor where most ARM-based RISCs means outstanding. Many current mid-range 16-bit microcontrollers based existing CISC architectures such S12, M16C etc., which common with 8-bit devices such 8051, have internal structure that dates back years more. With silicon vendor's need give existing users upgrade path, apparently designs often based closely existing architecture/instruction set, protecting user's investment expensive assembler code. Like workstations, microcontrollers programmed high level language (HLL) reduce coding times enhance maintainability. Inevitably, even with best compilers, some loss performance encountered, emphasizing again need improved performance. addition straightforward data processing, microcontrollers must also handle real-world peripherals such converters, PWMs, timers, Ports, PLLs etc., which require real time processing fast interrupt response.
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1.2.1 Conventional CISC Bottle-necks
Long Unpredictable Interrupt Latencies Complicated "labour-saving" instructions must hold CPU's entire attention during execution, thus preventing real-world generated interrupts from being serviced. Unpredictable latency times result, which cause serious problems hard real-time systems. approach overcoming CISC's poor real-time response been bolt secondary "time processor unit" other such auxiliary processor onto core off-load time-critical portions. However, this results awkward design need very terse microcode program addition more usual assembler CISC core itself. Vast Instruction Sets Give Slow Decoding Loaded instructions must recognised from potentially many hundreds even thousands possibilities. Decoding thus complicated lengthy. Frequent Accesses Slow Memory Devices Data typically fetched from off-chip memory placed accumulator-type registers. Mathematical logical operations performed then result written back memory. value likely required again course procedure, thus requiring further movements from off-chip memory. Slow Procedure Calling When calling subroutines with parameters (essential good programming), parameters must individually pushed stack. They must then moved through accumulator register(s) processing before being returned stack caller. Strictly time Each peripheral device interrupt source must have dedicated service routine which very least will require stacked restored data removed from peripheral device. Software Structured Suit Architecture. Embedded systems frequently contain many separate real time tasks which together form complete system. Conventional CPUs make switching between tasks slow. Often, many registers have stacked free them incoming task. This problem aggravated compilers which tend large number local variables library functions which must preserved. Redundant Instructions Addressing Modes With almost universal high level languages, compilers tending dictate which instructions should provided silicon. practice, compilers tend only make small number addressing modes. This results large number unused addressing modes that serve only complicate opcode decoding process. Inconsistent Instruction Sets Instruction sets that have evolved tend difficult large number different basic types inconsistent addressing modes allowed. Fully Utilised Whilst complex instructions being executed, idle.
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RISC Architecture Embedded Control
show RISC design used improve microcontroller throughput, C166S used example. Basic Definitions: state time 1/oscillator frequency fundamental unit time recognised within processor system. machine cycle state time minimum time required perform simplest meaningful task within CPU. unit state times used when making comparisons between RISCs CISCs this removes dependency clock frequency. state time counts given single chip operation mode both S12X C166S
1.3.1 Interface
maximise rate which instructions executed, RISC CPUs very heavily pipelined. Here, given machine cycle, instructions processed overlapping various steps. Simplified clarity, stages are: FETCH: DECODE: EXECUTE: WRITE-BACK: opcode from program store identify opcode from small list fetch operands perform operation denoted opcode result returned specified location
Thus although instruction takes four machine cycles, apparently executed just state time). Pipelining considerable benefits speeding sequential code execution guaranteed fully occupied. Some more advanced RISC devices (like C166S extra ADDRESS stage make total pipeline stages also 2-part "PREFETCH" unit: Instruction Fetch Unit (IFU) PREFETCH: instructions from program memory order predicted. branches detected prediction logic decides branches will taken not. FETCH: address next instruction fetched calculated using branch prediction rules.
Pipeline Unit DECODE: ADDRESS: MEMORY: EXECUTE: WRITE BACK:
instructions decoded and, required, register file accessed read used indirect addressing modes. operand addresses calculated. required operands fetched from registers. perform operation denoted opcode result returned specified location
This theoretically gives doubling performance straight-line code. However even though there branch prediction unit minimise loss performance caused branches real programs, quite twice throughput achieved.
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1.3.2 RISC Interrupt Response
C166S core, branches interrupts make injected instruction technique vectoring service routine achieved only machine cycles. effect complex necessary instructions such cycles respectively) stretch this interesting note that C166S does provide partially-interruptible instruction. first cycles lock interrupts remaining cycles interrupted. Very fast interrupt service crucial high-end applications such engine management systems, servo drives radar systems where real-world timings used DSP-style calculations. these normally form part larger closed control loop, erratic latency times manifest themselves undesirable jitter controller output.
1.3.3 Registers Multi-Tasking
Traditional microcontrollers have more special registers that used mathematical, logical Boolean operations. 8051, there single "accumulator" with other registers which used handling local variables intermediate results complex calculations. These additional registers also used access memory locations indirect and/or indexed addressing. pointed items above, conventional CPUs spend much time moving data from slow memory areas into active registers. RISC offers very large number general purpose registers which used locals, parameters intermediates. C166S provides word-wide general purpose registers (GPRs), each which effectively accumulator, indirect pointer index. With such large number GPRs available, becomes realistic keep locals intermediates within throughout quite large procedures. This yield great increase speed. Further significant benefits derived from RISC technique register windowing. been said, registers available program. However, making active register bank movable within larger on-chip RAM, real-time multi-tasking considerably eased. Central this concept "Context Pointer" (CP), which defines current absolute base address active registerbank program memory space. Thus reference "R0" means register address indicated (typically address 0xFD00). Thereafter, registers originating from accessed fast 4-bit offset. best example exploited perhaps background task real-time interrupt co-existing. When interrupt occurs, rather than pushing GPRs onto stack, current register bank stacked simply switched value, determined link time, yield fresh register bank. This results complete context switch just instruction does rule recursion. hybrid method, which permits re-entrancy, uses stack pointer calculate dynamically. Here, entering interrupt, number registers required subtracted from current result placed with stacked. Thus register bank located stack, with then stack following immediately afterwards. exiting interrupt routine, original registerbank restored POPping from stack. reinstated adding size register bank onto current
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further RISC refinement register window overlapping whereby when procedure called, part register bank defined coincident with original Register subroutine's locals intermediates Register subroutine's locals intermediates Common register, Common register, Register caller's locals intermediates Register caller's locals intermediates Register caller's locals intermediates Register caller's locals intermediates Register caller's locals intermediates Register caller's locals intermediates
MODULE Assignment GPRs Local Variables Caller x_var y_var parm1 parm2 `R0' `R1' `R6' `R7' Local variable Local variable Passed parameter Passed parameter
result `R6' Value returned from routine MODULE Assignment GPRs Local Variables Routine a_var b_var input1 input2 ret1 `R2' `R3' `R0' `R1' `R0' Local variable Local variable Received parameter Received parameter Final result returned
Fig. Giving GPRs Meaningful Names
programmer should plan value passed subroutine located common area, that normal loading unloading parameters avoided. This technique used either absolute SP-relative registerbank modes.
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ability switch working registers changing context pointer register useful when responding interrupts, avoids need save current registerbank contents before executing service routine instructions. This time-consuming registers saved. Typically this requires instruction (here switch context "SCXT start interrupt routine change registerbank base second instruction restore original one.
R15'
0xFD20
0xFD20
0xFD20
0xFD00
0xFD00
0xFD00
0xFD00 Background
0xFD20 Interrupt Service
0xFD00 Background
Another method possible some RISC devices relies "alternative" register sets that become visible when predefined interrupt source activated, that saving current register contents required. ARM7-TDMI RISC devices typically replace upper registers registerbank when (Fast Interrupt reQuest) fires, whereas C166S complete "local" banks sixteen registers that made appear when either interrupt sources triggered. Unlike conventional registerbanks, these registers usually exist normal memory space context switching required, thus saving time1. best from RISC's registers, location data needs close consideration: although highly orthogonal, limited number addressing modes provided example, appear somewhat restrictive. Fortunately though, most operands involved will already registers, eliminating need many addressing techniques. might expected, instructions with widest range addressing modes simple data moves fact that RISCs result very careful analysis requirements fast execution becomes obvious after short acquaintance!
fact current local registerbank given physical address made visible setting appropriate bits BANK field register.
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1.3.4 Coping With RISC Instruction (Apparent) Omissions
With largely single machine cycle execution, some conventional "fast" instructions such CLEAR, become redundant. Therefore, keep total number instructions minimum, RISCs simply omit them. Examples given below: Instruction 80C196 States C166S States -Clear Word Rn,#0 Decrement Word Rn,#01 Increment Word Rn,#01
direct addressing mode
Three-operand instructions also commonplace CISCs present RISCs. Although additional instructions required, overall number states still less than three-operand CISC equivalent, plus shorter RISC instructions allow greater opportunity interrupt servicing. following example illustrates this: Perform:
80C196 (CISC)
directly addressed memory locations
z,x,y states interrupt possible
C166S (RISC)
memory locations,
Rw,x Rw,y z,Rw states Interruptable here states Interruptable here states states
extra state required when using RISC approach.
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However, variables assigned recognising that this RISC: memory locations,
`R0' assigned LITeral definition states Interruptable here states states
state saved over CISC. above chosen worst case RISC, best case CISC example. normal operand ADD, RISC uses states compared CISC's improvement. Assigning variables GPRs would probably make sense context real program. This trivial example shows familiarity with RISC's programming techniques improves performance.
RISC Real World Peripherals
Within workstation desktop computer RISC, superscalar operation allows parallel execution instructions, made possible having discrete addition, multiplication, shift other dedicated units, each with their pipelines. RISC microcontroller (yet) quite offers this (although 32-bit Tricore heading this way) something similar possible service on-chip peripherals such converter. common situation occurs conventional microcontrollers whereby some regular event requires attention from load unload data. Typically, converter will cyclically read number channels, causing interrupt when completed simply waiting poll status. result valuable time spent doing what even microcontroller simple, repetitive task. RISC C166S allows interrupt service routine serviced completed single machine cycle (via "Peripheral Event Controller", described section 8.4). case periodic conversion, each conversion result from "ADDAT" register stored table from where readings later retrieved CPU. This mechanism requires perform only single-cycle instruction equivalent "MOV [table_addr+],ADDAT" after each conversion. table, traditional interrupt routine required reset table pointer permit another series conversions automatic result transfers. real-world generated data handled this way, leaving free data processing rather than simple data collection. many applications, close coupling between pins useful detection generation real time pulses. Traditional RISC CPUs often have lengthy unpredictable delays between example, software setting port actual changing state. input, reverse situation applies. Such delays caused RISC core being adapted hard real-time communicating with peripherals through VLSI (very large scale integration) bus. C166S being designed real-time controller does suffer from this kind problem there direct connection between core peripheral set.
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1.4.1 RISC Benefits Embedded Applications
Near-DSP throughput example, XC166 achieve million instructions second (20MIPS) 20MHz clock (50ns machine cycle time). 40MHz this rises 40MIPS with 25ns cycle time. This result pipelining ability contain active data entire procedures within registers. Simpler Assembler Coding Although instruction less diverse, consistency addressing modes makes assembler coding easier. Very Fast Response Non-Deterministic Events eliminating instructions that take many cycles, interrupt response improved. Smaller instructions effectively yield higher "sampling rate" real world events. Single Machine Cycle Context Switching careful multiple register banks controlled base pointer, context switching multitasking system performed just instruction. addition, parameter passing overhead subroutines eliminated overlapping register windows, that parameters common area. Alternate Local Registerbanks planning interrupts carefully, zero-time context switching possible.
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Traditional RISC RISC
Although RISC inherently conducive fast interrupt response/low latency, legacy having RISC designs with their roots 1980s desktop computers means that although handling single interrupts fast reasonably deterministic, with interrupt-intensive applications, some problems experienced. Interrupt systems have changed since days single input with multiple sources requesting interrupt service through Here single interrupt vector required user check source interrupt before servicing This ruled nesting interrupts with result that systems with significant interrupt activity, effective latency times could become very long completely unpredictable, despite very high straight line speed core.
Interrupt sources UART Pipeline Timers
Non-Vectored Interrupt Service Routine void NonVectoredIRQ (void) _attribute_ ((interrupt("IRQ"))) Test interrupt source If(VICIRQStatus 0x00008000) pins IOSET1 0x00FF0000;
Clear peripheral interrupt flag EXTINT Dummy write signal interrupt VICVectAddr 0x00000000; 0x00000002;
Interrupt Request Handling 1980's Style RISC
However, many traditional RISC CPUs still have interrupt management this type some variation which unfortunately negates inherent advantages fast interrupt response conferred RISC approach. effect that although best-case interrupt latency good, worst case figure almost impossible predict. Thus cannot taken granted that RISC microcontroller CPUs will suitable hard real-time systems.
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Later RISC devices like C166S more date approach interrupt handling, designed make best RISC inherently short interrupt latencies. Here interrupt sources freely assigned different levels, which prioritised allow full interrupt nesting. This allows short interrupt latency times permitted RISC fully exploited both best worst case latencies estimated with high degree certainty.
Interrupt sources IRQ0 UART Timers CAPCOM IRQ4 IRQx IRQ1 Pipeline IRQ2 IRQ3
void timer3_int(void) interrupt void serial_rx_interrupt(void) interrupt void RS485_timeout(void) interrupt void serial_tx_interrupt(void) interrupt void communication_timeout(void) interrupt void timer1_int(void) interrupt void trip_period_interrupt(void) interrupt
Interrupt Request Handling XC16x RISC
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Getting Started With XC166
Basic Considerations
2.1.1 Family Overview
XC166 family currently includes three main variants, XC161, XC164 XC167, although with different memory peripheral options this adds considerably more reality. According XC166 User Manual, family generation Infineon's 16-bit Microcontroller. first family member 80C166, available masked ROM, FLASH EPROM (88C166) ROMless versions. second member C167 which expanded addressing capability, integral chip selects plus many more peripherals introduced some assembler instructions. third generation added flexible power management. Although binary compatible with C167 (`Classic 167'), many enhancements have been made increase performance. XC166 family uses C166S core which includes number important enhancements. MAC-unit adds DSP-functionality handle digital filter algorithms greatly reduces execution time multiplications. 5-stage pipeline, single-cycle execution most instructions, PECtransfers within complete addressing range increase system performance. Debugging target system supported integrated functions On-Chip Debug Support (OCDS). other major enhancement addition full automotive spec on-chip FLASH.
2.1.2 Fundamental Design Factors
When starting XC166 family design, there number basic things must decide. Wrong decisions here have expensive consequences later project. There good many features architecture that puzzling those used conventional devices. What follows simple guide what really need know best from this ingenious powerful microcontroller family! What clock speed required achieve necessary processing power? What sort clock source suitable? What sort reset circuit should used? What sockets available configured? Will boot into internal external ROM? on-chip FLASH EPROM programmed? external FLASH EPROM programmed? external memory added? full 16-bit external necessary will 8-bit sufficient? external required all? Will there some external peripheral chips that will require different modes? much required implement application? Should WRH/WRL used? Should chip selects used? Which peripheral pins best allocated various different signal processing generation functions application? many others.
2.1.3 Setting Hardware Configuration Options
common with many modern microcontrollers, between /RESIN going high rising edge first pulse, reads start configuration. This read from places depending whether processor booting from internal external memory. This determined from level start High, then processor will boot from internal memory. this case startup configuration read from pins. With only three pins available, only minimum configuration achieved, configuration completed software during start
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following settings available internal start: Boot from standard alternate reset vector Enable standard alternate bootstrap mode P20.12 either /RSTOUT GPIO
Low, then processor will boot with external enabled. configuration read from pattern Port determine following fundamental settings: What default mode many pins port should used chip selects many segment address lines should used Whether on-circuit emulation mode entered Whether WRITEHIGH/WRITELOW mode required Whether BOOTSTRAP mode activated What clock factor used
pattern placed onto port user attaching pull-down resistors appropriate pins. example, processor booting from internal memory bootstrap mode, will High will need pulled through resistor. non-multiplexed mode from external start, will pull-down resistor added Port 0.7, while Port floats high. values pull-down resistors should calculated with reference overall loading Port from external memory devices etc., using formulae given section 2.2. value required typical EPROM system 8K0, this representing stated maximum value. covers designs seen date. extreme cases, little used this exceptional leakage currents from modern memory devices extremely small. Overall, user simply advised check situation design just blindly accept usual value! Note: databooks frequently refer port either 16-bit port 8-bit ports, made Port (LOW) Port (HIGH). Thus Port 0.15 bit-16 port which also Port 0H.7. same convention, Port also known Port 0L.7.
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Calculating Pull-Down Resistor Values
Finding value pull-down resistors your design fairly straightforward. will need know leakage current from devices such RAMs, ROMs that attached bus.
input leakage current input current
RESET
IP0L 100uA
Port
SYSL
VILMAX
XC16x
Pull-Down Resistor Current Flow
System.
VILMAX Highest voltage that will accepted ISYSL Leakage current from RAMs, ROMs etc. IP0L Current flow from XC166's Port when VILMAX Pull down resistor Port From XC166 Datasheet: VILMAX (0.2 Vcc) 0.1V 0.8V VILMAX 1.0V +/-10% 4.5V 5.5V Pull Down Resistor Calculation VILMAX VILMAX IP0L ISYSL
Example Without System Leakage Current, ISYSL: VILMAX 0.8V IP0L 100uA
Thus maximum recommended value 8K0. practice, almost always used, former value taking account typical leakage currents from memory devices bus.
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2.2.1 Pull-Up Resistor Calculations
some designs, loading such that there flow current into external devices ground, i.e. sinks current. extreme cases, this cause Port pattern read XC166 incorrect. must stressed that this very rare easily compensated using high-value pullup resistor. Such measures only required current sunk into external device ISYSH, greater equal 10uA. Before finalising design condition should checked pull-up resistor added necessary. procedure calculating pull-up resistor follows:
input leakage current input current
RESET
SYSH
IP0H 10uA
Port
VIHMIN
XC16x
Pull-Up Resistors Port
System.
VIHMIN Lowest voltage that will accepted ISYSH Current sunk into devices etc. IP0H Current that drawn from XC166's Port VIHMIN Pull resistor From XC166 Datasheet: VIHMIN 0.9v 0,1V 1.8V VIHMIN 2.0V +/-10% 4.5V 5.5V Pull Resistor Calculation VCCMIN VIHMIN ISYSH IP0H
Example: ISYSL 50uA 4.5v 1.8v 50uA 10uA 67.6K
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Start-Up Configuration
2.3.1 Internal Start Configuration
High, processor boots from internal memory. This diagram shows possible configuration functions: Description Standard start, ASC0 bootloader enabled (Addr. C0'0000H), P20.12 GPIO Standard start, ASC0 bootloader enabled (Addr. C0'0000H), P20.12 RSTOUT Alternate start (CAN) bootloader enabled (Addr. C1'0000H), P20.12 GPIO Alternate start (CAN) bootloader enabled (Addr. C1'0000H), P20.12 RSTOUT Standard internal Start (Addr. C0'0000H), P20.12 GPIO Standard internal Start (Addr. C0'0000H), P20.12 RSTOUT Alternate internal Start (Addr. C1'0000H), P20.12 GPIO Alternate internal Start (Addr. C1'0000H), P20.12 RSTOUT
other startup configuration initially defaults `safe' worst case mode. clock generation bypass mode with factor ensuring proper operation defined input frequency range 50MHz. RSTCFG register default vale 0x0DFF. Changes this configuration made software. Another consideration that should made with regard itself. Although this needs High internal start, recommendation that this should pulled high through resistor rather than being connected directly rail. This discussed more detail chapter should become necessary connect full in-circuit emulator board, emulator will need able pull low. majority XC166 designs, internal start mode should used. external required then this enabled through software running from internal FLASH.
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2.3.2 External Start Configuration
This diagram gives individual configuration functions Port pins when between reset rising edge first ALE:
P0.15 P0H.7
P0.7 P0L.7
P0.0 P0L.0
CLKCFG
SASEL
CSSEL
BUSTYP
SMOD
Clock Generator
Port Logic
Port Logic
Bootstrap mode select
EBCMOD0
Port Functions RSTCFG Register Layout
FCONCS0
XC16x Special Function Registers
When pulled Low, /RSTOUT deactivated automatically reset, otherwise deactivated user software On-circuit emulation mode puts XC's pins into high-impedance tristate condition that emulator's clip-over adaptor attached soldered-in device. Note that clock source crystal, XTAL2 must disconnected from processor that emulator's pick clock. PULL DOWN RESISTOR THIS PIN! Special Modes bootstrap loader P0L.5 P0L.4 P0L.3 P0L.2 Boot Mode Alternate start 0xC10000 Alternate TwinCAN bootstrap mode 0xC10000 Standard ASC0 bootstrap mode 0xC00000 Standard start (default) 0xC00000 Alternate SSC0 bootstrap mode 0xC00000 other combinations reserved future use.
SMOD
BUSTYP
external type shown below. These pins form BUSTYP field FCONCS0 special function register, where modified software. P0L.7 P0L.6 External Mode 8-bit non-multiplexed 8-bit multiplexed 16-bit non-multiplexed 16-bit multiplexed (default)
Cause become /WRH (write high) /BHE become /WRL (write low) make 8-bit RAMs 16-bit system easier. section 4.2.
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CSSEL
number chip selects that enabled Port Port XC164) P0H.2 P0H.1 Chip Select Lines Three: /CS2, /CS1, /CS0 Two: /CS1, /CS0 None: Four: /CS3, /CS2, /CS1, /CS0 (default)
SALSEL
Number "segment address" lines, i.e. many additional address lines above will enabled. P0H.4 P0H.3 Segment Address Lines Port Four: None: Eight: Two: A16, (default)
CLKCFG
Programming processor clock input, with optional phase lock loop (PLL) clock multiplier. P0H.7 P0H.6 P0H.5 Clock Generator fosc fosc 2.5, fosc 2.5, fosc, fosc fosc fosc 4.5, fosc Frequency Multiplier Control fosc 50MHz fosc 16MHz fosc 12MHz fosc 40MHz fosc 6MHz fosc 12.5 18.7MHz fosc 8.3MHz fosc 12.5MHz (default)
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Reset Control
family reset pins, /RSTIN /RSTOUT. former conventional active-low reset input while /RSTOUT output, operation which configurable. single chip applications /RSTOUT will probably needed consequently configured general purpose pin. being used, will same time /RSTIN stays either software when executes EINIT (end-ofinitialisation) instruction, until deactivated automatically internal reset. /RESOUT thus means keeping peripheral devices reset state until fully initialised. /RESIN input must kept until power supply reached 2.25v Vddi rail 4.5v Vddp. Once stable, level /RSTIN more than state times (50ns 40MHz) will reset CPU. times less than this must avoided. internal pull-up resistance, simplest reset circuit pull resistor capacitor ground. value must chosen give time constant long enough power supply stabilize. However, such simple arrangement suitable those situations where power supply could suffer from instability brown-outs. most commercial products, proper microprocessor power supply RESET manager such TLE7469 highly recommended. This device provides both 2.5v supplies CPU's RESET.
250K
/RESIN RESET 22uF
XC16x
Very Simple Reset Scheme
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Clock Speeds Sources
basic unit time C166S core single state time, corresponding 25ns 40MHz. Most instructions execute state time, i.e. 25ns. Oscillator modules must have rise fall time better than 8ns. XC166 equipped with system generate clock from external crystal. Exactly this handled determined boot mode. series multipliers dividers which configured user directly control registers indirectly three Port0H configuration bits.
Lock
Bypass PLLIDIV
Internal Clock Distribution Scheme
Testmode
PLLMULL
PLLODIV
output frequency fPLL calculated fPLL fosc N/(P This signal then used drive whole XC166 device. only notable exception real time clock, which driven either from main system clock auxiliary oscillator. Master clock period known "TCM".
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Master Clock
TwinCAN
Bus)
Core
Peripherals
Bus)
Output Distribution XC16x Modules
clock distributed from shown. clock peripherals further divided factor using CPSYS SYSCON1 register, although this rarely necessary.
Relationship between internal clocks
fCPU fPLL fSYS fPLL fPLL
2.5.1 Start
will provide stable clock even there external crystal oscillator fitted that run, albeit frequency. fact this clock used until synchronized external oscillator. base frequency selected software band select (PLLVB field PLLCON) which defaults 20MHz. factor (PLL output divider) divide under these conditions that will running 3.75MHz. starts once 2.5v rail reaches around 1.5v. running 3.75MHz this point begins monitoring incoming oscillator signal stability over 2000 cycles before attempting synchronize. processor bootstrap mode, there internal timeout 30ms after which further attempt synchronize made remains base frequency. Under these conditions, Baud rates above 9600 unlikely work. bypass mode give very clock speeds reduce power consumption. Here just dividers used give maximum division
2.5.2 External Start
There very cases where XC166 would started external mode. almost cases, internal start should used! external start, state Port0H pins read coming RESET, explained previous section. value three bits used form value that written into RSTCFG register. This value used automatically configure clock multiplier. pins pulled-down then multiplier divide with classic C167 devices. However when planning pull-down resistor configuration, user must make sure that input crystal frequency within acceptable range required frequency. example, multiplier, input frequency must range 4-6MHz (see CLKCFG table section 2.3.2). reason these limited ranges seen when internal structure examined detail below.
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user also select suitable values directly required multiplier changing value PLLCON register. This procedure covered detail next section.
2.5.3 Internal Start
this mode, Port0H pins examined pattern user clock multiplier manually. default clock multiplier will divided which typically means that 8MHz crystal, will only running 4MHz. This have some side effects, such preventing on-chip bootstrap loader from being able auto-baudrate-detect greater than 19200 Baud. This problem FLASH programmer (such MEMTOOL FLASHXC.DLL) using ASC0 bootstrap mode wants 115200 Baud minimize download time. change PLLCON aimed changing clock multiplier will require re-lock. This typically takes around 30us maximum 200us possible worst-case.
Note that values into this register must have subtracted from them i.e.: PLLMUL PLLODIV PLLIDIV Note: input divider must least (divide input clock does have guaranteed 50/50 duty ratio.
2.5.4 Choice Clock Speed
XC166 really intended single-chip microcontroller with code storage internal FLASH, there real reason anything other than full 40MHz permitted current silicon. Access external require waitstates (see chapter assuming that time-critical code execution will from internal FLASH then makes sense fast possible. Generally XC166 family needs wait state operation waitstates operation. However there exception XC166-32F devices which come into versions "Grade "Standard". Grade devices support waitstate operation waitstates MHz. Standard devices need additional wait state (i.e. waitstates) waitstate MHz. addition waitstate internal FLASH causes average 5-15% performance reduction typical applications. 5-stage pipeline combined with 64-bit FETCH from on-chip FLASH mean that waitstates added without prejudicing throughput linear code, loss being number wrongly-predicted branches that will occur real programs. system contains external FLASH then number waitstates independently using external chip select control registers.
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2.5.4.1 Choosing Values
combination oscillator frequency required frequency (Master Clock when CPSYS there usually several combinations that will give required result. question therefore choose best combination values. Master Clock usually driven from PLL, there inevitably some jitter output continuously adjusted keep frequency required value. design such that abrupt changes frequency prevented there small cycle-to-cycle variation period (the jitter) that needs considered hardware design.
2.5.4.2 Implications Jitter
Jitter master clock affect timings Memory accesses period Peripheral timebase accuracy
However almost situations level jitter from XC166 system extremely small still ought taken into account. quality clock source also should considered, common poorlydesigned crystal circuits (see later) cause significant variation period-to-period timing. extreme cases, poor clock combined with non-optimal choice PLLCON parameters cause transmission errors peripheral. addition, memory access calculations upset jitter reduce cycle time thus increase apparent clock frequency that data misread. Timing errors less problem with peripherals such CAPCOM ASC0 they tend deal with time periods microsecond millisecond range. oscillator design good values properly chosen, then jitter effects module regarded insignificant, although they still need examined light external devices that present design. example calculated memory access times must allow jitter, consider jitter across cycle: cycle requires CPUSYS divider From XC166 datasheet: Jitter (N)(ns) +/-(1.5 6.32 (N)/fMC) Where Number TCM's period over which jitter estimated. Note that this formula assumes that highest possible factor used (output divider). TCM's 40MHz, Jitter +/-(1.5 6.32 4/40) Jitter 2.132ns other value would increase jitter indeterminate amount. Therefore important choose highest possible Thus when calculating timings, this 2.132ns must added worst-case PhaseE. addition, oscillator tolerance must allowed similar way. This tolerance will frequency, temperature ageing tolerances typically more than around 0.02% period.
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2.5.5 Choosing PLLCON Values
Knowing that jitter significant, does reduction influence choice PLLCON parameters? Example: above, XTAL frequency 8MHz, Master Clock frequency 40MHz. This gives least three possible combinations shown. PLLCON 0x7884 (default value from DaVE) (ii) PLLCON 0x7D12 (iii) PLLCON 0x7D85
Which these three combinations depends several factors: PLLCON 0x7D12 input divider that clock source with non-50/50 duty ratio such oscillator module used clock source. 0x7884 uses lower multiplier higher divider than 0x7D12. This reduces jitter fPLL output compared with (i). 0x7D85 gives lowest clock jitter
Therefore (iii) preferred where external crystal being used.
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Approximate Accumulated Jitter Bold lines indicate minimum possible jitter. These only achieved setting maximum possible combination required crystal frequency.
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Generating Clock
2.6.1 Designing Clock Circuits
There basic choices clock source, crystal self-contained oscillator module. design traditional clock circuit trivial task requires some care reliable start-up when production tolerances component ageing taken into account. XC166 family more demanding this area than other microcontroller hints given following section should considered clock circuit design.
XC16x
XC16x
A0-A18.A23
XTAL2 XTAL1
XTAL2 XTAL1
A0-A18.A23
4MHz
4MHz
From Current Probe
Fundamental Mode Operation
Test Configuration
2.6.2 Oscillator Modules
Using oscillator module very simple, operating point calculations will have been taken care manufacturer. emissions also less metal case always grounded there will shorter signal path. only critical factor that rise fall time should less than 5ns. There small price premium over conventional crystal-plus-capacitors approach this great. Indeed, only microcontroller going used 25k+ annum quantity that extra cost module going become significant. oscillator output should connected XC166's XTAL1 pin.
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2.6.3 Designing Crystal Oscillator Circuits
traditional clock circuit usually comprises parallel resonant fundamental crystal plus capacitors resistor limit current through resonant device. XC166 uses crystals range 16MHz. selection series resistor value must made that oscillator guaranteed start within 0.1ms 5ms, even after mass production tolerances ageing effects taken into account. must also chosen keep power drive level crystal between typically 50uW 800uW, although device's datasheet should consulted. process defining "load capacitors", CX2, aimed making sure that there sufficient current flowing through crystal drive on-chip inverter that produces oscillation. crystal characteristic resistance known "equivalent series resistance" "load resonant resistance", which combination typical resistance (R1typ) residual capacitance (C0typ), stated manufacturer, plus reactive effects oscillation load capacitors CX2. This equivalent resistance given R1typ (C0typ/CL)2) Where: (CX1 CX2)/(CX1 CX2) stray capacitance clock circuit)
During this definition phase, small value resistor, should inserted series with crystal. temporary resistor, must increased until oscillator does start automatically when powered different values load capacitor. This value will Rqmax. ease adjustment, potentiometer used must bear mind that this engineering value arrived must verified replacing potentiometer with equivalent resistor repeating test. ratio Rqmax equivalent series resistance "Safety Factor" measure much spare capacity there circuit overcome tolerance ageing effects: Safety Factor (SF) Rqmax/RL current probe should used measure peak-to-peak current (Ipp), converted drive power with: (Ipp RL)/8 resulting relationships between safety factor power drive versus load capacitor value should plotted graph paper. From both curves, value load capacitors that gives best combination safety factor power consumption chosen.
2.6.4 Crystal Oscillator Components Test Procedure
Select value load capacitors, value given table Adjust until oscillation will self-start less than when XC166 powered-on. Record this resistance table, similar that given below: Test Record 680R 0.0pF 2.2pF 4.7pF 10pF 22pF 47pF 0.002075 0.0023 0.00255 0.0031 0.00455 0.008 25.27 26.09 27.48 32.17 51.59 122.5 Rqmax
Select next value load capacitors repeat steps pick another value repeat procedure.
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After number values have been tested this way, resulting curves should examined resistor load capacitor values that give best safety factor power level 50uW-800uW. Having selected values, resistor should removed current start-up times rechecked. adequate safety factor cannot achieved, particularly above 20MHz, possible series 1-10M resistor increase feedback XTAL1 input pin. Otherwise, third-overtone mode must used. Unfortunately, component selection process more complex when considered that extra inductor capacitor will required damp-out fundamental frequency, might prove more cost-effective oscillator module! simplify selection process, Infineon provide Excel spreadsheet template www.infineon.com/xc166-family that automates conversion test results characteristic curve plotting,
Excel Spreadsheet Oscillator Component Evaluation
illustrated below:
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clock circuit will fact produce drive currents: until RESOUT goes high, (after EINIT instruction executed), current drive clock will greater ensure that less likely upset during potentially noisy initialisation phase. also helps overcome initial high resistance crystal during startup phase. Typical load capacitor values 22pF with around However, should rely these serious project, selection procedure given earlier should followed.
2.6.4.1 Typical Component Values
table gives typical values selection commercially available crystals. These must used they stand without testing deliberately have given brand names this reason! recommended that compare characteristics C0typ, R1typ shaded panels) fundamental frequency your device with examples table pick which closest. Make clock circuit using load capacitors plus series resistor perform check safety factor drive power given previous section. chances that results will within limits would very embarrassing reliability problems occur production have admit that never verified component values clock circuit.
R1max (TK) (Ohm)
2.11 3.07 3.24 3.57 4.08 4.24 1000 6.50
1200 8.14 1800 12.50 2200 10.66 2700 14.17 3300 14.08
Typical Crystal Characteristics Component Values
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Safety Factor (SF)
Frequency (MHz)
Rqmax (Ohm)
R1max (Ohm)
R1typ (Ohm)
(Ohm)
C0typ (pF)
(pF)
(pF)
(uW)
(pF)
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2.6.5 Laying Clock Circuits
layout clock circuit critical determining both emissions susceptibility XC166 design. with high frequency system, loop areas must kept small possible, meaning practice that components must located close practicable each other XTAL1/XTAL2 pins CPU. With metal-canned crystals, case should soldered grounded area surface plus should connected main ground layer multi-layer board. This will also improve mechanical stability part.
XC16x
Decoupling capacitor reverse board XTAL1 XTAL2
Connections ground layer
Crystal
Sample Oscillator Circuit Layout
Inductive capacitive coupling reduced eliminating parallel runs tracks either same layer between layers. grounding load capacitors should have generous track width connected directly ground layer avoid ground loops, which major source emissions.
2.6.6 Symptoms Poor Clock
must emphasised that series resistor value must chosen with care. incorrect value unlikely result total failure, even erratic operation core, timers converter. However, first symptom poor choice that unexpectedly large number errors peripheral seen, timing erratic readily apparent reason. Such behaviour should never ignored shorting resistor problem goes away.
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Real Time Clock Oscillator
Real Time Clock (RTC) available XC161 XC167 that optionally have clock crystal. main oscillator (divided used input will still allow real time clock operation continued during XC166 sleep mode. maximum time-keeping accuracy though, external 32.768kHz "watch" crystal needs provided pins. Before entering sleep mode RTCCM SYSCON0 must enter "asynchronous" mode, provided FCPU greater than Fcount. However this dedicated oscillator synchronised clock, time registers cannot read written. Therefore after system reset, operating mode must back synchronous (RTCCM current consumption during sleep mode with running around 100uA. complete powering down device that requires power-on reset restart will leave real time clock registers undefined i.e. accumulated time will lost.
Further Information Oscillator Design
Application notes AP24205 AP242401 available from www.infineon.com/xc166-family that cover crystal oscillator ceramic resonator design detail.
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Modes Timings
Flexible Interface
XC166 family primarily intended single chip applications with variants having 256k automotive on-chip flash RAM. However, provision been made very flexible external interface. basic philosophy behind XC's interface simplicity, even external systems; providing 16-bit non-multiplexed modes, possible dispense with address latch provide just FLASH make working system. integral software-programmable chip selects make most address decoder logic redundant. Thus, despite fold improvement performance, XC's digital design simpler than that 8031! external required, XC's most useful features ability support different configurations single hardware design. Thus whilst external FLASH areas needed) 16-bit non-multiplexed with zero waitstates best speed, slow (and cost) peripherals such RTCs addressed with, example, 8-bit with waitstates.
3.1.1 Integral Chip Selects
family have external chip select regions. Chip selects each have ADDRSEL, FCON TCON registers that individually control mode, timing range Chip Select region. doesn't have ADDRSEL register active addresses that aren't covered another Chip Select internal memory registers). While looking user manual seem that also present, reality these used address internal peripherals. reserved future TwinCAN Module located 0x200000.
XC16x
TCONCS2 0x29A8 FCONCS2 0x0001 ADDRSEL2 0x3000
Non-Multiplex Waitstates
/CS2
Base Addr 0x300000 Length Non-Multiplex PhaseE cycles
TCONCS1 0x2868 FCONCS1 0x0021 ADDRSEL1 0x1006 /CS1
Base Addr 0x100000 Length 256k TCONCS0 0x2868 FCONCS0 0x0021 EBCMOD0 0x0800
WRCFG
/CS0
P0.8
P0.7 P0.6
BTYP
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Chip Select /CS0 /CS1 /CS2 /CS3 /CS4
Name P6.0 P6.1 P6.2 P6.3 P6.4
Control Register TCONCS0, FCONCS0 TCONCS1, FCONCS1 TCONCS2, FCONCS2 TCONCS3, FCONCS3 TCONCS4, FCONCS4
Address Range Register Applicable ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4
essential when setting ADDRSEL, FCON TCON registers make sure that configure ADDRESELx before corresponding FCONCSx TCONCSx. not, will enable ADDRSEL undefined configuration crash will ensue! Also note that while initialise these registers from variables located region controlled them will zeroed before main() compiler start-up code corresponding chip select will activated (low).
3.1.1.1 Overlapping Chip Selects
possible overlap regions covered external chip selects, provided that certain rules observed. When address generated that accessed, decides which device receives address according following rules: First checks whether address corresponds on-chip memory region peripheral directs access internally that will appear external bus. Thus example, external memory areas that partially overlap internal resources will inaccessible. Next registers ADDRSEL2 checked what areas they cover. match with these registers directs access respective external area. Thus ADDRSEL regions overlap ADDRSEL1, each other. overlapping windows ADDRSEL2 gives undefined behaviour. Next ADDRSEL1, checked address lies area covered these. Again, ADDRSEL1, overlap. However ADDRSEL2 overlap each other, These pairings only ones that allowed. Finally, addresses that range other ADDRSEL register cause chip select used. Thus chip select overlap other chip selects.
Setting Mode
3.2.1 On-Chip Boot
pulled high during reset, processor will boot from internal flash external controller will disabled. required, external configured through software. single chip mode virtually signals used external available I/O. External Controller Mode Registers (EBCMOD configure things such number signals segment address lines required, enabling /BHE signals well selecting ports address data busses.
3.2.2 External Boot
With during reset, reads pattern user-defined pull-down resistors P0.6 P0.7 default mode. fact, pull-down resistor pattern placed into BTYP field FCON0 register where changed software, although definitely recommended this external designs. number chip selects overall address range processor also Port pull-down resistors, covered section These also changed software modifying EBCMODx registers this should necessary.
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Setting Overall Addressing Capabilities
enabling segment address lines over above lines Port segment address lines demultiplexed mode), 16MB memory device used. Assuming processor's chip select signals going used, number segment address lines required determined largest device connected. example, 256KB memory connected Ethernet controller (with much smaller address range) connected CS2, only segment address lines would need enabled. setting ADDRSEL1 registers devices could enabled (pretty much) anywhere address space.
3.3.1 External Memory Access Times
access mode used XC166 Intel-style. timing each processor's chip select regions configured TCONx register. cycle divided into different timing phases number clock cycles each these phases TCONx register. phases are:
Phase Phase Phase Phase Phase Phase
Changing phase Address Setup /ALE Phase Delay Phase Write Data Setup Tristate Phase RD/WR Command Phase Address Write Data Hold Phase
clock cycles clock cycles clock cycles clock cycles clock cycles clock cycles
This allows great deal control over cycle cater different characteristics external devices. most applications, Phase will equal TWINCAN module being used, will always
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3.3.2 Calculating Timing Parameters Multiplexed
A0-A15
A0-A15 (ALEOUT)
Address
Timing Example (multiplexed)
timings based devices used Infineon starter kits. this example, Samsung K6R4016C1D SRAM fitted. This memory device organised 256K have access time 12ns. multiplexed. timings will calculated with 40MHz clock. timing always designed worst-case manufacturing tolerances. Please note that XC-microcontroller's signals always appear sync. output rise/fall time 4ns. delay falling edges WR-signals amount 13ns. case rising edges, this 6ns. 40MHz, clock duration 25ns. Phase Clocks Phase only necessary when working with more than chip select when certain still being driven from previous write- read access. Phase clocks will only inserted when address being accessed causes change chip select, such might happen when code being fetched from external FLASH accesses data external RAM. Most XC166 designs on-chip FLASH only external access might external SRAM, chip select changes will occur. Here assumed that only working with chip select have value fact almost always case. Phase Clock This clock required order address latch capture data. rule, address latch critical high clock speeds. However please note that guaranteed high-time only amounts 2ns. Phase Clock Phase serves delay through this, address latch able accept data. worstcase scenario, still 10ns long. High Clock.
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Phase Clock microcontroller puts address lines into tristate state order prevent XC-microcontroller from continuing drive them, well simultaneously lining data from memory. duration: 13ns Clock. Phase Clock After activation, READ line lasts 13ns until this state. READ signal's rising edge only completed when data been there least 24ns. Under worst-case conditions, this will result time 13ns 24ns 43ns. This corresponds Clocks. Phase Clock After deactivation READ line takes until reaches high state. Then will take further until memory lines into tristate condition. 6ns+6ns 12ns Clock. Note: values memory were taken from Samsung data. values XCMicrocontroller were taken from Infineon data sheet.
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3.3.3 Calculating Timing Demultiplexed
A0-A15 A16-A17, High Address, Chip Select
Timing Example (Demultiplexed)
timings based devices used used Infineon starter kits. previous example, Samsung K6R4016C1D SRAM employed. This memory device organised 256k access time 12ns. demultiplexed. timing will calculated with 40MHz clock. data given manufacturer worst-case timings. Please note that microcontroller's signals always appear simultaneously output, rise/fall time edges 4ns. Delays signals' falling edges 10ns. case rising edges, 6ns. 40MHz clock duration Phase Clocks Phase only necessary when working with more than chip select when certain still being driven from previous write- read access. Phase clocks will only inserted when address being accessed causes change chip select, such might happen when code being fetched from external FLASH accesses data external RAM. Most XC166 designs on-chip FLASH only external access might external SRAM chip select changes will occur. Here assumed that only working with just chip select value Phase Clock This clock always available cannot disabled configuration. Phase Clocks This phase does apply with demultiplexed bus. Phase Clocks This phase does apply with demultiplexed bus.
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Phase Clocks After activation READ line, takes 13ns fully low. data then inserted onto within memory. READ signal's rising edge only completed when data been present least 24ns. Under worst-case conditions, this will result time 13ns 24ns 43ns. This corresponds clocks. Phase Clocks This phase present with demultiplexed memory interface. Where external memory accesses 40MHz, clocks always required. Finally need reverse calculation fast clocked order accesses take place clocks. timing Phase employed.
23,25MHz 43ns
program implemented from internal memory, wise this value. better program 40MHz access memory with longer phases.
3.3.4 Tool Calculating Timing Parameters
spreadsheet application note (AP1608810) available from Infineon that allows values various phases calculated automatically, given memory access time memory device clock speed. These found www.infineon.com/xc166-family.
XC166 3.3.5 Timing Calculation Tool v.1.4 2005-06-08 PerMemory Devices Settings Commonly-Used Engdahl IFND) Microcontroller:
XC161CJ-16FF
Cycle Here settings 40MHz (25ns clock cycle) XC16x when used withswitch Phase memory devices. CLKOUT common Phase Config. These CLKOUT Ph-cycles would 25.0 valuesCYCLE PHASEinserted into TCONCSx registers. ABSOLUTE TIME Jitter [ns] Memory Device
TRUE TRUE TRUE
|Jitter| parameters tcMin tcMax TCONCSx PhaseA PhaseB PhaseC .32) PhaseE tc10 RDPHF WRPHF TRUE PhaseD TRUE tc11 A23-16, BHE#,CSx# tc12 K6R401C1D-TI10 16-bit 10ns SRAM 0x2868 width: 128.3 cyc. 125.0 tc13 29F800BB 16-bit 70ns FLASH 0x28A8 34.0 Memory parameters tc14 105.1 FLASH tc15 434096 8-bit 70ns SRAM 0x28A8 WR#(L/H) tacc tc16 tld= 173.7 94.9 Time Next Cycle 125.0 CS8900A Ethernet controller 0x29A8 tc17 A15-A0 Latch Output thoz tc18 48.2 tc19 AD15-AD0 (RD) tc20 tc21 Sampl. tc22 183.7 READ parameters: tc23 67.0 Minimal Lenght tc24 READ Condition 24.0 Addr? tc25 sampling Window 30.0 tc26 (OE-to-Data-valid)max OE-to-Data valid FALSE 34.7 120.0 (ADDR-to-Data-v)max tc27 Addr-to-Data valid FALSE 125.1 TRUE DATA (RD) Tristate RD-Data Tristate tc28 169.3 tc29 Sampl. WRITE Condition WRITE parameters: tc30 34.7 45.0 84.7 (ADDR-to-eof-WR)min tc31 Addr-v-to-eof-WR# TRUE 42.0 (WR-pulse-width)min Pulse Width FALSE 51.2 AD15-AD0 (WR) Latch <addr. latch> Data-write-Overlap TRUE WR-Data-hold-time TRUE
25.0 25.0 50.0 100.0 125.0 125.0
-1.7 -1.7 -1.8 1.82 -2.1 2.13 -2.3 2.29 -2.3
126.5
Timing Calculator Spreadsheet From Infineon
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Interfacing External Memory Devices
Despite power XC166 architecture, additional hardware necessary device running very small. many applications large on-chip FLASH sufficient. some cases, external added, especially application uses data. large systems, XC166 will boot into internal FLASH time-critical program sections will this area. Other code constant data will external FLASH. possible XC166 boot from external FLASH really makes almost sense Settings width (8/16-bit) type (mux/demux) best made RSTCFG register from software running from internal FLASH, rather than from using pull-down resistors Port classic C167fashion! standard XC166 series external bus, must ensure that memory device chosen compatible with this. Future versions will support 3.3v busses, giving wider choice devices, especially lead-free ROHS-compliance issue. following diagrams next sections illustrate simple examples common configurations.
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Using 16-Bit Memory Devices
This most common expand memory XC166 design. 16-bit FLASH comparatively cheap. Adding 16-bit demultiplexed will whole Ports plus bits Port which represents significant loss However does give fastest access times code data. should noted, though, that code execution from external much slower than from internal FLASH. This mainly fact that internal bits wide, whereas external just bits. 16bit memories word-orientated, XC166's fact really used address line that should routed memory device's smaller XC166 versions, might necessary external 16-bit multiplexed mode. This frees Port completely access times approximately doubled, with code execution speed worst affected. Therefore this should only done where large external data RAMs need added. these examples, FLASH programming routines must word-wise byte writes supported, although XC166 itself does support this. This unlikely problem where FLASH contains static code constant data. Where FLASH will also contain some adaptive data that updated system runs, such variables must types long, eliminate possibility byte-writes.
D0-D15
/BHE /BLE
IDT71016
A1-A16
/BHE
XC16x
D0-D15
29F400B
D0-D15
/CS1 /RESIN /CS0
A1-A20
/BYTE /RY/BY /RES
40MHz
(4MHz with PLL)
/RESET
16-Bit IDT71016 Demultiplexed
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D0-D15
74ABT573A
A1-A18
/BHE
XC16x
29F400B
D0-D15
LATCHED A0-A20
74ABT573A
P4.0-3
/CS1 /RESIN /CS0
AD0-AD15 A16-A20
/BYTE /RY/BY /RES
40MHz
(4MHz with PLL)
/RESET
16-Bit Memories Multiplexed
D0-D15
/BHE /BLE
IDT71016
A1-A16
/BHE
D0-D15
XC16x
29F400B
D0-D15
/CS1 /RESIN /CS0
A1-A20
/BYTE /RY/BY /RES
40MHz
(4MHz with PLL)
/RESET
16-Bit IDT71016 Demultiplexed
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4016CIC
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D0-D15
4016CIC
A1-A18
/BHE
XC16x
D0-D15
29F400B
D0-D15
/CS1 /RESIN /CS0
A1-A20
/BYTE /RY/BY /RES
40MHz
(4MHz with PLL)
/RESET
16-Bit Memories Demultiplexed
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Using Byte-Wide Memory Devices 16-bit XC166 Systems
successfully 8-bit RAMs user must remember that pins RAMs XC166. data lines connected XC166's D0-D7 (LOW) other wired D8-D15. effectively redundant such configuration. Failure realise this before committing will result track cutting hand-wiring. When reads word both RAMs enabled simultaneously /READ that read D0-D15 access across bus. XC166 16-bit machine, read accesses word-wide, even byte ones unwanted byte simply discarded. writes some means only enabling RAM's required, byte write even location would corrupt associated byte. traditional method preventing this create individual /WRITE signals each from /BHE However XC166 special /WRITEHIGH (/WRH) /WRITELOW (/WRL) pins, which connected corresponding pins high RAMs. enable this feature, user must write into EBCMOD0 register, Alternatively, external start mode being used (/EA pull-down resistor must fitted (P0.8).
D0-D7 A0-A17
551001
XC16x
D0-D7
D0-D7
29F040
A0-A18.A23
/CS1 /CS0
40MHz
(4MHz XTAL with PLL)
8-Bit Memories Demultiplexed 8-Bit
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D8-D15 D0-D7 A1-A18 /WRH /WRL
551001
551001
XC16x
D8-D15 D0-D7 D0-D7
D8-D15
A1-A19.A23
/CS1 /CS0
29F040
29F040
40MHz
(4MHz with PLL)
8-Bit Memories Demultiplexed 16-Bit Using WRH/WRL Mode
Using XC166 With Byte-Wide Memories #BHE
Where WRITEHIGH (/WRH) WRITELOW (/WRL) signals being used, different approach required. 8-bit memory devices chosen that have chip selects available, then /BHE (BYTE HIGH ENABLE) lines used enable either high bank memories.
D8-D15
HIGH
62256
D0-D7 A1-A15 /BHE
/CE2
62256
/CE2
XC16x
D8-D15 D0-D7 D0-D7
D8-D15
A1-A17
29F010
29F010
40MHz
(4MHz with PLL)
8-Bit Memories Demultiplexed 16-Bit Using WR/BHE Mode
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Here /BHE signals connected active chip selects both RAMs. When even byte addressed /BHE high, that enabled. addressing byte, high /BHE low, that high enabled. goes active high chip select, that RAMs enabled above 0x20000. also goes active chip select, mapping address zero.
Using DRAM With XC166 Family
Despite recent falls cost large, fast static RAMs, PC-style SIMM DRAM still cheapest means getting very large area XC166 design. conventional designs some method must provided refresh memory. This typically request every tens microseconds performing (Row Address Strobe) cycle only. address counter would then incremented. hardware this requires additional master with buffers counter. Another commonplace refresh method (Column Address Strobe) before RAS, which uses internal address refresh counter still requires complex logic ensure that precharge times met. XC166 family perform refresh task with virtually external logic that needed implement timing accessing DRAM. important peripheral (Peripheral Event Controller), which covered detail section 8.4. current context simply used conjunction with on-chip timer) means generating read from each every 15.6us. source pointer used make read then automatically incremented next row. destination simply throws away read data writing unused location on-chip area. period calculated refresh time divided number rows DRAM. typical 256k HYB14256 DRAM this would 8ms/512 rows 15.6us. steals 40ns cycle every transfer, overhead DRAM refresh (0.1/15.6), which negligible.
PAL16R6
/RAS /CAS
XC16x
SMUX
CLKOUT
A10-A19
A0-A9
/CAS /RAS A0-A9
DRAM Array
D0-D15
D0-D15
DRAM Refresh With XC16x
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Using FLASH Memory Cards With XC166
4.5.1 Cheap Gigabyte Storage
becoming increasingly common microcontroller applications need very large non-volatile storage. This might storing values part data logger monitoring function even allowing updating on-chip FLASH without using serial port bootstrap mode. Low-cost mass storage devices like Compact FLASH SD/Multimedia cards widely available result popularity digital cameras PDAs. They hold prospect vast memory capacity easy movement data between microcontroller. only data moved from embedded device, even complete microcontroller application software updates feasible just through card insertion. Typical FLASH card storage costs around cents falling, they particularly attractive memory-hungry applications like data-logging.
4.5.2 Using CompactFLASH Cards XC166 Program Updates
interesting FLASH cards program updates field. XC166 contains boot program some applications access larger program Compact FLASH card. FLASH card written with XC166 program card slot, using FAT16 file system (i.e. MS-DOS). boot program XC166 able read this format either using home-made commercial embedded file system. Several modes operation typically used: boot program loads application from FLASH card writes into large external every time system powered-on. This makes XC166 appear boot from FLASH card, although does not. Holding program large external means that significant performance loss occurs compared on-chip FLASH operation. When XC166 boot program starts, detects presence FLASH card, checks whether program internal FLASH same card. not, program card loaded into internal FLASH application runs. This approach means that full performance available.
(ii)
However there obstacles overcome before memory card added microcontroller. Firstly, huge storage capacity usually dictates some sort file system keep track objects stored memory. Also, cards likely read written some time, this invariably means file system like FAT16 (MS-DOS/Windows FAT32 (Windows 2k/XP) needed. Secondly, card physically connected microcontroller's ports. Fortunately, this difficult might expected.
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4.5.3 Interfacing SD/Multimedia Cards
Secure Digital (SD) cards physically identical MultiMediaCards equipped with SPI, function supported XC166 synchronous serial ports (SSCs). "secure digital" mode uses more pins make total four data lines, giving speeds 10MByte/s rather than 100kbyte/s SPI, does require special form UART which present XC166. Thus cards must Multimedia mode. user must provide pins microcontroller clock, card select memory write protect. illustration below shows possible connection SSC/SPI peripheral XC166.
Interfacing Memory Card XC16x Peripheral
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4.5.4 Interfacing CompactFLASH
CompactFLASH cards equipped with both familiar ("ANSI ATA") interface standard PCMCIA card) interface found PCs. latter mode, they addressed simple 8-bit memory-mapped devices, which makes interfacing microcontroller very straightforward. XC166 example illustrates this below. using 8-bit multiplexed external mode, only Port lost, thus minimising impact compact FLASH overall count. Typically CompactFLASH cards require least wait-states (Phase They comparatively slow devices used polled mode. therefore important insert delay between writing control register then trying read back check status flag. software drive FLASH cards quite simple (you find www.infineon.com/xc166-family).
/CS4 /SDCE
P0L.0/AD0
XC16x
74ABTHC573
P0L.7/AD7
Simple Scheme Attaching Compact FLASH Card XC16x 8-Bit Mode (courtesy Embedded)
4.5.5 Managing Large FLASH Cards
FLASH cards like resident FLASH that address data held linear fashion. base card's address range bank control registers which user's code must configure device read write data. internal structure FLASH cards usually similar hard disk indeed common method accessing them "True IDE" mode. This rather like paging scheme, where enormous memory space accessed through small window using "page number offset" scheme. most cases, random access individual bytes addresses card possible. Usually, bytes must read into buffer microcontroller system individual bytes read written required. changes then back into card re-writing entire bytes. this make handling card quite tricky keeping track where data through plethora base pages, offsets local buffers easy. Therefore, majority cases much simpler treat FLASH card file system, just like digital camera does. This allows data stored named areas logical fashion (i.e. directories files) makes retrieval data much easier. There also added advantage being able write data onto card embedded system then being able read directly card slot vice-versa.
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Although simple use, creation flash file system from scratch complicated process. Fortunately there number ready-made systems available off-the-shelf C-source code which handle FLASH card hardware interface manage file system. Such file systems support FAT16, FAT12 FAT32 systems, found MS-DOS Windows. Usually they will offer wear-levelling media error handling cope with vagaries real FLASH devices. File systems traditionally associated with large CPUs like 8086, SH4, where RTOS often present along with huge memory resources. However this file-based approach handling FLASH cards applied single-chip 16-bit devices like XC166.
4.5.6 File System Embedded Programs
many embedded programmers, having file system present application hard visualise. used dealing with pointers arrays, pointers malloc() then thinking file-orientated very strange! Here some examples common file system operations Here creating directory FLASH file system card:
create Hello.dir ret=f_mkdir("Hello.dir"); (ret) return _f_result(1,ret);
Here making directory current directory:
change into hello.dir ret=f_chdir("hello.dir"); (ret) return _f_result(23,ret);
Here opening file READ-only access. Here file handle used, just programming:
file=f_open("file.bin","r"); (file) return _f_result(0,0);
Here writing array called "buffer" containing ones into file represented file handle:
memset(buffer,1,512); elements buffer test write (size!=512) return _f_result(5,size);
general format functions used control file system should familiar anybody worked with MS-DOS files example, Microsoft Visual C/C++.
4.5.7 Resources Implement File System XC166
XC166 CompactFLASH example given above, EFFS-THIN (from Embedded) small-footprint file system uses around minimum DOS-style file system complete file system, including formatting functions. Data usage under with 0.5k extra each file permitted opened simultaneously ("MAXFILES"). memory statically allocated neither heap operating system required. However many embedded RTOS like CMX-RTX ARTX166 able incorporate file system. Providing means "scale" file system according user's needs available resource important. example, file system code eliminated omitting FLASH card formatting function, relying card reader instead.
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4.5.7.1 Issues When Porting Embedded File System
File systems like EFFS-THIN written platform-independent sometimes require some configuration host microcontroller's peripherals programmer. However XC166 standard configuration range, this already done. SPI-driven Multimedia cards, user choose either XC166's SSC/SPI interface, file system provide "bit-bashing" simulated SPI. files written with time date stamp, then hardware real time clock required. Other typical user-defined configurations are: (ii) (iii) (iv) random number generation serial number generation during format recommended only formatting media required. semaphores mutual exclusion only required where pre-emptive RTOS present. which functions exclude include, depending target memory resources required features (e.g. including formatting capability) selecting FAT12/16/32 support selecting long name support
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In-Circuit Reprogrammable FLASH EPROM
Introduction
main reason introduction XC166 family addition FLASH successful C167 series. XC166 derivatives have on-chip FLASH sizes from 32kbytes 256kbytes. Future versions will have considerably larger FLASH ROMs. FLASH area programmed without that required. Typically FLASH programmed processor itself, even when soldered down, with program received serial port's bootstrap loader mode. Please refer section more information pull-down resistors. user's software then receive program file program into FLASH. important note that many competitive CPUs which appear offer convenience in-circuit reprogrammabilty actual fact not! Unlike earlier FLASH technologies used C167 devices, still execute code from FLASH during programming erase operations should FLASH module busy with program erase, instruction pipeline will wait ready before continuing. also possible program reprogram itself, i.e. receive version itself blow into FLASH. This requires specially written function, which downloaded from Infineon website Alternative bootstrap modes available that peripherals. application note available from Infineon that shows FLASH programmed CAN. JTAG unit also used programming conjunction with tool like Hitex XCFLASHer. This self-programming ability very useful cases where FLASH used massproduction, final program need only into device line. also makes field software updates very straightforward. further information using bootstrap loader, please refer section 5.6.
Internal FLASH Layout
XC167CI 256kbyte FLASH ROM, divided into four 8kbyte sectors, plus 32kbytes three 64kbytes. based 0xC00000 rather than usual 0x00000, which also default reset address single-chip boot mode. also means interrupt vector table address (VECSEG) must 0xC0. 128kbyte versions lose 64kbyte sectors. READ protection applied sector-by-sector basis entire FLASH area, with password system available temporarily unlock protected areas. defeat unauthorised reading FLASH ROM, data reads only made code itself which situated FLASH. Write operations performed "pages" 128bytes whilst erasing sector byte "wordline" basis. FLASH arranged 64-bit rows, XC166 instructions FETCHed access, giving significant performance increase over classic C167's 32-bit wide FLASH. Programming typically takes byte page sector erase around 200ms. entire FLASH erased programmed around seconds, using JTAG tool. Devices supplied from Infineon guaranteed erased state unusually, this equates numerical zero each location.
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5.2.1 FLASH Identification
IDCHIP register address 0xF07C returns value that allows type FLASH silicon revision level determined. values common XC166 derivatives listed below.
Device Type Stepping XC161-16, step AC/AD/AE: XC161-16, step BA/BB: XC164-16, step AC/AD/AE: XC164-16, step BA/BB: XC161-32, step XC161-32, step BA/BB: XC164-32, step XC164-32, step BA/BB:
IDCHIP Value 2003 2004 2303 2304 2001 2002 2301 2302
Chip Identification Information Hitop5
FLASH Reliability
Vast effort been into guaranteeing integrity FLASH data, even degree automotive temperature range. FLASH memory failure rate defects tunnel oxide plus deterioration erasing cause charge stored floating gate leak. It's just matter much when. data retention quality required automotive applications least orders magnitude greater than that needed standard industrial consumer applications. Automotive quality requirements moving ZERO defects million. Providing reliable FLASH this kind environment proved huge challenge silicon manufacturers taken years plus technology perfected.
5.3.1 Dynamic Error Correction
high reliability FLASH dynamic error correction. Hamming codes detect single double-bit errors, correct single-bit errors well. contrast, simple parity code cannot detect errors where bits transposed, help correct errors find. XC166 devices Hamming distance which means that FLASH really 72-bits wide, bits might appear. system allows correction single erroneous bits detection wrong bits. This process occurs real time, instructions data read from FLASH. event double error occurring, immediately vectors class trap (exception) where user's program expected take some action rectify situation. Single errors cause trap just flagged FLASH Status Register (FSR) where user choose carry some action such reprogramming 256-byte wordline within which error occurred. However single errors fatal, program proceeds normal. Hamming code correction FLASH errors required assure automotive quality needed existing high quality FLASH process cannot used substitute poor FLASH. must stressed that even single-bit errors extremely rare likely only occur where FLASH been mistreated taken beyond nominal write-erase cycles. Double errors only likely occur extremes probability, although good software engineering practice dictates that they should handled properly.
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5.3.2 FLASH Endurance
stated year data retention assumes programming cycles (erase-programme) full rated operating temperature device. With programming cycles, data retention time reduced years, worst case. With XC166 FLASH module, these just baseline figures Infineon have provided mechanism whereby data retention extended almost indefinitely, albeit with small software overhead. examination typical 16-bit automotive microcontrollers reveals: Part nimum Data Retention ite/Erase Cycles XC167CS-32FF: years years DeviceX: DeviceY: years years years
1000 20000 1000 10000
This kind data really only gives estimate FLASH reliability course, manufacturer could such test real time. There many factors that determine long data will retained, which number erase cycles usually most significant. rigorousness test regime methodology used also critical this does vary from silicon manufacturer another. numbers above based qualification test 1008 hours degrees when de-rated room temperature, equate over 1000 years data retention. However they really just very well-informed estimates such, indicate that microcontroller FLASH very reliable these days. practice, silicon manufacturers cannot store wafers many months prove defect million quality levels. This where hardware error correction helps GUARANTEE automotive quality requirements even uncorrected retention quality worsens slightly particular batch process parameter shifts, still guarantees quality. FLASH quality that cannot guaranteed detected very easily.
Managing FLASH Under Extreme Conditions
However some applications close worst-case limits stated nature high-volume production that even very probability event like FLASH error will become likely, given enough units shipped. Normally user check state programmed data certainly easy correct potential problems. that user provide some sort fail-safe mode where FLASH error will cause hazardous condition.
5.4.1 When Manage FLASH
This where FLASH used XC166 unique, allows user check state FLASH cells reprogram where retained charge floating-gate cell changed unexpectedly. This requires small software overhead only required applications where: product must guaranteed last more than years service sector FLASH will erased written more than 20000 times years 1000 times years part normal operation product. sector used storing adaptive constants that updated every days would example.
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will operated outside normal temperature specification2 stated Infineon without their approval (i.e. oilwell applications) large number erase/programming cycles will occur temperatures degC). Very high integrity applications such flight controls medical systems with very long service life involved.
other FLASH microcontrollers, natural charge leakage FLASH over time will cause eventual failure small percentage units. This will require unit either scrapped perhaps reprogrammed under original factory conditions, although this always realistic solution. most cases product which microcontroller fitted will warranty/fashion/use after years, normal FLASH reliability adequate. However XC166 FLASH allows user extend useful life FLASH data, described following paragraphs
5.4.2 Dynamic Recovery From Double Errors
probability double error (i.e. automatically compensated hardware error correction) extremely low. Double errors avoided performing recovery operation after single error been detected. This requires following steps: Detect byte wordline containing erroneous bit. Reduce speed 10MHz Store contents wordline temporarily another FLASH sector (safer) Erase wordline FLASH, provided ambient temperature above degrees Reprogram erased wordline using byte write-page operations
Note: XC166-32F devices including BB-step, plus XC166-16F including BA-step, speed must 0.5MHz duration Erase wordline command, ambient temperature below degrees wordline data copied from FLASH temporary buffer will valid because single error during READ automatically corrected hardware error correction. erase programming done using standard command sequences.
5.4.3 Predicting Future FLASH Failures
further even more rigorous type check possible that will spot single errors before they ever occur. really intended production-line FLASH programmers, although could used application software regular basis. This test based examining threshold levels ("margins") cell considered contain independent hardware error correction system. unwanted changes cell's charge results from charge-coupling from writes neighbouring cells, sectors updated regularly with adaptive data might risk. margin check involves reading each address sector maintained. "margin" control would "standard" first value read from location temporarily stored RAM. margin would then level read repeated whether previously read become `1'. there problem that causes double error, class trap would generated exactly same margin were normal. This indicates change charge FLASH cell that means that this might continue wander become read `1', even using standard margin. single error would eventually occur, possibly with double error final outcome. read then repeated with margin upper limit `1's have become `0's. Given very remote possibility even single error, this FLASH "routine maintenance" procedure need carried very often. might take form service procedure during periodic annual
Infineon will permit XC16x devices used 1500 hours ambient temperatures 140degC, subject junction temperature exceeding 150degC, clock 20MHz less FLASH reprogramming above 125degC.
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maintenance system incorporating XC166 microcontroller e.g. visit servicing outlet automotive application. Alternatively program could perform these checks continuously normal background housekeeping operation. Another margin control facility allow wordlines that give double-bit errors recovered; reducing margin, possible that reads that previously gave double errors repeated only give single-bit errors. recovered data would then re-programmed procedure given above.
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Tools Programming FLASH
Infineon produce freeware programmer their FLASH microcontrollers (including 32-bit Tricore). This MEMTOOL available download from www.infineon.com. This assumes that host serial port, which unfortunately many not, especially laptop computers. Some USB-COM adaptors will work some experimentation required. MEMTOOL also works with K-Line (ISO1314), given suitable RS232-K Line interface. There some commercial tools that allow FLASH programming interface. user's solutions Infineon FLASH-On-The-Fly application note gives example that reasonably easy adapt.
5.5.1 Programming XC166 FLASH Production
Whilst MEMTOOL very quick useful laboratory FLASH programming tool, suitable highvolume production programming. This especially true where XC166 application itself high-integrity engineered tested quality standard like IEC61508 SIL2 above.
5.5.1.1 Hitex FLASHXC.DLL Bootstrap-Loaded Production FLASH Programmer
cases where JTAG cannot used either because tracked-out rendered inaccessible, serial bootstrap mode good program FLASH production. FLASHXC.DLL programmer uses Microsoft perform programming function when called from user-defined front running This might programming station that part production line control system. simply slots takes care bootstrapping processor, decoding XC166 program's HEXfile transmission XC166 system. called via:
result BootLoadFLASH(Hex_File_Name, COMport, NULL, NULL, KLine, baud_rate, secondary_baudrate, PLLCON_value, XTAL_freq);
This programmer been independently validated suitable high volume production use. Typical programming times seconds 256kbyte binary image.
5.5.1.2 Hitex FLASHCANXC.DLL CAN-Based Production FLASH Programmer
Where serial port bootstrap mode cannot used, there CAN-based equivalent available that uses Softing CAN-USB interface communicate with XC166. Functionally very similar serial version.
5.5.1.3 Hitex XCFLASHer JTAG Production Programmer
programming multiple XC166-based systems parallel, JTAG best choice. This requires special tool such Hitex XCFLASHer that allows systems programmed simultaneously through USB. typical programming time serial FLASH programmer around seconds 256kb FLASH image whereas with JTAG, this comes down around seconds.
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Introduction Bootstrap Loader Programs
5.6.1 XC166 Serial Bootstrap Loader
Like C167 forebear, XC166 series serial bootstrap loader serial port ASC0 that commonly used means programming on-chip FLASH both during program development series production. This loader program made available special mode, entered powering with lines held high (single chip 3ULPDU\ ERRWVWUDS start). ASC0 then ORDGHU monitored ERRW normally-hidden 0xFF0000 bootstrap loader 6HFRQGDU\ ERRWVWUDS program located ORDGHU 0xFF0000. This sets 365$0 processor 0xE00004 minimum usable )/$6+ SURJUDPPHU configuration that 365$0 watchdog disabled, serial port ready 0xE00024 receive transmit TxD0 output. seeing character start bit, eight data bits zero stop bit, bootstrap loader measures baud rate then proceeds place next bytes received into PSRAM 0xE00004. These bytes fact simple XC166 program that represents "secondary" bootloader whose receive much larger program. Finally "primary" bootstrap loader jumps this address runs user's 32-byte program. most cases, larger program received secondary loader complete FLASH programming system that will eventually receive final 128kbyte 256kbyte application burn into XC166 FLASH ROM. size FLASH programmer limited size PSRAM some variants) secondary loader limited Infineon's bootstrap loader bytes, thus these programs must tightly coded located memory very precisely. Also they must operate directly CPU's FLASH memory controller manner prescribed silicon manufacturer with room misunderstandings. additional complication that XC166 comes reset with clock divided that typically only running 4MHz. such frequency, bootstrap loader cannot auto-baudrate detect reliably above 9600 baud. Therefore downloaded FLASH programmer must Typical Secondary Bootstrap Loader change serial port control registers clock something more reasonable like 40MHz, allowing 115.2kbaud used program transmission. Writing such programs quite test engineer's competence familiarity with both compiler! FLASH programmer ultimately used programming finished products high-volume production line, then program will need extensively tested, errors could result complete chaos huge costs thousands units wrongly programmed. Unfortunately very common quickly thrown-together FLASH programming tools find their from "casual" laboratory into production environment! Programming tools provided Infineon approved production most companies forced write their tools from scratch.
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Testing FLASH Programmers Under IEC61508 Other Standards
constraints bootstrap-loaded FLASH programmers outlined above make their formal testing significant challenge. simple system-level test relatively easy perform probably consists just "send test application programmed into FLASH application runs properly". However this type test usually adequate anything most trivial applications certainly sufficient programming tool destined series production. sort proper software testing regime, techniques such unit testing coverage analysis mandatory. application programmed production line itself safety-critical then programmer needs tested same level. Thus example, application conducted IEC61508 SIL2 must include unit (i.e. module) testing implication some form coverage testing. Inevitably FLASH programmers split into distinct parts. Firstly there application that initialises XC's bootstrap mode sends HEXfile version application serial port XC166 target. Secondly there small XC166 programs sent end, running XC's PSRAM. testing program relatively straightforward Microsoft Developer Studio debugger used simple tests there multitude commercial tools available unit testing software. real challenge debugging testing code special tools required done properly.
Unit Testing Requirements IEC61508 SIL2 Above (RiskCAT)
Bootstrap Mode Debugging Problems With JTAG
Whilst just about possible debug bootloaded-FLASH programmer waving port pins down other crude methods, virtually impossible test verify correct operation. Using debugger pretty well essential with basic JTAG debugger like Keil uLINK even advanced like Hitex TantinoXC, there fundamental problem with debugging bootstrap-loaded programs that JTAG disabled bootstrap mode until primary loader completed user's secondary loader started. Thus this mode possible control while secondary loader being received written into PSRAM. partial solution this write small application that mimics Infineon integral bootstrap loader manually blow this into FLASH using MEMTOOL utility. When boots single-chip mode, program monitors serial port zero byte, measures baud rate, loads 32-byte secondary loader just like built-in loader. risk with this method that user's bootloader emulation function might quite like Infineon there high probability incorrectly initialised registers stacks, which could result unpredictable behaviour later
Insiders Guide
V1.0, 2006-02
Insiders Guide Planning XC166 Family Designs
Bootstrap Mode Debugging Using In-Circuit Emulator
best solution proper XC166 in-circuit emulator like DPROBEXC. This based special form device that additional pins external control program tracing. However unlike traditional "bondout" chip, this "emulation device" real FLASH memory. also contains real Infineon bootloader behaves identically production XC166 device same step level. Thus state stack, serial port, DPPs other critical registers entirely representative standard silicon bootloader-dependent programs developed DPROBEXC will also first time production hardware. This combination features makes possible properly emulate XC166 device bootstrap mode allow erasure programming State Configured Bootstrap Loader Entry Secondary Loader representative FLASH memory. therefore feasible breakpoint exit user's secondary bootloader break FLASH programmer called. Following from this, single-stepping actual FLASH programming lines possible importantly, programming errors simulated intercepting FLASH status register check that occurs after writing wordline erasing sector.
5.10 Hardware Aspects In-Circuit FLASH Programming
capability programming FLASH EPROM (external on-chip) after XC166 been soldered down extremely useful. program device, access serial port required plus access pins whilst coming reset. following internal start examples show various means doing this.
Program
XC16x FLASH
XC16x FLASH
Floating
Floating
RS232
RS232
S0TX /RESIN S0RX
S0TX /RESIN S0RX
Programming Add-On Board
Ex1: Simple Method Entering Bootstrap mode
Ex2: Using Special Serial Connector Enter Bootstrap
Program
XC16x FLASH
XC16x FLASH
Floating
RS232
/RESIN S0RX
CANH
TLE6250G
S0TX
CAN1_RXD /RESIN CAN1_TXD
Program
CANL
Programming Add-On Board
Ex4: TwinCAN Bootstrap Mode
Ex3: Holding Line Down Enter Bootstrap
Insiders Guide
V1.0, 2006-02
Insiders Guide Planning XC166 Family Designs
example uses RS232 link might connected MAX232 similar LT7011 etc.) XC166's bootstrap mode entered simple push button pin. host sends null byte with start stop until device replies with acknowledge byte 0xD5. user must then send 32byte loader program, which then receives FLASH programming utility which then receives user's application program. integral bootstrap loader second 32-byte program necessarily very simple, only binary code sent them, which supported commercial compilers. number binary convertors available bridge gap. single-line physical communication layer such RS485 ISO-K used, S0TX S0RX effectively connected together. integral bootstrap loader disables receive side until acknowledge byte been completely transmitted that will confused with first byte initial 32-byte program. shows means dispensing with manually oper
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