LC2MOS 12-Bit Serial Mini-DIP DACPORT AD7233 VOUT 12-BIT LATCH

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LC2MOS 12-Bit Serial Mini-DIP DACPORT AD7233 VOUT 12-BIT LATCH

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FEATURES 12-Bit CMOS with On-Chip Voltage Reference Output Amplifier Output Range Serial Interface Update Rate Small Size: 8-Pin Mini-DIP Nonlinearity: TMIN TMAX Power Dissipation: APPLICATIONS Process Control Industrial Automation Digital Signal Processing Systems Input/Output Ports
LC2MOS 12-Bit Serial Mini-DIP DACPORT AD7233
VOUT 12-BIT LATCH
AD7233
INPUT SHIFT REGISTER
GENERAL DESCRIPTION
AD7233 complete 12-bit, voltage-output, digital-toanalog converter with output amplifier Zener voltage reference 8-pin package. external trims required achieve full specified performance. data format complement, output range AD7233 features fast, versatile serial interface which allows easy connection both microcomputers 16-bit digital signal processors with serial ports. When SYNC input taken low, data SDIN clocked into input shift register each falling edge SCLK. completion 16-bit data transfer, bringing LDAC updates latch with lower bits data updates output. Alternatively, LDAC tied permanently low, this case register automatically updated with contents shift register when sixteen data bits have been clocked serial data applied rates allowing update rate kHz. applications which require greater flexibility unipolar output ranges with single supply operation, please refer AD7243 data sheet. AD7233 fabricated Linear Compatible CMOS (LC2MOS), advanced, mixed-technology process. packaged 8-pin package.
DACPORT registered trademark Analog Devices, Inc.
SDIN SCLK SYNC LDAC
PRODUCT HIGHLIGHTS
Complete 12-Bit DACPORT®. AD7233 complete, voltage output, 12-bit single chip. This single-chip design inherently more reliable than multichip designs. Simple 3-wire interface most microcontrollers processors. Update Rate-300 kHz. Space Saving 8-Pin Package.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7233-SPECIFICATIONS1 ==100 pFVtotoGND. specifications T-15to TGNDunlessV,otherwise noted.)
Parameter STATIC PERFORMANCE Resolution Relative Accuracy3 Differential Nonlinearity3 Bipolar Zero Error3 Full-Scale Error3 Full-Scale Temperature Coefficient DIGITAL INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current Input Capacitance4 ANALOG OUTPUTS Output Voltage Range Output Impedance CHARACTERISTICS4 Voltage Output Settling Time Positive Full-Scale Change Negative Full-Scale Change Digital-to-Analog Glitch Impulse3 Digital Feedthrough3 POWER REQUIREMENTS Range Range
Units
Test Conditions/Comments
Bits Guaranteed Monotonic Latch Contents 0000 0000 0000 FSR/°C Settling Time Within Final Value Typically Latch 100. .000 011. .111 Typically Latch 011. .111 100. .000 Latch Contents Toggled Between LDAC High Specified Performance Unless Otherwise Stated Specified Performance Unless Otherwise Stated Output Unloaded; Typically Output Unloaded; Typically
+10.8/+16.5 -10.8/-16.5
+11.4/+15.75 -11.4/-15.75
secs secs min/V min/V
NOTES Temperature Ranges follows: Versions: -40°C +85°C. Power Supply Tolerance: Version: 10%; Version: Terminology. Sample tested +25°C ensure compliance. Specifications subject change without notice.
TIMING CHARACTERISTICS1,
Parameter
(VDD +10.8 +16.5 -10.8 -16.5 Specifications TMIN TMAX unless otherwise noted.)
Limit TMIN, TMAX (All Versions) Units Conditions/Comments SCLK Cycle Time SYNC SCLK Falling Edge Setup Time SYNC SCLK Hold Time Data Setup Time Data Hold Time SYNC High LDAC LDAC Pulse Width LDAC High SYNC
Limit (All Versions)
NOTES Sample tested +25°C ensure compliance. input signals specified with (10% timed from voltage level Figure SCLK Mark/Space Ratio range 40/60 60/40.
REV.
AD7233
ABSOLUTE MAXIMUM RATINGS
+25°C unless otherwise noted)
-0.3 +0.3 VOUT2 +0.3 Digital Inputs -0.3 +0.3 Operating Temperature Range Industrial Versions) -40°C +85°C Storage Temperature Range -65°C +150°C Lead Temperature (Soldering, secs) +300°C Power Dissipation +75°C Derates above +75°C mW/°C
NOTES Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. output shorted voltages this range provided power dissipation package exceeded. Short circuit current typically
ORDERING GUIDE
Model AD7233AN AD7233BN
Plastic DIP.
Temperature Range -40°C +85°C -40°C +85°C
Relative Accuracy
Package Option*
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7233 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
TERMINOLOGY
RELATIVE ACCURACY (LINEARITY)
FULL-SCALE ERROR
Relative accuracy, endpoint linearity, measure maximum deviation transfer function from straight line passing through endpoints transfer function. measured after allowing zero full-scale errors expressed LSBs percentage full-scale reading.
DIFFERENTIAL NONLINEARITY
Full-scale error measure output error when amplifier output full scale (full scale either positive negative full scale).
DIGITAL-TO-ANALOG GLITCH IMPULSE
Differential nonlinearity difference between measured change ideal change between adjacent codes. specified differential nonlinearity less over operating temperature range ensures monotonicity.
BIPOLAR ZERO ERROR
This voltage spike that appears output when digital code latch changes before output settles final value. energy glitch specified secs, measured codes change (0000 0000 0000 1111 1111 1111).
DIGITAL FEEDTHROUGH
Bipolar zero error voltage measured VOUT when loaded with combination offset errors DAC, amplifier mismatch between internal gain resistors around amplifier.
This measure voltage spike that appears VOUT result feedthrough from digital inputs AD7233. measured with LDAC held high.
REV.
AD7233
FUNCTION DESCRIPTION
Mnemonic SCLK SDIN SYNC LDAC
Description Positive Supply (+12 Serial Clock, Logic Input. Data clocked into input register each falling SCLK edge. Serial Data Logic Input. 16-bit serial data word applied this input. Data Synchronization Pulse, Logic Input. Taking this input initializes internal logic readiness data word. Load DAC, Logic Input. Updates output. output updated falling edge this signal, alternatively this line permanently low, automatic update mode selected whereby updated 16th falling SCLK pulse. Ground Analog Output Voltage. This buffered output voltage Negative Supply (-12
VOUT
SCLK SDIN SYNC
VOUT LDAC
AD7233
VIEW (Not Scale)
CIRCUIT INFORMATION Section
DIGITAL INTERFACE
AD7233 contains 12-bit voltage-mode converter consisting highly stable thin-film resistors high speed NMOS single-pole, double-throw switches.
Section
output voltage-mode converter buffered noninverting CMOS amplifier. buffer amplifier capable developing across load GND.
VOUT INTERNAL REFERENCE
AD7233 contains input serial parallel shift register latch. simplified diagram input loading circuitry shown Figure Serial data SDIN input loaded input register under control SYNC SCLK. When complete word held shift register then loaded into latch under control LDAC. Only data latch determines analog output AD7233. SYNC input provides frame synchronization signal which tells AD7233 that valid serial data SDIN input will available next falling edges SCLK. internal counter/decoder circuit provides gating signal that only data bits clocked into input shift register. After SCLK pulses internal gating signal goes inactive (high) thus locking further clock pulses. Therefore, either continuous clock burst clock source used clock data. SYNC input should taken high after complete 16-bit word loaded Although bits data clocked into input register, only latter bits transferred into latch. first bits 16-bit stream don't cares since their value does affect latch data. Therefore data format don't cares followed 12-bit data word with last serial stream.
DB10 DB11
Figure Simplified Converter
REV.
AD7233
There ways which latch hence analog output updated. status LDAC input examined after SYNC taken low. Depending status, update modes selected. LDAC then automatic update mode selected. this mode latch analog output updated automatically when last serial data stream clocked update thus takes place sixteenth falling SCLK edge. LDAC then automatic update disabled latch updated taking LDAC time after 16-bit data transfer complete. update occurs falling edge LDAC. This facility useful simultaneous update multi-DAC systems. Note that LDAC input must taken back high again before next data transfer initiated.
SYNC RESET COUNTER/ DECODER GATING SIGNAL GATED SCLK INPUT SHIFT REGISTER BITS)
SCLK
SDIN
AUTO-UPDATE CIRCUITRY LATCH BITS) LDAC
Figure Simplified Loading Structure
SCLK
SDIN
DB15 DON'T CARE DB14 DON'T CARE DB13 DON'T CARE DB12 DON'T CARE
DB11
SYNC
LDAC
Figure Timing Diagram
REV.
AD7233-Typical Performance Graphs
0.50
OUTPUT WITH DECOUPLING DECOUPLING DECOUPLING
0.40
PSRR
OUTPUT WITH
LINEARITY LSBs
+15V
DECOUPLING
0.30
+15V WITH 100mV SIGNAL
0.20
0.10
OUTPUT WITH FREQUENCY 100k
10.5
/VSS Volts
FREQUENCY
100k
POWER SUPPLY DECOUPLING CAPACITORS 10µF 0.1µF.
Linearity Power Supply Voltage
Power Supply Rejection Ratio Frequency
Noise Spectral Density Frequency
APPLYING AD7233 Bipolar Configuration
Table AD7233 Bipolar Code Table
AD7233 provides output voltage range from without external components. This configuration shown Figure data format complement. output code table shown Table offset binary coding required, then this done inverting software before data loaded AD7233.
+12V +15V
Input Data Word XXXX 0111 1111 1111 XXXX 0000 0000 0001 XXXX 0000 0000 0000 XXXX 1111 1111 1111 XXXX 1000 0000 0001 XXXX 1000 0000 0000
Don't Care Note: V/2048
Analog Output, VOUT (2047/2048) (1/2048) (1/2048) (2047/2048) (2048/2048)
AD7233
VOUT 12-BIT
-12V -15V
Figure Circuit Configuration
Power Supply Decoupling
achieve optimum performance when using AD7233, lines should each decoupled using capacitors. very noisy environments recommended that capacitors connected parallel with capacitors.
REV.
AD7233
MICROPROCESSOR INTERFACING
Microprocessor interfacing AD7233 serial which uses standard protocol compatible with processors microcontrollers. communications channel requires three-wire interface consisting clock signal, data signal synchronization signal. AD7233 requires 16-bit data word with data valid falling edge SCLK. interfaces, update done automatically when data clocked done under control LDAC. Figures show AD7233 configured interfacing number popular processors microcontrollers.
AD7233-ADSP-2101/ADSP-2102 Interface
LDAC
DSP56000 AD7233*
ADDITIONAL PINS OMITTED CLARITY SCLK SDIN SYNC
Figure shows serial interface between AD7233 ADSP-2101/ADSP-2102 processor. ADSP-2101/ ADSP-2102 contains serial ports, either port used interface. data transfer initiated going low. Data from ADSP-2101/ADSP-2102 clocked into AD7233 falling edge SCLK. When data transfer complete taken high. interface shown updated using external timer which generates LDAC pulse. This could also done using control decoded address line from processor. Alternatively, LDAC input could hardwired low, this case automatic update mode selected whereby update takes place automatically 16th falling edge SCLK.
TIMER
Figure AD7233 DSP56000 Interface
AD7233-87C51 Interface
serial interface between AD7233 87C51 microcontroller shown Figure 87C51 drives SCLK AD7233 while drives serial data line part. SYNC signal derived from port line P3.3. 87C51 provides SBUF register first serial data stream. Therefore, user will have ensure that data SBUF register arranged correctly that don't care bits first transmitted AD7233 last sent word loaded AD7233. When data transmitted part, P3.3 taken low. Data valid falling edge TXD. 87C51 transmits serial data 8-bit bytes with only eight falling clock edges occurring transmit cycle. load data AD7233, P3.3 kept after first eight bits transferred second byte data then transferred serially AD7233. When second serial transfer complete, P3.3 line taken high. Figure shows LDAC input AD7233 hardwired low. result, latch analog output will updated sixteenth falling edge after SYNC signal gone low. Alternatively, scheme used previous interfaces, whereby LDAC input driven from timer, used.
LDAC
ADSP-2101/ ADSP-2102*
SCLK ADDITIONAL PINS OMITTED CLARITY
AD7233*
SYNC SCLK SDIN
Figure AD7233 ADSP-2101/ADSP-2102 Interface
AD7233-DSP56000 Interface
LDAC
serial interface between AD7233 DSP56000 shown Figure DSP56000 configured Normal Mode Asynchronous operation with Gated Clock. also 16-bit word with outputs control internally generated DSP56000 applied AD7233 SCLK input. Data from DSP56000 valid falling edge SCK. output provides framing pulse valid data. This line must inverted before being applied SYNC input AD7233. LDAC input AD7233 connected update latch takes place automatically 16th falling edge SCLK. external timer could also used previous interface external update required.
87C51*
P3.3
AD7233*
SYNC
SCLK SDIN
ADDITIONAL PINS OMITTED CLARITY
Figure AD7233 87C51 Interface
REV.
AD7233
AD7233-68HC11 Interface
Figure shows serial interface between AD7233 68HC11 microcontroller. 68HC11 drives SCLK AD7233 while MOSI output drives serial data line. SYNC signal derived from port line (PC7 shown). correct operation this interface, 68HC11 should configured such that CPOL CPHA When data transmitted part, taken low. When 68HC11 configured like this, data MOSI valid falling edge SCK. 68HC11 transmits serial data 8-bit bytes with only eight falling clock edges occurring transmit cycle. load data AD7233, kept after first eight bits transferred second byte data then transferred serially AD7233. When second serial transfer complete, line taken high. Figure shows LDAC input AD7233 hardwired low. result, latch analog output will updated sixteenth falling edge after respective SYNC signal gone low. Alternatively, scheme used previous interfaces, whereby LDAC input driven from timer, used.
LDAC
68HC11*
AD7233*
SYNC
MOSI
SCLK SDIN
ADDITIONAL PINS OMITTED CLARITY
Figure AD7233 68HC11 Interface
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
Plastic (N-8) Package
0.280 (7.11) 0.240 (6.10)
0.430 (10.92) 0.348 (8.84) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33)
0.325 (8.25) 0.300 (7.62) 0.195 (4.95)
0.150 (3.81)
0.015 (0.381) 0.008 (0.204)
0.100 (2.54 BSC) 0.70 (1.77) 0.045 (1.15)
REV.
PRINTED U.S.A.
0.022 (0.558) 0.014 (0.356)
C1494-10-1/91

LC2MOS 12-Bit Serial Mini-DIP DACPORT AD7233 VOUT 12-BIT LATCH

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