Application Briefs Prescaled Counters FLEX 8000 Devices Parity Ge

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Application Briefs Prescaled Counters FLEX 8000 Devices Parity Ge

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Application Briefs
Prescaled Counters FLEX 8000 Devices Parity Generators FLEX 8000 Devices State Machine Encoding Ripple-Carry Gray Code Counters FLEX 8000 Devices
Application Notes
Configuring FLEX 8000 Devices Designing with FLEX 8000 Devices Configuring Multiple FLEX 8000 Devices IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices Applications Altera Devices Metastability Altera Devices Designing with 9000 Devices APacket Scheduler FLEX 8000 Devices Implementing CRCCs Altera Devices Using Programmable Logic Gate Array Designs Guidelines Handling J-Lead, Devices Implementing Filters FLEX Devices Evaluating Power Altera Devices High-Speed Board Designs Understanding FLEX 8000 Timing Understanding 9000 Timing Understanding 5000 Classic Timing Selecting Sockets Altera Devices Reflow Soldering Guidelines Surface-Mount Devices Highly Optimized Convolvers FLEX Devices Binary Numbering Systems Implementing with On-Chip FLEX Devices
Altera Corporation
In-System Programming Times Devices Implementing pci_a Master/Target FLEX Devices Using Language Embedded Processor SameFrame Pin-Out Designs FineLine Packages Understanding FLEX Timing Understanding FLEX 6000 Timing Understanding 7000 Timing In-System Programmability Devices Performance Measurements Typical Applications Comparing Performance High-Density PLDs Comparing Performance Common Megafunctions Comparing Performance Dual-Port Memory Functions
In-System Programmability Guidelines Improving Performance FLEX Devices with Synplify Software Improving Performance FLEX Devices with Leonardo Spectrum Software Designing with 2.5-V Devices Using Altera Devices Multiple Voltage Systems Using 3070 Tester In-System Programming Gate Counting Methodology APEX Devices Embedded Programming using 8051 Byte-Code Integrating Product-Term Logic APEX Devices Plastic Package Reliability Testing Designing with FineLine Packages Using ClockLock ClockBoost Features APEX Devices Configuring APEX 20K, FLEX FLEX 6000 Devices Using Selectable Standards Altera Devices Scripting with Quartus Software Implementing High-Speed Search Applications with APEX Using Timing Analysis Quartus Software
Brochures
APEX Devices Brochure MAX+PLUS Brochure Quartus Brochure
Altera Corporation
Customer Applications
Altera Delivers Speed GigaNet AProtocol Engine Customer Application Bailey Controls Uses Megafunctions Solve Challenge Customer Application FLEX 8000 Devices "Grab" Vitana's Fancy Customer Application
Catalogs
Intellectual Property Catalog Quick Reference Guide
Data Sheets
a16450 Universal Asynchronous Receiver/Transmitter Data Sheet a6402 Universal Asynchronous Receiver/Transmitter Data Sheet a6850 Asynchronous Communications Interface Adapter Data Sheet a8237 Programmable Controller Data Sheet a8251 Programmable Communications Interface Data Sheet a8255 Programmable Peripheral Interface Adapter Data Sheet a8259 Programmable Interrupt Controller Data Sheet Altera Device Package Information Data Sheet Altera Programming Hardware Data Sheet APEX Programmable Logic Device Family Data Sheet BitBlaster Serial Download Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet Classic EPLD Family Data Sheet Configuration Elements Data Sheet Configuration Devices APEX FLEX Devices Data Sheet MegaCore Function Parameterized Generator/Checker Data Sheet Fast Fourier Transform Data Sheet FLEX Embedded Programmable Logic Family Data Sheet FLEX 10KE Embedded Programmable Logic Family Data Sheet FLEX Prototype Board Data Sheet FLEX 10KE Development Board Data Sheet FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 6000 Programmable Logic Device Family Data Sheet MasterBlaster Serial/USB Communications Data Sheet
Altera Corporation
9000 Programmable Logic Device Family Data Sheet 7000 Programmable Logic Device Family Data Sheet 7000A Programmable Logic Device Family Data Sheet 7000B Programmable Logic Device Family Data Sheet 3000A Programmable Logic Device Family Data Sheet MAX+PLUS Programmable Logic Development System Software Data Sheet Operating Requirements Altera Devices Data Sheet Master/Target MegaCore Function with Data Sheet pci_b Master/Target MegaCore Function Data Sheet pcit1 Target MegaCore Function Data Sheet Carrier Development Socket Data Sheet Quartus Programmable Logic Development System Software Data Sheet RGB2YCrCb YCrCb2RGB Color Space Converters Data Sheet SignalTap Embedded Logic Analyzer Megafunction Data Sheet
Functional Specifications
Filters fp_add_sub Floating-Point Adder/Subtractor fp_mult Floating-Point Multiplier round Data Word Rounder saturate Data Word Saturator fft_on_chip Fast Fourier Transform
General Information
Abbreviations About this CD-ROM BASELINE E+MAX Installation Instructions Software Support E+MAX Overview In-Circuit Test Vendor Support Glossary Contact Altera Introduction Altera 1999 Data Book) Byte-Code Compiler Version README File
Altera Corporation
Byte-Code Player Version README File Compiler Player Installation Instructions Player Version 2.12 README File Programming Test Language Specification Legal Notice MAX+PLUS BASELINE Overview MAX+PLUS Version READ.ME File Ordering Information Programming Hardware Manufacturers Sales Offices, Distributors Representatives Saving Board Space with 7000S 7000A TQFP Packages Technical Support from Altera Applications Third-Party Programmer Support Programming Test Language
Product Information Bulletins
CPLDs FPGAs Comparing High-Capacity Programmable Logic Benefits Embedded FLEX Devices Implementing Logic with Embedded Array FLEX Devices Design Tools 100,000 Gate Programmable Logic Devices Digital Signal Processing FLEX Devices Advantages ISP-Based PLDs over Traditional PLDs Concurrent Programming through JTAG Interface Devices Programming Test Language Overview
Selector Guides
Component Selector Guide Development Tools Selector Guide Megafunctions Selector Guide
Solution Briefs
High-Speed Adaptive Filter Megafunction Biquad Filter Megafunction Complex Multiplier/Mixer Megafunction Numerically Controlled Oscillator Megafunction
Altera Corporation
Target Megafunction ADPCM Megafunction Discrete Cosine Transform Megafunctions Digital Modulator Megafunction Linear Feedback Shift Register Megafunction Fast Fourier Transform MegaCore Function Speedbridge Megafunction Convolutional Interleaver Megafunction Early/Late Gate Synchronizer Megafunction Binary Pattern Correlator Megafunction EC210 Master/Target Megafunction Master/Target MegaCore Function a8259 Programmable Interrupt Controller MegaCore Function Megafunction Microperipheral MegaCore Library Function Controller Megafunction Target Interface Megafunction Master/Target Interface Megafunction RGB2YCrCb YCrCb2RGB Color Space Converter MegaCore Functions Host Controller Megafunction MegaCore Function Parameterized Generator/Checker Telephony Tone Generation Megafunction Viterbi Decoder Megafunction Deframer Megafunction IEEE 1394-Compatible LLC-I Megafunction 64-Bit Target Megafunction SDRAM Controller Megafunction Master Interface Megafunction Slave Interface Megafunction Compiler MegaCore Function Interleaver/Deinterleaver MegaCore Function 64-Bit Master/Target MegaCore Function FLEX Development System-on-a-Programmable Chip (SOPC) Development Board
Altera Corporation
Technical Briefs
FLEX Devices Alternatives ASSPs ASICs Using FLEX Devices Coprocessors Implementing Multipliers FLEX EABs Implementing Multirate Filters FLEX Devices Implementing 100,000-Gate Gate Array Design EPF10K100 Device Advantages Using OpenCore Evaluation Feature FLEX pci_a: Complete Solution Advantages ISP-Based CPLDs Internal Tri-State Emulation Authorization Codes Advantages FLEX Devices Versus Lucent ORCA Devices Programming Methods Ordering Codes Evaluating 7000S Device Utilization Fitting 7000S Power Consumption Timing-Driven Compilation Improvements MAX+PLUS Version FLEX 10KA-1 Devices: Fastest High-Density Devices Available Using Synopsys Design Compiler FPGA Compiler Synthesize Designs MAX+PLUS Software Advantages MAX+PLUS Fitting Power Measurements: FLEX 10KA XC4000 Devices Using Synopsys FPGA Express Software Synthesize Designs MAX+PLUS Software Using MAX+PLUS Software with Exemplar Logic Leonardo Software Using Synplicity Synplify Software Synthesize Designs MAX+PLUS Software Importing Synthesized Files from Tools into MAX+PLUS Software Place Route Passing Hierarchical Timing Constraints from Synopsys Tools MAX+PLUS Version Generating Post-Route Files MAX+PLUS Software Third-Party Verification Tools Advantages Quartus Internet Integration Increasing Performance Using ATOM Netlist Files Quartus Software Feature Comparison with Xilinx Alliance 2.1i Quartus Revision Control Software Support
Altera Corporation
Using APEX 20KE Fast Search Applications Power Consumption Comparison: APEX Virtex Devices In-Circuit Test Support with 7000 Devices Hierarchical Design Methodology with Quartus Software Advantages APEX PLLs Over Virtex DLLs Comparison: APEX 20KE Virtex-E Devices 7000AE Performance Comparison Programming Time Comparison: 7000AE XC9500XL Devices
User Guides Software Manuals
Compiler MegaCore Function User Guide MAX+PLUS Getting Started Manual pci_b pcit1 MegaCore Function User Guide pci_c MegaCore Function User Guide MegaCore Function User Guide Quartus Installation Licensing Quartus Installation Licensing UNIX Workstations Quartus SignalTap User's Guide Quartus Tutorial Reed-Solomon Compiler MegaCore Function User Guide Reed-Solomon MegaCore Function User Guide Symbol Interleaver/De-Interleaver MegaCore Function User Guide
White Papers
ATF1500AS Analysis Report White Paper
Altera Corporation

Application Briefs Prescaled Counters FLEX 8000 Devices Parity Ge

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