Programmable Logic Development Software SignalTap User's Guide
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Quartus
Programmable Logic Development Software
SignalTap User's Guide
Altera Corporation Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
Quartus SignalTap User's Guide Version 1999.10 Revision November 1999
P25-04733-01
Altera Altera logo registered trademarks Altera Corporation United States other countries. AMPP, APEX, ByteBlasterMV, EP20K100, MasterBlaster, Quartus Quartus logo, SignalTap, System-on-aProgrammable-Chip trademarks and/or service marks Altera Corporation United States other countries. Product design elements mnemonics used Altera Corporation protected copyright and/or trademark laws. Altera Corporation acknowledges trademarks other organizations their respective products services mentioned this document. including following: Windows Windows trademarks Microsoft Corporation. Altera reserves right make changes, without notice, devices device specifications identified this document. Altera advises customers obtain latest version device specifications verify, before placing orders, that information being relied upon customer current. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty. Testing other quality control techniques used extent Altera deems such testing necessary support this warranty. Unless mandated government requirements, specific testing parameters each device necessarily performed. absence written agreement contrary, Altera assumes liability Altera applications assistance, customer's product design, infringement patents copyrights third parties arising from semiconductor devices described herein. does Altera warrant represent patent right, copyright, other intellectual property right Altera covering relating combination, machine, process which such semiconductor devices might used. Altera products authorized critical components life support devices systems without express written approval president Altera Corporation. used herein: Life support devices systems devices systems that intended surgical implant into body support sustain life, whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness. Products mentioned this document covered more following U.S. patents: 5,915,017; 5,909,450; 5,909,375; 5,909,126; 5,905,675; 5,904,524; 5,900,743; 5,898,628; 5,898,318; 5,894,228; 5,893,088; 5,892,683; 5,883,526; 5,880,725; 5,880,597; 5,880,596; 5,878,250; 5,875,112; 5,873,113; 5,872,529; 5,872,463; 5,870,410; 5,869,980; 5,869,979; 5,861,760; 5,859,544; 5,859,542; 5,850,365; 5,850,152; 5,850,151; 5,848,005; 5,847,617; 5,845,385; 5,844,854; RE35,977; 5,838,628; 5,838,584; 5,835,998; 5,834,849; 5,828,229; 5,825,197; 5,821,787: 5,821,773; 5,821,771; 5,815,726; 5,815,024; 5,815,003; 5,812,479; 5,812,450; 5,809,281; 5,809,034; 5,805,516; 5,802,540; 5,801,541; 5,796,267; 5,793,246; 5,790,469; 5,787,009; 5,771,264; 5,768,562; 5,768,372; 5,767,734; 5,764,583; 5,764,569; 5,764,080; 5,764,079; 5,761,099; 5,760,624; 5,757,207; 5,757,070; 5,744,991; 5,744,383; 5,740,110; 5,732,020; 5,729,495; 5,717,901; 5,705,939; 5,699,020; 5,699,312; 5,696,455; 5,693,540; 5,694,058; 5,691,653; 5,689,195; 5,668,771; 5,680,061; 5,672,985; 5,670,895; 5,659,717; 5,650,734; 5,649,163; 5,642,262; 5,642,082; 5,633,830; 5,631,576; 5,621,312; 5,614,840; 5,612,642; 5,608,337; 5,606,276; 5,606,266; 5,604,453; 5,598,109; 5,598,108; 5,592,106; 5,592,102; 5,590,305; 5,583,749; 5,581,501; 5,574,893; 5,572,717; 5,572,148; 5,572,067; 5,570,040; 5,567,177; 5,565,793; 5,563,592; 5,561,757; 5,557,217; 5,555,214; 5,550,842; 5,550,782; 5,548,552; 5,548,228; 5,543,732; 5,543,730; 5,541,530; 5,537,295; 5,537,057; 5,525,917; 5,525,827; 5,523,706; 5,523,247; 5,517,186; 5,498,975; 5,495,182; 5,493,526; 5,493,519; 5,490,266; 5,488,586; 5,487,143; 5,486,775; 5,485,103; 5,485,102; 5,483,178; 5,477,474; 5,473,266; 5,463,328, 5,444,394; 5,438,295; 5,436,575; 5,436,574; 5,434,514; 5,432,467; 5,414,312; 5,399,922; 5,384,499; 5,376,844; 5,371,422; 5,369,314; 5,359,243; 5,359,242; 5,353,248; 5,352,940; 5,309,046; 5,350,954; 5,349,255; 5,341,308; 5,341,048; 5,341,044; 5,329,487; 5,317,210; 5,315,172; 5,301,416; 5,294,975; 5,285,153; 5,280,203; 5,274,581; 5,272,368; 5,268,598; 5,266,037; 5,260,611; 5,260,610; 5,258,668; 5,247,478; 5,247,477; 5,243,233; 5,241,224; 5,237,219; 5,220,533; 5,220,214; 5,200,920; 5,187,392; 5,166,604; 5,162,680; 5,144,167; 5,138,576; 5,128,565; 5,121,006; 5,111,423; 5,097,208; 5,091,661; 5,066,873; 5,045,772; 4,969,121; 4,930,107; 4,930,098; 4,930,097; 4,912,342; 4,903,223; 4,899,070; 4,899,067; 4,871,930; 4,864,161; 4,831,573; 4,785,423; 4,774,421; 4,713,792; 4,677,318; 4,617,479; 4,609,986; 4,020,469; certain foreign patents. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Copyright 1999 Altera Corporation. rights reserved.
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Quartus SignalTap User's Guide
Contents
Introduction Quartus SignalTap Embedded Logic Analyzer Overview.1 Configuring Embedded Logic Analyzer Megafunction.2 Embedded Logic Analyzer Megafunction Debug Port Trigger Output Mode Logic Element Usage.5 Embedded System Block Usage.5 Embedded Logic Analyzer Sample Rate.6 Compilation Requirements MasterBlaster Communications Cable.7 ByteBlasterMV Parallel Port Download Cable Using Embedded Logic Analyzer Embedded Logic Analyzer Setup Creating, Opening Closing Embedded Logic Analyzer File Saving, Copying Renaming Embedded Logic Analyzer File Setting Embedded Logic Analyzer Preferences.16 Assigning Signals Embedded Logic Analyzer File.17 Deleting Signals from Embedded Logic Analyzer File.17 Selecting Acquisition Clock Signal Specifying Sample Buffer Depth. Triggering Embedded Logic Analyzer Setting Trigger Positions Trigger Pattern.21 Defining Trigger Pattern.21 Setting Trigger Input Output Signals Setting Trigger Input.22 Setting Trigger Output.23 Setting Debug Port.24 Compiling Embedded Logic Analyzer Megafunction Downloading Design Running Embedded Logic Analyzer Auto Stop Viewing Waveforms.29 Enabling Disabling Embedded Logic Analyzer Megafunction.
Quartus SignalTap User's Guide
Communications Hardware. Running Embedded Logic Analyzer Demo Mode Selecting Communications Cable Selecting MasterBlaster Baud Rate Selecting MasterBlaster Voltage Contacting Altera Technical Support. Product Information. Revision History Index
Introduction
SignalTapEmbedded Logic Analyzer megafunction, which provided with Quartussoftware used with APEX20K programmable logic devices (PLDs), allows analyze verify MasterBlasterand ByteBlasterMVcommunications cables provide analysis support, allowing transfer signal data Quartus software. Using intuitive Quartus interface, select signals, triggering events, configure memory, display waveforms. also data retrieved Embedded Logic Analyzer debug verify your design. This manual explains Embedded Logic Analyzer megafunction, gives detailed, step-by-step procedures Embedded Logic Analyzer.
Quartus SignalTap Embedded Logic Analyzer Overview
Quartus SignalTap Embedded Logic Analyzer powerful tool that lets capture signals from internal nodes while device running system, which gives non-intrusive access signals from internal device nodes. optimize SignalTap Embedded Logic Analyzer megafunction various tasks. Embedded Logic Analyzer megafunction works within Quartus software design development, debugging, verification. assign internal nodes capture using Quartus Node Finder. Once Embedded Logic Analyzer megafunction configured, compile download with rest device design MasterBlaster ByteBlasterMV communications cable. make triggering changes Embedded Logic Analyzer without recompiling your device design. Quartus software displays data acquired Embedded Logic Analyzer waveforms.
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Configuring Embedded Logic Analyzer Megafunction
Embedded Logic Analyzer megafunction parameterized, which means customize particular analysis task. Different methods capturing signals allow configure device resources maximum performance. Embedded Logic Analyzer megafunction provides three methods capturing signals, which combination:
Embedded Logic Analyzer Debugging port Trigger output
Embedded Logic Analyzer Megafunction
Embedded Logic Analyzer megafunction configuration, acquisition data saved internal device RAM, then streamed off-chip IEEE Std. 1149.1 Joint Test Action Group (JTAG) port. This configuration requires greatest number memory resources fewest number pins. Figure shows Embedded Logic Analyzer megafunction configuration.
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Figure Embedded Logic Analyzer Megafunction Configuration
From Clock (One Signal) From Input Channels (Multiple Signals)
Embedded Logic Analyzer
from JTAG Port
Memory
APEX Device
Quartus software automatically assigns internal memory acquisition storage when specify that Embedded Logic Analyzer acquisition memory should more Embedded System Blocks (ESBs). "Embedded System Block Usage" page "Specifying Sample Buffer Depth" page more information.
Debug Port
When device limited, route internal signals unused pins capture external analyzer. debug port configuration conserves ESBs expense pins, useful data-intensive applications which amount saved data exceeds available sample buffer depth. Figure illustrates routing debug port mode.
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Figure Debug Port Configuration
Acquisition Data Pins (Multiple Signals Embedded Logic Analyzer Trigger Trigger (Two Signals) from JTAG Port
Input Channels (Multiple Signals)
Unused Pins
APEX Device
When debug port configuration, Quartus software automatically generates pins signals that selected output debug port. assign pins manually, Quartus Floorplan Editor.
more information, "Setting Debug Port" page
Trigger Output Mode
Embedded Logic Analyzer generates trigger output signal when trigger pattern been recognized. pulse polarity active high active low. Configuring Embedded Logic Analyzer megafunction trigger output mode requires ESBs only pin. Figure
Figure Using Embedded Logic Analyzer Megafunction Event Analyzer
Clock Embedded Logic Analyzer Input Channels (Multiple Signals) APEX Device
Trigger
Unused
from JTAG Port
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more information, "Triggering Embedded Logic Analyzer" page
Logic Element Usage
number input channels assign internal device nodes determines logic element (LE) usage. select number channels; however, Embedded Logic Analyzer parameters rounded nearest power on). example, specify channels, Embedded Logic Analyzer parameterized channels. Table shows usage several channel configurations using EP20K100 device.
Table Logic Element Usage EP20K100 Device
Analyzer Channels Logic Elements Percent Usage 15.4
"Assigning Signals Embedded Logic Analyzer File" page instructions assigning signals.
Embedded System Block Usage
Embedded Logic Analyzer configuration, acquisition data saved device ESBs, then transferred off-chip IEEE Std. 1149.1 JTAG port. number ESBs used this function depends number
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input channels used depth sample buffer. Table shows number ESBs used store values different configurations APEX device. instructions setting sample buffer depth, "Specifying Sample Buffer Depth" page
Table APEX Embedded System Block Usage
Buffer Samples Channels 1,024 2,048
Embedded Logic Analyzer Sample Rate
Embedded Logic Analyzer samples synchronously specified global clock. analyzer samples internal signals rising edge clock. "Selecting Acquisition Clock Signal" page information selecting Embedded Logic Analyzer clock.
Compilation Requirements
Embedded Logic Analyzer megafunction compiled with your APEX project. Configuration changes, such adding channels changing acquisition buffer depth, affect Embedded Logic Analyzer
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parameters require recompile your design. Table lists possible changes Embedded Logic Analyzer indicates whether changes require recompilation.
Table Compilation Requirements Design Changes
Recompilation Required
Design Change Changing trigger pattern. Running stopping logic analyzer. Changing number input signals. Changing Embedded Logic Analyzer clock signal. Changing sample buffer depth. Enabling debug port.
MasterBlaster Communications Cable
MasterBlaster communications cable hardware interface standard UNIX serial port, port (Windows only), used transferring configuration programming data Altera® devices. MasterBlaster cable supports in-system debugging when with Embedded Logic Analyzer APEX devices. Figure
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Figure MasterBlaster Serial/USB Communications Cable
more information MasterBlaster communications cable, MasterBlaster Serial/USB Communications Cable Data Sheet. MasterBlaster cable connects target circuit using 10-pin female plug that connects 10-pin male header printed circuit board (PCB). 10-pin male header rows five pins, which connected device's configuration pins. Table shows assignments MasterBlaster communications cable.
Table Female Plug Names Download Modes (Part
Passive Serial Mode Signal DCLK CONF_DONE nCONFIG Description Clock signal Signal ground Configuration control Power supply Configuration control Signal Description Clock signal Signal ground Data from device Power supply JTAG state machine control JTAG Mode
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Table Female Plug Names Download Modes (Part
Passive Serial Mode Signal nSTATUS Description Reference voltage output driver Configuration status connect Data device Signal ground Signal Description Reference voltage output driver JTAG Mode
connect connect Data device Signal ground
DATAO
Figures show female male connector dimensions.
Figure 10-Pin Female Plug Header Dimensions (Inches)
0.425 Typ.
Color Strip
0.250 Typ.
0.100 0.700 Typ.
0.025
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Figure 10-Pin Male Header Dimensions (Inches)
View
0.100
Side View
0.100 0.025
0.235
ByteBlasterMV Parallel Port Download Cable
ByteBlasterMV parallel port download cable hardware interface standard parallel port used transferring configuration programming data Altera devices. ByteBlasterMV cable also supports in-system debugging when with Embedded Logic Analyzer APEX devices. ByteBlasterMV cable 25-pin male header that connects parallel port, 10-pin female plug that connects circuit board. more information ByteBlasterMV parallel port download cable, ByteBlasterMV Parallel Port Download Cable Data Sheet.
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Using Embedded Logic Analyzer
Quartus SignalTap Embedded Logic Analyzer user interface Embedded Logic Analyzer controls integrated into Quartus software provide access trigger setup, sample depth selection, controls. Figure shows Embedded Logic Analyzer window Quartus software.
Figure Embedded Logic Analyzer User Interface Quartus Software
Preferences Hardware Download Controls Trigger Position Sample Depth
Trigger Input
Trigger Output
Embedded Logic Analyzer captures stores data Embedded Logic Analyzer File (.ela). This data displayed Embedded Logic Analyzer Waveform window. Figure
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Figure Data Displayed Waveforms Quartus Software
Quartus status displays bottom Quartus window have turned Display status General Options dialog (Tools menu). Embedded Logic Analyzer icons status indicate your stage Embedded Logic Analyzer debug process. When point icon status bar, brief description that item's function appears next Figure
Figure Embedded Logic Analyzer Icons Quartus Status
Design Target
Compile Program
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following Embedded Logic Analyzer icons available from Quartus status bar: Icon: Name: Design Description: When open project contains design file, Design icon changes from dimmed normal indicate that there open design file. After make design changes Embedded Logic Analyzer configuration changes that require recompilation, Compile arrow status highlighted yellow indicate that must compile. After compile design, icon changes from dimmed normal indicate that have generated programming file. After compile design, Program arrow highlighted yellow indicate that must download design. After have downloaded design, Target icon changes from dimmed normal indicate that Embedded Logic Analyzer ready run.
Compile
Program
Target
Embedded Logic Analyzer Setup
Embedded Logic Analyzer, follow these steps:
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Create open Embedded Logic Analyzer File (.ela). necessary, save File. necessary, Embedded Logic Analyzer preferences. Assign signals Embedded Logic Analyzer. Select Embedded Logic Analyzer clock signal. Configure sample buffer depth. trigger pattern. trigger position. Configure communications cable. necessary, compile SignalTap Embedded Logic Analyzer megafunction into your file. Download Embedded Logic Analyzer.
Quartus SignalTap User's Guide
Embedded Logic Analyzer.
Creating, Opening Closing Embedded Logic Analyzer File
order modify Embedded Logic Analyzer, must first create, name, save Embedded Logic Analyzer File (.ela) open existing File. Before opening creating File, must create open project. "Creating Project" Quartus Help more information.
create File, follow these steps: Choose (File menu). Click Standard Compile Mode toolbar. dialog box, click Other Files tab. Select Embedded Logic Analyzer File. Click File name box, type file name. Click Save.
open existing File, follow these steps: Choose Open (File menu). Click Open Standard Compile Mode toolbar. Open dialog box, select Waveform/Vector Files from Files Type list.
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Files box, select desired file. File name box, type desired file name.
Click Open.
close open File, follow these steps: Select desired File. Choose Close (File menu).
Saving, Copying Renaming Embedded Logic Analyzer File
Once create edit File, save changes existing File copy rename file. save changes existing file: Click Save button Standard Compile Mode toolbar. Choose Save (File menu).
save untitled File copy rename previously saved file under name, follow these steps: Choose Save (File menu). Save dialog box, select desired target directory from Save list, necessary. Files list, specify file name, File name box, type file name. Save type list, select Embedded Logic Analyzer File (.ela), necessary.
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Turn file current project. Click Save.
Setting Embedded Logic Analyzer Preferences
preferences Embedded Logic Analyzer using Preferences list. Enabling these preferences allows Embedded Logic Analyzer prompt compile Embedded Logic Analyzer, and/or download SRAM Object Files (.sof) Chain Description Files (.cdf) when necessary. enable these preferences, Embedded Logic Analyzer performs next step without prompting first. default settings, options Preferences list enabled. Embedded Logic Analyzer preferences, follow these steps: open Embedded Logic Analyzer window, choose Auxiliary Windows Embedded Logic Analyzer (View menu). Click Preferences button Embedded Logic Analyzer toolbar.
Preferences list, select preferences that want enable. Figure
Figure Embedded Logic Analyzer Preferences
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Assigning Signals Embedded Logic Analyzer File
Embedded Logic Analyzer captures signals from internal device node (including pins). However, before capturing signals, must first assign internal nodes input channels. number signals assign determines amount device resources used. "Logic Element Usage" page "Embedded System Block Usage" page more information resource usage. assign internal node signal File, follow these steps: Open create File. Choose Node (Insert menu). Insert Node dialog box, click Node Finder. Nodes Found list, select more nodes groups nodes after performing sorted search. Click button copy selected nodes groups Selected Nodes list. Click Click Insert Node dialog box.
"Copying Node Names Embedded Logic Analyzer File with Node Finder" Quartus Help more information using Node Finder.
Deleting Signals from Embedded Logic Analyzer File
delete signals from File, follow these steps: Open File.
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Select node group wish remove. Choose Delete (Edit menu). Choose Delete (right button pop-up menu).
Selecting Acquisition Clock Signal
must select designate signal Embedded Logic Analyzer acquisition clock. input channels sampled rising edge acquisition clock signal. Altera recommends using global clock signal acquisition signal. select acquisition clock signal, follow these steps: Open File. signal want acquisition clock signal File, choose Insert Node (Insert menu). Embedded Logic Analyzer window, select appropriate acquisition clock signal. Press right mouse button signal name choose Clock (right button pop-up menu).
"Copying Node Names Embedded Logic Analyzer File with Node Finder" Quartus Help more information using Node Finder.
Specifying Sample Buffer Depth
must specify number ESBs that Embedded Logic Analyzer uses saving acquisition data. number ESBs used depends depth sample buffer number internal nodes assigned Embedded Logic Analyzer. configure sample buffer depth, follow these steps:
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Open File. Click Sample Depth button Embedded Logic Analyzer toolbar.
Select desired sample depth. Figure
Figure Configuring Sample Buffer Depth
Using ESBs acquisition memory decreases number ESBs available other applications.
Triggering Embedded Logic Analyzer
When Embedded Logic Analyzer, SignalTap Embedded Logic Analyzer megafunction continually samples input signals places data circular buffer with samples replacing samples. Figure When trigger pattern recognized, Embedded Logic Analyzer stops immediately, continues sampling refill entire buffer, continues sampling indefinitely, depending trigger position setting.
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Figure Trigger Sampling
Trigger Post-Trigger Pre-Trigger
Sample Memory Buffer
Setting Trigger Positions
Trigger Position controls offer four choices: Icon: Name: Pre-trigger Center Post-trigger Continuous trigger Description: Captures signals immediately before triggering (92% pre-trigger, post-trigger). Captures signals before after triggering (half pre-trigger half post-trigger). Captures signals that occur immediately after triggering (12% pre-trigger, post-trigger). Captures signals indefinitely (which useful when using Trigger Out).
trigger position, follow these steps: open Embedded Logic Analyzer window, choose Auxiliary Windows Embedded Logic Analyzer (View menu). Click desired Trigger position button Embedded Logic Analyzer toolbar.
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Trigger Pattern
Embedded Logic Analyzer uses single pattern recognizer triggering, which referred "trigger pattern." logic condition (High, Low, Rising Edge, Falling Edge, Don't Care) each input signal specify trigger pattern. Embedded Logic Analyzer triggered when input signals match trigger pattern. trigger pattern appears column Embedded Logic Analyzer window.
Defining Trigger Pattern
define triggering pattern, must assign logic condition each input channel. default, bits trigger pattern "Don't Care" setting, masking them from trigger recognition. also bits High, Low, Rising Edge, Falling Edge, Either Edge. Table describes these conditions.
Table Triggering Pattern Logic Conditions
Condition Don't Care High Falling Edge Rising Edge Either Edge Description Signal condition doesn't matter. Signal must high trigger occur. Signal must trigger occur. Signal must falling trigger occur. Signal must rising trigger occur. Signal must either rising falling trigger occur.
define trigger pattern, follow these steps: open Embedded Logic Analyzer window, choose Auxiliary Windows Embedded Logic Analyzer (View menu). Pattern column, select desired signal. Choose trigger condition from right button pop-up menu. Figure
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Figure Defining Trigger Pattern
Setting Trigger Input Output Signals
trigger input trigger output signals synchronize Embedded Logic Analyzer with external equipment, such oscilloscope system-level logic analyzer, allowing synchronize capture internal external events.
Setting Trigger Input
trigger Embedded Logic Analyzer. Trigger recognize High, Low, Rising Edge, Falling Edge, Either Edge, Don't Care condition that pin. When assign signal condition trigger input signal, global ~trig_in generated design. must assign this signal device compile. change signal condition (High, Low, after assign node without requiring recompilation. enable trigger input signal, perform following steps: open Embedded Logic Analyzer window, choose Auxiliary Windows Embedded Logic Analyzer (View menu).
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Click Trigger Input button Embedded Logic Analyzer toolbar.
Trigger list, select desired Trigger condition (such Low, Falling, Rising, on). Figure
Figure Enabling Trigger Input
Setting Trigger Output
spare trigger output signal indicate that trigger pattern occurred. also specify polarity output pulse high low. When enable trigger output signal, global node ~trig_out generated design. must assign this signal device compile. then change output pulse settings without recompiling. enable trigger output signal, perform following steps: open Embedded Logic Analyzer window, choose Auxiliary Windows Embedded Logic Analyzer (View menu). Click Trigger Output button Embedded Logic Analyzer toolbar.
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Trigger list, select appropriate polarity (Active High Active Low). Figure
Figure Selecting Trigger Output
Setting Debug Port
Using debug port setting, route Embedded Logic Analyzer input signal spare capture external equipment. When assign Embedded Logic Analyzer input signal debug port, Embedded Logic Analyzer automatically generates device design. debug port named "~out[n]," where number representing order which debug port occurs signal list. default, input signals routed debug port. must assign debug port nodes device pins, compile device after adding deleting debug port signals. remove signal from debug port, follow these steps: open Embedded Logic Analyzer window, choose Auxiliary Windows Embedded Logic Analyzer (View menu). Select signal name. Choose Debug Port (right button pop-up menu). Figure
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Figure Setting Debug Port
Compiling Embedded Logic Analyzer Megafunction
must compile project design entity before running Embedded Logic Analyzer, have already done made changes that require recompilation. "Compilation Requirements" page information whether your changes require recompilation. compile Embedded Logic Analyzer megafunction into your design, follow these steps: open Embedded Logic Analyzer window, choose Auxiliary Windows Embedded Logic Analyzer (View menu). Click Embedded Logic Analyzer toolbar.
Click dialog that prompts, design changed. wish recompile before running logic analyzer?
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Downloading Design
download design APEX device JTAG chain consisting single device multiple Altera devices. download design, follow these steps: open Embedded Logic Analyzer window, choose Auxiliary Windows Embedded Logic Analyzer (View menu). Select communications cable used download. "Selecting Communications Cable" page Click Download button Embedded Logic Analyzer toolbar.
JTAG chain contains single Altera device, Download list, select Program with current CDF/SOF. JTAG chain contains multiple Altera devices, Download list, select appropriate Chain Description File (.cdf), then select desired SRAM Object File (.sof).
Running Embedded Logic Analyzer
Embedded Logic Analyzer controls consist Run, Auto Run, Stop. These controls allow start stop analysis. Figure shows controls.
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Figure SignalTap Embedded Logic Analyzer Controls
Stop
AutoRun
During compilation, Embedded Logic Analyzer controls dimmed indicate that they available.
When press button, Embedded Logic Analyzer samples specified input signals rising edge selected clock. "Selecting Acquisition Clock Signal" page more details. trigger position "Continuous," Embedded Logic Analyzer samples until press Stop button. "Setting Trigger Positions" page more details. ESBs save acquisition data, Embedded Logic Analyzer captures stores samples input signals until triggering occurs trigger position satisfied. Embedded Logic Analyzer then transfers acquisition data from device ESBs host computer communications cable. acquisition data stored File displayed Waveform window. Embedded Logic Analyzer then returns idle state. choose device ESBs save acquisition data, Embedded Logic Analyzer stops sampling returns idle when triggered. Running Embedded Logic Analyzer does affect rest device logic. Embedded Logic Analyzer, follow these steps: open Embedded Logic Analyzer window, choose Auxiliary Windows Embedded Logic Analyzer (View menu).
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Click Embedded Logic Analyzer toolbar.
Auto
Auto control continuous display updates from Embedded Logic Analyzer. Auto works like except that, instead remaining idle after acquisition, Auto automatically restarts. disable Auto Run, must stop Embedded Logic Analyzer manually. "Stop," next. enable Auto Run, follow these steps: open Embedded Logic Analyzer window, choose Auxiliary Windows Embedded Logic Analyzer (View menu). Click Auto Embedded Logic Analyzer toolbar.
Embedded Logic Analyzer halted while uploading acquisition data Quartus software. Signal activity that occurs during this time captured.
Stop
stop Embedded Logic Analyzer manually using Stop button. data saved internal memory transferred immediately host computer displayed File. Embedded Logic Analyzer returns idle state. stop Embedded Logic Analyzer, follow these steps: open Embedded Logic Analyzer window, choose Auxiliary Windows Embedded Logic Analyzer (View menu).
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Click Stop Embedded Logic Analyzer toolbar.
Viewing Waveforms
Acquisition data displayed Embedded Logic Analyzer Waveform window. "Waveform Editor" section Quartus Help more information.
Enabling Disabling Embedded Logic Analyzer Megafunction
When enabled, Embedded Logic Analyzer megafunction compiled into design provides access signals from internal nodes. When disabled, removed from design during next compilation. default, Embedded Logic Analyzer megafunction enabled design. disable Embedded Logic Analyzer megafunction time closing Embedded Logic Analyzer window.
disable Embedded Logic Analyzer megafunction, follow these steps: Close Embedded Logic Analyzer window. When asked, Embedded Logic Analyzer been disabled. wish recompile remove from design?, click Yes.
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Communications Hardware
Quartus software communicates with APEX devices MasterBlaster ByteBlasterMV communications cables. download designs, control Embedded Logic Analyzer, retrieve acquisition data. Hardware button Embedded Logic Analyzer toolbar allows specify settings required communication.
Running Embedded Logic Analyzer Demo Mode
Running Embedded Logic Analyzer Demo mode causes random data appear your File. This random data allows view demonstrate Embedded Logic Analyzer works without using target board communications cable. Embedded Logic Analyzer Demo mode, follow these steps: open Embedded Logic Analyzer window, choose Auxiliary Windows Embedded Logic Analyzer (View menu). Click Hardware button Embedded Logic Analyzer toolbar.
Hardware list, select Demo. Figure
Figure Running Demo Mode
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Click button Embedded Logic Analyzer toolbar.
View data Embedded Logic Analyzer Waveform window.
Selecting Communications Cable
download data using MasterBlaster ByteBlasterMV communications cable. select communications cable, follow these steps: Select communications cable Programmer window. Refer "Changing Hardware Setup" Quartus Help information selecting communications cable Programmer. open Embedded Logic Analyzer window, choose Auxiliary Windows Embedded Logic Analyzer (View menu). Click Hardware button Embedded Logic Analyzer toolbar.
Hardware list, select desired communications cable then select appropriate communications port from submenu. using Windows also listed available communications port. Figure
Figure Selecting Communications Cable Communications Port
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Selecting MasterBlaster Baud Rate
default, MasterBlaster communications cable connects 115k bps. baud rate manually need lower speed. baud rate manually, follow these steps: open Embedded Logic Analyzer window, choose Auxiliary Windows Embedded Logic Analyzer (View menu). Select MasterBlaster cable communications cable. "Selecting Communications Cable" page Click Hardware button Embedded Logic Analyzer toolbar.
Hardware list, select Baud, then select desired baud rate. Figure
Figure Selecting Baud Rate
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Quartus SignalTap User's Guide
Selecting MasterBlaster Voltage
MasterBlaster communications cable supports wide range device voltages. voltage automatically correspond reference voltage JTAG cable (see Table page manually specific voltage. voltage overrides manual setting. want voltage manually, leave unconnected.
device voltage, follow these steps: open Embedded Logic Analyzer window, choose Auxiliary Windows Embedded Logic Analyzer (View menu). Select MasterBlaster cable communications cable. "Selecting Communications Cable" page more information. Click Hardware button Embedded Logic Analyzer toolbar.
Hardware list, select (External), then select appropriate voltage select Vio. Figure
Figure Setting Voltage Level Manually
Altera Corporation
Quartus SignalTap User's Guide
Contacting Altera
have additional questions about Altera products, contact Altera technical support product information.
Technical Support
need technical support, call Altera Applications Department Monday through Friday. Tel: Fax: (800) 800-EPLD (408) 544-7000 (408) 544-6401 (6:00 a.m. 6:00 p.m. Pacific Time) (7:30 a.m. 5:30 p.m. Pacific Time)
also e-mail Altera Applications Department support@altera.com. addition, visit Atlas online solutions database, which available from Altera site http://www.altera.com. additional technical support Quartus software, refer Quartus support site choosing Altera Quartus Home Page (Help menu), pointing your browser https://websupport.altera.com. This site provides information register your software obtain license information, provides other support information.
Product Information
need latest Altera product information literature, Altera site, which available hours day, seven days week. "Contacting Altera" Quartus Help complete information Altera technical support services.
Altera Corporation
Quartus SignalTap User's Guide
Revision History
information contained Quartus SignalTap User's Guide version 1999.10 revision supersedes information published previous versions. pages references assigning pins Trigger Input, Trigger Output, Debug Port lists have been deleted.
Altera Corporation
Index
acquisition data acquisition memory Altera, contacting Embedded Logic Analyzer File (.ela) assigning internal nodes assigning logic conditions assigning signals copying creating saving Embedded System Block configuring sampling triggering
buffer ByteBlasterMV
communications cable configuration pins contacting Altera
MasterBlaster
preferences debug port download modes
controls
File assigning internal nodes assigning logic conditions assigning signals copying creating saving Embedded Logic Analyzer configuration enabling disabling general description preferences running sample buffer depth sample rate stopping triggering
sample buffer depth sample rate sampling input signals signals assigning specifying trigger input specifying trigger output SignalTap Embedded Logic Analyzer Megafunction configuration enabling disabling general description system debugging
Quartus SignalTap User's Guide
technical support trigger input signal output signal patterns positions sampling signals
support
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