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Quartus

Programmable Logic Development Software

Quartus
Programmable Logic Development Software
Altera Corporation 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com
P25-04733-01
Printed on Recycled Paper.
Contents
Introduction ................................................... 1 Quartus SignalTap Embedded Logic Analyzer Overview...........1 Configuring the Embedded Logic Analyzer Megafunction..........2 Embedded Logic Analyzer Megafunction ....................2 Debug Port .............................................3 Trigger Output Mode ..................................... 4 Logic Element Usage.....................................5 Embedded System Block Usage............................5 Embedded Logic Analyzer Sample Rate......................6 Compilation Requirements ................................6 MasterBlaster Communications Cable..........................7 ByteBlasterMV Parallel Port Download Cable ................... 10 Using the Embedded Logic Analyzer ..............................11 Embedded Logic Analyzer Setup .............................13 Creating, Opening & Closing an Embedded Logic Analyzer File ...........................................14 Saving, Copying & Renaming an Embedded Logic Analyzer File .................................................. 15 Setting the Embedded Logic Analyzer Preferences............16 Assigning Signals to the Embedded Logic Analyzer File........17 Deleting Signals from the Embedded Logic Analyzer File......17 Selecting an Acquisition Clock Signal ......................18 Specifying the Sample Buffer Depth........................ 18 Triggering the Embedded Logic Analyzer ...................19 Setting Trigger Positions ..............................20 Trigger Pattern......................................21 Defining the Trigger Pattern...........................21 Setting the Trigger Input & Output Signals ..................22 Setting the Trigger Input..............................22 Setting the Trigger Output............................23 Setting the Debug Port...................................24 Compiling the Embedded Logic Analyzer Megafunction ..........25 Downloading a Design ......................................26 Running the Embedded Logic Analyzer ........................26 Run .................................................. 27 Auto Run .............................................. 28 Stop .................................................. 28 Viewing Waveforms........................................29 Enabling and Disabling the Embedded Logic Analyzer Megafunction............................................. 29
Communications Hardware................................. 30 Running the Embedded Logic Analyzer in Demo Mode ....... 30 Selecting a Communications Cable ........................ 31 Selecting the MasterBlaster Baud Rate ..................... 32 Selecting the MasterBlaster I / O Voltage .................... 33 Contacting Altera .............................................. 34 Technical Support...................................... 34 Product Information.................................... 34 Revision History ........................................ 35 Index ........................................................ 36
Introduction
The SignalTap Embedded Logic Analyzer megafunction, which is provided with the Quartus software and is used with APEX 20K programmable logic devices (PLDs), allows you to analyze and verify System-on-a-Programmable-Chip designs. The MasterBlaster and ByteBlasterMV communications cables provide analysis support, allowing you to transfer signal data to the Quartus software. Using the intuitive Quartus interface, you can select signals, set up triggering events, configure memory, and display waveforms. You can also use data retrieved by the Embedded Logic Analyzer to debug and verify your design. This manual explains how to use the Embedded Logic Analyzer megafunction, and gives detailed, step-by-step procedures on how to set up and run the Embedded Logic Analyzer.
Quartus SignalTap Embedded Logic Analyzer Overview
The Quartus SignalTap Embedded Logic Analyzer is a powerful tool that lets you capture signals from internal PLD nodes while the device is running in system, which gives you non-intrusive access to signals from internal device nodes. You can optimize the SignalTap Embedded Logic Analyzer megafunction for various tasks. The Embedded Logic Analyzer megafunction works within the Quartus software for design development, debugging, and verification. You can assign internal nodes for capture using the Quartus Node Finder. Once the Embedded Logic Analyzer megafunction is configured, you can compile and download it with the rest of the device design via the MasterBlaster or ByteBlasterMV communications cable. You can make triggering changes to the Embedded Logic Analyzer without recompiling your device design. The Quartus software displays data acquired by the Embedded Logic Analyzer as waveforms.
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Configuring the Embedded Logic Analyzer Megafunction
The Embedded Logic Analyzer megafunction is parameterized, which means you can customize it to fit a particular analysis task. Different methods for capturing signals allow you to configure device resources for maximum performance. The Embedded Logic Analyzer megafunction provides three methods for capturing signals, which you can use in any combination:
Embedded Logic Analyzer Debugging port Trigger output
Embedded Logic Analyzer Megafunction
In the Embedded Logic Analyzer megafunction configuration, acquisition data is saved to internal device RAM, then streamed off-chip via the IEEE Std. 1149.1 Joint Test Action Group (JTAG) port. This configuration requires the greatest number of memory resources but the fewest number of I / O pins. Figure 1 shows the Embedded Logic Analyzer megafunction configuration.
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Figure 1. Embedded Logic Analyzer Megafunction Configuration
From Clock (One Signal) From Input Channels (Multiple Signals)
Embedded Logic Analyzer
To and from JTAG Port
Memory
APEX 20K Device
The Quartus software automatically assigns internal memory for acquisition storage when you specify that the Embedded Logic Analyzer acquisition memory should use one or more Embedded System Blocks (ESBs). See "Embedded System Block Usage" on page 5 and "Specifying the Sample Buffer Depth" on page 18 for more information.
Debug Port
When device RAM is limited, you can route internal signals to unused I / O pins for capture by an external analyzer. The debug port configuration conserves ESBs at the expense of I / O pins, and is useful for data-intensive applications in which the amount of saved data exceeds the available sample buffer depth. Figure 2 illustrates the I / O pin routing for the debug port mode.
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Figure 2. Debug Port Configuration
Acquisition Data to I / O Pins (Multiple Signals Embedded Logic Analyzer Trigger In and Trigger Out (Two Signals) To and from JTAG Port
Input Channels (Multiple Signals)
Unused I / O Pins
APEX 20K Device
When you use the debug port configuration, the Quartus software automatically generates pins for signals that are selected for output via the debug port. To assign pins manually, use the Quartus Floorplan Editor.
For more information, see "Setting the Debug Port" on page 24.
Trigger Output Mode
The Embedded Logic Analyzer generates a trigger output signal when the trigger pattern has been recognized. You can set the pulse polarity to active high or active low. Configuring the Embedded Logic Analyzer megafunction for trigger output mode requires no ESBs and only one I / O pin. See Figure 3.
Figure 3. Using the Embedded Logic Analyzer Megafunction as an Event Analyzer
Clock Embedded Logic Analyzer Input Channels (Multiple Signals) APEX 20K Device
Trigger Out
Unused I / O Pin
To and from JTAG Port
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For more information, see "Triggering the Embedded Logic Analyzer" on page 19.
Logic Element Usage
The number of input channels you assign to internal device nodes determines logic element (LE) usage. You can select any number of channels however, the Embedded Logic Analyzer parameters are rounded up to the nearest power of two (1, 2, 4, 8, 16, 32, and so on). For example, if you specify 14 channels, the Embedded Logic Analyzer is parameterized for 16 channels. Table 1 shows the LE usage for several channel configurations using an EP20K100 device.
Table 1. Logic Element Usage in an EP20K100 Device
Analyzer Channels 1 2 4 8 16 32 64 Logic Elements 136 144 160 192 256 384 640 Percent LE Usage 3.3 3.5 3.8 4.6 6.2 9.2 15.4
See "Assigning Signals to the Embedded Logic Analyzer File" on page 17 for instructions on assigning signals.
Embedded System Block Usage
In the Embedded Logic Analyzer configuration, acquisition data is saved to device ESBs, and then is transferred off-chip via the IEEE Std. 1149.1 JTAG port. The number of ESBs used for this function depends on the number of
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input channels used and the depth of the sample buffer. Table 2 shows the number of ESBs used to store the values for different configurations for an APEX 20K device. f For instructions on setting the sample buffer depth, go to "Specifying the Sample Buffer Depth" on page 18.
Table 2. APEX 20K Embedded System Block Usage
Embedded Logic Analyzer Sample Rate
The Embedded Logic Analyzer samples synchronously to a specified global clock. The analyzer samples internal signals on the rising edge of the clock. f Go to "Selecting an Acquisition Clock Signal" on page 18 for information on selecting the Embedded Logic Analyzer clock.
Compilation Requirements
The Embedded Logic Analyzer megafunction is compiled with your APEX 20K project. Configuration changes, such as adding channels or changing the acquisition buffer depth, affect the Embedded Logic Analyzer
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parameters and may require you to recompile your design. Table 3 lists possible changes to the Embedded Logic Analyzer and indicates whether the changes require recompilation.
Table 3. Compilation Requirements for Design Changes
Recompilation Required No No Yes Yes Yes Yes
Design Change Changing the trigger pattern. Running or stopping the logic analyzer. Changing the number of input signals. Changing the Embedded Logic Analyzer clock signal. Changing the sample buffer depth. Enabling the debug port.
MasterBlaster Communications Cable
The MasterBlaster communications cable is a hardware interface to a standard UNIX or PC serial port, or to a PC USB port (Windows 98 only), and is used for transferring configuration and programming data to Altera® devices. The MasterBlaster cable supports in-system debugging when you use it with the Embedded Logic Analyzer and APEX 20K devices. See Figure 4.
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Figure 4. MasterBlaster Serial / USB Communications Cable
Table 4. Female Plug Pin Names & Download Modes (Part 1 of 2)
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Table 4. Female Plug Pin Names & Download Modes (Part 2 of 2)
Passive Serial Mode Pin Signal 6 7 8 9 10 VIO nSTATUS Description Reference voltage for output driver Configuration status No connect Data to device Signal ground TDI GND VIO Signal Description Reference voltage for output driver JTAG Mode
No connect No connect Data to device Signal ground
DATAO GND
Figures 5 and 6 show the female and male connector dimensions.
Figure 5. 10-Pin Female Plug Header Dimensions (Inches)
0.425 Typ.
Color Strip
0.100 Sq. 0.700 Typ.
0.025 Sq.
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Figure 6. 10-Pin Male Header Dimensions (Inches)
Top View
Side View
0.100 0.025 Sq.
ByteBlasterMV Parallel Port Download Cable
The ByteBlasterMV parallel port download cable is a hardware interface to a standard PC parallel port and is used for transferring configuration and programming data to Altera devices. The ByteBlasterMV cable also supports in-system debugging when you use it with the Embedded Logic Analyzer and APEX 20K devices. The ByteBlasterMV cable has a 25-pin male header that connects to the PC parallel port, and a 10-pin female plug that connects to the circuit board. f For more information on the ByteBlasterMV parallel port download cable, see the ByteBlasterMV Parallel Port Download Cable Data Sheet.
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Using the Embedded Logic Analyzer
The Quartus SignalTap Embedded Logic Analyzer user interface and the Embedded Logic Analyzer controls are integrated into the Quartus software and provide access to trigger setup, sample depth selection, and run controls. Figure 7 shows the Embedded Logic Analyzer window in the Quartus software.
Figure 7. Embedded Logic Analyzer User Interface in the Quartus Software
Preferences Hardware Download Run Controls Trigger Position Sample Depth
Trigger Input
Trigger Output
The Embedded Logic Analyzer captures and stores data in an Embedded Logic Analyzer File (.ela). This data is displayed in the Embedded Logic Analyzer Waveform window. See Figure 8.
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Figure 8. Data Displayed as Waveforms by the Quartus Software
Figure 9. Embedded Logic Analyzer Icons on the Quartus Status Bar
Design SOF Target
Compile Program
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The following Embedded Logic Analyzer icons are available from the Quartus status bar: Icon: Name: Design Description: When you open a project and it contains a design file, the Design icon changes from dimmed to normal to indicate that there is an open design file. After you make design changes or Embedded Logic Analyzer configuration changes that require recompilation, the Compile arrow on the status bar is highlighted in yellow to indicate that you must compile. After you compile the design, the SOF icon changes from dimmed to normal to indicate that you have generated a programming file. After you compile the design, the Program arrow is highlighted in yellow to indicate that you must download the design. After you have downloaded the design, the Target icon changes from dimmed to normal to indicate that the Embedded Logic Analyzer is ready to run.
Compile
Program
Target
Embedded Logic Analyzer Setup
To set up the Embedded Logic Analyzer, follow these steps: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.
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Create or open an Embedded Logic Analyzer File (.ela). If necessary, save the ELA File. If necessary, set the Embedded Logic Analyzer preferences. Assign signals to the Embedded Logic Analyzer. Select an Embedded Logic Analyzer clock signal. Configure the sample buffer depth. Set the trigger pattern. Set the trigger position. Configure the communications cable. If necessary, compile the SignalTap Embedded Logic Analyzer megafunction into your file. Download the Embedded Logic Analyzer.
Run the Embedded Logic Analyzer.
Creating, Opening & Closing an Embedded Logic Analyzer File
In order to set up and modify the Embedded Logic Analyzer, you must first create, name, and save an Embedded Logic Analyzer File (.ela) or open an existing ELA File. 1 Before opening or creating an ELA File, you must create or open a project. See "Creating a New Project" in Quartus Help for more information.
To create an ELA File, follow these steps: 1. Choose New (File menu). or Click New on the Standard Compile Mode toolbar. 2. 3. 4. 5. 6. In the New dialog box, click the Other Files tab. Select Embedded Logic Analyzer File. Click OK. In the File name box, type a file name. Click Save.
To open an existing ELA File, follow these steps: 1. Choose Open (File menu). or Click Open on the Standard Compile Mode toolbar. 2. In the Open dialog box, select Waveform / Vector Files from the Files of Type list.
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In the Files box, select the desired file. or In the File name box, type the desired file name.
Click Open.
To close an open ELA File, follow these steps: 1. 2. Select the desired ELA File. Choose Close (File menu).
Saving, Copying & Renaming an Embedded Logic Analyzer File
Once you create and edit an ELA File, you can save any changes to the existing ELA File or you can copy and rename the file. To save changes to an existing file: v or v Click the Save button on the Standard Compile Mode toolbar. Choose Save (File menu).
To save an untitled ELA File or to copy and rename a previously saved file under a new name, follow these steps: 1. 2. Choose Save As (File menu). In the Save As dialog box, select the desired target directory from the Save in list, if necessary. In the Files list, specify a file name, or in the File name box, type a file name. In the Save as type list, select Embedded Logic Analyzer File (.ela), if necessary.
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Turn on Add file to current project. Click Save.
Setting the Embedded Logic Analyzer Preferences
In the Preferences list, select the preferences that you want to enable. See Figure 10.
Figure 10. Embedded Logic Analyzer Preferences
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Assigning Signals to the Embedded Logic Analyzer File
The Embedded Logic Analyzer captures signals from any internal device node (including I / O pins). However, before capturing signals, you must first assign internal nodes to the input channels. The number of signals you assign determines the amount of device resources used. f Go to "Logic Element Usage" on page 5 and "Embedded System Block Usage" on page 5 for more information on resource usage. To assign an internal node signal to the ELA File, follow these steps: 1. 2. 3. 4. Open or create an ELA File. Choose Node or Bus (Insert menu). In the Insert Node dialog box, click Node Finder. In the Nodes Found list, select one or more nodes or groups of nodes after performing a sorted search. Click the button to copy the selected nodes or groups to the Selected Nodes list. Click OK. Click OK in the Insert Node or Bus dialog box.
Go to "Copying Node Names to an Embedded Logic Analyzer File with the Node Finder" in Quartus Help for more information on using the Node Finder.
Deleting Signals from the Embedded Logic Analyzer File
To delete signals from the ELA File, follow these steps: 1. Open an ELA File.
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Select the node or group you wish to remove. Choose Delete (Edit menu). or Choose Delete (right button pop-up menu).
Selecting an Acquisition Clock Signal
You must select and designate one signal as the Embedded Logic Analyzer acquisition clock. All input channels are sampled on the rising edge of the acquisition clock signal. Altera recommends using a global clock signal as the acquisition signal. To select the acquisition clock signal, follow these steps: 1. 2. Open an ELA File. To add the signal you want to use as the acquisition clock signal to the ELA File, choose Insert Node or Bus (Insert menu). In the Embedded Logic Analyzer window, select the appropriate acquisition clock signal. Press the right mouse button on the signal name and choose Clock (right button pop-up menu).
Go to "Copying Node Names to an Embedded Logic Analyzer File with the Node Finder" in Quartus Help for more information on using the Node Finder.
Specifying the Sample Buffer Depth
You must specify the number of ESBs that the Embedded Logic Analyzer uses for saving acquisition data. The number of ESBs used depends on the depth of the sample buffer and the number of internal nodes assigned to the Embedded Logic Analyzer. To configure the sample buffer depth, follow these steps:
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Open an ELA File. Click the Sample Depth button on the Embedded Logic Analyzer toolbar.
Select the desired sample depth. See Figure 11.
Figure 11. Configuring the Sample Buffer Depth
Using ESBs for acquisition memory decreases the number of ESBs available for other applications.
Triggering the Embedded Logic Analyzer
When you run the Embedded Logic Analyzer, the SignalTap Embedded Logic Analyzer megafunction continually samples input signals and places data in a circular buffer with new samples replacing old samples. See Figure 12. When the trigger pattern is recognized, the Embedded Logic Analyzer stops immediately, or continues sampling to refill the entire buffer, or continues sampling indefinitely, depending on the trigger position setting.
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Figure 12. Trigger Sampling
Trigger Post-Trigger 1 0 1 1 0 1 Pre-Trigger 0 1
Sample Memory Buffer
Setting Trigger Positions
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Trigger Pattern
Defining the Trigger Pattern
Table 5. Triggering Pattern Logic Conditions
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Figure 13. Defining the Trigger Pattern
Setting the Trigger Input & Output Signals
You can use trigger input and trigger output signals to synchronize the Embedded Logic Analyzer with external equipment, such as an oscilloscope or system-level logic analyzer, allowing you to synchronize the capture of internal and external events.
Setting the Trigger Input
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Click the Trigger Input button on the Embedded Logic Analyzer toolbar.
In the Trigger In list, select the desired Trigger In condition (such as Low, Falling, Rising, and so on). See Figure 14.
Figure 14. Enabling Trigger Input
Setting the Trigger Output
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In the Trigger Out list, select the appropriate polarity (Active High or Active Low). See Figure 15.
Figure 15. Selecting Trigger Output
Setting the Debug Port
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Figure 16. Setting the Debug Port
Compiling the Embedded Logic Analyzer Megafunction
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Downloading a Design
If the JTAG chain contains a single Altera device, in the Download list, select Program with current CDF / SOF. or If the JTAG chain contains multiple Altera devices, in the Download list, select the appropriate Chain Description File (.cdf), and then select the desired SRAM Object File (.sof).
Running the Embedded Logic Analyzer
The Embedded Logic Analyzer run controls consist of Run, Auto Run, and Stop. These controls allow you to start and stop the analysis. Figure 17 shows the run controls.
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Figure 17. SignalTap Embedded Logic Analyzer Run Controls
Run Stop
AutoRun
During compilation, the Embedded Logic Analyzer run controls are dimmed to indicate that they are not available.
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Click Run on the Embedded Logic Analyzer toolbar.
Auto Run
The Embedded Logic Analyzer is halted while uploading acquisition data to the Quartus software. Signal activity that occurs during this time is not captured.
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Click Stop on the Embedded Logic Analyzer toolbar.
Viewing Waveforms
Acquisition data is displayed in the Embedded Logic Analyzer Waveform window. See the "Waveform Editor" section in Quartus Help for more information.
Enabling and Disabling the Embedded Logic Analyzer Megafunction
When enabled, the Embedded Logic Analyzer megafunction is compiled into the design and provides access to signals from internal nodes. When disabled, it is removed from the design during the next compilation. 1 By default, the Embedded Logic Analyzer megafunction is enabled in the design. You can disable the Embedded Logic Analyzer megafunction at any time by closing the Embedded Logic Analyzer window.
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Communications Hardware
The Quartus software communicates with APEX devices via the MasterBlaster and ByteBlasterMV communications cables. You can download designs, control the Embedded Logic Analyzer, and retrieve acquisition data. The Hardware button on the Embedded Logic Analyzer toolbar allows you to specify settings required for communication.
Running the Embedded Logic Analyzer in Demo Mode
In the Hardware list, select Demo. See Figure 18.
Figure 18. Running Demo Mode
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Click the Run button on the Embedded Logic Analyzer toolbar.
View the data in the Embedded Logic Analyzer Waveform window.
Selecting a Communications Cable
In the Hardware list, select the desired communications cable and then select the appropriate communications port from the submenu. If you are using Windows 98, USB is also listed as an available communications port. See Figure 19.
Figure 19. Selecting a Communications Cable & Communications Port
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Selecting the MasterBlaster Baud Rate
In the Hardware list, select Baud, and then select the desired baud rate. See Figure 20.
Figure 20. Selecting a Baud Rate
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Selecting the MasterBlaster I / O Voltage
The MasterBlaster communications cable supports a wide range of device I / O voltages. The I / O voltage can be set automatically to correspond to the reference voltage on the VIO pin of the JTAG cable (see Table 4 on page 8) or you can set it manually to a specific voltage. 1 The voltage on the VIO pin overrides any manual setting. If you want to set the I / O voltage manually, leave the VIO pin unconnected.
In the Hardware list, select Vio (External), and then select the appropriate I / O voltage or select Vio. See Figure 21.
Figure 21. Setting the I / O Voltage Level Manually
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Contacting Altera
If you have any additional questions about Altera products, contact Altera for technical support and product information.
Technical Support
If you need technical support, call or fax the Altera Applications Department Monday through Friday. Tel: Fax: (800) 800-EPLD (408) 544-7000 (408) 544-6401 (6:00 a.m. to 6:00 p.m. Pacific Time) (7:30 a.m. to 5:30 p.m. Pacific Time)
Product Information
If you need the latest Altera product information or literature, use the Altera web site, which is available 24 hours a day, seven days a week. Go to "Contacting Altera" in Quartus Help for complete information on Altera technical support services.
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Revision History
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Index
acquisition data 29 acquisition memory 19 Altera, contacting 34 Embedded Logic Analyzer File (.ela) assigning internal nodes 17 assigning logic conditions 21 assigning signals 17 copying 15 creating 14 saving 15 Embedded System Block configuring 26 sampling 27 triggering 27
buffer 18 ByteBlasterMV 10, 31
communications cable 7, 10, 31 configuration pins 8 contacting Altera 34
MasterBlaster 7, 8
preferences 16 debug port 3, 24 download modes 8
run controls 27
ELA File assigning internal nodes 17 assigning logic conditions 21 assigning signals 17 copying 15 creating 14 saving 15 Embedded Logic Analyzer configuration 2 enabling and disabling 29 general description 1 preferences 16 running 26 , 27 sample buffer depth 18 sample rate 6 stopping 28 triggering 19
sample buffer depth 18 sample rate 6 sampling input signals 19, 20 signals assigning 17 specifying trigger input 22 specifying trigger output 23 SignalTap Embedded Logic Analyzer Megafunction configuration 2 enabling and disabling 29 general description 1 system debugging 7, 10
technical support 34 trigger input signal 22 output signal 23 patterns 21 positions 20 sampling signals 20
web support 34