Target Applications: PCI-based systems Family: APEX20K, FLEX® Ord

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Target Applications: PCI-based systems Family: APEX20K, FLEX® Ord

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64-Bit Master/Target MegaCore Function
Target Applications:
PCI-based systems Family: APEX20K, FLEX® Ordering Code: PLSM-PCI/C Vendor:
Features
Innovation Drive Jose, 95134 http://www.altera.com Tel. (408) 544-7000
flexible, general-purpose 64-bit peripheral component interconnect (PCI) interface that customized specific peripheral requirements 66-MHz compliant APEX FLEX 10KE devices Fully compliant with Special Interest Group (PCI SIG) Local Specification, Revision timing functional requirements Dramatically shortens design cycles Verified using industry-proven Phoenix Technologies test bench Hardware tested using following hardware software (see "Compliance Summary" pci_c MegaCore Function User Guide details) E2928A Analyzer Exerciser E2920 Computer Verification Tools, series Altera's FLEX 10KE development board Optimized APEX FLEX architectures No-risk OpenCorefeature allows designers instantiate simulate designs Quartusand MAX+PLUS® software prior purchase master features: Infinite zero-wait state cycles read/write operation Mbytes second) Initiates 64-bit addressing, using dual-address cycles (DACs) Initiates 64-bit 32-bit transactions Dynamically negotiates 64-bit transactions automatically multiplexes data local 64-bit data Functions host bridge applications target features: Zero-wait state read/write Mbytes second) Capabilities list pointer support base address registers (BARs) with adjustable memory size type Expansion support Abnormal target terminations Supports 64-bit addressing Automatically responds 64-bit transactions Local-side interrupt request Configuration registers: Parameterized registers: device vendor class code, revision BAR0 through BAR5, subsystem subsystem vendor maximum latency, minimum grant, capabilities list pointer, expansion Non-parameterized registers: command, status, header type, latency timer, cache line size, interrupt pin, interrupt line
General Description
pci_c MegaCorefunction (ordering code: PLSM-PCI/C) hardware-tested, high-performance, flexible implementation 64-bit master/target interface. This function handles complex protocol stringent timing requirements internally, allowing designers focus their engineering efforts value-added custom development, significantly reducing time-to-market. guarantee robustness strict compliance, hardware tested using E2928A Exerciser Analyzer. E2928A Exerciser Analyzer simulates random behavior randomizing transactions with variable parameters.
Altera Corporation
A-SB-044-01
64-Bit Master/Target MegaCore Function
Optimized Altera® APEX FLEX 10KE devices, pci_c function supports configuration, I/O, memory transactions. With high density APEX FLEX devices, designers have ample resources custom local logic after implementing interface. pci_c function either 33-MHz 66-MHz clock speeds, thus achieving Mbytes second throughput 64-bit, 33-MHz system, Mbytes second throughput 64-bit, 66-MHz system. parameterized function, pci_c configuration registers that modified upon instantiation. These features provide scalability, adaptability, efficient silicon implementation. result, same MegaCore function used multiple projects with different requirements. example, pci_c function offers base address registers (BARs) multiple local-side devices. However, some applications require only contiguous memory range. designers choose instantiate only BAR, which reduces logic cell consumption. After designers define parameter values, Quartus MAX+PLUS software automatically efficiently modifies design implements logic. high-end systems that require more than Gbytes memory space, pci_c function also supports 64-bit BAR. Additionally, pci_c function initiate 64-bit addressing using DACs. This solution brief should used conjunction with latest user guide. Users should fairly familiar with standard before using this function. Figure shows pci_c functional block diagram.
Figure pci_c Functional Block Diagram
pci_c rstn idsel Parameterized Configuration Registers cmd_reg[5.0] stat_reg[5.0] cache[7.0]
ad[63.0] cben[7.0]
Address/ Data Buffer Local Master Control
gntn reqn intan framen req64n irdyn trdyn devseln ack64n stopn Master Control
lm_req32n lm_req64n lm_lastn lm_rdyn lm_ackn lm_adr_ackn lm_dxfrn lm_tsr[9.0]
Local Address/ Data/Command/ Byte Enable
l_adi[63.0] l_cbeni[7.0] l_dato[63.0] l_adro[63.0] l_beno[7.0] l_cmdo[3.0] l_ldat_ackn l_hdat_ackn
Target Control lt_rdyn lt_discn lt_abortn lirqn lt_framen lt_ackn lt_dxfrn lt_tsr[11.0]
Local Target Control par64 perrn serrn Parity Checker Generator
Altera Corporation
64-Bit Master/Target MegaCore Function
Table shows commands that initiated responded pci_c MegaCore function.
Table Command Support Summary
cben[3.0] Value
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Note:
memory read multiple memory read line commands treated memory reads. memory write invalidate command treated memory write. local side sees exact command l_cbeni[3.0] with encoding shown Table
Command Cycle
Interrupt acknowledge Special cycle read write Reserved Reserved Memory read Memory write Reserved Reserved Configuration read Configuration write Memory read multiple Dual address cycle Memory read line Memory write invalidate
Master
Ignored Ignored Ignored Ignored Ignored Ignored
Target
Ignored Ignored Ignored Ignored Ignored Ignored
Altera Corporation
64-Bit Master/Target MegaCore Function
Configuration Registers
Table shows defined 64-byte configuration space. registers within this range used identify device, control functions, provide status. shaded areas indicate registers that supported pci_c function.
Table Configuration Registers
Address
Maximum Latency Subsystem Reserved Reserved Minimum Grant Interrupt Interrupt Line BIST Device Status Register Class Code Header Type Latency Timer Base Address Register Base Address Register Base Address Register Base Address Register Base Address Register Base Address Register Card Pointer Subsystem Vendor Capabilities Pointer Expansion Base Address Register
Byte
Vendor Command Register Revision Cache Line Size
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
Copyright 1999 Altera Corporation. Altera, APEX, APEX 20K, FLEX, FLEX 10K, MAX, MAX+PLUS, MAX+PLUS MegaCore, OpenCore, Quartus trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.
Altera Corporation

Target Applications: PCI-based systems Family: APEX20K, FLEX® Ord

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