Programmable Radio Chip Power PRoCLP Features Single Device,
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CYRF69103
Programmable Radio Chip Power
PRoCLP Features
Single Device, Functions 8-bit, Flash based function radio transceiver function single device. Flash-Based Microcontroller Function based 8-bit CPU, optimized Human Interface Devices (HID) applications Bytes SRAM Kbytes Flash memory with EEPROM emulation In-System reprogrammable speed 16-bit free-running timer power wakeup timer 12-bit Programmable Interval Timer with interrupts Watchdog timer Industry-Leading Radio Transceiver Function Operates unlicensed worldwide Industrial, Scientific, Medical (ISM) band (2.4 GHz-2.483 GHz) DSSS data rates Kbps GFSK data rate Mbps receive sensitivity Programmable output power Auto Transaction Sequencer (ATS) Framing Auto Received Signal Strength Indication (RSSI) Automatic Gain Control (AGC) Component Reduction Integrated 1.8V boost converter GPIOs that require external components Operates single crystal Flexible High current drive GPIO pins. Configurable 8-mA 50-mA/pin current sink designated pins Each GPIO supports high-impedance inputs, configurable pull open drain output, CMOS/TTL inputs, CMOS output Maskable interrupts pins Operating voltage from 1.8V 3.6V Operating temperature from 70°C Lead-free 40-lead package Advanced development tools based Cypress's PSoC® tools
PROCLP CYRF69103 Block Diagram
MOSI
47µF 470nF 10µF VBat1 VBat2 VBat3 VCC1 VCC2 VCC3 470nF
VDD_MICRO
VReg
RFbias
Microcontroller Function
P0_2:4,7 P1_0:2,6:7 P2_0:1 P1.5/MOSI P1.4/SCK P1.3/nSS
Radio Function
IRQ/GPIO MISO/GPIO XOUT/GPIO PACTL/GPIO RESV Xtal
12MHz
Cypress Semiconductor Corporation Document 001-07611
Champion Court
Jose, 95134-1709 408-943-2600 Revised January 2007
CYRF69103
Applications
CYRF69103 PRoC targeted following applications: Wireless devices Mice Remote Controls Presenter tools Barcode scanners terminal General purpose wireless applications: Industrial applications Home automation White goods Consumer electronics Toys
radio meets following world-wide regulatory requirements: Europe ETSI 489-1 V1.4.1 ETSI 328-1 V1.3.1 North America Part Japan ARIB STD-T66 Data Transmission Modes radio supports four different data transmission modes: GFSK mode, data transmitted Mbps, without DSSS mode, byte encoded each code symbol transmitted mode, bits encoded each code symbol transmitted mode, single encoded each code symbol transmitted Both 64-chip 32-chip data codes supported. four data transmission modes apply data after Start Packet (SOP). particular, packet length, data sent same mode. Microcontroller Function function 8-bit Flash-programmable microcontroller. instruction been optimized specifically variety other embedded applications. function eight Kbytes Flash user's code bytes stack space user variables. addition, function includes Watchdog timer, vectored interrupt controller, 16-bit Free-Running Timer, 12-bit Programmable Interrupt Timer. microcontroller GPIO pins grouped into multiple ports. With exception four radio function GPIOs, each GPIO port supports high-impedance inputs, configurable pull open drain output, CMOS/TTL inputs CMOS output. pins support programmable drive strength Additionally, each used generate GPIO interrupt microcontroller. Each GPIO port GPIO interrupt vector with exception GPIO Port GPIO Port three dedicated pins that have independent interrupt vectors (P0.2 P0.4). microcontroller features internal oscillator. PRoC includes Watchdog timer, vectored interrupt controller, 12-bit programmable interval timer with configurable 1-ms interrupt 16-bit free-running timer with capture registers. addition, CYRF69103 Power Management Unit (PMU), which allows direct connection device battery voltage range 1.8V 3.6V. conditions battery voltage provide supply voltages required device, supply external devices.
Functional Description
PRoC devices integrated radio microcontroller functions same package provide dual-role single-chip solution. Communication between microcontroller radio radio's interface.
Functional Overview
CYRF69103 complete Radio System-on-Chip device, providing complete system solution with single device discrete components. CYRF69103 designed implement low-cost wireless systems operating worldwide Industrial, Scientific, Medical (ISM) frequency band (2.400 GHz-2.4835 GHz). Radio Function contains 1-Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), interface data transfer device configuration. radio supports discrete channels (regulations limit some these channels certain jurisdictions). DSSS modes baseband performs DSSS spreading/despreading, while GFSK Mode Mb/s GFSK) baseband performs Start Frame (SOF), Frame (EOF) detection CRC16 generation checking. baseband also configured automatically transmit Acknowledge (ACK) handshake packets whenever valid packet received. When receive mode, with packet framing enabled, device always ready receive data transmitted supported rates, except SDR, enabling implementation mixed-rate systems which different devices different data rates. This also enables implementation dynamic data rate systems, which high data rates shorter distances and/or low-moderate interference environment, change lower data rates longer distances and/or high interference environments.
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Backward Compatibility CYRF69103 fully interoperable with main modes other Cypress radios CYWUSB6934 CYRF69103. 62.5-kbps mode supported selecting 32-chip DATA_CODE_ADR codes, mode, disabling SOP, length, CRC16 fields. Similarly, 15.675-kHz
mode supported selecting 64-chip DATA_CODE_ADR codes mode. this way, suitably configured CYRF69103 device transmit data and/or receive data from first generation device.
Pinout
Name P0.4 XTAL P0.3 P0.1 Vbat1 P2.1 Vbat2 RFbias P2.0 RESV P1.0 P1.1 VDD_micro P1.2 P1.3 P1.4 P1.5 MOSI MISO XOUT PACTL P1.6 P1.7 VDD1.8 P0.7 Vbat0 VREG GPIO Reserved. Must connect GPIO GPIO supply connected GPIO Slave Select Clock Radio Function Interrupt output, configure High, Radio GPIO MOSI from microcontroller function radio function 3-wire mode configured Radio GPIO. 4-wire mode sends data function Buffered CLK, PACTL_n Radio GPIO Control external Radio GPIO GPIO 1.8V 3.6V main power supply rail Radio Radio Reset. Connected with 0.47 Must have RST=HIGH event very first time power applied radio otherwise state radio control registers unknown GPIO Regulated logic bypass. Connected 0.47µF Inductor/Diode connection Boost. When Internal being used connect GND. GPIO Connected to1.8V 3.6V main power supply, through 0.047-µF bypass Boost regulator output voltage feedback Individually configured GPIO crystal 2.4V 3.6V supply. Connected (0.047-µF bypass) Individually configured GPIO Individually configured GPIO Connect 1.8V 3.6V power supply, through 47-ohm series/1-µF shunt GPIO. Port Connected to1.8V 3.6V main power supply, through 0.047-µF bypass voltage reference Differential to/from antenna Differential to/from antenna Function/Description
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CYRF69103
Pinout
Name E-pad Function/Description
Pinout Diagram
Figure Pinout 40-pin Lead-Free LY40
PACTL GPIO
VDD_1.8
VREG
P1.7
P0.7
P1.6
VBAT
Corner tabs
P0.4 XTAL P0.3 P0.1 VBAT P2.1 VBAT
E-PAD Bottom Side
XOUT GPIO MISO GPIO
CYRF69103 WirelessUSB
P1.5 MOSI GPIO P1.4 P1.3 P1.2 VREG VDD_Micro P1.1 P1.0
RFBIAS P2.0 RESV
Functional Block Overview
blocks that make PRoC presented here. 2.4-GHz Radio radio transceiver dual conversion architecture optimized power range/robustness. radio employs channel-matched filters achieve high performance presence interference. integrated Power Amplifier (PA) provides transmit power, with output power control range steps. supply current device reduced output power reduced. Table Internal Output Power Step Table Setting Typical Output Power (dBm)
Table Internal Output Power Step Table Setting Frequency Synthesizer Before transmission reception commence, necessary frequency synthesizer settle. settling time varies depending channel; fast channels provided with maximum settling time "fast channels" (<100-µs settling time) every frequency, starting 2400 including 2472 (i.e., 0,3,6,9.69 72). Baseband Framer baseband framer blocks provide DSSS encoding decoding, generation reception CRC16 generation checking, well detection length field. Typical Output Power (dBm)
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Data Transmission Modes Data Rates supports four different data transmission modes: GFSK mode, data transmitted Mbps, without DSSS. mode, bits encoded each DATA_CODE_ADR derived code symbol transmitted. mode, 2-bits encoded each DATA_CODE_ADR derived code symbol transmitted. CYWUSB6934 mode). mode, encoded each DATA_CODE_ADR derived code symbol transmitted. CYWUSB6934 standard modes.) Both 64-chip 32-chip DATA_CODE_ADR codes supported. four data transmission modes apply data after SOP. particular length, data, CRC16 sent same mode. general, lower data rates reduces packet error rate given environment. CYRF69103 supports following data rates: 1000-kbps (GFSK) 250-kbps (32-chip 8DR) 125-kbps (64-chip 8DR) 62.5-kbps (32-chip DDR) 31.25-kbps (64-chip DDR) 15.625-kbps (64-chip SDR) Lower data rates typically provide longer range and/or more robust link. Link Layer Modes CYRF69103 device supports following data packet framing features: Packets begin with 2-symbol Start Packet (SOP) marker. This required GFSK modes, optional mode supported mode; framing disabled then event inferred whenever
successive correlations detected. SOP_CODE_ADR code used different from that used "body" packet, desired different length. must configured same length both sides link. There options detecting packet. enabled, then packet length field enabled. GFSK must enable length field. This first bits after symbol, transmitted payload data rate. length field enabled, Packet (EOP) condition inferred after reception number bytes defined length field, plus bytes CRC16 enabled-see below). alternative using length field infer condition from configurable number successive non-correlations; this option available GFSK mode only recommended when using mode. CRC16 device configured append 16-bit CRC16 each packet. CRC16 uses polynomial with added programmability seed. enabled, receiver will verify calculated CRC16 payload data against received value CRC16 field. starting value CRC16 calculation configurable, CRC16 transmitted calculated using either loaded seed value zero seed; received data CRC16 will checked against both configured zero CRC16 seeds. CRC16 detects following errors: error bits error matter apart, which column, number bits error matter where they are) error burst wide checksum itself Figure shows example packet with SOP, CRC16 lengths fields enabled.
Figure Example Default Packet Format
Preamble 16us Framing Symbol*
Framing Symbol*
Length
Packet length Byte Period
Payload Data
*Note:32 64us
Packet Buffers Radio Configuration Registers Packet data configuration registers accessed through interface. configuration registers directly addressed through address field packet CYWUSB6934). Configuration registers provided allow configuration DSSS codes, data rate, operating mode, interrupt masks, interrupt status, others.
Packet Buffers data transmission reception uses 16-byte packet buffers-one transmission reception. transmit buffer allows complete packet bytes payload data loaded burst transaction, then transmitted with further intervention. Similarly, receive buffer allows entire packet payload data bytes received with firmware intervention required until packet reception complete.
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CYRF69103 supports packet length bytes; interrupts provided allow transmit receive buffers FIFOs. When transmitting packet longer than bytes, load bytes initially, further bytes transmit buffer transmission data creates space buffer. Similarly, when receiving packets longer than bytes, must fetch received data from FIFO periodically during packet reception prevent from overflowing. Auto Transaction Sequencer (ATS) CYRF69103 provides automated support transmission reception acknowledged data packets. When transmitting data packet, device automatically starts crystal synthesizer, enters transmit mode, transmits packet transmit buffer, then automatically switches receive mode waits handshake packet-and then automatically reverts sleep mode idle mode when either packet received, time-out period expires. Similarly, when receiving transaction mode, device waits receive mode valid packet received, then automatically transitions transmit mode, transmits packet, then switches back receive mode await next packet. contents packet buffers affected transmission reception packets. each case, entire packet transaction takes place without need firmware action; transmit data simply needs load data packet transmitted, length, bit. Similarly, when receiving packets transaction mode, firmware simply needs retrieve fully received packet response interrupt request indicating reception packet. Interrupts radio function provides interrupt (IRQ) output, which configurable indicate occurrence various different events. programmed either active high active low, either CMOS open drain output. radio function features three sets interrupts: transmit, receive, system interrupts. These interrupts share single (IRQ), independently enabled/disabled. transmit mode, receive interrupts automatically disabled, receive mode transmit interrupts automatically disabled. However, contents enable registers preserved when switching between transmit receive modes. more than radio interrupt enabled time, necessary read relevant status register determine which event caused assert. Even when given interrupt source disabled, status condition that would otherwise cause interrupt determined reading appropriate status register. therefore possible devices without making polling status register(s) wait event, rather than using pin. Clocks 12-MHz crystal (30-ppm better) directly connected between XTAL without need external capacDocument 001-07611
itors. digital clock function provided, with selectable output frequencies 0.75, 1.5, MHz. This output used clock external microcontroller (MCU) ASIC. This output enabled default, disabled. Below requirements crystal directly connected XTAL GND: Nominal Frequency: Operating Mode: Fundamental Mode Resonance Mode: Parallel Resonant Frequency Initial Stability: Series Resistance: ohms Load Capacitance: Drive Level: µW-100 function features internal oscillator. clock generator provides 12-MHz 24-MHz clocks that remain internal microcontroller. GPIO Interface function features general-purpose (GPIO) pins.The pins grouped into three ports (Port pins Port Port each configured individually while pins Port only configured group. Each GPIO port supports high-impedance inputs, configurable pull open drain output, CMOS/TTL inputs, CMOS output with pins that support programmable drive strength 50-mA sink current. Additionally, each used generate GPIO interrupt microcontroller. Each GPIO port GPIO interrupt vector with exception GPIO Port GPIO Port three dedicated pins that have independent interrupt vectors (P0.1, P0.3-P0.4). Power-On Reset/Low-Voltage Detect power-on reset circuit detects logic when power applied device, resets logic known state, begins executing instructions Flash address 0x0000. When power falls below programmable trip voltage, generates reset configured generate interrupt. There low-voltage detect circuit that detects when drops below programmable trip voltage. configurable generate interrupt inform processor about low-voltage event. share same interrupt. There separate interrupt each. Watchdog timer used ensure firmware never gets stalled infinite loop. Timers free-running 16-bit timer provides interrupt sources: programmable interval timer with 1-µs resolution 1.024-ms outputs. timer used measure duration event under firmware control reading timer start event, then calculating difference between values. Power Management operating voltage device 1.8V 3.6V which applied VBAT pin. device shut down fully static sleep mode writing STATE bits XACT_CFG_ADR register over Page
CYRF69103
interface. device will enter sleep mode within after last positive edge this transaction. Alternatively, device configured automatically enter sleep mode after completing packet transmission reception. When sleep mode, on-chip oscillator stopped, interface remains functional. device will wake from sleep mode automatically when device commanded enter transmit receive mode. When resuming from sleep mode, there short delay while oscillator restarts. device configured assert when oscillator stabilized. output voltage (VREG) Power Management Unit (PMU) configurable several minimum values between 2.4V 2.7V. VREG used provide (average load) external devices. possible disable PMU, provide externally regulated supply voltage device range 2.4V 3.6V. also provides regulated 1.8V supply logic. been designed provide high boost efficiency (74-85% depending input voltage, output voltage load) when using Schottky diode power inductor, eliminating need external boost converter many systems where other components require boosted voltage. However, reasonable efficiencies (69-82% depending input voltage, output voltage load) achieved when using low-cost components such SOT23 diodes 0805 inductors. also provides configurable battery detection function which read over interface. seven thresholds between 1.8V 2.7V selected. interrupt configured assert when voltage VBAT falls below configured threshold. latched event. Battery monitoring disabled when device sleep mode. following three figures show different examples PRoC with without PMU. Figure shows most common circuit making boost battery voltage 2.7v. Figure example circuit used when supply voltage will always above 2.7V. This could three 1.5v battery cells series along with linear regulator, some similar power source. Figure shows example using PRoC with disabled external boost supply power device. This might required when load much greater than average load that PRoC support.
Figure Enabled
VBat 10µF 6.3V 6.3V 0.047µF 0.047µF 0.047µF 0.047µF 0.047µF
0.047µF
VBat2
VBat3
VReg
VCC1
VCC2
VBat1
VDD_MICRO
PRoC
0.1µF
VBat BAT400D
100µF
10µF6.3V
Figure Disabled Linear Regulator
0.047µF
0.047µF 0.047µF
0.047µF 0.047µF 0.047µF 0.047µF 0.047µF
VBat2
VBat3
VReg
VCC1
VCC2
VDD_MICRO
VBat1
PRoC
0.1µF
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VCC3
VCC3
CYRF69103
Figure Disabled External Boost Converter
External DC-DC Boost Converter VBat
10µF 6.3V 6.3V 0.047µF 0.047µF 0.047µF 0.047µF 0.047µF
(Master Slave In), (Serial Clock), (Slave Select). There alternate 4-wire MISO Interface that requires connection external pins. interface controlled configuring Configure Register. (SPICR Addr: 0x3D). 3-Wire Interface radio function receives clock from function pin. MOSI multiplexed with MISO pin. Bidirectional data transfer takes place between function radio function through this multiplexed MOSI pin. When using this mode user firmware should ensure that MOSI function high impedance state, except when actively transmitting data. Firmware must also control direction data flow switch directions between function radio function setting SWAP [Bit Configure Register. asserted prior initiating data transfer between function radio function. function optionally multiplexed with MOSI pin; when this option enabled function available while low. When using this configuration, user firmware should ensure that MOSI function function high-impedance state whenever high. Figure 3-Wire Mode
0.047µF
VBat2
VBat3
VReg
VCC1
VCC2
VDD_MICRO
VBat1
PRoC
0.1µF
VCC3
MOSI
Noise Amplifier (LNA) Received Signal Strength Indication (RSSI) gain receiver controlled directly clearing writing Noise Amplifier (LNA) RX_CFG_ADR register. When cleared, receiver gain reduced approximately allowing accurate reception very strong received signals (for example when operating receiver very close transmitter). additional receiver attenuation added setting Attenuation (ATT) bit; this allows data reception limited devices very short ranges. Disabling enabling recommended unless receiving from device using external RSSI register returns relative signal strength on-channel signal power. When receiving, device configured automatically measure store relative strength signal being received 5-bit value. When enabled, RSSI reading taken read through interface. RSSI reading taken automatically when start packet detected. addition, RSSI reading taken every time previous reading read from RSSI register, allowing background energy level given channel easily measured when RSSI read when signal being received. reading occur fast once every 4-Wire Interface 4-wire communications interface consists MOSI, MISO, SCK, device receives from function pin. Data from function shifted MOSI pin. Data function shifted MISO pin. active must asserted functions communicate. function optionally multiplexed with MOSI pin; when this option enabled function available while low. When using this configuration, user firmware should ensure that MOSI function function high-impedance state whenever high.
Function
P1.5/MOSI
MOSI/MISO multiplexed MOSI
Radio Function
MOSI
P1.4/SCK
P1.3/nSS
Interface
interface between function radio function 3-wire Interface. three pins MOSI Document 001-07611
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Figure 4-Wire Mode
MOSI
helps read write consecutive bytes from contiguous memory locations single burst mode operation. Slave Select asserted then master function reads byte from radio, address incremented byte location, then byte that location read, Slave Select asserted then function reads/writes bytes same register burst mode, register file then reads/writes bytes that register file. interface between radio function dependent internal 12-MHz oscillator radio. Therefore, radio function registers read from written into while radio sleep mode. Voltage References interfaces between function radio have separate voltage reference VIO. CYRF69103 normally VCC. Connects External Devices three wires, MOSI, SCK, also drawn package external pins allow user interface their external devices (such optical sensors others) through SPI. radio function also wires MISO IRQ, which used send data back function send interrupt request function. They also configured GPIO pins.
Function
Radio Function
P1.5/MOSI
MOSI
P1.6/MISO
P1.4/SCK
MISO
P1.3/nSS
This connection external PRoC Chip
Communication Transactions transactions single byte multi-byte. function initiates data transfer through Command/Address byte. following bytes data bytes. transaction format shown Figure specifies direction data transfer. Master reads from slave. Master writes slave.
Figure Transaction Format
Byte Name [5:0] Address Byte [7:0] Data
Architecture
This family microcontrollers based high-performance, 8-bit, Harvard architecture microprocessor. Five registers control primary operation core. These registers affected various instructions, directly accessible through register space user. Table Registers Register Name Register Flags Program Counter Accumulator Stack Pointer Index Register Name CPU_F CPU_PC CPU_A CPU_SP CPU_X
Accumulator Register (CPU_A) general-purpose register that holds results instructions that specify source addressing modes. Index Register (CPU_X) holds offset value that used indexed addressing modes. Typically, this used address block data within data memory space. Stack Pointer Register (CPU_SP) holds address current top-of-stack data memory space. affected PUSH, POP, LCALL, CALL, RETI, instructions, which manage software stack. also affected SWAP instructions. Flag Register (CPU_F) three status bits: Zero Flag [1]; Carry Flag [2]; Supervisory State [3]. Global Interrupt Enable used globally enable disable interrupts. user cannot manipulate Supervisory State status [3]. flags affected arithmetic, logic, shift operations. manner which each flag changed dependent upon instruction being executed (for example, AND, XOR). Table
16-bit Program Counter Register (CPU_PC) allows direct addressing full eight Kbytes program memory space.
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Registers
Flags Register Flags Register only reset with logical instruction. Table Flags Register (CPU_F) [R/W]
Field Read/Write Default Bits Reserved user select between register banks Bank Bank Super Indicates whether executing user code Supervisor Code. (This code cannot accessed directly user.) User Code Supervisor Code Carry indicate whether there been carry previous logical/arithmetic operation Carry Carry Zero indicate whether there been zero result previous logical/arithmetic operation Equal Zero Equal Zero Reserved Super Carry Zero Global
Global Determines whether interrupts enabled disabled Disabled Enabled Note: This register readable with explicit address 0xF7. expr expr must used clear CPU_F bits
Accumulator Register Table Accumulator Register (CPU_A)
Field Read/Write Default
Accumulator [7:0]
Bits Accumulator [7:0] 8-bit data value holds result logical/arithmetic instruction that uses source addressing mode
Index Register Table Register (CPU_X)
Field Read/Write Default [7:0]
Bits [7:0] 8-bit data value holds index instruction that uses indexed addressing mode
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Stack Pointer Register Table Stack Pointer Register (CPU_SP)
Field Read/Write Default
Stack Pointer [7:0]
Bits Stack Pointer [7:0] 8-bit data value holds pointer current top-of-stack
Program Counter High Register Table Program Counter High Register (CPU_PCH)
Field Read/Write Default
Program Counter [15:8]
Bits Program Counter [15:8] 8-bit data value holds higher byte program counter
Program Counter Register Table Program Counter Register (CPU_PCL)
Field Read/Write Default
Program Counter [7:0]
Program Counter [7:0] 8-bit data value holds lower byte program counter
Addressing Modes
Examples different addressing modes discussed this section example code given. Source Immediate result instruction using this addressing mode placed register, register, register, register, which specified part instruction opcode. Operand immediate value that serves source instruction. Arithmetic instructions require sources. Instructions using this addressing mode bytes length. Table Source Immediate Opcode Instruction Operand Immediate Value
Examples
this case, immediate value added with Accumulator, ;and result placed ;Accumulator. this case, immediate value moved register. this case, immediate value logically ANDed with ;register result placed register.
Source Direct result instruction using this addressing mode placed either register register, which specified part instruction opcode. Operand address that points location either memory space register space that source instruction. Arithmetic instructions require sources; second source register register specified opcode. Instructions using this addressing mode bytes length. Page
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Table 10.Source Direct Opcode Instruction Examples
this case, value ;the memory location ;address added with ;Accumulator, result placed Accumulator. this case, value ;the register space address moved register.
Examples Operand Source Address
[7], this case, value ;the memory location ;address added with ;Accumulator, result placed memory ;location address ;Accumulator unchanged. this case, ;Accumulator moved ;register space location ;address Accumulator unchanged.
REG[8],
REG[8]
Destination Indexed Source Indexed result instruction using this addressing mode placed either register register, which specified part instruction opcode. Operand added register forming address that points location either memory space register space that source instruction. Arithmetic instructions require sources; second source register register specified opcode. Instructions using this addressing mode bytes length. Table 11.Source Indexed Opcode Instruction Examples
[X+7] this case, value ;the memory location ;address added with ;the Accumulator, ;result placed ;Accumulator. this case, value ;the register space ;address moved ;the register.
result instruction using this addressing mode placed within either memory space register space. Operand added register forming address that points location result. source instruction register. Arithmetic instructions require sources; second source location specified Operand added with register. Instructions using this addressing mode bytes length. Table 13.Destination Indexed Opcode Instruction Operand Destination Index
Operand Source Index Example
[X+7], this case, value ;memory location address added with Accumulator, ;and result placed ;the memory location address ;x+7. Accumulator ;unchanged.
REG[X+8]
Destination Direct Source Immediate result instruction using this addressing mode placed within either memory space register space. Operand address result. source instruction Operand which immediate value. Arithmetic instructions require sources; second source location specified Operand Instructions using this addressing mode three bytes length. Table 14.Destination Direct Source Immediate Opcode Instruction Operand Destination Address Operand Immediate Value
Destination Direct result instruction using this addressing mode placed within either memory space register space. Operand address that points location result. source instruction either register register, which specified part instruction opcode. Arithmetic instructions require sources; second source location specified Operand Instructions using this addressing mode bytes length. Table 12.Destination Direct Opcode Instruction Operand Destination Address
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Examples
[7], this case, value ;memory location address ;added immediate value result placed ;the memory location address this case, immediate ;value moved into ;register space location ;address
Example
[7], this case, value ;memory location address ;moved memory location ;address
REG[8],
Source Indirect Post Increment result instruction using this addressing mode placed Accumulator. Operand address pointing location within memory space, which contains address (the indirect address) source instruction. indirect address incremented part instruction execution. This addressing mode only valid instruction. instruction using this addressing mode bytes length. Refer PSoC Designer: Assembly Language User Guide further details instruction. Table 17.Source Indirect Post Increment Opcode Instruction Example
this case, value ;memory location address indirect address. memory ;location pointed ;indirect address moved into ;Accumulator. indirect ;address then incremented.
Destination Indexed Source Immediate result instruction using this addressing mode placed within either memory space register space. Operand added register form address result. source instruction Operand which immediate value. Arithmetic instructions require sources; second source location specified Operand added with register. Instructions using this addressing mode three bytes length. Table 15.Destination Indexed Source Immediate Opcode Instruction Examples
[X+7], this case, value ;the memory location ;address added with ;the immediate value ;and result placed ;the memory location ;address X+7. this case, ;immediate value ;moved into location ;the register space ;address X+8.
Operand Source Address Address
Operand Destination Index
Operand Immediate Value
Destination Indirect Post Increment result instruction using this addressing mode placed within memory space. Operand address pointing location within memory space, which contains address (the indirect address) destination instruction. indirect address incremented part instruction execution. source instruction Accumulator. This addressing mode only valid instruction. instruction using this addressing mode bytes length. Table 18.Destination Indirect Post Increment Opcode Instruction Example
[8], this case, value ;the memory location ;address indirect ;address. Accumulator ;moved into memory location ;pointed indirect ;address. indirect address then incremented.
REG[X+8],
Destination Direct Source Direct result instruction using this addressing mode placed within memory. Operand address result. Operand address that points location memory that source instruction. This addressing mode only valid instruction. instruction using this addressing mode three bytes length. Table 16.Destination Direct Source Direct Opcode Instruction Operand Destination Address Operand Source Address
Operand Destination Address Address
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Instruction Summary
instruction summarized Table numerically serves quick reference. more information needed, Table 19.Instruction Summary Sorted Numerically Opcode Order[1,
Opcode Opcode Cycles Cycles Bytes Bytes Instruction Format Flags Instruction Format
Instruction Summary tables described detail PSoC Designer Assembly Language User Guide (available www.cypress.com site).
Opcode
Cycles
Flags
Bytes
Instruction Format
Flags
expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr PUSH expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr PUSH expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr ROMX expr [expr] [X+expr] [expr],
[X+expr], [expr], expr [X+expr], expr HALT expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr expr [expr] [X+expr] [expr], expr [X+expr], expr [expr]++ [expr]++ reg[expr], expr reg[X+expr], expr reg[expr], expr reg[X+expr], expr reg[expr], expr reg[X+expr], expr [expr], expr [X+expr], expr reg[expr], expr reg[X+expr], expr SWAP SWAP [expr] SWAP [expr] SWAP expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr [expr] [X+expr]
[expr], reg[expr] reg[X+expr] [expr], [expr] reg[expr], reg[X+expr], reg[expr], expr reg[X+expr], expr [expr] [X+expr] [expr] [X+expr] [expr] [X+expr] [expr] [X+expr] expr expr expr [expr] [X+expr] [expr] [X+expr] LCALL LJMP RETI CALL JACC INDEX
(A=B) (A<B)
Notes Interrupt routines take cycles before execution resumes interrupt vector table. number cycles required instruction increased instructions that span 256-byte boundaries Flash memory space.
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Memory Organization
Flash Program Memory Organization Figure Program Memory Space with Interrupt Vector Table after reset 16-bit Address 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 Program execution begins here after reset POR/LVD Reserved Transmitter Empty Receiver Full GPIO Port GPIO Port INT1 Reserved Reserved Reserved Reserved Reserved 1-ms Interval Timer Programmable Interval Timer Reserved Reserved 16-bit Free Running Timer Wrap INT2 Reserved GPIO Port Reserved Reserved Reserved Reserved Sleep Timer Program Memory begins here below interrupts used, program memory start lower)
0x1FFF
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Data Memory Organization function provides bytes data Figure Data Memory Organization after reset 8-bit Address 0x00 Stack begins here grows upward
Memory Flash
0xFF accessed normal user code operating from Flash. SROM exists separate memory space from user code. SROM functions accessed executing Supervisory System Call instruction (SSC), which opcode 00h. Prior executing SSC, M8C's accumulator needs loaded with desired SROM function code from Table Undefined functions will cause HALT called from user code. SROM functions executing code with calls; therefore, functions require stack space. With exception Reset, SROM functions have parameter block SRAM that must configured before executing SSC. Table lists possible parameter block variables. meaning each parameter, with regards specific SROM function, described later this chapter Table 20.SROM Function Codes Function Code Function Name SWBootReset ReadBlock WriteBlock EraseBlock EraseAll TableRead CheckSum Stack Space
This section describes Flash block CYRF69103. Much user-visible Flash functionality, including programming security, implemented Supervisory Read Only Memory (SROM). CYRF69103 Flash endurance 1000 cycles 10-year data retention. Flash Programming Security Flash programming performed code SROM. registers that control Flash programming only visible when executing SROM. This makes impossible read, write, erase Flash bypassing security mechanisms implemented SROM. Customer firmware only program Flash SROM calls. data code images sourced interface with appropriate support firmware. This type programming requires `boot-loader'-a piece firmware resident Flash. safety reasons this boot-loader should over written during firmware rewrites. Flash provides four auxiliary rows that used hold Flash block protection flags, boot time calibration values, configuration tables, device values. routines accessing these auxiliary rows documented SROM section. auxiliary rows affected device erase function. In-System Programming CYRF69103 enables this type in-system programming using P1.0 P1.1 pins serial programming mode interface. This allows external controller cause CYRF69103 enter serial programming mode then test queue issue Flash access functions SROM. SROM SROM holds code that used boot part, calibrate circuitry, perform Flash operations (Table lists SROM functions). functions SROM Document 001-07611
important variables that used functions KEY1 KEY2. These variables used help discriminate between valid SSCs inadvertent SSCs. KEY1 must always have value 3Ah, while KEY2 must have same value stack pointer when SROM function begins execution. This would Stack Pointer value when opcode executed, plus three. either keys match expected values, will halt (with exception SWBootReset function). following code puts correct value KEY1 KEY2. code starts with
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halt, force program jump directly into setup code into halt SSCOP: [KEY1], [KEY2], Table 21.SROM Function Parameters Variable Name Key1/Counter/Return Code Key2/TMP BlockID Pointer Clock Mode Delay SRAM Address 0,F8h 0,F9h 0,FAh 0,FBh 0,FCh 0,FDh 0,FEh 0,FFh
SWBootReset Function SROM function, SWBootReset, function that responsible transitioning device from reset state running user code. SWBootReset function executed whenever SROM entered with accumulator value 00h; SRAM parameter block used input function. This will happen, design, after hardware reset, because M8C's accumulator reset when user code executes instruction with accumulator value 00h. SWBootReset function will execute when instruction executed with value nonzero function code. CYRF69103 device will execute HALT instruction value given either KEY1 KEY2. SWBootReset function verifies integrity calibration data 16-bit checksum, before releasing user code. ReadBlock Function ReadBlock function used read contiguous bytes from Flash-a block. first thing this function does check protection bits determine desired BLOCKID readable. read protection turned ReadBlock function will exit setting accumulator KEY2 back 00h. KEY1 will have value 01h, indicating read failure. read protection enabled, function will read bytes from Flash using ROMX instruction store results SRAM using instruction. first bytes will stored SRAM address indicated value POINTER parameter. When ReadBlock completes successfully, accumulator, KEY1 KEY2, will have value 00h. Table 23.ReadBlock Parameters
SROM also features Return Codes Lockouts. Return Codes Return codes determination success failure particular function. return code stored KEY1's position parameter block. CheckSum TableRead functions have return codes because KEY1's position parameter block used return other data. Table 22.SROM Return Codes Return Code Success Function allowed level protection block Software reset without hardware reset Fatal error, SROM halted Description
Name KEY1 KEY2 BLOCKID POINTER
Address 0,F8h 0,F9h 0,FAh 0,FBh
Description Stack Pointer value, when executed Flash block number First addresses SRAM where returned data should stored
Read, write, erase operations fail target block read write protected. Block protection levels during device programming. EraseAll function overwrites data addition leaving entire user Flash erase state. EraseAll function loops through number Flash macros product, executing following sequence: erase, bulk program zeros, erase. After user space Flash macros erased, second loop erases then programs each protection block with zeros. SROM Function Descriptions SROM functions described following sections.
WriteBlock Function WriteBlock function used store data Flash. Data moved bytes time from SRAM Flash using this function. first thing WriteBlock function does check protection bits determine desired BLOCKID writable. write protection turned WriteBlock function will exit, setting accumulator KEY2 back 00h. KEY1 will have value 01h, indicating write failure. configuration WriteBlock function straightforward. BLOCKID Flash block, where data stored, must determined stored SRAM address FAh. SRAM address first bytes stored Flash must indicated using POINTER variable parameter block (SRAM address FBh). Finally, CLOCK DELAY values must correctly. CLOCK value Page
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determines length write pulse that will used store data Flash. CLOCK DELAY values dependent CPU. Refer `Clocking' Section additional information. Table 24.WriteBlock Parameters Name KEY1 KEY2 BLOCK Address 0,F8h 0,F9h 0,FAh Stack Pointer value, when executing 8-KB Flash block number (00h-7Fh) 4-KB Flash block number (00h-3Fh) 3-KB Flash block number (00h-2Fh) First addresses SRAM where data stored Flash located prior calling WriteBlock Clock Divider used write Pulse width speed Description
ability perform external reads writes. internal writes, used. Internal reading always permitted ROMX instruction. ability read SROM ReadBlock function indicated protection level stored bits, according Table These bits packed into bytes protection block. Therefore, each protection block byte stores protection level four Flash blocks. bits packed into byte, with lowest numbered block's protection level stored lowest numbered bits. first address protection block contains protection level blocks through second address blocks through 64th byte will store protection level blocks through 255. Table 26.Protection Modes Mode Settings Description Marketing Unprotected Factory upgrade
POINTER
0,FBh
CLOCK DELAY
0,FCh 0,FEh
Unprotected Read protect
Disable external Field upgrade write Disable internal write Full protection
EraseBlock Function EraseBlock function used erase block contiguous bytes Flash. first thing EraseBlock function does check protection bits determine desired BLOCKID writable. write protection turned EraseBlock function will exit, setting accumulator KEY2 back 00h. KEY1 will have value 01h, indicating write failure. EraseBlock function only useful first step programming. Erasing block will cause data block hundred percent unreadable. objective obliterate data block, best method perform EraseBlock followed WriteBlock zeros. parameter block EraseBlock function, correct values must stored KEY1 KEY2. block number erased must stored BLOCKID variable CLOCK DELAY values must based current speed. Table 25.EraseBlock Parameters Name KEY1 KEY2 BLOCKID CLOCK DELAY Address 0,F8h 0,F9h 0,FAh 0,FCh 0,FEh Stack Pointer value when executed Flash block number (00h-7Fh) Clock Divider used erase pulse width speed Description
Block
Block
Block
Block
level protection only decreased EraseAll, which places zeros locations protection block. level protection, ProtectBlock function used. This function takes data from SRAM, starting address 80h, with current values protection block. result operation then stored protection block. EraseBlock function does change protection level block. Because SRAM location protection data fixed there only protection block Flash macro, ProtectBlock function expects very variables parameter block prior calling function. parameter block values that must set, besides keys, CLOCK DELAY values. Table 27.ProtectBlock Parameters Name KEY1 KEY2 CLOCK DELAY Address 0,F8h 0,F9h 0,FCh 0,FEh Stack Pointer value when executed Clock Divider used write pulse width speed Description
EraseAll Function ProtectBlock Function CYRF69103 device offers Flash protection block-by-block basis. Table lists protection modes available. table, used indicate EraseAll function performs series steps that destroy user data Flash macros resets protection block each Flash macro zeros (the unprotected state). EraseAll function does affect three hidden blocks above protection block each Flash macro. first Page
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these four hidden blocks used store protection table eight Kbytes user data. EraseAll function begins erasing user space Flash macro with highest address range. bulk program zeros then performed same Flash macro, destroy traces previous contents. bulk program followed second erase that leaves Flash macro state ready writing. erase, program, erase sequence then performed next lowest Flash macro address space exists. Following erase user space, protection block Flash macro with highest address range erased. Following erase protection block, zeros written into every protection table. next lowest Flash macro address space then protection block erased filled with zeros. result EraseAll function that user data Flash destroyed Flash left unprogrammed state, ready accept various write commands. protection bits user data also reset zero state. parameter block values that must set, besides keys, CLOCK DELAY values. Table 28.EraseAll Parameters Name KEY1 KEY2 CLOCK DELAY Address 0,F8h 0,F9h 0,FCh 0,FEh Stack Pointer value when executed Clock Divider used write pulse width speed Description
Revision hard coded into SROM. Revision discussed more detail later this section. internal table holds alternate trim values device returns one-byte internal revision counter. internal revision counter starts with value zero incremented each time other revision numbers incremented. reset zero each time other revision numbers incremented. internal revision count returned CPU_A register. CPU_X register will always when trim values read. BLOCKID value, parameter block, used indicate which table should returned user. Only three least significant bits BLOCKID parameter used TableRead function CYRF69103. upper five bits ignored. When function called, transfers bytes from table SRAM addresses F8h-FFh. M8C's registers used TableRead function return die's Revision Revision 16-bit value hard coded into SROM that uniquely identifies die's design. Checksum Function Checksum function calculates 16-bit checksum over user-specifiable number blocks, within single Flash macro (Bank) starting from block zero. BLOCKID parameter used pass number blocks calculate checksum over. BLOCKID value will calculate checksum only block while BLOCKID value will calculate checksum 256-user blocks. 16-bit checksum returned KEY1 KEY2. parameter KEY1 holds lower eight bits checksum parameter KEY2 holds upper eight bits checksum. checksum algorithm executes following sequence three instructions over number blocks times checksummed. romx [KEY1], [KEY2], Table 30.Checksum Parameters Name KEY1 Address 0,F8h 0,F9h 0,FAh Stack Pointer value when executed Number Flash blocks calculate checksum Description
TableRead Function TableRead function gives user access part-specific data stored Flash during manufacturing. also returns Revision (not confused with Silicon ID). Table 29.Table Read Parameters Name KEY1 KEY2 Address 0,F8h 0,F9h Stack Pointer value when executed Table number read Description
KEY2 BLOCKID
BLOCKID 0,FAh
Clocking
table space CYRF69103 simply 64-byte broken into eight tables eight bytes. tables numbered zero through seven. user hidden blocks CYRF69103 consist bytes. internal table holds Silicon returns Revision Silicon returned SRAM, while Revision returned CPU_A CPU_X registers. Silicon value placed table programming Flash controlled Cypress Semiconductor Product Engineering. CYRF69103 internal oscillator outputs frequencies, Internal 24-MHz Oscillator 32-KHz Low-power Oscillator. Internal 24-MHz Oscillator designed such that trimmed output frequency over temperature voltage variation. Internal 24-MHz Oscillator accuracy -22% +10% (between 0°-70°C). external components required achieve this level accuracy.
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Firmware responsible selecting correct trim values from User match power supply voltage application writing values trim registers IOSCTR LPOSCTR. internal low-speed oscillator nominally provides slow clock source CYRF69103 suspend mode, particularly generate periodic wake-up interrupt also provide clock sequential logic during power-up power-down events when main clock stopped. addition, this oscillator also used clocking source Interval Timer clock (ITMRCLK) Capture Timer clock (TCAPCLK). 32-kHz Low-power Oscillator operate low-power mode provide more accurate clock normal mode. Internal 32-kHz Low-power Oscillator accuracy ranges from -53.12% +56.25%. 32-KHz power oscillator calibrated against internal 24-MHz oscillator another timing source desired. CYRF69103 provides ability load trim values 24-MHz oscillator based voltage. This allows monitored have firmware trim oscillator based voltage present. IOSCTR register used trim values 24-MHz oscillator. CYRF69103 initialized with 3.30V trim values power-on, then firmware responsible transferring correct trim values trim registers match application's actual Vdd. 32-KHz oscillator generally does require trim adjustments voltage trim values 32-KHz also stored Supervisory ROM. Table Oscillator Trim Values Voltage Settings Supervisory FLASH User Address 0xC094 0xC095 0xC096 0xC097 0xC098 0xC099 0xC09A 0xC09B Function 24-MHz IOSCTR 3.30V 24-MHz IOSCTR 3.00V 24-MHz IOSCTR 2.85V 24-MHz IOSCTR 2.70V 32-kHz LPOSCTR@3.30V 32-kHz LPOSCTR@3.00V 32-kHz LPOSCTR@2.85V 32-kHz LPOSCTR@2.70V
sending/receiving data. following firmware example assumes developer interested lower byte PIT. Read_PIT_counter: reg[PITMRL] [57h], reg[PITMRL] [58h],A [59h], reg[PITMRL] [60h], ;;;Start comparison A,[60h] [59h] [59h] done [59h] [58h] [58h] done [57h] ;;;correct data memory location done: [57h], CYRF69103 optionally sourced from external crystal oscillator. external clock driving CLKIN range from MHz. Clock Architecture Description CYRF69103 clock selection circuitry allows selection independent clocks CPU, Interval Timers, Capture Timers. CYRF69103, external oscillator sourced crystal oscillator, when crystal oscillator disabled sourced directly from CLKIN pin. Clock clock, CPUCLK, sourced from external crystal oscillator, Internal 24-MHz Oscillator, Internal 32-KHz Low-power Oscillator. selected clock source optionally divided 2n-1 where (see Table 33).
When using 32-KHz oscillator PITMRL/H should read until consecutive readings match before Table 32.CPU Clock Config (CPUCLKCR) [0x30] [R/W]
Field Read/Write Default Bits Reserved Reserved Reserved
Select Internal 24-MHz Oscillator Reserved Note speed selection configured using OSC_CR0 Register (Figure
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Table 33.OSC Control (OSC_CR0) [0x1E0] [R/W]
Field Read/Write Default Bits Reserved Buzz During sleep (the Sleep CPU_SCR Register-Table 37), detection circuit turned periodically detect events (the Sleep Duty Cycle bits ECO_TR used control duty Reserved Buzz Speed [2:0]
Sleep Timer [1:0]
cycle-Table 41). facilitate detection events, Buzz used force detection circuit continuously enabled during sleep. This results faster response event during sleep expense slightly higher than average sleep current. Obtaining absolute lowest power usage sleep mode requires Buzz clear detection circuit turned periodically configured Sleep Duty Cycle Sleep Duty Cycle value overridden. detection circuit always enabled Note periodic Sleep Duty Cycle enabling independent with sleep interval shown Sleep [1:0] bits below Bits Sleep Timer [1:0]
Sleep Timer Clock Frequency (Nominal) Sleep Period (Nominal) 1.95 15.6 Watchdog Period (Nominal)
Sleep Timer [1:0]
Note Sleep intervals approximate Bits Speed [2:0] CYRF69103 operate over range clock speeds. reset value Speed bits zero; therefore, default speed MHz.
when Internal Oscillator selected (Default) Reserved Reserved External Clock Clock In/8 Clock In/4 Clock In/2 Reserved Clock In/16 Clock In/32 Clock In/128 Reserved
Speed [2:0]
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Table 34.Timer Clock Config (TMRCLKCR) [0x31] [R/W]
Field Read/Write Default Bits
TCAPCLK Divider
TCAPCLK Select
ITMRCLK Divider
ITMRCLK Select
TCAPCLK Divider [1:0] TCAPCLK Divider controls TCAPCLK divisor Divider Value Divider Value Divider Value Divider Value
TCAPCLK Select TCAPCLK Select field controls source TCAPCLK Internal 24-MHz Oscillator =Reserved Internal 32-KHz Low-power Oscillator TCAPCLK Disabled Note 1024-µs interval timer based assumption that TCAPCLK running MHz. Changes TCAPCLK frequency will cause corresponding change 1024-µs interval timer frequency Bits ITMRCLK Divider ITMRCLK Divider controls ITMRCLK divisor Divider value Divider value Divider value Divider value ITMRCLK Select Internal 24-MHz Oscillator Reserved Internal 32-KHz Low-power Oscillator TCAPCLK Note Changing source TMRCLK requires that both source destination clocks running. Attempting change clock source away from TCAPCLK after that clock been stopped will successful Bits
Bits
Interval Timer Clock (ITMRCLK) Interval Timer clock (ITMRCLK) sourced from internal 24-MHz oscillator, internal 32-kHz low-power oscillator, timer capture clock. programmable prescaler then divides selected source. 12-bit Programmable Interval Timer simple down counter with programmable reload value. provides 1-µs resolution default. When down counter reaches zero, next clock spent reloading. reload value read written while counter running, care should taken ensure that counter does unintentionally reload while 12-bit reload value only partially stored-for example, between writes 12-bit value. programmable interval timer generates interrupt each reload. parameters will appear device editor view PSoC Designer once place enCoRe timer user module. parameters PITIMER_Source PITIMER_Divider. PITIMER_Source clock
timer PITIMER_Divider value clock divided interval register (PITMR) holds value that loaded into counter terminal count. counter down counter. Programmable Interval Timer resolution configurable. example: TCAPCLK divide clock (for example TCAPCLK divide 24-MHz clock will give frequency MHz) ITMRCLK divide TCAPCLK (for example, ITMRCLK divide TCAPCLK resolution 0.25 µs). Timer Capture Clock (TCAPCLK) Timer Capture clock (TCAPCLK) sourced from external crystal oscillator, internal 24-MHz oscillator internal 32-kHz low-power oscillator. programmable prescaler then divides selected source.
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Figure Programmable Interval Timer Block Diagram
Internal Clock Trim Table 35.IOSC Trim (IOSCTR) [0x34] [R/W]
Field Read/Write Default foffset[2:0] Gain[4:0]
IOSC Calibrate register used calibrate internal oscillator. reset value undefined during boot SROM writes calibration value that determined during manufacturing test. indicates that default value trimmed 3.30V power Bits foffset [2:0] This value used trim frequency internal oscillator. These bits used factory calibration will zero. Setting each these bits causes appropriate fine offset oscillator frequency foffset foffset foffset Bits Gain [4:0] effective frequency change offset input controlled through gain input. lower value gain setting increases gain offset input. This value sets size each offset step internal oscillator. Nominal gain change (KHz/offsetStep) each bit, typical conditions (24-MHz operation) Gain -1.5 Gain -3.0 Gain Gain
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LPOSC Trim Table 36.LPOSC Trim (LPOSCTR) [0x36] [R/W]
Field Read/Write Default 32-kHz Power Reserved
32-kHz Bias Trim [1:0]
32-kHz Freq Trim [3:0]
This register used calibrate 32-KHz Low-speed Oscillator. reset value undefined during boot SROM writes calibration value that determined during manufacturing test. This meaning Default field. trim value adjusted voltage noted Table 32-KHz Power 32-KHz Low-speed Oscillator operates normal mode 32-KHz Low-speed Oscillator operates low-power mode. oscillator continues function normally with reduced accuracy Bits Reserved 32-KHz Bias Trim [1:0] These bits control bias current low-power oscillator bias High bias Reserved Reserved Important Note program 32-KHz Bias Trim [1:0] field with reserved value oscillator does oscillate corner conditions with this setting Bits 32-kHz Freq Trim [3:0] These bits used trim frequency low-power oscillator
Clock During Sleep Mode When enters sleep mode CPUCLK Select (Bit [0], Table forced internal oscillator, oscillator stopped. When comes sleep mode running internal oscillator. internal oscillator recovery time three clock cycles Internal 32-kHz Low-power Oscillator. system requires external clock after awakening from sleep mode, firmware will need switch clock source CPU. external clock source external oscillator oscillator disabled, firmware will need enable external oscillator, wait stabilize, then change clock source.
Reset
microcontroller supports types resets: Power-on Reset (POR) Watchdog Reset (WDR). When reset initiated, registers restored their default states interrupts disabled. occurrence reset recorded System Status Control Register (CPU_SCR). Bits within this register record occurrence Reset respectively. firmware interrogate these bits determine cause reset. microcontroller resumes execution from Flash address 0x0000 after reset. internal clocking mode active after reset, until changed user firmware. Note clock defaults (Internal 24-MHz Oscillator divide-by-8 mode) guarantee operation that might present during supply ramp.
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Table 37.System Status Control Register (CPU_SCR) [0xFF] [R/W]
Field Read/Write Default GIES Reserved WDRS R/C[3] PORS R/C[3] Sleep Reserved Reserved Stop
bits CPU_SCR register used convey status control events various functions CYRF69103 device. GIES Global Interrupt Enable Status read-only status discouraged. GIES legacy bit, which used provide ability read CPU_F register. However, CPU_F register readable. When this set, indicates that CPU_F register also which, turn, indicates that microprocessor will service interrupts Global interrupts disabled Global interrupt enabled Reserved WDRS WDRS indicate that event occurred. user read this determine type reset that occurred. user clear this event occurred PORS PORS indicate that event occurred. user read this determine type reset that occurred. user clear this event occurred. (Note that events will occur until this cleared.) SLEEP user enable sleep state. will remain sleep mode until interrupt pending. Sleep covered more detail Sleep Mode section Normal operation Sleep Reserved STOP This user halt CPU. will remain halted until reset (WDR, POR, external reset) taken place. application wants stop code execution until reset, preferred method would HALT instruction rather than writing this Normal operation halted (not recommended)
Bits
Power-on Reset occurs every time power device switched released when supply typically 2.6V upward supply transition, with typically hysteresis during power-on transient. System Status Control Register (CPU_SCR) record this event (the register contents 00010000 POR). After POR, microprocessor held approximately supply stabilize before executing first instruction address 0x00 Flash. voltage drops below downward supply trip point, reasserted. supply needs ramp linearly from Important PORS status only cleared user, cannot firmware. Watchdog Timer Reset user option enable WDT. enabled clearing PORS bit. Once PORS
cleared, cannot disabled. only exception this event takes place, which will disable WDT. sleep timer used generate sleep time period Watchdog time period. sleep timer uses Internal 32-kHz Low-power Oscillator system clock produce sleep time period. user program sleep time period using Sleep Timer bits OSC_CR0 Register (Table 33). When sleep time elapses (sleep timer overflows), interrupt Sleep Timer Interrupt Vector will generated. Watchdog Timer period automatically three counts Sleep Timer overflows. This represents between three sleep intervals depending count Sleep Timer previous clear. When this timer reaches three, generated. user either clear WDT, Sleep Timer. Whenever user writes Reset Register (RES_WDT), will cleared. data that written
Note Clear. This only cleared user cannot firmware.
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value 0x38, Sleep Timer will also cleared same time. Table 38.Reset Watchdog Timer (RESWDT) [0xE3]
Field Read/Write Default Reset Watchdog Timer [7:0]
write this register will clear Watchdog Timer, write 0x38 will also clear Sleep Timer. Bits Reset Watchdog Timer [7:0]
Sleep Mode
only sleep firmware. This accomplished setting Sleep System Status Control Register (CPU_SCR). This stops from executing instructions, will remain asleep until interrupt comes pending, there reset event (either Power-on Reset, Watchdog Timer Reset). Low-voltage Detection circuit (LVD) drops into fully functional power-reduced states, latency increased. actual latency traded against power consumption changing Sleep Duty Cycle field ECO_TR Register. Internal 32-KHz Low-speed Oscillator remains running. Prior entering suspend mode, firmware optionally configure 32-KHz Low-speed Oscillator operate low-power mode help reduce overall power consumption (using 32-KHz Power bit, Table 36). This will help save approximately however, trade that 32-KHz Low-speed Oscillator will less accurate (-53.12% +56.25% deviation). interrupts remain active. Only occurrence interrupt will wake part from sleep. Stop System Status Control Register (CPU_SCR) must cleared part resume sleep. Global Interrupt Enable Flags Register (CPU_F) does have effect. unmasked interrupt will wake system result, interrupts intended waking should disabled through Interrupt Mask Registers. When enters sleep mode CPUCLK Select (Bit Table forced Internal Oscillator. internal oscillator recovery time three clock cycles Internal 32-kHz Low-power Oscillator. Internal 24-MHz Oscillator restarts immediately exiting Sleep mode. external crystal oscillator used, firmware will need switch clock source CPU. Unlike Internal 24-MHz Oscillator, external oscillator automatically shut down during sleep. Systems that need external oscillator disabled sleep mode will need disable external oscillator prior entering sleep mode. systems where runs external oscillator, firmware will need switch internal oscillator prior disabling external oscillator. exiting sleep mode, once clock stable delay time expired, instruction immediately following
sleep instruction executed before interrupt service routine enabled). Sleep interrupt allows microcontroller wake periodically poll system components while maintaining very average power consumption. Sleep interrupt also used provide periodic interrupts during non-sleep modes. Sleep Sequence SLEEP input into sleep logic circuit. This circuit designed sequence device into hardware sleep state. hardware sequence device sleep shown Figure defined follows. Firmware sets SLEEP CPU_SCR0 register. Request (BRQ) signal immediately asserted. This request system halt operation instruction boundary. samples positive edge CPUCLK. specific timing register write, issues Request Acknowledge (BRA) following positive edge clock. sleep logic waits following negative edge clock then asserts system-wide Power Down (PD) signal. Figure halted system-wide power down signal asserted. system-wide (power down) signal controls several major circuit blocks: Flash memory module, internal 24-MHz oscillator, EFTB filter bandgap voltage reference. These circuits transition into zero power state. only operational circuits chip Power oscillator, bandgap refresh circuit, supply voltage monitor (POR/LVD) circuit. external crystal oscillator CYRF69103 devices automatically powered down when enters sleep state. Firmware must explicitly disable external crystal oscillator order reduce power levels specified. Note achieve lowest possible power consumption during suspend/sleep, following conditions must observed addition considerations sleep timer external crystal oscillator: GPIOs must outputs driven port pins P1.0 P1.1 should configured inputs with their pull enabled.
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Figure Sleep Timing
Firmware write SLEEP causes immediate
captures next CPUCLK edge
responds with
falling edge CPUCLK, asserted. 24/48 system clock halted; Flash bandgap powered down
CPUCLK SLEEP
Wakeup Sequence Once asleep, only event that wake system interrupt. global interrupt enable flag register does need set. unmasked interrupt will wake system optional actually take interrupt after wakeup sequence. wakeup sequence synchronized 32-KHz clock purposes sequencing startup delay, allow Flash memory module enough time power before asserts first read access. Another reason delay allow oscillator, Bandgap, LVD/POR circuits time settle before actually being used system. shown Figure wake sequence follows: wakeup interrupt occurs synchronized negative edge 32-KHz clock. following positive edge 32-KHz clock, system-wide signal negated. Flash memory module, internal oscillator, EFTB, bandgap circuit powered normal operating state. following positive edge 32-KHz clock, current values precision have settled sampled. following negative edge 32-KHz clock (after about nominal), signal negated sleep logic circuit. following CPUCLK, negated instruction execution resumes. Note that Figure fixed function blocks, such Flash, internal oscillator, EFTB, bandgap, have about start wakeup times (interrupt operational) will range from
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Figure Wakeup Timing
leep interrupt occurs
Interrupt double pled clock negated system
restarted after (nom inal)
LK32K SLEEP
ABLE
Scale)
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Low-Voltage Detect Control
Table 39.Low-voltage Control Register (LVDCR) [0x1E3] [R/W]
Field Read/Write Default Reserved PORLEV[1:0] Reserved VM[2:0]
This register controls configuration Power-on Reset/Low-voltage Detection circuit. This register only accessed second bank space. This requires setting flags register. Bits Reserved Bits PORLEV[1:0] This field controls level below which precision power-on-reset (PPOR) detector generates reset 2.7V Range (trip near 2.6V) Range (trip near 2.9V) Reserved PPOR will generate reset, values read from Voltage Monitor Comparators Register (Table give internal PPOR comparator state with trip point range setting. Reserved VM[2:0] This field controls level below which low-voltage-detect trips-possibly generating interrupt level which Flash enabled operation. Trip Point VM[2:0] Min. 2.69 2.90 3.00 3.10 Max. 2.72 2.94 3.04 3.15 Reserved Reserved Reserved Reserved Typical 2.92 3.02 3.13
Bits
Compare State Table 40.Voltage Monitor Comparators Register (VLTCMP) [0x1E4]
Field Read/Write Default Bits Reserved This indicate that low-voltage-detect comparator tripped, indicating that supply voltage gone below trip point VM[2:0] (See Table 39.) low-voltage-detect event low-voltage-detect tripped Reserved PPOR
This read-only register allows reading current state Low-voltage Detection Precision-Power-On-Reset comparators
PPOR This indicate that precision-power-on-reset comparator tripped, indicating that supply voltage below trip point PORLEV[1:0] precision-power-on-reset event precision-power-on-reset event tripped Note This register only accessed second bank space. This requires setting flags register
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Trim Register Table 41.ECO (ECO_TR) [0x1EB] [R/W]
Field Read/Write Default Bits Reserved
Sleep Duty Cycle [1:0]
This register controls ratios numbers 32-KHz clock periods) `on' time versus `off' time detection circuit Sleep Duty Cycle [1:0] periods Internal 32-kHz Low-speed Oscillator periods Internal 32-KHz Low-speed Oscillator periods Internal 32-KHz Low-speed Oscillator periods Internal 32-KHz Low-speed Oscillator Note This register only accessed second bank space. This requires setting flags register
General-Purpose Ports
general-purpose ports discussed following sections. Port Data Registers Table 42.P0 Data Register (P0DATA)[0x00] [R/W]
Field Read/Write Default P0.7 Reserved P0.4/INT2 P0.3/INT1 Reserved P0.1/CLKOUT Reserved
This register contains data Port Writing this register sets values output output enabled pins. Reading from this register returns current state Port pins. P0.7 Data Bits Bits Reserved P0.4-P0.3Data/INT2-INT0 addition their P0.4-P0.2 GPIOs, these pins also used alternative functions Interrupt pins (INT0-INT2). configure P0.4-P0.2 pins, refer P0.2/INT0-P0.4/INT2 Configuration Register (Table Reserved P0.1 Data/Clock-output. Reserved
Table 43.P1 Data Register (P1DATA) [0x01] [R/W]
Field Read/Write Default P1.7 P1.6 P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2 P1.1 P1.0
This register contains data Port Writing this register sets values output output enabled pins. Reading from this register returns current state Port pins. Bits P1.7- P1.6 Bits P1.5-P1.3 Data/SPI Pins (SMISO, SMOSI, SCLK, SSEL) addition their P1.6-P1.3 GPIOs, these pins also used alternative function interface pins. configure P1.6-P1.3 pins, refer P1.3-P1.6 Configuration Register (Table P1.2-P1.1 P1.0
Bits
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Table 44.P2 Data Register (P2DATA) [0x02] [R/W]
Field Read/Write Default Reserved P2.1-P2.0
This register contains data Port Writing this register sets values output output enabled pins. Reading from this register returns current state Port pins Bits Data [7:2] Bits Data [1:0]
GPIO Port Configuration GPIO configuration registers have common configuration controls. following definitions GPIO configuration registers. default GPIOs configured inputs. order prevent inputs from floating, pull-up resistors enabled. Firmware will need configure each GPIOs prior use. Enable When set, Enable allows GPIO generate interrupts. Interrupt generate occur regardless whether configured input output. interrupts edge sensitive, however interrupt that shared multiple sources (that Ports inputs must deasserted before interrupt occur. When clear, corresponding interrupt disabled pin. possible configure GPIOs outputs, enable interrupt then generate interrupt driving appropriate state. This useful test have value applications well. When clear, corresponding interrupt active HIGH. When set, interrupt active LOW. P0.2-P0.4 clear causes interrupts active rising edge. causes interrupts active falling edge. Thresh When set, input threshold. When clear, input standard CMOS threshold. Important Note GPIOs default CMOS threshold. User's firmware needs configure threshold mode necessary. High Sink When set, output sink When clear, output sink
CY7C601xx, only P3.7, P2.7, P0.1, P0.0 have 50-mA sink drive capability. Other pins have 8-mA sink drive capability. CY7C602xx, only P1.7-P1.3 have 50-mA sink drive capability. Other pins have 8-mA sink drive capability. Open Drain When set, output determined Port Data Register. corresponding Port Data Register set, high impedance state. corresponding Port Data Register clear, driven LOW. When clear, output driven HIGH. Pull-up Enable When pull VDD. When clear, pull disabled. Output Enable When set, output driver enabled. When clear, output driver disabled. pins with shared functions there some special cases. P0.0 (CLKIN) P0.1 (CLKOUT) output enabled when crystal oscillator enabled. Output enables these pins overridden XOSC Enable. P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI) P1.6 (SMISO) used their dedicated functions GPIO. enable GPIO use, clear corresponding Output Enable will have effect. P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI) P1.6 (SMISO) pins used their dedicated functions GPIO. enable GPIO, clear corresponding bit. function controls output enable dedicated function pins when their GPIO enable clear.
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Table 45.P0.1/CLKOUT Configuration (P01CR) [0x06] R/W]
Field Read/Write Default Output Enable Thresh High Sink Open Drain
Pull-up Enable Output Enable
This shared between P0.1 GPIO CLKOUT external crystal oscillator. When external oscillator enabled settings this register ignored. When output set, internally selected clock sent onto P0.1CLKOUT alternate function CLKOUT only available CY7C601xx. When external oscillator enabled (the XOSC Enable CLKIOCR Register set-Table 73), GPIO function disabled 50-mA sink drive capability only available CY7C601xx. CY7C602xx, only 8-mA sink drive capability available this regardless setting High Sink this used general-purpose output will draw current. This should configured input reduce current draw Output clock output disabled clock selected Select field (Bit [1:0] CLKIOCR Register-Table driven
Table 46.P0.3-P0.4 Configuration (P03CR-P04CR) [0x07-0x09] [R/W]
Field Read/Write Default Reserved Thresh Reserved Open Drain
Pull-up Enable Output Enable
These registers control operation pins P0.2-P0.4 respectively. These pins shared between P0.2-P0.4 GPIOs INT0-INT2. INT0-INT2 interrupts different than other GPIO interrupts. These pins connected directly interrupt controller provide three edge-sensitive interrupts with independent interrupt vectors. These interrupts occur rising edge when clear falling edge when set. These pins enabled interrupt sources interrupt controller registers (Table Table these pins interrupt inputs, configure them inputs clearing corresponding Output Enable. INT0-INT2 pins configured outputs with interrupts enabled, firmware generate interrupt writing appropriate value P0.2, P0.3, P0.4 data bits Data Register Regardless whether pins used Interrupt GPIO pins Enable, Low, Threshold, Open Drain, Pull-up Enable bits control behavior P0.2/INT0-P0.4/INT2 pins individually configured with P02CR (0x07), P03CR (0x08), P04CR (0x09) respectively Note Changing state cause unintentional interrupt generated. When configuring these interrupt sources, best follow following procedure: Disable interrupt source Configure interrupt source Clear pending interrupts from source Enable interrupt source
Table 47.P0.7 Configuration (P07CR) [0x0C] [R/W]
Field Read/Write Default Reserved Enable Thresh Reserved Open Drain
Pull-up Enable Output Enable
This register controls operation P0.7
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Table 48.P1.1 Configuration (P11CR) [0x0E] [R/W]
Field Read/Write Default Reserved Enable Reserved Open Drain Reserved Output Enable
This register controls operation P1.1 pull-up resistor this enabled P10CR Register Note There 2-mA sourcing capability this pin. only sink VOL3 section
Table 49.P1.2 Configuration (P12CR) [0x0F] [R/W]
Field Read/Write Default Output Enable Threshold Reserved Open Drain
Pull-up Enable Output Enable
This register controls operation P1.2 Output internally selected clock sent onto P1.2 When Output set, internally selected clock sent onto P1.2 pin.
Table 50.P1.3 Configuration (P13CR) [0x10] [R/W]
Field Read/Write Default Reserved Enable Reserved High Sink Open Drain
Pull-up Enable Output Enable
This register controls operation P1.3 P1.3 GPIO's threshold always When hardware enabled, output enable output state controlled circuitry. When hardware disabled, controlled Output Enable corresponding data register Regardless whether used GPIO Enable, Low, High Sink, Open Drain, Pull-up Enable control behavior 50-mA sink drive capability available
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Table 51.P1.4-P1.6 Configuration (P14CR-P16CR) [0x11-0x13] [R/W]
Field Read/Write Default Enable Reserved High Sink Open Drain
Pull-up Enable Output Enable
These registers control operation pins P1.4-P1.6, respectively P1.4-P1.6 GPIO's threshold always When hardware enabled, pins that configured have their output enable output state controlled circuitry. When hardware disabled clear, controlled Output Enable corresponding data register Regardless whether used GPIO Enable, Low, High Sink, Open Drain, Pull-up Enable control behavior 50-mA sink drive capability only available CY7C602xx. CY7C601xx, only 8-mA sink drive capability available this regardless setting High Sink Disable alternate function. used GPIO Enable function. circuitry controls output Important Note Comm Modes (SPI Master Slave, Table When configured (SPI Comm Modes [1:0] Master Slave mode), input/output direction pins P1.3, P1.5, P1.6 automatically logic. However, P1.4's input/output direction automatically set; must explicitly firmware. Master mode, P1.4 must configured output; Slave mode, P1.4 must configured input
Table P1.7 Configuration (P17CR) [0x14] [R/W]
Field Read/Write Default Reserved Enable Reserved High Sink Open Drain
Pull-up Enable Output Enable
This register controls operation P1.7 50-mA sink drive capability available. P1.7 GPIO's threshold always
Table 53.P2 Configuration (P2CR) [0x15] [R/W]
Field Read/Write Default Reserved Enable Thresh High Sink Open Drain
Pull-up Enable Output Enable
This register controls operation pins P2.0-P2.1
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Serial Peripheral Interface (SPI)
Master/Slave Interface core logic runs clock domain. clock divider CPUCLK when Master Mode. four-pin serial interface comprised clock, enable, data pins Figure Block Diagram
Register Block Speed Clock Generation
Master/Slave
Clock Select
SCK_OE
Polarity Phase
Clock Phase/Polarity Select
Little Endian
LE_SEL GPIO Block SS_N SS_N
State Machine SS_N Data bit) Load Empty Master/Slave LE_SEL Shift Buffer MISO/MOSI Crossbar Output Shift Buffer
SS_N_OE
MISO_OE
MISO
MOSI_OE
MOSI Data bit) Load Full Input Shift Buffer
Sclk Output Enable Slave Select Output Enable Master Slave Master Out, Slave
SCK_OE SS_N_OE MISO_OE MOSI_OE
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Data Register Table 54.SPI Data Register (SPIDATA) [0x3C] [R/W]
Field Read/Write Default SPIData[7:0]
When read, this register returns contents receive buffer. When written, loads transmit holding register. Bits Data [7:0]
When interrupt occurs indicate firmware that byte receive data available, transmitter holding register empty, firmware clocks manage buffers-to empty receiver buffer, refill transmit holding register. Failure meet this timing requirement will result incorrect data transfer. Configure Register Table 55.SPI Configure Register (SPICR) [0x3D] [R/W]
Field Read/Write Default Swap First Comm Mode CPOL CPHA SCLK Select
Swap Swap function disabled block swaps SMOSI SMISO. Among other things, this useful implementing single wire SPI-like communications First transmits receives (Most Significant Bit) first transmits receives (Least Significant Bit) first Comm Mode [1:0] communication disabled master mode slave mode Reserved CPOL This controls clock (SCLK) idle polarity SCLK idles SCLK idles high CPHA Clock Phase controls phase clock which data sampled. Table shows timing various combinations First, CPOL, CPHA SCLK Select This field selects speed master SCLK. When master mode, SCLK generated dividing base CPUCLK
Bits
Bits
Important Note Comm Modes (SPI Master Slave): When configured SPI, (SPI 1-Table 51), input/output direction pins P1.3, P1.5, P1.6 automatically logic. However, P1.4's input/output direction automatically set; must explicitly firmware. Master mode, P1.4 must configured output; Slave mode, P1.4 must configured input
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Table 56.SPI Mode Timing First, CPOL CPHA First CPHA CPOL
SCLK SSEL
Diagram
SSEL
SSEL
SSEL
SCLK SSEL
SCLK SSEL
SCLK SSEL
SSEL
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Table 57.SPI SCLK Frequency SCLK CPUCLK Select Divisor SCLK Frequency when CPUCLK
clock. 16-bit free-running counter used time-base timer captures also used general time-base software. Registers Free-Running Counter 16-bit free-running counter clocked 4-/6-MHz source. read software general-purpose time base. When low-order byte read, high-order byte registered. Reading high-order byte reads this register allowing read 16-bit value atomically (loads bits time). free-running timer generates interrupt 1024-µs rate. also generate interrupt when free-running counter overflow occurs-every 16.384 This allows extending length timer software.
Interface Pins interface between radio function function uses pins P1.3-P1.5 optionally P1.6. These pins configured using P1.3 P1.4-P1.6 Configuration.
Timer Registers
timer functions CYRF69103 provided single timer block. timer block asynchronous from
Figure 16-bit Free Running Counter Block Diagram
Overflow Interrupt
Capture lock
16-bit Free Running Counter
1024-µs Interrupt
Table 58.Free-Running Timer Low-Order Byte (FRTMRL) [0x20] [R/W]
Field Read/Write Default Bits
Free-running Timer [7:0]
Free-running Timer [7:0]
This register holds low-order byte 16-bit free-running timer. Reading this register causes high-order byte moved into holding register allowing automatic read bits simultaneously reads, actual read occurs cycle when order read. writes actual time write occurs cycle when high order written When reading free-running timer, low-order byte should read first high-order second. When writing, low-order byte should written first then high-order byte
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Table 59.Free-Running Timer High-Order Byte (FRTMRH) [0x21] [R/W]
Field Read/Write Default
Free-running Timer [15:8]
Bits Free-running Timer [15:8] When reading free-running timer, low-order byte should read first high-order second. When writing, low-order byte should written first then high-order byte.
Table 60.Programmable Interval Timer (PITMRL) [0x26]
Field Read/Write Default
Prog Interval Timer [7:0]
Bits Prog Interval Timer [7:0] This register holds order-byte 12-bit programmable interval timer. Reading this register causes high-order byte moved into holding register allowing automatic read bits simultaneously
Table 61.Programmable Interval Timer High (PITMRH) [0x27]
Field Read/Write Default Bits Reserved Reserved
Prog Interval Timer [11:8]
Bits Prog Internal Timer [11:8] This register holds high-order nibble 12-bit programmable interval timer. Reading this register returns high-order nibble 12-bit timer instant that low-order byte last read
Table 62.Programmable Interval Reload (PIRL) [0x28] [R/W]
Field Read/Write Default
Prog Interval [7:0]
Bits Prog Interval [7:0] This register holds lower bits timer. While writing into 12-bit reload register, write lower byte first then higher nibble.
Table 63.Programmable Interval Reload High (PIRH) [0x29] [R/W]
Field Read/Write Default Bits 7:4] Reserved Reserved
Prog Interval[11:8]
Bits Prog Interval [11:8] This register holds higher bits timer. While writing into 12-bit reload register, write lower byte first then higher nibble
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Figure 16-Bit Free-Running Counter Loading Timing Diagram
clk_sys write
valid addr write data reload ready Timer Prog Timer reload interrupt 12-bit programmable timer load timing Capture timer free running counter load free running counter
00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 ACBE ACBF ACC0
16-bit free running counter loading timing
Figure Memory Mapped Registers Read/Write Timing Diagram
clk_sys rd_wrn
Valid Addr rdata wdata Memory mapped registers Read/Write timing diagram
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Interrupt Controller
interrupt controller associated registers allow user's code respond interrupt from almost every functional block CYRF69103 devices. registers associated with interrupt controller allow interrupts disabled either globally individually. registers also provide mechanism which user clear pending posted interrupts, clear individual posted pending interrupts. following table lists interrupts priorities that available CYRF69103. Table 64.Interrupt Priorities, Address, Name Interrupt Priority Interrupt Address 0000h 0004h 0008h 000Ch 0010h 0014h 0018h 001Ch 0020h 0024h 0028h 002Ch 0030h 0034h 0038h 003Ch 0040h Reset POR/LVD Reserved Transmitter Empty Receiver Full GPIO Port GPIO Port INT1 Reserved Reserved Reserved Reserved Reserved 1-ms Interval timer Programmable Interval Timer Reserved Reserved Name
Table 64.Interrupt Priorities, Address, Name (continued) Interrupt Priority Interrupt Address 0044h 0048h 004Ch 0050h 0054h 0058h 005Ch 0060h 0064h INT2 Reserved GPIO Port Reserved Reserved Reserved Reserved Sleep Timer Name 16-bit Free Running Timer Wrap
Architectural Description interrupt posted when interrupt conditions occur. This results flip-flop Figure clocking `1'. interrupt will remain posted until interrupt taken until cleared writing appropriate INT_CLRx register. posted interrupt pending unless enabled setting interrupt mask appropriate INT_MSKx register). pending interrupts processed Priority Encoder determine highest priority interrupt which will taken Global Interrupt Enable CPU_F register. Disabling interrupt clearing interrupt mask INT_MSKx register) does clear posted interrupt, does prevent interrupt from being posted. simply prevents posted interrupt from becoming pending. Nested interrupts accomplished reenabling interrupts inside interrupt service routine. this, Flag Register. block diagram CYRF69103 Interrupt Controller shown Figure
Figure Interrupt Controller Block Diagram
Interrupt Taken INT_CLRx Write Posted Interrupt Pending Interrupt
Priority Encoder
Interrupt Vector
Interrupt Request Core
Interrupt Source (Timer, GPIO, etc.) INT_MSKx Mask Setting
CPU_F[0]
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Interrupt Processing sequence events that occur during interrupt processing follows: interrupt becomes active, either because: interrupt condition occurs (for example, timer expires). previously posted interrupt enabled through update interrupt mask register. interrupt pending from Flag register. current executing instruction finishes. internal interrupt dispatched, taking cycles. During this time, following actions occur: Program Counter Flag registers (CPU_PC CPU_F) stored onto program stack automatic CALL instruction cycles) generated during interrupt acknowledge process. PCH, PCL, Flag register (CPU_F) stored onto program stack that order) automatic CALL instruction cycles) generated during interrupt acknowledge process. CPU_F register then cleared. Since this clears additional interrupts temporarily disabled. (PC[15:8]) cleared zero. interrupt vector read from interrupt controller value placed into (PC[7:0]). This sets program counter point appropriate address interrupt table (for example, 0004h POR/LVD interrupt). Program execution vectors interrupt table. Typically, LJMP instruction interrupt table sends execution user's Interrupt Service Routine (ISR) this interrupt. executes. Note that interrupts disabled since ISR, interrupts re-enabled desired Table Interrupt Clear (INT_CLR0) [0xDA] [R/W]
Field Read/Write Default GPIO Port Sleep Timer INT1
setting (care must taken avoid stack overflow). ends with RETI instruction which restores Program Counter Flag registers (CPU_PC CPU_F). restored Flag register re-enables interrupts, since again. Execution resumes next instruction, after that occurred before interrupt. However, there more pending interrupts, subsequent interrupts will processed before next normal program instruction. Interrupt Latency time between assertion enabled interrupt start calculated from following equation. Latency Time current instruction finish Time internal interrupt routine execute Time LJMP instruction interrupt table execute. example, 5-cycle instruction executing when interrupt becomes active, total number clock cycles before begins would follows: cycles finish) cycles interrupt routine) cycles LJMP) cycles. example above, MHz, clock cycles take 2.08 Interrupt Registers Interrupt Registers discussed following sections. Interrupt Clear Register Interrupt Clear Registers (INT_CLRx) used enable individual interrupt sources' ability clear posted interrupts. When INT_CLRx register read, bits that indicates interrupt been posted that hardware resource. Therefore, reading these registers gives user ability determine posted interrupts.
Receive
Transmit
Reserved
POR/LVD
GPIO Port
When reading this register, There's posted interrupt corresponding hardware Posted interrupt corresponding hardware present Writing bits will clear posted interrupts corresponding hardware. Writing bits ENSWINT (Bit INT_MSK3 Register) will post corresponding hardware interrupt.
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Table Interrupt Clear (INT_CLR1) [0xDB] [R/W]
Reserved Field Read/Write Default Reserved Prog Interval 1-ms ProTimer grammable Interrupt
When reading this register, There's posted interrupt corresponding hardware Posted interrupt corresponding hardware present Writing bits will clear posted interrupts corresponding hardware. Writing bits ENSWINT Reserved
Table 67.Interrupt Clear (INT_CLR2) [0xDC] [R/W]
Field Read/Write Default Reserved Reserved Reserved GPIO Port2 Reserved INT2 16-bit Counter Wrap Reserved
When reading this register, There's posted interrupt corresponding hardware Posted interrupt corresponding hardware present Writing bits will clear posted interrupts corresponding hardware. Writing bits ENSWINT (Bit INT_MSK3 Register) will post corresponding hardware interrupt Bits 7,6,5,3,0] Reserved
Interrupt Mask Registers Interrupt Mask Registers (INT_MSKx) used enable individual interrupt sources' ability create pending interrupts. There four Interrupt Mask Registers (INT_MSK0, INT_MSK1, INT_MSK2, INT_MSK3), which referred general INT_MSKx. cleared, each INT_MSKx register prevents posted interrupt from becoming pending interrupt (input priority encoder). However, interrupt still post even mask zero. INT_MSKx bits independent other INT_MSKx bits. INT_MSKx set, interrupt source associated with that mask generate interrupt that will become pending interrupt. Table 68.Interrupt Mask (INT_MSK3) [0xDE] [R/W]
Field Read/Write Default ENSWINT
Enable Software Interrupt (ENSWINT) INT_MSK3[7] determines individual value written INT_CLRx register interpreted. When cleared, writing INT_CLRx register effect. However, writing INT_CLRx register, when ENSWINT cleared, will cause corresponding interrupt clear. ENSWINT set, written INT_CLRx registers ignored. However, written INT_CLRx register, while ENSWINT set, will cause interrupt post corresponding interrupt. Software interrupts debugging interrupt service routines eliminating need create system level interactions that sometimes necessary create hardware-only interrupt.
Reserved
Enable Software Interrupt (ENSWINT) Disable. Writing INT_CLRx register, when ENSWINT cleared, will cause corresponding interrupt clear Enable. Writing INT_CLRx register, when ENSWINT set, will cause corresponding interrupt post Reserved
Bits
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Table 69.Interrupt Mask (INT_MSK2) [0xDF] [R/W]
Reserved Field Read/Write Default Reserved Reserved GPIO Port Enable Reserved INT2 Enable 16-bit Counter Wrap Enable Reserved
Reserved Reserved Reserved GPIO Port Interrupt Enable Mask GPIO Port interrupt Unmask GPIO Port interrupt Reserved INT2 Interrupt Enable Mask INT2 interrupt Unmask INT2 interrupt 16-bit Counter Wrap Interrupt Enable Mask 16-bit Counter Wrap interrupt Unmask 16-bit Counter Wrap interrupt Reserved
Table 70.Interrupt Mask (INT_MSK1) [0xE1] [R/W]
Reserved Field Read/Write Default Reserved Prog Interval Timer Interrupt Enable Mask Prog Interval Timer interrupt Unmask Prog Interval Timer interrupt 1-ms Timer Interrupt Enable Mask 1-ms interrupt Unmask 1-ms interrupt Reserved Prog Interval Timer Enable 1-ms Timer Enable Reserved
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Table Interrupt Mask (INT_MSK0) [0xE0] [R/W]
Field Read/Write Default GPIO Port Enable Sleep Timer Enable INT1 Enable GPIO Port Enable Receive Enable Transmit Enable Reserved POR/LVD Enable
GPIO Port Interrupt Enable Mask GPIO Port interrupt Unmask GPIO Port interrupt Sleep Timer Interrupt Enable Mask Sleep Timer interrupt Unmask Sleep Timer interrupt INT1 Interrupt Enable Mask INT1 interrupt Unmask INT1 interrupt GPIO Port Interrupt Enable Mask GPIO Port interrupt Unmask GPIO Port interrupt Receive Interrupt Enable Mask Receive interrupt Unmask Receive interrupt Transmit Enable Mask Transmit interrupt Unmask Transmit interrupt Reserved POR/LVD Interrupt Enable Mask POR/LVD interrupt Unmask POR/LVD interrupt
Interrupt Vector Clear Register Table 72.Interrupt Vector Clear Register (INT_VC) [0xE2] [R/W]
Field Read/Write Default
Pending Interrupt [7:0]
Interrupt Vector Clear Register (INT_VC) holds interrupt vector highest priority pending interrupt when read, when written will clear pending interrupts Bits Pending Interrupt [7:0] 8-bit data value holds interrupt vector highest priority pending interrupt. Writing this register will clear pending interrupts
Microcontroller Function Register Summary
Addr 08-09 Name P0DATA P1DATA P2DATA P01CR P03CR- P04CR P07CR Output Enable P0.7 P1.7 Reserved Reserved P0.4/INT2 P1.4/SCLK P0.3/INT1 P1.3/SSEL Reserved P1.2 P0.1/ CLKOUT P1.1 Reserved P1.0 b-bb-bbbbbbbb-bb bbbbbbbb -bb-bbb -bbb-bbb Default 00000000 00000000 00000000 00000000 00000000 00000000
P1.6/SMISO P1.5/SMOSI
Reserved Thresh Thresh Thresh High Sink Reserved Reserved Open Drain Open Drain Open Drain
P2.1-P2.0 Pull-up Enable Pull-up Enable Pull-up Enable Output Enable Output Enable Output Enable
Reserved Reserved Enable
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Microcontroller Function Register Summary (continued)
Addr 11-13 Name P11CR P12CR P13CR P14CR- P16CR P17CR P2CR FRTMRL FRTMRH PITMRL PITMRH PIRL PIRH CPUCLKCR Reserved Reserved Reserved Prog Interval [7:0] Prog Interval [11:8] Select Reserved ITMRCLK Divider Gain[4:0] 32-kHz Bias Trim [1:0] SPIData[7:0] Swap First Comm Mode INT1 GPIO Port CPOL Receive CPHA Transmit Reserved GPIO Port Reserved INT2 16-bit Counter Wrap Reserved SCLK Select Reserved POR/LVD 32-kHz Freq Trim [3:0] ITMRCLK Select Reserved Output Reserved Reserved Reserved Enable Enable Enable Enable Enable Enable Reserved Threshold Reserved Reserved Reserved Thresh Reserved High Sink High Sink High Sink High Sink Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Reserved Pull-up Enable Pull-up Enable Pull-up Enable Pull-up Enable Pull-up Enable Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable -bb-b-b bbbb-bbb -bb-bbbb bbb-bbbb -bb-bbbb -bbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr Prog Interval Timer [11:8] -rrrr bbbbbbbb -rrrr Default 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
Free-Running Timer [7:0] Free-Running Timer [15:8] Prog Interval Timer [7:0]
TMRCLKCR IOSCTR LPOSCTR SPIDATA SPICR
TCAPCLK Divider foffset[2:0] 32-kHz Power Reserved
TCAPCLK Select
bbbbbbbb bbbbbbbb 0-bbbbbb bbbbbbbb bbbbbbbb bbbbbb-b -bb-b-bb-
10001111 000ddddd d-dddddd 00000000 00000000 00000000 00000000 00000000
INT_CLR0 GPIO Port Sleep Timer INT_CLR1 INT_CLR2 Reserved Reserved
Prog Interval 1-ms Timer Timer Reserved Reserved
INT_MSK3 INT_MSK2
ENSWINT Reserved Reserved Reserved GPIO Port Enable
Reserved Reserved INT2 Enable 16-bit Counter Wrap Enable Reserved
r-b-bb-
00000000 00000000
INT_MSK1
Reserved
Prog Interval 1-ms Timer Timer Enable Enable INT1 Enable GPIO Port Enable Receive Enable
Reserved
-bb-
00000000
INT_MSK0 GPIO Port Sleep Timer Enable Enable INT_VC RESWDT CPU_A CPU_X CPU_PCL CPU_PCH CPU_SP CPU_F CPU_SCR OSC_CR0 LVDCR ECO_TR VLTCMP GIES Reserved Reserved
Transmit Enable
Reserved
POR/LVD Enable
bbbbbb-b bbbbbbbb wwwwwww
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000010 00010100 00000000 00000000 00000000 00000000
Pending Interrupt [7:0] Reset Watchdog Timer [7:0] Temporary Register [7:0] X[7:0] Program Counter [7:0] Program Counter [15:8] Stack Pointer [7:0] WDRS Buzz PORS Super Sleep Carry Reserved Zero Reserved Speed [2:0] VM[2:0] Global Stop
-brbbb r-ccb-b -bbbbbb -bb-bbb
Reserved Reserved Sleep Duty Cycle [1:0]
Sleep Timer [1:0] Reserved Reserved Reserved
PORLEV[1:0]
PPOR
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Radio Function Register Summary
registers read writable, except where noted. Registers written read from either individually sequential groups. single-byte read write reads writes from addressed register. Incrementing burst read write sequence that begins with address, then reads writes to/from each register address order long clocking continues. possible repeatedly read (poll) single register using non-incrementing burst read. Table 73.Register Summary
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 RX_CFG_ADR 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x27 0x28 0x29 0x32 0x35 0x39 0x20 0x21 0x22 0x23 0x24 0x25 RX_IRQ_STATUS_ADR RX_STATUS_ADR RX_COUNT_ADR RX_LENGTH_ADR PWR_CTRL_ADR XTAL_CTRL_ADR IO_CFG_ADR GPIO_CTRL_ADR XACT_CFG_ADR FRAMING_CFG_ADR DATA32_THOLD_ADR DATA64_THOLD_ADR RSSI_ADR EOP_CTRL_ADR CRC_SEED_LSB_ADR CRC_SEED_MSB_ADR TX_CRC_LSB_ADR TX_CRC_MSB_ADR RX_CRC_LSB_ADR RX_CRC_MSB_ADR TX_OFFSET_LSB_ADR TX_OFFSET_MSB_ADR MODE_OVERRIDE_ADR RX_OVERRIDE_ADR TX_OVERRIDE_ADR CLK_OVERRIDE_ADR CLK_EN_ADR RX_ABORT_ADR AUTO_CAL_TIME_ADR AUTO_CAL_OFFSET_ADR ANALOG_CTRL_ADR TX_BUFFER_ADR RX_BUFFER_ADR SOP_CODE_ADR DATA_CODE_ADR PREAMBLE_ADR MFG_ID_ADR RSVD RSVD RSVD Used RSVD RSVD RSVD RSVD Used RSVD RXTX RSVD RSVD RSVD Used RXACK RSVD RSVD RSVD ABORT LVIRQ Mode Force XSIRQ MISO PACTL Used Used HINT SEED SEED STRIM Used AWAKE RXDR TXACK RSVD RSVD RSVD CRC0 OVRD RSVD RSVD RSVD STRIM Used RXCRC TXCRC RSVD RSVD RSVD Used RSVD RSVD Used 00000000 RSVD RSVD RSVD 00000000 00000000 00000000 00000011 00000000 RSVD RSVD SLOW 00000000 -Note Note Note wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww wwwwwwww rrrrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr bbbbbbbb Used TH64 RSSI RXOW SOFDET RXB16 HILO RXB8 CRC0 Mnemonic CHANNEL_ADR TX_LENGTH_ADR TX_CTRL_ADR TX_CFG_ADR TX_IRQ_STATUS_ADR RX_CTRL_ADR Used Used RSVD TXB15 IRQEN DATA CODE LENGTH TXB15 RXB16 IRQEN Used TXB8 IRQEN Channel Length TXB0 IRQEN TXBERR IRQEN IRQEN SETTING TXBERR RXBERR IRQEN Used RXBERR Code IRQEN RXOW IRQEN 00000000 00001-00000000 00000000 Used PACTL PACTL GPIO XOUT STATE TH32 MISO OUTV FREQ 3PIN PACTL GPIO 10100000 000-100 00000000 0000-1-000000 10100101 -0100 -01010 0-100000 10100100 00000000 00000000 -11111111 11111111 00000000 -0000 00000-0 0000000brrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbb-bbbb bbb-bbb bbbbbbbb bbbbrrrr b-bbbbbb bbbbbbbb -bbbb -bbbbb r-rrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbbbbbbb -bbbb wwwww-w bbbbbbb10111000 00000111 10010-10 rrrrrrrr bbbbbbbb bbbbb-bb IRQEN Default[4] -1001000 00000000 00000011 -000101 DATA MODE TXB8 RXB8 IRQEN TXB0 RXB1 IRQEN FAST TURN RXB1 Access[4] -bbbbbbb bbbbbbbb bbbbbbbb -bbbbbb
Data Mode
Count Length Used Used XOUT
XOUT XOUT Used Used MISO Used Used Used Used
AUTO_CAL_TIME_MAX AUTO_CAL_OFFSET_MINUS_4 RSVD RSVD
Register Files Buffer File Buffer File Code File Data Code File Preamble File File
Notes read/write, read only, write only, used, default value undefined. SOP_CODE_ADR default 0x17FF9E213690C782. DATA_CODE_ADR default PREAMBLE_ADR default 0x333302.
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Mnemonic Default Read/Write Function Bits Used
CHANNEL_ADR Channel
Address
0x00
This field selects channel. 0x00 sets 2400 MHz; 0x62 sets 2498 MHz. Values above 0x62 valid. default channel fast channel above frequency typically used non-overlapping WiFi systems. write this register will impact time takes synthesizer settle. fast (100-µs) medium (180-µs) slow (270-µs) Usable channels subject regulation. access modify register during transmit receive.
Mnemonic Default Read/Write Function Bits
TX_LENGTH_ADR Length
Address
0x01
This register sets length packet transmitted. length zero valid, will transmit packet with SOP, length CRC16 fields enabled), data field. Packet lengths more than bytes will require that some data bytes written after transmission packet begun. Typically, length updated prior setting maximum packet length packets bytes except framed 64-chip where maximum packet length bytes.
Maximum packet length limited delta between transmitter receiver crystals 60-ppm better.
Mnemonic Default Read/Write Function
TX_CTRL_ADR TXB15 IRQEN TXB8 IRQEN TXB0 IRQEN TXBERR IRQEN
Address IRQEN
0x02
IRQEN
Start Transmission. Setting this triggers transmission packet. Writing this flag effect. This cleared automatically packet transmission. transmit buffer loaded either before after setting this bit. data loaded after setting this bit, length time available load buffer depends starting state (sleep, idle synth), length code, length preamble, packet data rate. example, starting from idle mode fast channel mode with chip codes time available (synth start) (preamble) (SOP length) (length byte) there bytes buffer transmission length field, TXBERR will occur. Clear Buffer. Writing this register clears transmit buffer. Writing this effect. previous packet retransmitted setting setting this bit. transmit packet loaded transmitted without setting this after packet loaded buffer. TX_BUFFER_ADR loaded after been set, then this should before loading transmit packet buffer before set. Buffer Full Interrupt Enable. TX_IRQ_STATUS_ADR description. Buffer Half Empty Interrupt Enable. TX_IRQ_STATUS_ADR description. Buffer Empty Interrupt Enable. TX_IRQ_STATUS_ADR description. Buffer Error Interrupt Enable. TX_IRQ_STATUS_ADR description. Transmission Complete Interrupt Enable. TX_IRQ_STATUS_ADR description. IRQEN IRQEN must together. Transmit Error Interrupt Enable. TX_IRQ_STATUS_ADR description. IRQEN IRQEN must together.
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CYRF69103
Mnemonic Default Read/Write Function Bits Bits Used Used
TX_CFG_ADR Data Code Length Data Mode
Address Setting
0x03
Data Code Length. This selects length DATA_CODE_ADR code data portion packet. This ignored when data mode GFSK. chip codes. chip codes. Data Mode. This field sets data transmission mode. 1-Mbps GFSK, Mode, Mode, Mode. recommended that firmware sets SLOW register ANALOG_CTRL_ADR when using GFSK data rate mode. Setting. This field sets transmit signal strength. dBm, dBm, dBm, dBm, dBm, dBm, dBm, dBm.
Mnemonic Default Read/Write Function
TX_IRQ_STATUS_ADR TXB15 TXB8 TXB0 TXBERR
Address
0x04
state status bits valid regardless whether enabled. output device active state whenever more bits this register corresponding enable also set. Status bits non-atomic (different flags change value different times response single event). particular, standard error handling only effective premature termination transmission exception does leave device inconsistent state. Oscillator Stable Status. This when internal crystal oscillator settled (synthesizer sequence starts). Voltage Interrupt Status. This when voltage VBAT below threshold (see PWR_CTL_ADR). This interrupt automatically disabled whenever disabled. When enabled, this reflects voltage VBAT. Buffer Full Interrupt Status. This whenever there fewer bytes remaining transmit buffer. Buffer Half Empty Interrupt Status. This whenever there fewer bytes remaining transmit buffer. Buffer Empty Interrupt Status. This time that transmit buffer empty. Buffer Error Interrupt Status. This triggered either events: When transmit buffer (TX_BUFFER_ADR) empty number bytes remaining transmitted greater than zero; When byte written transmit buffer buffer already full. This cleared setting TX_CTRL_ADR. Transmission Complete Interrupt Status. This triggered when transmission complete. transaction mode enabled then this interrupt triggered immediately after transmission last CRC16. transaction mode enabled, this interrupt triggered transaction. Reading this register clears this bit. flags change value different times response single event. transaction mode enabled first read this register returns then firmware must execute second read this register determine error occurred examining status TXE. There case when this triggered when there error transmission. first read this register returns then firmware must execute second read this register given transaction. received asserted instead IRQ. Transmit Error Interrupt Status. This triggered when there error transmission. This interrupt only applicable transaction mode. triggered whenever valid packet received within timeout period. Reading this register clears this bit.
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CYRF69103
Mnemonic Default Read/Write Function RSVD
RX_CTRL_ADR RXB16 IRQEN RXB8 IRQEN RXB1 IRQEN RXBERR IRQEN
Address IRQEN
0x05
IRQEN
Status bits non-atomic (different flags change value different times response single event). Start Receive. Setting this causes device transition receive mode. necessary, crystal oscillator synthesizer will start automatically after this set. Firmware must never clear this bit. This must until after self clears. recommended method exit receive mode when error occurred force STATE then dummy read RX_COUNT_ADR bytes from RX_BUFFER_ADR poll RSSI_ADR.SOP (bit until set. XACT_CFG_ADR RX_ABORT_ADR description. Start Packet Detect Interrupt Enable. RX_IRQ_STATUS_ADR description. Buffer Full Interrupt Enable. RX_IRQ_STATUS_ADR description. Buffer Half Empty Interrupt Enable. RX_IRQ_STATUS_ADR description. Buffer Empty Interrupt Enable. RX_IRQ_STATUS_ADR description. Buffer Error Interrupt Enable. RX_IRQ_STATUS_ADR description. Packet Reception Complete Interrupt Enable. RX_IRQ_STATUS_ADR description. Receive Error Interrupt Enable. RX_IRQ_STATUS_ADR description.
Mnemonic Default Read/Write Function
RX_CFG_ADR HILO FAST TURN Used
Address RXOW
0x06
Status bits non-atomic (different flags change value different times response single event). Automatic Gain Control (AGC) Enable. When this set, enabled, controlled circuit. When this cleared controlled manually using bit. Typical applications will clear this during initialization. recommended that this disabled (LNA) enabled unless device will used system where receive data from device using external transmit signals dBm. Noise Amplifier (LNA) Manual Control. When (Bit cleared, this controls state receiver LNA; when set, this effect. Setting this enables LNA; clearing this disabl
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