PSoCMixed Signal Array Preliminary Data Sheet Silicon Revision Oc
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PSoCMixed Signal Array Preliminary Data Sheet Silicon Revision
October 2003 Cypress MicroSystems 2700 162nd Street Building Lynnwood, 98037 Phone: 800.669.0557 FAX: 425.787.4641 http://www.cypress.com Document 38-12011 Rev.
CY8C24xxx Preliminary Data Sheet
Cypress MicroSystems, Inc. 2000 -2003. rights reserved. PSoC(Programmable System-on-ChipTM) trademark Cypress MicroSystems, Inc. other trademarks registered trademarks referenced herein property respective corporations. information contained herein subject change without notice. Cypress MicroSystems assumes responsibility circuitry other than circuitry embodied Cypress MicroSystems product. does convey imply license under patent other rights. Cypress MicroSystems does authorize products critical components life support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress MicroSystems' products life-support system applications implies that manufacturer assumes risk such doing indemnifies Cypress MicroSystems against charges.
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Contents
SECTION OVERVIEW
Features Getting Started Development Kits Tele-Training Consultants Technical Support Top-Level Architecture Development Tools PSoC Designer Software Subsystems Hardware Tools User Modules Development Process Ordering Information Organization Conventions Document Organization Document Conventions
Information
Summary Pinouts Packaging Dimensions.27 Thermal Impedances
Packaging Information
SECTION CORE ARCHITECTURE
Top-Level Core Architecture Core Register Summary
Core (M8C)
Internal Registers Address Spaces Instruction Summary.39 Instruction Format 3.4.1 One-Byte Instructions.40 3.4.2 Two-Byte Instructions.40 3.4.3 Three-Byte Instructions Addressing Modes 3.5.1 Source Immediate 3.5.2 Source Direct 3.5.3 Source Indexed 3.5.4 Destination Direct.42 3.5.5 Destination Indexed
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3.5.6 Destination Direct Source Immediate 3.5.7 Destination Indexed Source Immediate 3.5.8 Destination Direct Source Direct.44 3.5.9 Source Indirect Post Increment.44 3.5.10 Destination Indirect Post Increment Register Definitions.45 3.6.1 CPU_F (Flag) Register Architectural Description 4.1.1 Additional SROM Feature 4.1.2 SROM Function Descriptions.48 Register Definitions.51 4.2.1 CPU_SCR1 Register Clocking Architectural Description Register Definitions.55 5.2.1 INT_CLRx Register.55 5.2.2 INT_MSKx Register 5.2.3 INT_VC Register.55 5.2.4 CPU_F Register.55 Architectural Description Register Definitions.60 6.2.1 PRTxDR Registers.60 6.2.2 PRTxIE Registers 6.2.3 PRTxGS Registers.60 6.2.4 PRTxDMx Registers 6.2.5 PRTxICx Registers Register Definitions.63 7.1.1 ABF_CR0 Register Register Definitions.65 8.1.1 IMO_TR Register Register Definitions.67 9.1.1 ILO_TR Register External Components.70 Register Definitions.70 10.2.1 OSC_CR0 Register.70 10.2.2 ECO_TR Register 10.2.3 CPU_SCR1 Register Register Definitions.73 11.1.1 OSC_CR0 Register.73 11.1.2 OSC_CR2 Register.74
Supervisory (SROM)
Interrupt Controller
General Purpose (GPIO)
Analog Output Drivers
Internal Main Oscillator (IMO)
Internal Speed Oscillator (ILO)
Crystal Oscillator (ECO)
10.1 10.2
Phase Locked Loop (PLL)
11.1
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Sleep Watchdog
12.1 Architectural Description 12.1.1 Clock Selection 12.1.2 Sleep Timer 12.1.3 Sleep Bit.76 Application Description.76 Register Definitions 12.3.1 INT_MSK0 Register 12.3.2 RES_WDT Register 12.3.3 OSC_CR0 Register.77 12.3.4 CPU_SCR1 Register.78 12.3.5 ILO_TR Register 12.3.6 ECO_TR Register 12.3.7 CPU_SCR0 Register.78 Timing Diagrams 12.4.1 Sleep Sequence.79 12.4.2 Wake Sequence 12.4.3 Bandgap Refresh 12.4.4 Watchdog Timer (WDT) Power Consumption.82
12.2 12.3
12.4
12.5
SECTION REGISTER REFERENCE
Register Conventions Register Mapping Tables Register Table: User Space Register Table: Configuration Space
Register Details
13.1 Bank Registers.88 13.1.1 PRTxDR 13.1.2 PRTxIE 13.1.3 PRTxGS 13.1.4 PRTxDM2 13.1.5 DxBxxDR0 13.1.6 DxBxxDR1 13.1.7 DxBxxDR2 13.1.8 DxBxxCR0 13.1.9 DxBxxCR0 13.1.10 DxBxxCR0 13.1.11 DxBxxCR0 13.1.12 DCBxxCR0 13.1.13 DCBxxCR0 .100 13.1.14 DCBxxCR0 .101 13.1.15 DCBxxCR0 .102 13.1.16 AMX_IN .103 13.1.17 ARF_CR .104 13.1.18 CMP_CR0 .105 13.1.19 ASY_CR .106 13.1.20 CMP_CR1 .107 13.1.21 ACBxxCR3 .108 13.1.22 ACBxxCR0 .109 13.1.23 ACBxxCR1 .110 13.1.24 ACBxxCR2 .111 13.1.25 ASCxxCR0 .112
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13.2
13.1.26 ASCxxCR1 .113 13.1.27 ASCxxCR2 .114 13.1.28 ASCxxCR3 .115 13.1.29 ASDxxCR0 .116 13.1.30 ASDxxCR1 .117 13.1.31 ASDxxCR2 .118 13.1.32 ASDxxCR3 .119 13.1.33 RDIxRI .120 13.1.34 RDIxSYN .121 13.1.35 RDIxIS .122 13.1.36 RDIxLT0 .123 13.1.37 RDIxLT1 .124 13.1.38 RDIxRO0 .125 13.1.39 RDIxRO1 .126 13.1.40 I2C_CFG .127 13.1.41 I2C_SCR .128 13.1.42 I2C_DR .129 13.1.43 I2C_MSCR .130 13.1.44 INT_CLR0 .131 13.1.45 INT_CLR1 .133 13.1.46 INT_CLR3 .134 13.1.47 INT_MSK3 .135 13.1.48 INT_MSK0 .136 13.1.49 INT_MSK1 .137 13.1.50 INT_VC .138 13.1.51 RES_WDT .139 13.1.52 DEC_DH .140 13.1.53 DEC_DL .141 13.1.54 DEC_CR0 .142 13.1.55 DEC_CR1 .143 13.1.56 MUL_X .144 13.1.57 MUL_Y .145 13.1.58 MUL_DH .146 13.1.59 MUL_DL .147 13.1.60 MAC_X/ACC_DR1 .148 13.1.61 MAC_Y/ACC_DR0 .149 13.1.62 MAC_CL0/ACC_DR3 .150 13.1.63 MAC_CL1/ACC_DR2 .151 13.1.64 CPU_F .152 13.1.65 CPU_SCR1 .153 13.1.66 CPU_SCR0 .154 Bank Registers.155 13.2.1 PRTxDM0 .155 13.2.2 PRTxDM1 .156 13.2.3 PRTxIC0 .157 13.2.4 PRTxIC1 .158 13.2.5 DxBxxFN .159 13.2.6 DxBxxIN .161 13.2.7 DxBxxOU .162 13.2.8 CLK_CR0 .164 13.2.9 CLK_CR1 .165 13.2.10 ABF_CR0 .166 13.2.11 AMD_CR0 .167 13.2.12 AMD_CR1 .168
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13.2.13 13.2.14 13.2.15 13.2.16 13.2.17 13.2.18 13.2.19 13.2.20 13.2.21 13.2.22 13.2.23 13.2.24 13.2.25 13.2.26 13.2.27 13.2.28
ALT_CR0 .169 GDI_O_IN .170 GDI_E_IN .171 GDI_O_OU .172 GDI_E_OU .173 OSC_CR4 .174 OSC_CR3 .175 OSC_CR0 .176 OSC_CR1 .177 OSC_CR2 .178 VLT_CR .179 VLT_CMP .180 IMO_TR .181 ILO_TR .182 BDG_TR .183 ECO_TR .184
SECTION DIGITAL SYSTEM
Top-Level Digital Architecture .185 Digital Register Summary .186
Global Digital Interconnect (GDI)
14.1 14.2 Architectural Description .187 Register Definitions .189 14.2.1 GDI_O_IN GDI_E_IN Registers.189 14.2.2 GDI_O_OU GDI_E_OU Registers .189 Architectural Description .191 Architectural Description .193 Register Definitions .196 16.2.1 RDIxRI Register .196 16.2.2 RDIxSYN Register .196 16.2.3 RDIxIS Register .196 16.2.4 RDIxLTx Registers .197 16.2.5 RDIxROx Registers.197 Timing Diagram .197 Architectural Description .199 17.1.1 Input Multiplexers .199 17.1.2 Input Clock Resynchronization.200 17.1.3 Output De-Multiplexers .201 17.1.4 Block Chaining Signals .201 17.1.5 Timer Function .201 17.1.6 Counter Function.202 17.1.7 Dead Band Function .202 17.1.8 CRCPRS Function .204 17.1.9 Protocol Function .205 17.1.10 Master Function.206 17.1.11 Slave Function.206 17.1.12 Asynchronous Transmitter Function.207 17.1.13 Asynchronous Receiver Function .207
Array Digital Interconnect (ADI)
15.1 16.1 16.2
Digital Interconnect (RDI)
16.3 17.1
Digital Blocks
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17.2
17.3
Register Definitions.208 17.2.1 DxBxxDRx Registers .208 17.2.2 DxBxxCR0 Register .213 17.2.3 INT_MSK1 Register .213 17.2.4 DxBxxFN Registers.213 17.2.5 DxBxxIN Registers.214 17.2.6 DxBxxOU Registers .214 Timing Diagrams.214 17.3.1 Timer Timing .215 17.3.2 Counter Timing .216 17.3.3 Dead Band Timing .216 17.3.4 CRCPRS Timing .218 17.3.5 Mode Timing .218 17.3.6 SPIM Timing .219 17.3.7 SPIS Timing .222 17.3.8 Transmitter Timing .225 17.3.9 Receiver Timing .226
SECTION ANALOG SYSTEM
Top-Level Analog Architecture .229 Analog Register Summary .231
Analog Interface
18.1 Architectural Description .233 18.1.1 Analog Data Interface .233 18.1.2 Analog Comparator Interface.233 18.1.3 Analog Column Clock Generation.235 18.1.4 Decimator Incremental Interface .236 18.1.5 Analog Modulator Interface (Mod Bits) .236 18.1.6 Analog Synchronization Interface (Stalling) .236 18.1.7 Hardware Acceleration .236 Register Definitions.238 18.2.1 CMP_CR0 Register .238 18.2.2 CMP_CR1 Register .238 18.2.3 ASY_CR Register .238 18.2.4 DEC_CR0 Register.239 18.2.5 DEC_CR1 Register.239 18.2.6 CLK_CR0 Register .240 18.2.7 CLK_CR1 Register .240 18.2.8 AMD_CR0 Register .240 18.2.9 AMD_CR1 Register .240 18.2.10 ALT_CR0 Register .240 Architectural Description .241 19.1.1 Analog Comparator Bus.243 Temperature Sensing Capability.243 Register Definitions.245 20.1.1 AMX_IN Register .245 20.1.2 ABF_CR0 Register .245 Architectural Description .246
18.2
Analog Array
19.1 19.2 20.1
Analog Input Configuration
20.2
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Analog Reference
21.1 21.2 Architectural Description .247 Register Definitions .248 21.2.1 ARF_CR Register .248 Architectural Description .250 Application Description.251 Register Definitions .251 22.3.1 ASCxxCR0 Register.252 22.3.2 ASCxxCR1 Register.252 22.3.3 ASCxxCR2 Register.252 22.3.4 ASCxxCR3 Register.253 22.3.5 ASDxxCR0 Register.253 22.3.6 ASDxxCR1 Register.253 22.3.7 ASDxxCR2 Register.253 22.3.8 ASDxxCR3 Register.254 Architectural Description .255 Register Definitions .257 23.2.1 ACBxxCR0 Register.257 23.2.2 ACBxxCR1 Register.257 23.2.3 ACBxxCR2 Register.257 23.2.4 ACBxxCR3 Register.257
Switched Capacitor Block
22.1 22.2 22.3
Continuous Time Block
23.1 23.2
SECTION SYSTEM RESOURCES
Top-Level System Resources Architecture .261 System Resources Register Summary .262
Digital Clocks
24.1 Architectural Description .263 24.1.1 Internal Main Oscillator .263 24.1.2 Internal Speed Oscillator .264 24.1.3 Crystal Oscillator.264 24.1.4 External Clock .264 Register Definitions .266 24.2.1 INT_CLR0 Register.266 24.2.2 INT_MSK0 Register .266 24.2.3 OSC_CR0 Register.266 24.2.4 OSC_CR1 Register.267 24.2.5 OSC_CR2 Register.267 24.2.6 OSC_CR3 Register.268 24.2.7 OSC_CR4 Register.268 Architectural Description .269 Application Description.270 25.2.1 Multiplication with Accumulation.270 25.2.2 Accumulation After Multiplication .270 Register Definitions .270 25.3.1 MUL_X Register.270 25.3.2 MUL_Y Register.270 25.3.3 MUL_DH Register .270 25.3.4 MUL_DL Register.270 25.3.5 MAC_X/ACC_DR1 .270
24.2
Multiply Accumulate (MAC)
25.1 25.2
25.3
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25.3.6 25.3.7 25.3.8 26.1
MAC_Y/ACC_DR0.271 MAC_CL0/ACC_DR3.271 MAC_CL1/ACC_DR2.271
Decimator
Register Definitions.273 26.1.1 DEC_DH Register.273 26.1.2 DEC_DL Register .274 26.1.3 DEC_CR0 Register.274 26.1.4 DEC_CR1 Register.274 Architectural Description .276 27.1.1 Basic Data Transfer.276 Application Description .277 27.2.1 Slave Operation .277 27.2.2 Master Operation .278 Register Definitions.279 27.3.1 I2C_CFG Register .279 27.3.2 I2C_SCR Register .281 27.3.3 I2C_DR Register.283 27.3.4 I2C_MSCR Register .283 Timing Diagrams.284 27.4.1 Clock Generation .284 27.4.2 Enable Command Synchronization.285 27.4.3 Basic Input/Output Timing.285 27.4.4 Status Timing .286 27.4.5 Master Start Timing .287 27.4.6 Master Restart Timing .288 27.4.7 Master Stop Timing .288 27.4.8 Master/Slave Stall Timing .289 27.4.9 Master Lost Arbitration Timing .289 27.4.10 Master Clock Synchronization .290 Register Definitions.291 28.1.1 VLT_CR Register .291 28.1.2 VLT_CMP Register .291 Architectural Description .293 Register Definitions.293 29.2.1 BDG_TR Register .293 Register Definitions.296 30.1.1 VLT_CR Register .296 Register Definitions.297 31.1.1 CPU_SCR0 Register .297 31.1.2 CPU_SCR1 Register .298 Timing Diagrams.298 31.2.1 Power Reset (POR) .298 31.2.2 External Reset (XRES) .298 31.2.3 Watchdog Timer Reset (WDR) .298 31.2.4 Reset Details.300
27.1 27.2
27.3
27.4
28.1
Internal Voltage Reference
29.1 29.2
Switch Mode Pump (SMP)
30.1
System Resets
31.1
31.2
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31.3
Power Consumption.301
SECTION ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings .304 Operating Temperature .304 Electrical Characteristics .305 Chip-Level Specifications .305 General Purpose (GPIO) Specifications .305 Operational Amplifier Specifications .306 Analog Output Buffer Specifications .308 Switch Mode Pump Specifications .309 Analog Reference Specifications .310 Analog PSoC Block Specifications .311 Specifications .312 Programming Specifications .313 Electrical Characteristics .314 Chip-Level Specifications .314 General Purpose (GPIO) Specifications .314 Operational Amplifier Specifications .315 Digital Block Specifications .317 Analog Output Buffer Specifications .318 External Clock Specifications .319 Programming Specifications .319 Specifications .320
SECTION REVISION HISTORY
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SECTION
OVERVIEW
PSoCfamily consists many Mixed Signal Array with On-Chip Controller devices. These devices designed replace multiple traditional MCU-based system components with one, cost single-chip programmable component. PSoC device includes configurable blocks analog digital logic, well programmable interconnect. This architecture allows user create customized peripheral configurations, match requirements each individual application. Additionally, fast CPU, Flash program memory, SRAM data memory, configurable included range convenient pin-outs. Overview section discusses Features, Getting Started, Top-Level Architecture, Development Tools, User Modules Development Process, along with Ordering Information. also lists Conventions used this document. This section encompasses following chapters:
Information page
Packaging Information page
Features
Powerful Harvard Architecture Processor -M8C Processor Speeds Multiply, 32-Bit Accumulate -Low Power High Speed -3.0 5.25 Operating Voltage -Operating Voltages Down Using On-Chip Switch Mode Pump (SMP) -Industrial Temperature Range: -40°C +85°C Advanced Peripherals (PSoC Blocks) Rail-to-Rail Analog PSoC Blocks Provide: 14-Bit ADCs 8-Bit DACs -Programmable Gain Amplifiers -Programmable Filters Comparators Digital PSoC Blocks Provide: 32-Bit Timers, Counters PWMs -CRC Modules -Full-Duplex UART -Multiple Masters Slaves -Connectable GPIO Pins -Complex Peripherals Combining Blocks Flexible On-Chip Memory Bytes Flash Program Storage 50,000 Erase/Write Cycles -256 Bytes SRAM Data Storage -In-System Serial Programming (ISSP) -Partial Flash Updates -Flexible Protection Modes -EEPROM Emulation Flash
Precision, Programmable Clocking -Internal 2.5% 24/48 Oscillator -High-Accuracy with Optional Crystal -Optional External Oscillator, -Internal Oscillator Watchdog Sleep Programmable Configurations Drive GPIO -Pull Pull down, High Strong, Open Drain Drive Modes GPIO Analog Inputs GPIO -Two Analog Outputs GPIO -Configurable Interrupt GPIO Additional System Resources -I2C Slave, Master, Multi-Master -Watchdog Sleep Timers -User-Configurable Voltage Detection -Integrated Supervisory Circuit -On-Chip Precision Voltage Reference
Complete Development Tools -Free Development Software (PSoC Designer) -Full-Featured, In-Circuit Emulator Programmer: Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory
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Getting Started
quickest path understanding PSoC silicon through PSoC Designer software GUI. This data sheet useful understanding details PSoC integrated circuit, good starting point PSoC developer seeking general overview this technology. PSoC developers required build their ADCs, DACs, other peripherals. Embedded PSoC Designer software individual data sheets, performance graphs, PSoC User Modules (graphically selected code packets) peripherals, such incremental ADCs, DACs, controllers, amps, low-pass filters, etc. With simple GUI-based selection, placement, connection, basic architecture design developed within PSoC Designer software without ever writing single line code.
Development Kits
Development Kits available from following distributors: Digi-Key, Avnet, Arrow, Future. Cypress.com Online Store contains development kits, compilers, accessories PSoC development. Online Store site click PSoC (Programmable System-on-Chip) view current list available items.
Tele-Training
PSoC "Tele-training" available beginners every Friday Pacific Time taught live marketing application engineer over phone. Please more details. Five training classes available accelerate learning curve including introduction, designing, debugging, advanced design, advanced analog, well application-specific classes covering topics like PSoC bus.
Consultants
Certified PSoC Consultants offer everything from technical assistance completed PSoC designs. contact become PSoC Consultant following site,
Technical Support
PSoC application engineers take pride fast accurate response. They reached with 4-hour guaranteed response
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Top-Level Architecture
figure below illustrates top-level architecture PSoc CY8C24xxx.
SYSTEM
Port
Port
Port
Analog Drivers
Global Digital Interconnect Global Analog Interconnect
PSoC CORE
SRAM Interrupt Controller Supervisory (SROM) Flash Nonvolatile Memory
Core (M8C)
Sleep Watchdog
Internal Main Oscillator (IMO)
Internal Speed Oscillator (ILO) Phased Locked Loop (PLL)
Crystal Oscillator (ECO)
DIGITAL SYSTEM
Digital PSoC Block Array
ANALOG SYSTEM
Analog PSoC Block Array Analog Refs Analog Input Muxing
Digital
Analog Column
Digital Clocks
Multiply Accumulate (MAC)
Decimator
System Resets
Internal Voltage Reference
Switch Mode Pump
SYSTEM RESOURCES
PSoC CY8C24xxx Top-Level Block Diagram
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Development Tools
Cypress MicroSystems PSoC Designer Microsoft® Windows-based, integrated development environment Programmable System-on-Chip (PSoC) devices. PSoC Designer runs Windows Windows 4.0, Windows 2000, Windows Millennium (Me), Windows (Reference PSoC Designer Functional Flow diagram below.) PSoC Designer helps customer select operating configuration PSoC, write application code that uses
Graphical Designer Interface
Commands
PSoC, debug application. This system provides design database management project, integrated debugger with In-Circuit Emulator, in-system programming support, CYASM macro assembler CPUs. PSoC Designer also supports high-level language compiler developed specifically devices family.
Context Sensitive Help
Results
Importable Design Database
Device Database
PSoC Configuration Sheet
Application Database
Project Database
Manufacturing Information File
User Modules Database
Emulation
In-Circuit Emulator
Device Programmer
PSoC Designer Subsystems
PSoC Designer Software Subsystems
Device Editor
PSoC Designer several main functions. Design Editor easily configure design APIs automatically generated user modules. Device Editor subsystem allows user select different onboard analog digital components called user modules using PSoC blocks. Examples user modules ADCs, DACs, Amplifiers, Filters. device editor also supports easy development multiple configurations dynamic reconfiguration. Dynamic configuration allows changing configuration time. PSoC Designer sets power-on initialization tables selected PSoC block configurations creates source code application framework. framework contains software operate selected components and, project uses more than operating configuration, contains routines switch between different sets PSoC block configurations runtime. PSoC Designer print configuration sheet given project configuration during application programming conjunction with Device Data Sheet. Once framework generated, user application-specific code flesh framework. It's also possible change selected components regenerate framework.
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Design Browser
Design Browser allows users select import preconfigured designs into user's project. User's easily browse catalog preconfigured designs facilitate timeto-design. Recent examples provided tools include 300-baud modem, master slave, controller, magnetic card reader.
Online Help System
online help system displays online, context-sensitive help user. Designed procedural quick reference, each functional subsystem context-sensitive help. This system also provides tutorials links FAQs Online Support Forum designer getting started.
Application Editor
Application Editor edit your language Assembly language source code. also assemble, compile, link, build.
Assembler. macro assembler allows assembly code merged seamlessly with code. link libraries automatically absolute addressing compiled relative mode, linked with other software modules absolute addressing. Language Compiler. ANSI language compiler supports Cypress MicroSystems' PSoC family devices (except 64-bit doubles). Even have never worked language before, product quickly allows create complete programs PSoC family devices.
Hardware Tools
In-Circuit Emulator
cost, high functionality (In-Circuit Emulator) available development support. This hardware capability program single devices. emulation consists base unit that connects parallel port. base unit universal will operate with PSoC devices. Emulation pods each device family available separately. emulation takes place PSoC device target board performs full speed MHz) operation.
embedded, optimizing compiler provides features tailored PSoC architecture. comes complete with embedded libraries providing port operations, standard keypad display support, extended math functionality.
Debugger
PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing designer test program physical system while providing internal view PSoC device. Debugger commands allow designer read write program data memory, read write registers, read write registers, clear breakpoints, provide program run, halt, step control. debugger also allows designer create trace buffer registers memory locations interest.
PSoC Development Tool
User Modules Development Process
development process PSoC different than traditional fixed function microcontroller. flexibility PSoC architecture comes from configurable analog digital hardware blocks called PSoC Blocks. These blocks have capability implement wide variety user selectable functions. Each block several registers that allow select function. These registers also determine interconnections between this block other blocks, well connection pins. (Reference Figure below.) make entire development process your project easier, PSoC Designer Integrated Development Environment (IDE) libraries open source code software modules, called "User Modules," that simplify configuration process. These user modules have been created make selecting implementing peripheral functions very easy. User modules come analog, digital, mixed signal varieties. Each user module contains register settings implement selected function also contains Application Programmer Interface (API) software make interface your source code simple. development process starts when open project. than pick user modules, basis custom configuration that project. view details available user modules inside development software pick user modules that perfect your application. then must assign each these user
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modules hardware resources. also make interconnections between user modules, between user modules pins. This process step takes place Device Editor subsystem within PSoC Designer. There views inside this step: selecting user
modules assigning them hardware blocks interconnecting them. last action this step "Generate Application," which causes development software automatically generate required files selected configuration.
Device Editor
Browse libraries User Module View datasheets User Modules Select individual User Modules configuration Calculate resource requirements slected User Modules
User Module Selection View
Assign User Modules Hardware PSoC Blocks Make interconnections between User Modules Make interconnections device pins
User Module Placement View
"Generate Application"
Application Editor
Edit source code files written Assembly language Assemble/Compile breakpoints "Make" function generation enitre project including subfiles
Source Code Editor
"Make" Automatic Object Code Generation
Interface In-Circuit Emulator debug Define complex break events Enable trace capability View contents program/ register/ram space Run/stop/step program
Debugger
Interface In-Circuit Emulator
User Modules Development Process Flow Chart
next step process write your main program, other sub-routines required your application. This step takes place Application Editor subsystem. will have subroutines automatically generated user modules have chosen source code these routines viewed this step well. different files created project contained tree structure easy reference. development software
handy "Make" function, which assembles compiles source files, links them into object file ready debugging process. last step development takes place Debugger subsystem. This where object code downloaded into In-Circuit Emulator run. Debugger both interface also contains advanced
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tools finding removing bugs from your software. Some capabilities tools full-speed emula-
tion, defining complex breakpoint events, large trace memory.
Ordering Information
following table lists PSoC Device family's features ordering codes.
PSoC Device Family Features
Analog PSoC Blocks Digital PSoC Blocks Temperature Range Switch Mode Pump Analog Outputs
Ordering Code
Flash (Kbytes)
Digital Pins
Analog Inputs
(Columns
(Bytes)
(Rows
(300 Mil) (150 Mil) SOIC (300 Mil) (210 Mil) SSOP (210 Mil) SSOP (Tape Reel) (300 Mil) SOIC (300 Mil) SOIC (Tape Reel) (300 Mil) (210 Mil) SSOP (210 Mil) SSOP (Tape Reel) (300 Mil) SOIC (300 Mil) SOIC (Tape Reel) (5x5
CY8C24123-24PI CY8C24123-24SI CY8C24223-24PI CY8C24223-24PVI CY8C24223-24PVIT CY8C24223-SI CY8C24223-SIT CY8C24423-24PI CY8C24423-24PVI CY8C24423-24PVIT CY8C24423-SI CY8C24423-SIT CY8C24423-24LFI
-40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C
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Package
SECTION OVERVIEW
CY8C24xxx Preliminary Data Sheet
Organization Conventions
Document Organization
This document organized into following sections:
Units Measure
following table lists units measure used this document.
Symbol
Overview Architecture Registers Digital System Analog System System Resources Electrical Specifications Revision History
Units Measure degree Celsius alternating current decibels direct current femto Farad hertz kilo, 1000 210, 1024 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microsecond microvolts microvolts root-mean-square milliampere millisecond millivolts nanoampere nanosecond nanovolts pico Farad peak-to-peak parts million samples second sigma: standard deviation volts
Kbit
Each section associated chapters organized according PSoC functionality. applicable, chapters have brief introduction, architectural/application description, register definitions, timing diagrams. last section, Electrical Specifications, chapters associated with presents PSoC device's electrical specifications. Revision History section chronologically lists document's history.
Document Conventions
Register Conventions
following table lists register conventions that specific this document.
Convention register name Empty, grayedout table cell Example ACBxxCR1 RW:00 R:00 W:00 RL:00 RC:00 RW:00 RW:XX 0,04h x,F7h Description Multiple instances/address ranges same register. Read write register bit(s) Read register bit(s) Write register bit(s) Logical register bit(s) Clearable register bit(s) Reset value 0x00 Register reset Register bank Register bank Register exists register bank register bank Reserved group bits, unless otherwise stated.
µVrms
Numeric Naming
Hexidecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexidecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (for example, 01010100b' `01000011b'). Numbers indicated decimal.
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SECTION OVERVIEW
Acronyms Used
following table lists acronyms that used this document.
Acronym APOR CMRR EEPROM GPIO IPOR ISSP LFSR MISO MOSI PDDSC PPOR PSoCPSRR alternating current analog input application programming interface analog power reset broadcast clock common mode rejection ratio central processing unit cyclic redundancy check continuous time digital-to-analog converter direct current differential nonlinearity digital data output external crystal oscillator electrically erasable programmable read-only memory feedback full scale range global interrupt enable general purpose in-circuit emulator integrated development environment internal speed oscillator integral nonlinearity input/output write imprecise power reset interrupt request acknowledge interrupt request interrupt service routine in-circuit system serial programming interrupt vector read linear feedback shift register pass filter least-significant lookup table master-in-slave-out master-out-slave-in most-significant program counter power down power system sleep duty cycle programmable gain amplifier power reset precision power reset pseudo random sequence Programmable System-on-Chip power supply rejection ratio process voltage temperature pulse width modulator Description Acronym RETI random access memory access strobe return from interrupt input output read only memory successive approximation register switched capacitor signal-to-noise ratio start instruction stack pointer sequential phase detector serial peripheral interconnect terminal count voltage controlled oscillator watchdog timer watchdog reset Description
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Information
This chapter lists, describes, illustrates PSoC device pins pinouts. Table presents summary device pins, following tables illustrations detail representation device's pinouts.
Summary
Name Description Switch Mode Pump Supply Voltage Ground External Reset (Active High) Port 0[0], 0[1], 0[2], Analog Input Port 0[3], Analog Input/Output Port 0[4], Analog Input Port 0[5], Analog Input/Output Port 0[6], 0[7], Analog Input Port 1[0], XTALOut/SDATA Port 1[1], XTALIn/SCLK Port 1[2] Port 1[3] Port 1[4], EXTCLK Port 1[5], Port 1[6] Port 1[7], Input/Output Power Power Power Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Table 1-1. PSoC Device Descriptions
XRES P0[0] P0[2] P0[3] P0[4] P0[5] P0[6] P0[7] P1[0] P1[1] P1[2] P1[3] P1[4] P1[5] P1[6] P1[7] P2[0] P2[3] P2[4] P2[5] P2[6] P2[7]
Port 2[0], 2[1], 2[2], 2[3], Non-Multiplexed Analog Input (Switched Capacitor) Port 2[4], External AGND Port 2[5] Port 2[6], External VREF Port 2[7]
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Pinouts
PSoC devices available variety packages. Refer following information details individual devices. Note that every port (labeled with "P"), except Vss, Vdd, SMP, XRES following tables illustrations, capable Digital
Table 1-2. 8-Pin Part Pinout (PDIP, SOIC)
Description P0[5], P0[3], P1[1], XTALin, P1[0], XTALout, P0[2], Description P0[4], Description
LEGEND analog, digital, input output.
AIO, P0[5] AIO, P0[3] SCL, XTALin, P1[1]
PDIP SOIC
P0[4], P0[2], P1[0], XTALout,
Table 1-3. 20-Pin Part Pinout (PDIP, SSOP, SOIC)
P0[7], P0[5], P0[3], P0[1], P1[7], P1[5], Description P1[3] P1[1], XTALin, P1[0], XTALout, P1[2] P1[4], EXTCLK P1[6] Description XRES P0[0], P0[2], P0[4], P0[6], Description
LEGEND analog, digital, input output.
P0[7] AIO, P0[5] AIO, P0[3] P0[1] SCL, P1[7] SDA, P1[5] P1[3] SCL, XTALin, P1[1]
PDIP SSOP SOIC
P0[6], P0[4], P0[2], P0[0], XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout,
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Information
Table 1-4. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
P0[7], P0[5], P0[3], P0[1], P2[7] P2[5] P2[3], (ASC10) P2[1], (ASD20, ASC10) P1[7], Description Description P1[5], P1[3] P1[1], XTALin, P1[0], XTALout, P1[2], P1[4], EXTCLK P1[6] XRES P2[0], (ASC21) Description P2[2], (ASD11, ASC21) P2[4], External AGND P2[6], External VREF P0[0], P0[2], P0[4], P0[6],
LEGEND analog, digital, input output.
P0[7] AIO, P0[5] AIO, P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] SCL, P1[7] SDA, P1[5] P1[3] SCL, XTALin, P1[1]
PDIP SSOP SOIC
P0[6], P0[4], P0[2], P0[0], P2[6], External VREF P2[4], External AGND P2[2], P2[0], XRES P1[6] P1[4] EXTCLK P1[2] P1[0], XTALout,
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Table 1-5. 32-Pin Part Pinout (MLF)
P2[7] P2[5] P2[3], (ASC10) P2[1], (ASD20) P1[7], P1[5], P1[3] P1[1], XTALin,
Description
Description P1[0], XTALout, P1[2] P1[4], EXTCLK P1[6] XRES P2[0], (ASC23) P2[2], (ASD13) P2[4], (AGND) P2[6], (Ref)
P0[0], P0[2], P0[4], P0[6], P0[7],
Description
P0[5], P0[3], P0[1],
LEGEND analog, digital, input output, connection.
Note package center that must connected same ground pin.
P0[3] P0[5] P0[7] P0[6] P0[4] P0[1]
P2[7] P2[5] (ASC10) P2[3] (ASD20) P2[1] P1[7] P1[5]
P1[3] XTALin, P1[1] XTALout, P1[0] P1[2] EXTCLK P1[4]
(Top View)
P0[2] P0[0] P2[6] (Ref) P2[4] (AGND) P2[2] (ASD13) P2[0] (ASC23) XRES P1[6]
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Packaging Information
This chapter presents illustrates packaging specifications PSoC device, along with thermal impedances each package.
Packaging Dimensions
51-85075
Figure 2-1. 8-Lead (300-Mil) PDIP
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51-85066
Figure 2-2. 8-Lead (150-Mil) SOIC
51-85011-A
Figure 2-3. 20-Lead (300-Mil) Molded
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Packaging Information
51-85077
Figure 2-4. 20-Lead (210-Mil) SSOP
51-85024
Figure 2-5. 20-Lead (300-Mil) Molded SOIC
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51-85079
Figure 2-6. 28-Lead (210-Mil) SSOP
51-85014-B
Figure 2-7. 28-Lead (300-Mil) Molded
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Packaging Information
51-85026
Figure 2-8. 28-Lead (300-Mil) Molded SOIC
51-85188
Figure 2-9. 32-Lead (5x5
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Thermal Impedances
Typical oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W oC/W
Table 2-1. Thermal Impedances Package
Package PDIP SOIC PDIP SSOP SOIC PDIP SSOP SOIC
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SECTION
CORE ARCHITECTURE
Architecture section discusses core components PSoC device registers associated with those components. This section encompasses following chapters:
Core (M8C) page Supervisory (SROM) page Interrupt Controller page General Purpose (GPIO) page Analog Output Drivers page
Internal Main Oscillator (IMO) page Internal Speed Oscillator (ILO) page Crystal Oscillator (ECO) page Phase Locked Loop (PLL) page Sleep Watchdog page
Top-Level Core Architecture
figure below displays top-level architecture PSoC's core. Each component figure discussed length this section.
Port Port Port
Analog Drivers
SYSTEM
Supervisory (SROM)
Flash Nonvolatile Memory Sleep Watchdog
SRAM
Interrupt Controller
Core (M8C)
Internal Main Oscillator (IMO)
Internal Speed Oscillator (ILO) Phased Locked Loop (PLL)
Crystal Oscillator (ECO)
PSoC Core Block Diagram
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Core Register Summary
table below lists PSoC registers that core device uses.
Summary Table Core Registers
Address Name REGISTERS Register x,F7h 1,E0h x,FFh CPU_F OSC_CR0 CPU_SCR0 Select GIES Mode Buzz WDRS Sleep[1:0] PORS Sleep Carry Zero Speed[2:0] STOP Related Registers Access
SUPERVISORY (SROM) REGISTER x,FEh CPU_SCR1 INTERRUPT CONTROLLER REGISTERS 0,DAh 0,DBh 0,DDh 0,DEh 0,E0h 0,E1h 0,E2h x,F7h INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC CPU_F GENERAL PURPOSE (GPIO) REGISTERS 0,00h 0,01h 0,02h 0,03h 1,00h 1,01h 1,02h 1,03h 0,04h 0,05h 0,06h 0,07h 1,04h 1,05h 1,06h 1,07h 0,08h 0,09h 0,0Ah 0,0Bh 1,08h 1,09h 1,0Ah 1,0Bh PRT0DR PRT0IE PRT0GS PRT0DM2 PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 Data Input[7:0] Interrupt Enables[7:0] Global Select[7:0] Drive Mode 2[7:0] Drive Mode 0[7:0] Drive Mode 1[7:0] Interrupt Control 0[7:0] Interrupt Control 1[7:0] Data Input[7:0] Interrupt Enables[7:0] Global Select[7:0] Drive Mode 2[7:0] Drive Mode 0[7:0] Drive Mode 1[7:0] Interrupt Control 0[7:0] Interrupt Control 1[7:0] Data Input[7:0] Interrupt Enables[7:0] Global Select[7:0] Drive Mode 2[7:0] Drive Mode 0[7:0] Drive Mode 1[7:0] Interrupt Control 0[7:0] Interrupt Control 1[7:0] ANALOG OUTPUT DRIVER REGISTER 1,62h ABF_CR0 ACol1Mux ABUF1EN0 ABUF0EN0 Bypass ENSWINT Sleep GPIO DCB03 Pending Interrupt[7:0] Carry Zero Analog DCB02 Analog DBB01 Sleep GPIO DCB03 Analog DCB02 Analog DBB01 Monitor DBB00 Monitor DBB00 IRAMDIS
INTERNAL MAIN OSCILLATOR (IMO) REGISTER 1,E8h IMO_TR Trim[7:0] INTERNAL SPEED OSCILLATOR (ILO) REGISTER 1,E9h ILO_TR Bias Trim[1:0] Freq Trim[3:0]
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Summary Table Core Registers (continued)
Address Name Access
CRYSTAL OSCILLATOR (ECO) REGISTER 1,E0h 1,EBh x,FEh OSC_CR0 ECO_TR CPU_SCR1 PHASE LOCKED LOOP (PLL) REGISTERS 1,E0h 1,E2h OSC_CR0 OSC_CR2 Select PLLGAIN SLEEP WATCHDOG REGISTERS 0,E0h 0,E3h x,FEh 1,E0h 1,E9h 1,EBh x,FFh INT_MSK0 RES_WDT CPU_SCR1 OSC_CR0 ILO_TR ECO_TR CPU_SCR0 PSSDC[1:0] GIES WDRS PORS Sleep STOP Select Mode Buzz Bias Trim[1:0] Sleep GPIO WDSL_Clear ECO_EXW Sleep[1:0] ECO_EX Speed[2:0] Freq Trim[3:0] IRAMDIS Analog Analog Monitor Mode Buzz Sleep[1:0] EXTCLKEN Speed[2:0] IMODIS SYSCLKX2 Select Mode Buzz Sleep[1:0] Speed[2:0] IRAMDIS
PSSDC[1:0]
LEGEND AND, flag instructions used modify this register. Access specific. Refer register detail additional information. value power reset unknown. before comma address field indicates that this register accessed written matter what bank used.
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Core (M8C)
This chapter explains Core, called M8C, associated registers. covers internal registers, address spaces, instruction formats, addressing modes. additional information concerning instruction set, reference Assembly Language User Guide available CypressMicro.com site.
Table 3-1. Registers
Address Register x,F7h 1,E0h x,FF CPU_F OSC_CR0 CPU_SCR0 Select GIES Mode Buzz WDRS Sleep[1:0] PORS Sleep Carry Zero Speed[2:0] STOP Related Registers Name Access
LEGEND AND, flag instructions used modify this register. before comma address field indicates that this register accessed written matter what bank used.
four MIPS 8-bit Harvard architecture microprocessor. Code selectable processor clock speeds from 93.7 allow tuned particular application's performance power requirements. supports rich instruction which allows efficient low-level language support.
With exception register, internal registers accessible explicit register address. internal registers accessed using instructions such
Internal Registers
expr expr SWAP expr LABEL
five internal registers that used program execution. following list these registers.
register read using address either register bank.
Accumulator Index Program Counter (PC) internal only Stack Pointer (SP) Flags
Address Spaces
internal registers eight bits width except which bits wide. Upon reset, reset 00h. Flag register reset 02h, indicating that flag set. With each stack operation, automatically incremented decremented that always points next stack byte RAM. last byte stack address Stack Pointer will wrap address 00h. firmware developer's responsibility ensure that stack does overlap with user-defined variables RAM.
three address spaces: ROM, RAM, registers. address space includes supervisory (SROM) Flash. address space accessed address data bus. Figure illustrates arrangement PSoC microcontroller address spaces. address space composed Supervisory on-chip Flash program store. Flash organized into 64-byte blocks. user need concerned with program store page boundaries, automatically increments 16-bit every instruction making block boundaries invisible user code. Instructions occurring 256-byte Flash page boundary (with
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exception instructions) incur extra clock cycle upper byte incremented. register address space used configure PSoC microcontroller's programmable blocks. consists banks bytes each. switch between banks,
Flag register cleared (set Bank1, cleared Bank0). common convention leave bank Bank0 (XIO cleared), switch Bank1 needed (set XIO), then switch back Bank0.
DB[7:0] DA[7:0]
ID[7:0] Registers Bank Bytes Page Bytes
PC[15:0]
SROM
Bank Bytes
LEGEND Total number Flash blocks device XIO: Register bank selection IOR: Register read IOW: Register write Memory read Memory write
Flash Byte Blocks
Figure 3-1. Microcontroller Address Spaces
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Instruction Summary
instruction summarized below Table 3-2. described detail PSoC Designer Assembly Language User Guide (reference CypressMicro.com site).
Table 3-2. Instruction Summary
Opcode Opcode Opcode Cycles Cycles Cycles Bytes Bytes Bytes
Instruction Format
Flags
Instruction Format
Flags
Instruction Format
Flags
expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr PUSH expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr PUSH expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr ROMX expr [expr] [X+expr] [expr],
[X+expr], [expr], expr [X+expr], expr HALT expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr expr [expr] [X+expr] [expr], expr [X+expr], expr [expr]++ [expr]++ reg[expr], expr reg[X+expr], expr reg[expr], expr reg[X+expr], expr reg[expr], expr reg[X+expr], expr [expr], expr [X+expr], expr reg[expr], expr reg[X+expr], expr SWAP SWAP [expr] SWAP [expr] SWAP expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr [expr] [X+expr]
[expr], reg[expr] reg[X+expr] [expr], [expr] reg[expr], reg[X+expr], reg[expr], expr reg[X+expr], expr [expr] [X+expr] [expr] [X+expr] [expr] [X+expr] [expr] [X+expr] expr expr expr [expr] [X+expr] [expr] [X+expr] LCALL LJMP RETI CALL JACC INDEX
(A=B) (A<B)
Note Interrupt routines take cycles before execution resumes Interrupt Vector table.
Note number cycles required instruction increased instructions that span byte boundaries Flash memory space.
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Instruction Format
3.4.2
Two-Byte Instructions
total seven instruction formats which instruction lengths one, two, three bytes. instruction bytes fetched from program memory (Flash) using address data that independent from address data buses used register access. While examples instructions will given this section, refer PSoC Designer Assembly Language User Guide detailed information individual instructions.
majority instructions bytes length. While these instructions divided into categories identical one-byte instructions this would provide useful distinction between three two-byte instruction formats that uses.
Table 3-4. Two-Byte Instruction Formats
Byte Byte 4-bit opcode 12-bit relative address 8-bit opcode 8-bit data 8-bit address
3.4.1
One-Byte Instructions
8-bit opcode
Many instructions, such some instructions, have single-byte forms because they address data operand. shown Table 3-3, one-byte instructions 8-bit opcode. one-byte instructions divided into four categories according where their results stored.
Table 3-3. One-Byte Instruction Format
Byte 8-bit opcode
first two-byte instruction format shown Table used short jumps calls: CALL, JMP, JACC, INDEX, JNC, JNZ, This instruction format uses only 4-bits instruction opcode leaving 12-bits store relative destination address two's-complement form.These instructions change program execution address relative current address -2048 +2047. second two-byte instruction format (Table 3-4) used instructions that employ Source Immediate addressing mode ("Source Immediate" page 41). destination these instructions internal register while source constant value. example this type instruction would third two-byte instruction format used wide range instructions addressing modes. following list addressing modes that this third two-byte instruction format:
first category one-byte instructions those that update registers RAM. Only one-byte instructions this category. While Program Counter incremented these instructions execute they cause other internal registers updated these instructions directly affect register space address space. instruction will cause SROM code which will modify internal registers. second category only PUSH instructions PUSH instructions unique because they only one-byte instructions that cause address modified. These instructions automatically increment third category only HALT instruction HALT instruction unique because only single-byte instruction that causes user register modified. HALT instruction modifies user register space address (CPU_SCR). final category single-byte instructions those that cause internal registers updated. This category holds largest number instructions: ASL, ASR, CPL, DEC, INC, MOV, POP, RET, RETI, RLC, ROMX, RRC, SWAP. These instructions cause registers SRAM updated.
Source Direct (ADD [7]) Source Indexed (ADD [X+7]) Destination Direct (ADD [7], Destination Indexed (ADD [X+7], Source Indirect Post Increment (MVI [7]) Destination Indirect Post Increment (MVI [7],
more information addressing modes "Addressing Modes" page
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3.4.3
Three-Byte Instructions
instructions 8-bit opcode leaving room 16bit destination address. second three-byte instruction format shown Table used following addressing modes:
three-byte instruction formats second most prevalent instruction formats. These instructions need three bytes because they either move data between addresses user-accessible address space (registers RAM) they hold 16-bit absolute addresses destination long jump long call.
Table 3-5. Three-Byte Instruction Formats
Byte 8-bit opcode 8-bit opcode 8-bit opcode Byte 16-bit address (MSB, LSB) 8-bit address 8-bit address 8-bit data 8-bit address Byte
Destination Direct Source Immediate (ADD [7], Destination Indexed Source Immediate (ADD [X+7],
first instruction format shown Table used LJMP LCALL instructions. These instructions change program execution unconditionally absolute address.
third three-byte instruction format Destination Direct Source Direct addressing mode which used only instruction. This instruction format uses 8-bit opcode followed 8-bit addresses. first address destination address while second address source address RAM. following example this instruction: [7], [5].
Addressing Modes
addressing modes: Source Immediate Source Direct Source Indexed Destination Direct Destination Indexed
Destination Direct Source Immediate Destination Indexed Source Immediate Destination Direct Source Direct Source Indirect Post Increment Destination Indirect Post Increment
3.5.1
Source Immediate
instruction's opcode. instructions using Source Immediate addressing mode bytes length.
these instructions source value stored operand instruction. result these instructions placed either register indicated
Table 3-6. Source Immediate
Opcode Instruction Operand Immediate Value
Source Immediate Examples:
Source Code
Machine Code
Comments
immediate value added Accumulator. result placed Accumulator. immediate value moved into register. immediate value logically AND'ed with register result placed register.
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3.5.2
Source Direct
placed either register indicated instruction's opcode. instructions using Source Direct addressing mode bytes length.
these instructions source address stored operand instruction. During instruction execution address will used retrieve source value from register address space. result these instructions
Table 3-7. Source Direct
Opcode Instruction Operand Source Address
Source Direct Examples:
Source Code
REG[8]
Machine Code
Comments
value memory address added Accumulator result placed into Accumulator. value register space address moved into Accumulator.
3.5.3
Source Indexed
register address space. result these instructions placed either register indicated instruction's opcode. instructions using Source Indexed addressing mode bytes length.
these instructions source offset from register stored operand instruction. During instruction execution current register value added signed offset determine address source value
Table 3-8. Source Indexed
Opcode Instruction Source Index Operand
Source Indexed Examples:
Source Code
[X+7] [X+8]
Machine Code
Comments
value memory address added Accumulator. result placed Accumulator. value address moved into register.
3.5.4
Destination Direct
instruction's opcode. instructions using Destination Direct addressing mode bytes length.
these instructions destination address stored machine code instruction. source operation either register indicated
Table 3-9. Destination Direct
Opcode Instruction Operand Destination Address
Destination Direct Examples:
Source Code
[7],
Machine Code
Comments
value Accumulator added memory, address result placed memory address Accumulator unchanged. Accumulator value moved register space address Accumulator unchanged.
REG[8],
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3.5.5
Destination Indexed
immediate value indicated instruction's opcode. instructions using Destination Indexed addressing mode bytes length.
these instructions destination offset from register stored machine code instruction. source operation either register
Table 3-10. Destination Indexed
Opcode Instruction Operand Destination Index
Destination Indexed Example:
Source Code
[X+7],
Machine Code
Comments
value memory address added Accumulator. result placed memory address X+7. Accumulator unchanged.
3.5.6
Destination Direct Source Immediate
nation Direct Source Immediate addressing mode three bytes length.
these instructions destination address stored operand instruction. source value stored operand instruction. instructions using Desti-
Table 3-11. Destination Direct Source Immediate
Opcode Instruction Operand Destination Address Operand Immediate Value
Destination Direct Source Immediate Examples:
Source Code
[7], REG[8],
Machine Code
Comments
value memory address added immediate value result placed memory address immediate value moved into register space address
3.5.7
Destination Indexed Source Immediate
tions using Destination Indexed Source Immediate addressing mode three bytes length.
these instructions destination offset from register stored operand instruction. source value stored operand instruction. instruc-
Table 3-12. Destination Indexed Source Immediate
Opcode Instruction Operand Destination Index Operand Immediate Value
Destination Indexed Source Immediate Examples:
Source Code
[X+7], REG[X+8],
Machine Code
Comments
value memory address added immediate value result placed memory address X+7. immediate value moved into register space address X+8.
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3.5.8
Destination Direct Source Direct
instructions using Destination Direct Source Direct addressing mode three bytes length.
Only instruction uses this addressing mode. destination address stored operand instruction. source address stored operand instruction.
Table 3-13. Destination Direct Source Direct
Opcode Instruction Operand Destination Address Operand Source Address
Destination Direct Source Direct Example:
Source Code
[7],
Machine Code
Comments
value memory address moved memory address
3.5.9
Source Indirect Post Increment
Read (DPR_DR) register used determine which page with source address. Therefore, values from pages other than current page retrieved without changing Current Page Pointer (CPP_DR). pointer always read from current page. information DPR_DR CPP_DR registers, device data sheet.
Only instruction uses this addressing mode. source address stored operand actually address pointer. During instruction execution pointer's current value read determine address where source value will found. pointer's value incremented after source value read. PSoC microcontrollers with more than bytes RAM, Data Page
Table 3-14. Source Indirect Post Increment
Opcode Instruction Operand Source Address Pointer
Source Indirect Post Increment Example:
Source Code
Machine Code
Comments
value memory address (the indirect address) points memory location RAM. value memory location pointed indirect address moved into Accumulator. indirect address, address memory, then incremented.
3.5.10
Destination Indirect Post Increment
used determine which page with destination address. Therefore, values stored pages other than current page without changing Current Page Pointer (CPP_DR). pointer always read from current page. information DPR_DR CPP_DR registers, device data sheet.
Only instruction uses this addressing mode. destination address stored operand actually address pointer. During instruction execution pointer's current value read determine destination address where Accumulator's value will stored. pointer's value incremented after value written destination address. PSoC microcontrollers with more than bytes RAM, Data Page Write (DPW_DR) register
Table 3-15. Destination Indirect Post Increment
Opcode Instruction Operand Destination Address Pointer
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Destination Indirect Post Increment Example:
Source Code
[8],
Machine Code
Comments
value memory address (the indirect address) points memory location RAM. Accumulator value moved into memory location pointed indirect address. indirect address memory, address then incremented.
3.6.1
Register Definitions
CPU_F (Flag) Register
Flag register four chip dependent bits (FL[7:4]) four dedicated bits (FL[3:0]), shown Table 3-1.
3.6.1.1
Chip-Dependent Flag Bits
chip-dependent Flag bits have effect internally M8C. These bits manipulated user with Flag-Logic opcodes (for example, 80h). Definitions PSoC Mixed Signal Array family follows.
Bits Reserved. XOI. Bank Select. This used select between register banks, order support more than registers.
3.6.1.2
Dedicated Flag Bits
dedicated Flag bits described follows.
Reserved. Carry. Carry Flag. This cleared response result several instructions. also manipulated Flag-Logic opcodes (for example, PSoC Designer Assembly Guide User Manual more details. Zero. Zero Flag. This cleared response result several instructions. also manipulated Flag-Logic opcodes (for example, PSoC Designer Assembly Guide User Manual more details. GIE. Global Interrupt Enable. state this determines whether interrupts IRQ) will recognized M8C. This cleared user, using Flag-Logic opcodes (e.g., also cleared automatically interrupt routine, after flag byte been stored stack.
GIE=1, samples input each instruction. GIE=0, ignores IRQ. additional information, reference CPU_F register page 152.
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Supervisory (SROM)
This chapter discusses Supervisory (SROM) associated register. covers both physical SROM block code stored SROM PSoC devices.
Table 4-1. SROM Register
Address x,FEh Name CPU_SCR1 IRAMDIS Access RW:00
LEGEND before comma address field indicates that this register accessed written matter what bank used.
SROM holds code that used boot part, calibrate circuitry, perform Flash operations. functions SROM accessed normal user code, operating from Flash.
Architectural Description
SROM used boot part provide interface functions Flash macros. (Table lists SROM functions.) SROM functions accessed executing Supervisory System Call instruction (SSC) which opcode 00h. Prior executing M8C's accumulator needs loaded with desired SROM function code from Table 4-2. Undefined functions will cause HALT called from user code. SROM functions executing code with calls; therefore, functions require stack space. With exception Reset, SROM functions have parameter block SRAM that must configured before executing SSC. Table lists possible parameter block variables. meaning each parameter, with regards specific SROM function, described later this chapter.
important variables that used functions KEY1 KEY2. These variables used help discriminate between valid SSCs inadvertent SSCs. KEY1 must always have value 3Ah, while KEY2 must have same value stack pointer when SROM function begins execution. This would value when opcode executed, plus three. either keys match expected values, will halt (with exception SWBootReset function). following code puts correct value KEY1 KEY2. code starts with halt, force program jump directly into setup code into halt SSCOP: [KEY1], [KEY2],
Table 4-3. SROM Function Variables
Variable Name KEY1 COUNTER RETURN CODE KEY2 BLOCKID SRAM Address 0,F8h 0,F9h 0,FAh 0,FBh 0,FCh 0,FDh 0,FEh 0,FFh
Table 4-2. List SROM Functions
Function Code Function Name SWBootReset ReadBlock WriteBlock EraseBlock TableRead CheckSum Calibrate0 Calibrate1 Stack Space Needed
POINTER CLOCK Reserved DELAY Reserved
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4.1.1
Additional SROM Feature
SROM following additional SROM feature.
Return Codes: These determination success failure particular function. return code stored KEY1's position parameter block. CheckSum TableRead functions have return codes because KEY1's position parameter block used return other data. Table 4-4. SROM Return Code Meanings
Return Code Value Description Success Function allowed level protection block Software reset without hardware reset Fatal error, SROM halted
Table documents value SRAM addresses page zero, after successful SWBootReset. cell table with "xx" indicates that SRAM address modified SWBootReset function. value cell indicates that address should always have indicated value after successful SWBootReset. cell with "??" indicates that value, after SWBootReset, determined value IRAMDIS CPU_SCR1. IRAMDIS set, these addresses will initialized 00h. IRAMDIS set, these addresses will modified SWBootReset. IRAMDIS allows variables preserved even watchdog reset occurs. IRAMDIS reset system resets except Watchdog reset. Therefore, this only useful Watchdog resets general resets.
Table 4-5. SRAM Post SWBootReset
Address 0x0_ 0x1_ 0x00 0x2_ 0x3_ 0x4_ 0x5_ 0x6_ 0x7_ 0x8_ 0x9_ 0xA_ 0xB_ 0xC_ 0xD_ 0xE_ 0xF_ 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Note Read, write, erase operations fail target block read write protected. Block protection levels during device programming.
4.1.2
4.1.2.1
SROM Function Descriptions
SWBootReset Function
SROM function SWBootReset function that responsible transitioning device from reset state running user code. Types Resets chapter more information what events will cause SWBootReset function execute. SWBootReset function executed whenever SROM entered with accumulator value 00h: SRAM parameter block used input function. This will happen, design, after hardware reset, because M8C's accumulator reset when user code executes instruction with accumulator value 00h. SWBootReset's calibration function, Calibrate1, transfers calibration data byte time from Flash SRAM. bytes transferred, bytes, plus hard coded offset value EBh, calculated 2byte SRAM variable (CHECKSUM). transfer value CHECKSUM (plus offset value EBh) zero, SWBootReset function uses values stored SRAM calibrate registers PSoC device. CHECKSUM non-zero value, IRES CPU_SCR1 set, which causes hardware reset similar event. more information this condition, "System Resets" page 297. checksum calibration data zero, SWBootReset function ends setting registers (CPU_SP, CPU_PC, CPU_X, CPU_F, CPU_A) 00h, after writing most SRAM addresses, then begins execute user code address 0000h.
Address return code byte SROM functions, this function, only acceptable values 02h. Address fail count variable. After POR, WDR, XRES, variable initialized SROM. Each time checksum fails, fail count incremented. Therefore, takes passes through
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SWBootReset good checksum, fail count would 01h.
Supervisory (SROM) Table 4-7. WriteBlock Parameters (02h)
Name KEY1 KEY2 BLOCKID POINTER Address 0,F8h 0,F9h 0,FAh 0,FBh Description Stack Pointer value, when executed. Flash block number (00h 3Fh). First addresses SRAM, where data stored Flash located prior calling WriteBlock. Clock divider used write pulse width. speed 56h.
4.1.2.2
Read Block Function
ReadBlock function used read contiguous bytes from Flash: block. number blocks device simply total number bytes divided CY8C24xxx, Flash contains blocks bytes. first thing this function does check protection bits determine desired BLOCKID readable. read protection turned ReadBlock function will exit setting accumulator KEY2 back 00h. KEY1 will have value 01h, indicating read failure. read protection enabled, function will read bytes from Flash using ROMX instruction store results SRAM using instruction. first bytes will stored SRAM address indicated value POINTER parameter. When ReadBlock completes successfully accumulator, KEY1 KEY2 will have value 00h.
CLOCK DELAY
0,FCh 0,FEh
4.1.2.4
EraseBlock Function
EraseBlock function used erase block contiguous bytes Flash. first thing EraseBlock function does check protection bits determine desired BLOCKID writeable. write protection turned EraseBlock function will exit setting accumulator KEY2 back 00h. KEY1 will have value 01h, indicating write failure. parameter block EraseBlock function, correct values must stored KEY1 KEY2. block number erased must stored BLOCKID variable CLOCK DELAY values must based current speed. more information setting CLOCK DELAY values, "Clocking" page
Table 4-6. ReadBlock Parameters (01h)
Name KEY1 KEY2 BLOCKID POINTER Address 0,F8h 0,F9h 0,FAh 0,FBh Description Stack Pointer value, when executed. Flash block number First addresses SRAM where returned data should stored.
Table 4-8. EraseBlock Parameters (03h)
Name KEY1 KEY2 BLOCKID CLOCK DELAY Address 0,F8h 0,F9h 0,FAh 0,FCh 0,FEh Description Stack Pointer value, when executed. Flash block number (00h 3Fh). Clock divider used erase pulse width. speed 56h.
4.1.2.3
WriteBlock Function
WriteBlock function used store data Flash. Data moved bytes time from SRAM Flash using this function. first thing WriteBlock function does check protection bits determine desired BLOCKID writeable. write protection turned WriteBlock function will exit setting accumulator KEY2 back 00h. KEY1 will have value 01h, indicating write failure. configuration WriteBlock function straight forward. BLOCKID Flash block, where data stored, must determined stored SRAM address FAh. Valid BLOCKID values between 3Fh. SRAM address first bytes stored Flash must indicated using POINTER variable parameter block (SRAM address FBh). Finally, CLOCK DELAY value must correctly. CLOCK value determines length write pulse that will used store data Flash. CLOCK DELAY values dependent speed must correctly. Refer "Clocking" page additional information.
4.1.2.5
TableRead Function
TableRead function gives user access part-specific data stored Flash during manufacturing. also returns Revision (not confused with Silicon stored Table
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Table 4-9. TableRead Parameters (06h)
Name KEY1 KEY2 BLOCKID Address 0,F8h 0,F9h 0,FAh Description Stack Pointer value, when executed. Table number read.
Table 4-10. Table with Assigned Values Flash Macro
Table Table Silicon Voltage Reference trim reg[1,EA] Table Table Mult Mult Main Oscillator trim reg[1,E8] Room Temperature Calibration 3.3V Temperature Calibration 3.3V Voltage Reference trim reg[1,EA] Main Oscillator trim reg[1,E8] Room Temperature Calibration Temperature Calibration (May used serialization future.)
4.1.2.6
Checksum Function
4.1.2.8
Calibrate1 Function
Checksum function calculates 16-bit checksum over user specifiable number blocks, within single Flash macro (Bank) starting from block zero. BLOCKID parameter used pass number blocks calculate checksum over. BLOCKID value will calculate checksum only block while BLOCKID value will calculate checksum user blocks. 16-bit checksum returned KEY1 KEY2. parameter KEY1 holds lower bits checksum parameter KEY2 holds upper bits checksum. checksum algorithm executes following sequence three instructions over number blocks times checksumed. romx [KEY1], [KEY2],
While Calibrate1 completely separate function from Calibrate0, they perform same function, which transfer calibration values stored special area Flash their appropriate registers. What unique about Calibrate1 that calculates checksum calibration data and, that checksum determined invalid, Calibrate1 will cause hardware reset setting IRES CPU_SCR1. Calibrate1 function uses SRAM calculate checksum calibration data. POINTER value used indicate address byte buffer used this function. When function completes, bytes will 00h. Calibrate1 created function SWBootReset. However, Calibrate1 function code added provide direct access. more information Calibrate1 works, SWBootReset section.
Table 4-11. Checksum Parameters (07h)
Name KEY1 KEY2 BLOCKID Address 0,F8h 0,F9h 0,FAh Description Stack Pointer value, when executed. Number Flash blocks calculate checksum
Table 4-13. Calibrate1 Parameters (09h)
Name KEY1 KEY2 POINTER Address 0,F8h 0,F9h 0,FBh Description Stack Pointer value, when executed. First SRAM addresses used this function.
4.1.2.7
Calibrate0 Function
Calibrate0 function transfers calibration values stored special area Flash their appropriate registers.
Table 4-12. Calibrate0 Parameters (08h)
Name KEY1 KEY2 Address 0,F8h 0,F9h Description Stack Pointer value, when executed.
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4.2.1
Register Definitions
CPU_SCR1 Register
CPU_SCR1 register used convey status control events related internal resets watchdog reset.
Bits Reserved. IRAMDIS. Initialize Disable control that readable writeable. default value this which indicates that maximum amount SRAM should initialized reset value 00h. When set, minimum amount SRAM initialized after watchdog reset. more information this bit, "SROM Function Descriptions" page
additional information, reference CPU_SCR1 register page 153.
Clocking
values Mult found Flash Table user must supply value which ambient temperate degrees Celsius. calculated value CLOCKW used write operations, while CLOCKE used erase operations.
CLOCK Mult CLOCK
Equation Equation
CLOCK 5648 1536
Equation valid speeds from Mhz. clock delay parameters support Flash operations. other clocking related parameter "DELAY." operation, value 56h. other speeds, following equation used.
DELAY
Equation
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Interrupt Controller
This chapter presents Interrupt Controller associated registers. interrupt controller provides mechanism hardware resource PSoC Mixed Signal Array devices change program execution address, without regard current task being performed code being executed.
Table 5-1. Interrupt Controller Registers
Address 0,DAh 0,DBh 0,DDh 0,DEh 0,E0h 0,E1h 0,E2h x,F7h Name INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC CPU_F ENSWINT Sleep GPIO DCB03 Pending Interrupt[7:0] Carry Zero Analog DCB02 Analog DBB01 Sleep GPIO DCB03 Analog DCB02 Analog DBB01 Monitor DBB00 Monitor DBB00 Access
LEGEND AND, flag instructions used modify this register. Cearable register bits. before comma address field indicates that this register accessed written matter what bank used.
interrupt controller associated registers allow user's code respond interrupt from almost every functional block PSoC devices. Interrupts digital blocks each analog columns available, well interrupts supply voltage, sleep, variable clocks, general GPIO (pin) interrupt. registers associated with interrupt controller allow interrupts disabled either globally individually. registers also provide mechanism which user clear pending posted interrupts, clear individual posted pending interrupts. software mechanism provided individual interrupts. Setting interrupt software very useful during code development, when have complete hardware system necessary generate real interrupt. following table lists interrupts priorities that available PSoC device.
Table 5-2. CY8C24xxx Interrupt Table
Interrupt Priority (highest) (lowest) Interrupt Address 0000h 0004h 0008h 000Ch 0018h 001Ch 0020h 0024h 0028h 002Ch 0060h 0064h Reset Supply voltage monitor Analog column Analog column GPIO PSoC block DBB00 PSoC block DBB01 PSoC block DCB02 PSoC block DCB03 Sleep timer Interrupt Name
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Architectural Description
block diagram PSoC Interrupt Controller shown Figure 5-1. illustrates notion posted pending interrupts.
Interrupt Taken INT_CLRx Write Posted Interrupt Pending Interrupt
Priority Encoder
Interrupt Vector
Interrupt Request Core CPU_F[0]
Interrupt Source (Timer, GPIO, etc.) INT_MSKx Mask Setting
Figure 5-1. Interrupt Controller Block Diagram
sequence events that occur during interrupt processing follows: interrupt becomes active, either because interrupt condition occurs (e.g., timer expires), previously posted interrupt enabled through update interrupt mask register, interrupt pending from Flag register. current executing instruction finishes. internal interrupt routine executes, taking cycles. During this time, following actions occur: PCH, PCL, Flag register (CPU_F) pushed onto stack that order). CPU_F register then cleared. Since this clears additional interrupts temporarily disabled. (PC[15:8]) cleared zero. interrupt vector read from interrupt controller value placed into (PC[7:0]). This sets program counter point appropriate address interrupt table (e.g., 001Ch GPIO interrupt). Program execution vectors interrupt table. Typically, LJMP instruction interrupt table sends execution user's Interrupt Service Routine (ISR) this interrupt. executes. Note that interrupts disabled since ISR, interrupts re-enabled desired setting (take care avoid stack overflow this case). ends with RETI instruction. This pops Flag register, PCL, from stack, restoring those registers. restored Flag register re-enables interrupts, since again.
Execution resumes next instruction, after that occurred before interrupt. However, there more pending interrupts, subsequent interrupts will processed before next normal program instruction. Interrupt Latency. time between assertion enabled interrupt start calculated from following equation.
Latency Time current instruction finish Time internal interrupt routine execute Time LJMP instruction interrupt table execute.
example, 5-cycle instruction executing when interrupt becomes active, total number clock cycles before begins would follows.
cycles finish) cycles interrupt routine) cycles LJMP) cycles.
example above, MHz, clock cycles take 1.042
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Register Definitions
behavior INT_CLRx registers. INT_CLRx register this section more information. Each interrupt source require configuration block level. Refer other chapters this document information configure individual interrupt source. additional information, reference INT_MSK0 register page 136, INT_MSK1 register page 137, INT_MSK3 register page 135.
Table gives overview registers related interrupt controller operation. following text presents details each register.
5.2.1
INT_CLRx Register
There three interrupt clear registers (INT_CLR0, INT_CLR1, INT_CLR3) which referred general INT_CLRx. INT_CLRx registers similar INT_MSKx registers that they hold each interrupt source. However, functionally INT_CLRx registers similar INT_VC register, although their operation completely independent. When INT_CLRx register read bits that indicate interrupt been posted that hardware resource. Therefore, reading these registers gives user ability determine posted interrupts. individual value written INT_CLRx register interpreted determined Enable Software Interrupt (ENSWINT) INT_MSK3[7]. When ENSWINT cleared (the default state) writing INT_CLRx register effect. However, writing INT_CLRx register, when ENSWINT cleared, will cause corresponding interrupt cleared. ENSWINT set, written INT_CLRx registers will ignored. However, written INT_CLRx register, while ENSWINT set, will cause interrupt posted corresponding interrupt. Enabling software interrupts allows user's code create software interrupts that debugging interrupt service routines, eliminating need create system level interactions that necessary create hardware interrupt. additional information, reference INT_CLR0 register page 131, INT_CLR1 register page 133, INT_CLR3 register page 134.
5.2.3
INT_VC Register
interrupt vector clear register (INT_VC) performs different functions. When register read, least significant byte highest priority pending interrupt returned. example, GPIO interrupts were pending INT_VC register read, value would read. However, interrupt were pending, value would returned. This reset vector interrupt table; however, reading from INT_VC register should considered indication that system reset pending. Rather, reading from INT_VC register simply indicates that there pending interrupts. highest priority interrupt, indicated value returned read INT_VC register, removed from list pending interrupts when performs Interrupt Vector Read (IVR). clear highest priority pending interrupt occurs asynchronously. Reading INT_VC limited usefulness. interrupts enabled, read INT_VC register would able determine that interrupt pending before interrupt actually taken. However, while interrupt, user wish read INT_VC register what next interrupt will When INT_VC register written, with value, pending posted interrupts cleared asserting clear line each interrupt. additional information, reference INT_VC register page 138.
5.2.2
INT_MSKx Register 5.2.4 CPU_F Register
Only CPU_F register related interrupt controller. This Global Interrupt Enable. When this set, will take pending interrupt. When cleared, will take interrupts. default, this cleared. clear this bit, expr, expr, expr instructions must used. (Written another way: AND/OR/XOR expr instructions must used.) flag covered more detail chapter titled "CPU Core (M8C)" page additional information, reference CPU_F register page 152.
There three interrupt mask registers (INT_MSK0, INT_MSK1, INT_MSK3) which referred general INT_MSKx. cleared, each INT_MSKx register prevents interrupt from becoming pending interrupt (input priority encoder). However, interrupt still post even mask zero. INT_MSKx bits independent other INT_MSKx bits. INT_MSKx set, interrupt source associated with that mask generate interrupt that will become pending interrupt. example, INT_MSK0[5] least GPIO configured generate interrupt, interrupt controller will allow GPIO interrupt request post become pending interrupt respond higher priority interrupt generated before responds GPIO interrupt, higher priority interrupt will pending GPIO interrupt. INT_MSK3[7] (ENSWINT) special non-mask that controls
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General Purpose (GPIO)
This chapter discusses General Purpose (GPIO) associated registers. GPIO blocks provide interface between core outside world. They offer large number configurations support several types input/ output operations both digital analog systems.
Table 6-1. GPIO Registers
Address 0,xxh 0,xxh 0,xxh 0,xxh 1,xxh 1,xxh 1,xxh 1,xxh Name PRTxDR PRTxIE PRTxGS PRTxDM2 PRTxDM0 PRTxDM1 PRTxIC0 PRTxIC1 Access Data Register Interrupt Enables Global Select Drive Mode Drive Mode Drive Mode Interrupt Control Interrupt Control
LEGEND after comma address field indicates that there multiple instances register. expanded address listing these registers, refer "Core Register Summary" page
GPIO contains input buffers, output drivers, register storage, configuration logic connecting bond from core. Ports arranged with bits port. Each full port contains eight identical GPIO blocks, with connections identify unique address register number each block. Therefore, registers shown Table actually GPIO port (eight GPIO blocks), where position indicates which eight GPIO blocks controlled GPIO port. Each GPIO block used following types
response this data bit, with drive strength determined drive mode setting (see below). actual voltage depends drive mode external load. read value port reading PRTxDR. When reads PRTxDR, current value voltage translated into logic value returned M8C. These operations read voltage, data drive state stored local PRTxDR register latch.
Global
GPIO ports also used interconnect signals from digital PSoC blocks, global inputs outputs. global feature each GPIO (port pin) default. access feature, parameters must changed. configure GPIO global input port global select must desired GPIO using PRTxGS register. Also, drive mode GPIO must digital Hi-Z state. (Refer "PRTxDMx Registers" page more information.) configure GPIO global output, port global select must again set. this case, drive state must non-Hi-Z states.
Digital (digital controlled software) Global (digital PSoC block Analog (analog PSoC block
Each also several possible drive modes, well interrupt capabilities. While GPIO pins identical provide digital some pins connect internally global analog functions.
Digital
basic operations GPIO ports allow send information chip information into from outside chip; this accomplished port data register (PRTxDR). Writes from PRTxDR store data state, GPIO. standard non-bypass mode, drivers drive
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Analog
Analog signals pass between chip core chip pins through block's AOUT pin. This provides resistive path (~300 ohms) directly through block. analog modes, GPIO block typically configured into High Impedance Analog Drive mode (Hi-Z).
another GPIO this again) could assert INTO pin, pulling common line assert interrupt. Note following behavior from this level-release feature. asserting INTO then second asserts INTO, when first releases INTO, second already driving INTO thus change will seen, i.e., interrupt would asserted GPIO interrupt. Care must taken, using polling and/or states GPIO global Interrupt Enables, catch interrupts among wire-OR GPIO blocks.
GPIO Block Interrupts
Each GPIO block individually configured interrupt capability. Blocks configured interrupt enables also selection interrupt state. Blocks interrupt when high, low, when changes from last time read. block provides open-drain interrupt output (INTO) that connected other GPIO blocks wire-OR fashion. interrupts that wire-OR'ed together tied same system GPIO interrupt. Therefore, interrupts enabled multiple pins, user's interrupt service routine must some user designed mechanism, determine which source interrupt. Using GPIO interrupt requires following steps: interrupt mode GPIO block. Enable interrupt GPIO block. mask (global) GPIO interrupt. Assert overall Global Interrupt Enable. These last steps common interrupts described "Interrupt Controller" page first steps, interrupt enable interrupt mode, GPIO block level (i.e., each port pin), block's configuration registers. GPIO block level, asserting INTO line depends only interrupt enable state relative chosen interrupt mode. chip level, their wire-OR nature, GPIO interrupts neither true edge-sensitive interrupts true level-sensitive interrupts. They could considered edge-sensitive asserting, level-sensitive release wire-OR interrupt line. GPIO interrupts asserting, GPIO interrupt will occur whenever GPIO Interrupt Enable GPIO transitions already transitioned) appropriately high match interrupt mode configuration). Once this happens, INTO line will pull assert GPIO interrupt. (This assumes other system-level enables such setting global GPIO interrupt enable Global Interrupt Enable.) Note that setting Interrupt Enable immediately assert INTO, Interrupt Mode conditions already being pin. Once INTO pulls low, will continue hold INTO until these conditions changes: Interrupt Enable cleared; voltage transitions opposite state; interrupt-on-change mode, GPIO data register read, thus setting local interrupt level opposite state; interrupt mode changed that current state does create interrupt. Once these conditions met, INTO releases. this point,
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Architectural Description
main block diagram GPIO block illustrated Figure 6-1. Note that some pins have functionality shown, depending internal connections.
Input Path
Global Input
Read PRTxDR
Drive Modes
Mode Resistive Pull Down Strong Drive High Impedence Resistive Pull Open Drain, Drives High Slow Strong Drive High Impedence Analog Open Drain, Drives DM[2:0]=110b CELLRD
Data Input
RESET QinLatch Readmux, Interrupt Logic)
Analog Input
Output Path
Vpwr Write PRTxDR Vpwr DATA 5.6K
Global Output Output Enable
Drive Logic
Slew Control
5.6K
Analog Output
Figure 6-1. GPIO- Block Diagram
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interrupt logic portion block shown Figure 6-2.
INTERRUPT LOGIC Falling INTO QinLatch CELLRD Change
Interrupt Mode Output Rising Disabled High Change from last read
INBUF
Figure 6-2. GPIO Interrupt Mode Block Diagram
Register Definitions
6.2.2 PRTxIE Registers
PRTxIE register used enable/disable interrupt enable internal GPIO block. enables INTO output block, disables INTO only HiZ. additional information, reference PRTxIE register page
selected GPIO block, individual registers addressed shown Table 6-2. register names, port number, configured chip level typically). DA[1:0] refers register address. register values readable, except PRTxDR register; reads this register return state instead register state.
Table 6-2. Internal Register Addressing
DA[1:0] Register PRTxDR PRTxIE PRTxGS PRTxDM2 PRTxDM0 PRTxDM1 PRTxIC0 PRTxIC1 Resets (Name) Function Data Interrupt Enable Global Select Drive Mode, Drive Mode, Drive Mode, Intrpt. Mask, Intrpt. Mask,
6.2.3
PRTxGS Registers
PRTxGS register used select block connection global inputs outputs. Writing this register high enables global bypass (BYP=1 Figure 6-1). drive mode digital Hi-Z (DM[2:0] 010b), then selected global input (PIN drives Global Input Bus). non-Hi-Z modes, block selected global output (the Global Output drives PIN), bypassing data register value (assuming Enable=0). PRTxGS register written zero, global in/out function disabled pin. additional information, reference PRTxGS register page
6.2.1
PRTxDR Registers
Writing PRTxDR register sets output drive state high (for DIN=1) (DIN=0), unless bypass mode selected (either Enable=1 global select register written high). Reading PRTxDR returns actual state, seen input buffer. This same expected output state, load pulls more strongly than pin's configured output drive. additional information, reference PRTxDR register page
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6.2.4
PRTxDMx Registers
6.2.5
PRTxICx Registers
There eight possible drive modes each port pin. Three mode bits required select these modes, these three bits spread into three different registers (PRTxDM0, PRTxDM1, PRTxDM2). position effected port (Example: Pin[2] Port same position each three Drive Mode register bits that control drive mode that (Example: Bit[2] PRT0DM0, bit[2] PRT0DM1 bit[2] PRT0DM2). three bits from three registers treated group. These referred DM2, DM1, DM0, together DM[2:0]. Drive modes shown Table 6-3.
interrupt mode determined bits registers: PRTxIC1 PRTxIC0. These referred IM0, together IM[1:0]. There four possible interrupt modes each port pin. mode bits required select these modes these bits spread into different registers (PRTxIC0 PRTxIC1). position effected port (Example: Pin[2] Port same position each Interrupt Control register bits that control interrupt mode that (Example: Bit[2] PRT0IC0 bit[2] PRT0IC1). bits from registers treated group. interrupt mode must non-zero modes listed Table 6-4, order interrupt from pin.
Table 6-3. Drive Modes
Drive Mode DM[2:0] 000b 001b 010b 011b 100b 101b 110b 111b State Resistive pull down Strong drive High impedance Resistive pull Open drain high Slow strong drive High impedance, analog (reset state) Open drain Description Strong high, resistive Strong high, strong Hi-Z high low, digital input enabled Resistive high, strong Slow strong high, Hi-Z Slow strong high, slow strong Hi-Z high low, digital input disabled (for zero power) (reset state) Slow strong low, Hi-Z high
Table 6-4. GPIO Interrupt Modes
Interrupt Mode IM[1:0] Description interrupt disabled, INTO de-asserted Assert INTO when Assert INTO when high Assert INTO when change from last read
analog drive mode should Hi-Z modes, either 010b 110b. 110b mode advantage that block's digital input buffer disabled, "crowbar" current flows even when analog input close either power rail. When digital inputs needed same analog inputs, 010b Drive mode should used. 110b Drive mode used, will always read zero will able generate useful interrupt. strictly required that Hi-Z mode selected analog operation). global input modes, drive mode must 010b. This GPIO provides default drive mode high impedance (Hi-Z). This achieved forcing reset state PRTxDM1 PRTxDM2 registers FFh. resistive drive modes place resistance series with output, outputs (mode 000b) high outputs (mode 011b). Strong drive mode 001b gives fastest edges high drive strength. Mode 101b gives same drive strength with slower edges. Open drain modes (100b 111b) also slower edge rate drive. These modes enable open drain functions such mode 111b (although slow edge rate slow enough meet fast mode specification). additional information, reference PRTxDM2 register page PRTxDM0 register page 155, PRTxDM1 register page 156.
GPIO interrupt mode "disabled" (00b) disables interrupts from pin, even GPIO's interrupt enable (from PRTxIE register). Interrupt mode means that block will assert interrupt line (INTO) when voltage low, providing block's interrupt enable line (high). Interrupt mode means that block will assert interrupt line (INTO), when voltage high, providing block's interrupt enable line (high). Interrupt mode means that block will assert interrupt line (INTO) when voltage opposite last state read from (again providing block's interrupt enable line high). This mode switches between mode high mode, depending last value that read from port during reads data register (PRTxDR). last value read from GPIO GPIO will subsequently interrupt high mode. last value read from GPIO GPIO will then interrupt mode.
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Last Value Read From State Waveform GPIO interrupt enable Interrupt occurs State Waveform GPIO interrupt enable Interrupt occurs
Last Value Read From State Waveform GPIO interrupt enable Interrupt occurs State Waveform GPIO interrupt enable Interrupt occurs
Figure 6-3. GPIO Interrupt Mode
Figure assumes that set, GPIO interrupt mask set, that GPIO interrupt mode been 11b. change interrupt mode different from other modes, that relies value GPIO's read latch determine state changed. Therefore, port that contains GPIO question must read during every interrupt service routine. port read, interrupt mode will high mode when latch value mode when latch value additional information, reference PRTxIC0 register page PRTxIC1 register page 158.
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Analog Output Drivers
This chapter presents Analog Output Drivers associated register. analog output drivers provide means driving analog signals off-chip.
Table 7-1. Analog Output Driver Register
Address 1,62h Name ABF_CR0 ACol1Mux ABUF1EN0 ABUF0EN0 Bypass Access
PSoC device analog drivers used output analog values port pins. detailed drawing analog output drivers relation analog system, reference Analog Input Configuration chapter page 245.
Register Definitions
Table presents overview registers related analog output drivers. following section presents detail register's bits.
P0[5]
7.1.1
ABF_CR0 Register
P0[3]
This register controls analog input muxes from Port output buffer amplifiers that drive column outputs device pins.
Array
ACol1MUX. selects output column input column input mux. When set, this sets column input column input output.
ACB01 ASD11 ASC21
ACB00 ASC10 ASD20
Reserved. Bits ABUFxEN0. These bits enable disable column output amplifiers. Bits Reserved. Bypass. Bypass mode connects amplifier input directly output. When this set, amplifiers controlled register will bypass mode. PWR. This used power level amplifiers. When this set, amplifiers controlled register will high power.
additional information, reference ABF_CR0 register page 166.
Figure 7-1. Analog Output Drivers
Each these drivers resource available analog blocks particular analog column. user must select analog block column drive signal analog output (ABUS), serve input analog driver that column. output from analog output driver each column enabled disabled using Analog Output Driver register ABF_CR0.
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Analog Output Drivers
CY8C24xxx Preliminary Data Sheet
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Internal Main Oscillator (IMO)
This chapter briefly presents Internal Main Oscillator (IMO) associated register. produces clock signals MHz.
Table 8-1. Internal Main Oscillator Register
Address 1,E8h Name IMO_TR Trim[7:0] Access
Internal Main Oscillator outputs clocks: SYSCLK, which internal clock external clock, SYSCLK2X that always twice SYSCLK frequency. absence high-precision input source from crystal oscillator, accuracy internal MHz/48 clocks will +/-2.5% over temperature variation voltage ranges (3.3V +/-.3V 5.0V +/-5%). external components required achieve this level accuracy. There option phase lock this oscillator External Crystal Oscillator. choice crystal inherent accuracy will determine overall accuracy oscillator. External Crystal Oscillator must stable prior locking frequency Internal Main Oscillator this reference source. disabled when using external clocking source. Also, frequency doubler circuit, which produces SYSCLK2X, disabled save power. Note that when using external clock, SYSCLK2X needed, then disabled. Registers controlling these operations found Digital Clocks chapter page 263.
8.1.1
Register Definitions
IMO_TR Register
device specific value volt operation loaded into Internal Main Oscillator Trim Register (IMO_TR) boot time. Internal Main oscillator will operate within specified tolerance over voltage range 4.75V 5.25V, with modification this register. device operated lower voltage, user code must modify contents this register. operation voltage range 3.3V +/-.3V, this accomplished with Table Read command Supervisor ROM, which will supply trim value operation this range. operation between these Voltage ranges, user code interpolate best value using both available factory trim values.
Bits Trim. These bits used trim Internal Main Oscillator. larger value this register will increase speed oscillator.
additional information, reference IMO_TR register page 181.
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Internal Main Oscillator (IMO)
CY8C24xxx Preliminary Data Sheet
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October 2003
Internal Speed Oscillator (ILO)
This chapter briefly explains Internal Speed Oscillator (ILO) associated register. Internal Speed Oscillator produces clock.
Table 9-1. Internal Speed Oscillator Register
Address 1,E9h Name ILO_TR Access Bias Trim[1:0] Freq Trim[3:0]
Internal Speed Oscillator internal speed oscillator nominally kHz. available generate Sleep wake-up interrupts Watchdog resets. This oscillator also used clocking source Digital PSoC blocks. oscillator operates three modes: normal power, power, off. normal power mode consumes more current produce more accurate frequency. power mode always used when part power down (sleep) state selected during non-sleep, provides less frequency accuracy.
Table 9-2. Bias Current PTAT
Bias Current Medium Bias Maximum Bias Minimum Bias needed
About higher than minimum bias.
9.1.1
Register Definitions
ILO_TR Register
Bits Freq Trim. Four bits used trim frequency. LSB, MSB. gets inverted inside register; therefore, code turns current sources (f=0 kHz), code turns only current source (f=mid-scale), code turns current sources (f=max).
additional information, reference ILO_TR register page 182.
This register sets adjustment ILO. device specific value, placed trim bits this register boot time, based factory testing.
strongly recommended that user alter register value.
Bits Reserved. Bits Bias Trim. bits used bias current PTAT Current Source. gets inverted, that medium bias selected when both bits bias current according Table 9-2.
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Internal Speed Oscillator (ILO)
CY8C24xxx Preliminary Data Sheet
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October 2003
Crystal Oscillator (ECO)
This chapter briefly explains Crystal Oscillator (ECO) associated register. crystal oscillator circuit allows user replace internal speed oscillator with more precise time source cost power.
Table 10-1. Crystal Oscillator Register
Address 1,E0h 1,EBh x,FEh Name OSC_CR0 ECO_TR CPU_SCR1 Select Mode Buzz Speed[2:0] IRAMDIS Access RW:00 Sleep[1:0]
PSSDC[1:0]
crystal oscillator circuit uses inexpensive watch crystal small valued load capacitors external components. other components PSoC chip. crystal oscillator configured provide reference internal main oscillator mode generating more accurate system clock. XTALIn XTALOut pins support connection 32.768 watch crystal. from external crystal, Oscillator Control Register (OSC_CR0) must (default off). only external components crystal load capacitors that connect Vdd. Transitions between internal external oscillator domains produce glitches clock bus. During process activating ECO, there must hold-off period before using source. This hold period partially implemented hardware using Sleep Timer. Firmware must sleep period second (maximum settling time), then enable OSC_CR0 register. second time-out (the Sleep Interrupt), switch made hardware ECO. subsequently deactivated, will again activated switch made back immediately. firmware steps involved switching between internal speed oscillator Crystal Oscillator follows. reset, chip begins operation, using internal speed oscillator. Select sleep interval second using bits[4:3] Oscillator Control Register (OSC_CR0), oscillator stabilization interval. Enable Crystal Oscillator, setting Oscillator Control Register (OSC_CR0)
Crystal Oscillator becomes selected source, one-second interval edge created Sleep Interrupt logic. one-second interval gives oscillator time stabilize, before becomes active source. Sleep Interrupt need enabled switch-over occur. Reset sleep timer this does interfere with ongoing real-time clock operation), guarantee interval length. Note that internal speed oscillator continues run, until oscillator automatically switched over sleep timer interrupt. strongly advised wait one-second stabilization period prior engaging mode lock Internal Main Oscillator frequency Crystal Oscillator frequency. Note internal speed oscillator switches back instantaneously writing Select control zero. Note proper settings selected PSoC Designer, above steps automatically done boot.asm. Note Transitions between oscillator domains produce glitches clock bus. Functions that require accuracy clock should enabled after transition oscillator domains.
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Crystal Oscillator (ECO)
CY8C24xxx Preliminary Data Sheet
10.1 External Components
External Crystal Oscillator component connections selections illustrated Figure 10-1.
10.2
10.2.1
Register Definitions
OSC_CR0 Register
Select. default, clock source Internal Low-Speed Oscillator (ILO). Optionally, External Crystal Oscillator (ECO) selected.
XTALOut P1[0]
XTALIn P1[1] Crystal
Mode. This only OSC_CR0 register that directly influences PLL. When set, this enables PLL. EXTCLKEN OSC_CR2 register should during operation. Buzz. Normally, when Sleep CPU_SCR register, chip systems powered down, including Band reference. However, facilitate detection events rate higher than Sleep Interval, Band circuit powered periodically about Sleep System Duty cycle (set ECO_TR), which independent Sleep Interval typically higher. When Buzz set, Sleep System Duty Cycle value overridden, Band circuit forced during sleep. This results faster response event (continuous detection opposed periodic), expense slightly higher average sleep current. Bits Sleep[1:0]. available sleep interval selections shown Table 10-3. must remembered that when selected clock source, sleep intervals approximate. Table 10-3. Sleep Interval Selections
Sleep Interval OSC_CR[4:3] Sleep Timer Clocks Sleep Period (nominal) Watchdog Period (nominal)
Figure 10-1. External Crystal Oscillator Connections
Crystal 32.768 watch crystal such Edson C002RX. Capacitors ceramic caps.
equation below employ mode.
(Package Cap) (Board Parasitic Cap)
employ with External Crystal Oscillator, Application Note AN2027 under Support http://www.cypressmicro.com/ equation details. error gives about error frequency.
Table 10-2: Typical Package Capacitance Crystal Pins
Package PDIP SOIC PDIP SSOP SOIC PDIP SSOP SOIC Package Capacitance
(default)
4096 32,768
1.95 15.6
Bits Speed[2:0]. PSoC operate over range clock speeds (Table 10-4), allowing M8C's performance power requirements tailored application.
reset value Speed bits zero. Therefore, default speed one-eighth clock source. internal main oscillator default clock source speed circuit; therefore, default speed MHz. frequency changed with write OSC_CR0 register. There eight frequencies generated from power-of-2 divide circuit, which selected 3bit code. given time, clock multiplexer selecting available frequencies, which re-synchronized master clock output.
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CY8C24xxx Preliminary Data Sheet
Crystal Oscillator (ECO)
Regardless speed bit's setting, actual speed greater than MHz, operating requirements apply. example this scenario device that configured external clock, which supplying frequency MHz. speed register's value 0b011, clock will MHz. Therefore, supply voltage requirements device same part operating internal main oscillator. operating voltage requirements relaxed until speed 12.0 less.
Table 10-4. OSC_CR0[2:0] Bits: Speed
Bits 000b 001b 010b 011b 100b 101b 110b 111b Internal Main Oscillator 187.5 93.7 External Clock EXTCLK/ EXTCLK/ EXTCLK/ EXTCLK/ EXTCLK/ EXTCLK/ EXTCLK/ EXTCLK/
additional information, reference OSC_CR0 register page 176.
10.2.2
ECO_TR Register
External Crystal Oscillator Trim register (ECO_TR) sets adjustment External Crystal Oscillator. device specific value placed this register boot time based factory testing. This register does adjust frequency External Crystal Oscillator. recommended that user alter bits this register.
Bits PSSDC[1:0]. These bits used sleep duty cycle. Bits Reserved.
additional information, reference ECO_TR register page 184.
10.2.3
CPU_SCR1 Register
CPU_SCR1 register used convey status control events related internal resets watchdog reset.
Bits Reserved. IRAMDIS. Initialize Disable control that readable writeable. default value this which indicates that maximum amount SRAM should initialized reset value 00h. When set, minimum amount SRAM initialized after watchdog reset. more information this bit, "SROM Function Descriptions" page
additional information, reference CPU_SCR1 register page 153.
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Crystal Oscillator (ECO)
CY8C24xxx Preliminary Data Sheet
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Phase Locked Loop (PLL)
This chapter briefly presents Phase Locked Loop (PLL) associated registers.
Table 11-1. Phase Locked Loop Registers
Address 1,E0h 1,E2h Name OSC_CR0 OSC_CR2 Select PLLGAIN Mode Buzz Speed[2:0] EXTCLKEN IMODIS SYSCLKX2 Access Sleep[1:0]
Phase-Locked Loop (PLL) function generates system clock with crystal accuracy. designed provide 23.986 oscillator when utilized with external 32.768 crystal. Although tracks crystal accuracy, requires time lock onto reference frequency when first starting. length time depends PLLGAIN controlled OSC_CR2 register. this held low, lock time will less than this held high, lock time will order After lock achieved, recommended that this forced high decrease jitter output. longer lock time tolerable, PLLGAIN held high time. After External Crystal Oscillator been selected enabled, following procedure should followed enable allow proper frequency lock.
11.1
11.1.1
Register Definitions
OSC_CR0 Register
Select. default, clock source Internal Low-Speed Oscillator (ILO). Optionally, External Crystal Oscillator (ECO) selected. Mode. This only OSC_CR0 register that directly influences PLL. When set, this enables PLL. EXTCLKEN OSC_CR2 register should during operation. Buzz. Normally, when Sleep CPU_SCR register, chip systems powered down, including Band reference. However, facilitate detection events rate higher than Sleep Interval, Band circuit powered periodically about Sleep System Duty cycle (set ECO_TR), which independent Sleep Interval typically higher. When Buzz set, Sleep System Duty Cycle value overridden, Band circuit forced during sleep. This results faster response event (continuous detection opposed periodic), expense slightly higher average sleep current. Bits Sleep[1:0]. available sleep interval selections shown Table 11-2. must remembered that when selected clock source, sleep intervals approximate.
Select frequency less. Enable PLL. Wait between depending OSC_CR2 register faster frequency, desired. this, write bits Speed[2:0] OSC_CR0 register. frequency will immediately change when these bits set.
proper settings selected PSoC Designer, above steps automatically done boot.asm.
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Phase Locked Loop (PLL)
CY8C24xxx Preliminary Data Sheet
Table 11-2. Sleep Interval Selections
Sleep Interval OSC_CR[4:3] Sleep Timer Clocks Sleep Period (nominal) Watchdog Period (nominal)
11.1.2
OSC_CR2 Register
(default)
4096 32,768
1.95 15.6
PLLGAIN. This only OSC_CR2 register that directly influences PLL. When set, this keeps gain mode. Bits Reserved. EXTCLKEN. When EXTCLKEN set, external clock becomes source internal clock tree, SYSCLK, which drives most chip clocking functions. external internal signals, including clock, whether derived from internal speed oscillator (ILO) crystal oscillator, synchronized this clock source. external clock enabled, mode should off. IMODIS. When set, Internal Main Oscillator disabled. doubler enabled (SYSCLKX2DIS
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