CapsenseLITE Configurable CapSenseLITE controller allows control

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CapsenseLITE Configurable CapSenseLITE controller allows control

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CY8C20160
CapsenseLITE Configurable
CapSenseLITE controller allows control configurable capacitive sensing buttons GPIOs driving LEDs interrupt signals based various button conditions. GPIOs also configurable waking device from sleep based interrupt input. user ability configure buttons, outputs, parameters, through specific commands sent port. have flexibility mapping capacitive buttons standard GPIO functions such interrupt output input, drive digital mapping input output using simple logical operations. This enables easy trace routing reduces size stack CapsenseLITE products designed easy integration into complex products.
configurable supporting CapSense buttons drive Interrupt outputs WAKE interrupt input User defined input/output 2.4V 5.25V operating voltage Industrial temperature range: -40°C +85°C slave interface configuration Reduce cost Internal oscillator external oscillators crystal Free development tool external tuning components operating current Active current: continuous sensor scan Sleep current: scan, continuous sleep 2.6uA Available 16-pin 16-pin SOIC packages
Architecture
logic block diagram shows internal architecture CY8C20160. user configure registers with parameters needed adjust operation sensitivity CapSense system. CY8C20160 supports standard serial communication interface that allows host configure device read sensor information real time through easy register access.
CapSenseLITE Core
CapSenseLITE Core powerful configuration control block. encompasses SRAM data storage, interrupt controller, sleep watchdog timers. System resources provide additional capability, such configurable slave communication interface various system resets. Analog System composed CapSense PSoC block internal 1.8V analog reference, which together support capacitive sensing inputs.
Cypress Semiconductor Corporation Document Number:001-17347 Rev.
Champion Court
Jose, 95134-1709 408-943-2600 Revised November 2007
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CY8C20160
Logic Block Diagram
External 5.25 CapSenseLITE Core Flash 512B SRAM
Configurable
Document Number:001-17347 Rev.
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CY8C20160
Pinouts
Figure Diagram
GP0[4] CSInt GP0[3]
GP0[0] GP0[1]
GP0[2] XRES
GP1[4] GP1[3]
GP1[0] GP1[1]
GP1[2]
Table Definitions Number Name GP0[0] GP0[1] GP1[0] GP1[1] GP1[2] GP1[3] GP1[4] XRES GP0[2] GP0[3] CSInt GP0[4] Description Configurable CapSense GPIO Configurable CapSense GPIO clock data Configurable CapSense GPIO Configurable CapSense GPIO Ground connection Configurable CapSense GPIO Configurable CapSense GPIO Configurable CapSense GPIO Active HIGH external reset with internal pull down Configurable CapSense GPIO Supply voltage Configurable CapSense GPIO Integrating capacitor input Configurable CapSense GPIO
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CY8C20160
Figure Diagram SOIC
GP0[3] CSInt GP0[4] GP0[0] GP0[1] I2CSCL I2CSDA GP1[0]
GP0[2] XRES GP1[4] GP1[3] GP1[2] GP1[1]
SOIC (Top View)
Table Definitions SOIC Number Name GP0[3] CSInt GP0[4] GP0[0] GP0[1] GP1[0] GP1[1] GP1[2] GP1[3] GP1[4] XRES GP0[2] Description Configurable CapSense GPIO Integrating Capacitor Input Configurable CapSense GPIO Configurable CapSense GPIO Configurable CapSense GPIO clock data Configurable CapSense GPIO Configurable CapSense GPIO Ground connection Configurable CapSense GPIO Configurable CapSense GPIO Configurable CapSense GPIO Active HIGH external reset with internal pull down. Configurable CapSense GPIO Supply voltage
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CY8C20160
CapSense Analog System
CapSense analog system contains capacitive sensing hardware. CapSense Successive Approximation (CSA) algorithm supported. This hardware performs capacitive sensing scanning without external components. Capacitive sensing configurable each pin.
Interface
modes operation interface are:
Device register configuration status read/write controller Command execution
Additional System Resources
System Resources provide additional capability useful complete systems. Additional resources voltage detection Power Reset (POR).
address programmable during configuration. locked prevent accidental change setting flag configuration register.
CapSenseLITE Software Tool
easy software tool integrated with PSoC Express available configuring tuning CapSenseLITE devices. Refer Application Note AN42137 details software tool.
slave provides 100, communication over wires. Voltage Detection (LVD) interrupts signal application falling voltage levels advanced (Power Reset) circuit eliminates need system supervisor.
internal 1.8V reference provides absolute reference capacitive sensing.
Electrical Specifications
Absolute Maximum Ratings
Parameter TSTG Description Storage temperature +100 Unit Notes Higher storage temperatures reduce data retention time. Recommended storage temperature +25°C 25°C. Extended duration storage temperatures above 65°C degrade reliability.
VIOZ IMIO
Ambient temperature with power applied Supply voltage relative input voltage voltage applied tri-state Maximum current into GPIO Electro static discharge voltage Latch current
-0.5 2000
+6.0
Human body model
Operating Temperature
Parameter Description Ambient temperature Junction temperature +100 Unit Notes
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CY8C20160
Electrical Characteristics
Chip Level Specifications
Parameter ISB27 Description Supply voltage Supply current Sleep mode current with active. temperature range Sleep mode current with active. 2.40 5.25 Unit Conditions 3.0V, 25°C 2.55V, 40°C Notes
Electrical Characteristics
3.3V, -40°C 85°C
3.3V General Purpose Specifications
Parameter VOH1 VOH2 VOH3 VOH4 VOH5 Description Pull resistor High output voltage Port pins High output voltage Port pins High output voltage Port pins High output voltage Port pins High output voltage Port pins with 3.0V regulator enabled High Output Voltage Port pins with 3.0V regulator enabled High Output Voltage Port pins with 2.4V regulator enabled High Output Voltage Port pins with 2.4V regulator enabled High Output Voltage Port pins with 1.8V regulator enabled High Output Voltage Port pins with 1.8V regulator enabled output voltage 2.75 Unit 3.0V, maximum source current IOs. 3.0V, maximum source current IOs. Vdd> 3.0V, maximum source current IOs. 3.0V, maximum source current IOs. Vdd> 3.1V, maximum sourcing 5mA. 3.1V, maximum source current IOs. 3.0V, maximum source current IOs. 3.0V, maximum source current IOs. 3.0V< 3.6V, 85°C, maximum source current IOs. 3.0V< 3.6V, 85°C, maximum source current IOs. maximum sink current even port pins (for example, P0[2] P1[4]) sink current port pins (for example, P0[3] P1[3]). 5.25V. 5.25V. Notes
VOH6
VOH7
VOH8
VOH9
1.95
VOH10
0.75
Input voltage Input high voltage Input hysteresis voltage
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CY8C20160
3.3V General Purpose Specifications (continued)
Parameter COUT Description Input leakage Capacitive load pins input Capacitive load pins output Unit Notes Gross tested Package dependent. Temp 25°C. Package dependent. Temp 25°C.
2.7V General Purpose Specifications
Parameter VOH1 VOH2 VOH3 VOH4 Description Pull resistor High output voltage Port pins High output voltage Port pins High output voltage Port pins High output voltage Port pins output voltage 0.75 Unit maximum source current IOs. maximum source current IOs. maximum source current IOs. maximum source current IOs. maximum sink current even port pins (for example, P0[2] P1[4]) sink current port pins (for example, P0[3] P1[3]). IOL=5mA Maximum 50mA sink current even port pins (for example, P0[2] P1[4]) 50mA sink current port pins (for example, P0[1] P1[3]). 2.4<=Vdd<=3.6V 3.6V. 2.7V. 3.6V Gross tested Package dependent. Temp 25°C. Package dependent. Temp 25°C. Notes
VOLP1
output voltage port pins
VIH1 VIH2 COUT
Input voltage Input high voltage Input high voltage Input hysteresis voltage Input leakage Capacitive load pins input Capacitive load pins output
0.75
Specifications
Parameter VPPOR0 VPPOR1 Description Value PPOR Trip VDD= 2.7V VDD= 3.3V,5V Value trip VDD= 2.7V VDD= 3.3V VDD= 2.36 2.60 2.40 2.65 Unit Notes must greater than equal 2.5V during startup, reset from XRES pin, reset from Watchdog.
VLVD0 VLVD2 VLVD6
2.39 2.75 3.98
2.45 2.92 4.05
2.51 2.99 4.12
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CY8C20160
5.0V 3.3V General Purpose Specifications Parameter TRise0 TRise1 TFall Description Rise time, strong mode, Cload 50pF, Port Rise time, strong mode, Cload 50pF, Port Fall time, strong mode, Cload 50pF, ports Unit Notes 3.0V 3.6V 4.75V 5.25V, 3.0V 3.6V, 3.0V 3.6V 4.75V 5.25V,
2.7V General Purpose Specifications Parameter TRise0 TRise1 TFall Description Rise time, strong mode, Cload 50pF, Port Rise time, strong mode, Cload 50pF, Port Fall time, strong mode, Cload 50pF, ports Unit Notes 2.4V 3.0V, 2.4V 3.0V, 2.4V 3.0V,
Specifications
Parameter FSCLI2C THDSTAI2C Description clock frequency Hold time (repeated) START condition. After this period, first clock pulse generated. period clock HIGH period clock Setup time repeated START condition Data setup time free time between STOP START condition Pulse width spikes suppressed input filter Standard Mode Fast Mode Fast mode supported 3.0V Unit Notes
TLOWI2C THIGHI2C TSUSTAI2C
THDDATI2C Data hold time TSUDATI2C TBUFI2C TSPI2C TSUSTOI2C Setup time STOP condition
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CY8C20160
Figure Definition Timing Fast/Standard Mode
TLOWI2C TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
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CY8C20160
Ordering Information
Ordering Code CY8C20160-LDX2I CY8C20160-SX2I Package Diagram 001-09116 51-85068 Package Type SOIC Operating Temperature Industrial Industrial
Thermal Impedances Package
Package SOIC
Note Power
Typical JA[1] °C/W 79.96 °C/W
Solder Reflow Peak Temperature
Package SOIC Minimum Peak Temperature[2] Maximum Peak Temperature
Note Higher temperatures required based solder melting point. Typical temperatures solder with Sn-Pb with Sn-Ag-Cu paste. Refer solder manufacturer specifications.
Package Diagram
Figure Chip Pb-free (Sawn)
DIMENSIONS MIN. MAX.
0.20
0.45 0.55
0.20 TYP. 0.05 0.60
(NOM) 0.152 REF.
0.30 0.18 0.50
SEATING PLANE
VIEW
SIDE VIEW
BOTTOM VIEW
PART LG16A LD16A
DESCRIPTION LEAD-FREE STANDARD
JEDEC MO-220 Package Weight: 0.014g
001-09116-*C
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CY8C20160
Figure (150-Mil) SOIC
51-85068-*B
Document Number:001-17347 Rev.
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CY8C20160
Document History Page
Document Title: CY8C20160 CapsenseLITE Configurable Document Number: 001-17347 REV. 1341766 1494145 Issue Date Orig. Change TUP/ Data Sheet SFVTMP TUP/AESA Changed FINAL Datasheet Removed table 2.7V General Purpose Specifications Open Drain with pull 1.8V Updated Logic Block Diagram TUP/AESA Removed table General Purpose Specifications Updated Logic Block Diagram Updated table Specifications Updated table Chip Level Specifications Updated table 3.3V General Purpose Specifications Updated table 2.7V General Purpose Specifications Updated table GPIO Specifications split into tables 5V/3.3V 2.7V Added section CapSenseLITE Software tool Updated 16-QFN Package Diagram Description Change
1773608
Cypress Semiconductor Corporation, 2007. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. Source Code (software and/or firmware) owned Cypress Semiconductor Corporation (Cypress) protected subject worldwide patent protection (United States foreign), United States copyright laws international treaty provisions. Cypress hereby grants licensee personal, non-exclusive, non-transferable license copy, use, modify, create derivative works compile Cypress Source Code derivative works sole purpose creating custom software firmware support licensee product used only conjunction with Cypress integrated circuit specified applicable agreement. reproduction, modification, translation, compilation, representation this Source Code except specified above prohibited without express written permission Cypress. Disclaimer: CYPRESS MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Cypress reserves right make changes without further notice materials described herein. Cypress does assume liability arising application product circuit described herein. Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress' product life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. limited subject applicable Cypress software license agreement.
Document Number:001-17347 Rev.
Revised November 2007
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PSoC DesignerTM, Programmable System-on-ChipTM, PSoC Expressare trademarks PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations. Purchase components from Cypress sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. products company names mentioned this document trademarks their respective holders.
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CapsenseLITE Configurable CapSenseLITE controller allows control

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