CapSenseLITE Configurable CapSenseLITE controller allows control
|
|
|
Top Searches for this datasheet
CY8C20142
CapSenseLITE Configurable
CapSenseLITE controller allows control four configurable capacitive sensing buttons GPIOs driving LEDs interrupt signals based various button conditions. GPIOs also configurable waking device from sleep based interrupt input. user ability configure buttons, outputs, parameters, through specific commands sent port. have flexibility mapping capacitive buttons standard GPIO functions such interrupt output input, drive digital mapping input output using simple logical operations. This enables easy trace routing reduces size stack CapsenseLITE products designed easy integration into complex products.
Four configurable supporting CapSense buttons drive Interrupt outputs WAKE interrupt input User defined Input/output 2.4V 5.25V operating voltage Industrial temperature range: -40°C +85°C slave interface configuration Reduce cost Internal oscillator external oscillators crystal Free development tool external tuning components Operating Current Active current: continuous sensor scan Sleep current: scan, continuous sleep 2.6uA Available 8-pin SOIC package
Architecture
logic block diagram shows internal architecture CY8C20142. user configure registers with parameters needed adjust operation sensitivity CapSense system. CY8C20142 supports standard serial communication interface that allows host configure device read sensor information real time through easy register access.
CapSenseLITE Core
CapSenseLITE Core powerful configuration control block. encompasses SRAM data storage, interrupt controller, sleep watchdog timers. System resources provide additional capability, such configurable slave communication interface various system resets. Analog System composed CapSense PSoC block internal 1.8V analog reference, which together support capacitive sensing inputs.
Cypress Semiconductor Corporation Document Number: 001-32159 Rev.
Champion Court
Jose, 95134-1709 408-943-2600 Revised November 2007
Feedback
CY8C20142
Logic Block Diagram
External 5.25 CapSenseLITE Core Flash 512B SRAM
Configurable
Document Number: 001-32159 Rev.
Page
Feedback
CY8C20142
Pinouts
Figure Diagram SOIC
GP1[0]
GP0[1] GP0[0] GP1[1]
Table Definitions SOIC Name Ground connection clock data Configurable CapSense GPIO Configurable CapSense GPIO Configurable CapSense GPIO Configurable CapSense GPIO Supply Voltage Description
GP1[0] GP1[1] GP0[0] GP0[1]
Document Number: 001-32159 Rev.
Page
Feedback
CY8C20142
CapSense Analog System
capsense analog system contains capacitive sensing hardware.The CapSense Successive Approximation (CSA) algorithm supported.This hardware performs capacitive sensing scanning without requiring external components. Capacitive sensing configurable each GPIO pin.
Interface
modes operation interface are:
Device register configuration status read/write controller Command execution
Additional System Resources
System resources provide additional capability useful complete systems. Additional resources voltage detection power reset.
address programmable during configuration. locked prevent accidental change setting flag configuration register.
CapSenseLITE Software Tool
easy software tool integrated with PSoC Express available configuring tuning CapSenseLITE devices. Refer Application Note AN42137 details software tool.
slave provides 100, communication over wires. Voltage Detection (LVD) interrupts signal application falling voltage levels advanced (Power Reset) circuit eliminates need system supervisor.
internal 1.8V reference provides absolute reference capacitive sensing.
Electrical Specifications
Absolute Maximum Ratings
Parameter TSTG Description Storage temperature +100 Unit Notes Higher storage temperatures reduce data retention time. Recommended storage temperature +25°C 25°C. Extended duration storage temperatures above 65°C degrade reliability.
VIOZ IMIO
Ambient temperature with power applied Supply voltage relative input voltage voltage applied tri-state Maximum current into GPIO Electro static discharge voltage Latch current
-0.5 2000
+6.0
Human body model
Operating Temperature
Parameter Description Ambient temperature Junction temperature +100 Unit Notes
Document Number: 001-32159 Rev.
Page
Feedback
CY8C20142
Electrical Characteristics
Chip Level Specifications
Parameter ISB27 Description Supply voltage Supply current Sleep mode current with active. temperature range Sleep mode current with active. 2.40 5.25 Unit Conditions 3.0V, 25°C 2.55V, 40°C 3.3V, -40°C 85°C Notes
3.3V General Purpose Specifications
Parameter VOH1 VOH2 VOH3 VOH4 VOH5 Description Pull resistor High output voltage Port pins High output voltage Port pins High output voltage Port pins High output voltage Port pins High output voltage Port pins with 3.0V regulator enabled High Output Voltage Port pins with 3.0V regulator enabled High Output Voltage Port pins with 2.4V regulator enabled High Output Voltage Port pins with 2.4V regulator enabled output voltage 2.75 Unit 3.0V, maximum source current IOs. 3.0V, maximum source current IOs. Vdd> 3.0V, maximum source current IOs. 3.0V, maximum source current IOs. Vdd> 3.1V, maximum sourcing 5mA. 3.1V, maximum source current IOs. 3.0V, maximum source current IOs. 3.0V, maximum source current IOs. maximum sink current even port pins (for example, P0[2] P1[4]) sink current port pins (for example, P0[3] P1[3]). 5.25V. 5.25V. Gross tested Package dependent. Temp 25°C. Package dependent. Temp 25°C. Notes
VOH6
VOH7
VOH8
0.75
COUT
Input voltage Input high voltage Input hysteresis voltage Input leakage Capacitive load pins input Capacitive load pins output
Document Number: 001-32159 Rev.
Page
Feedback
CY8C20142
2.7V General Purpose Specifications
Parameter VOH1 VOH2 VOH3 VOH4 Description Pull resistor High output voltage Port pins High output voltage Port pins High output voltage Port pins High output voltage Port pins output voltage 0.75 Unit maximum source current IOs. maximum source current IOs. maximum source current IOs. maximum source current IOs. maximum sink current even port pins (for example, P0[2] P1[4]) sink current port pins (for example, P0[3] P1[3]). IOL=5mA Maximum 50mA sink current even port pins (for example, P0[2] P1[4]) 50mA sink current port pins (for example, P0[1] P1[3]). 2.4<=Vdd<=3.6V 3.6V. 2.7V. 3.6V Gross tested Package dependent. Temp 25°C. Package dependent. Temp 25°C. Notes
VOLP1
output voltage port pins
VIH1 VIH2 COUT
Input voltage Input high voltage Input high voltage Input hysteresis voltage Input leakage Capacitive load pins input Capacitive load pins output
0.75
Specifications
Parameter VPPOR0 VPPOR1 Description Value PPOR Trip VDD= 2.7V VDD= 3.3V,5V Value trip VDD= 2.7V VDD= 3.3V VDD= 2.36 2.60 2.40 2.65 Unit Notes must greater than equal 2.5V during startup, reset from XRES pin, reset from Watchdog.
VLVD0 VLVD2 VLVD6
2.39 2.75 3.98
2.45 2.92 4.05
2.51 2.99 4.12
Document Number: 001-32159 Rev.
Page
Feedback
CY8C20142
Electrical Characteristics
5.0V 3.3V General Purpose Specifications Parameter TRise0 TRise1 TFall Description Rise time, strong mode, Cload 50pF, Port Rise time, strong mode, Cload 50pF, Port Fall time, strong mode, Cload 50pF, ports Unit Notes 3.0V 3.6V 4.75V 5.25V, 3.0V 3.6V, 3.0V 3.6V 4.75V 5.25V,
2.7V General Purpose Specifications Parameter TRise0 TRise1 TFall Description Rise time, strong mode, Cload 50pF, Port Rise time, strong mode, Cload 50pF, Port Fall time, strong mode, Cload 50pF, ports Unit Notes 2.4V 3.0V, 2.4V 3.0V, 2.4V 3.0V,
Specifications
Parameter FSCLI2C Description clock frequency Standard Mode Fast Mode Unit Notes Fast mode supported 3.0V
THDSTAI2C Hold time (repeated) START condition. After this period, first clock pulse generated. TLOWI2C THIGHI2C TSUSTAI2C period clock HIGH period clock Setup time repeated START condition
THDDATI2C Data hold time TSUDATI2C Data setup time TSUSTOI2C Setup time STOP condition TBUFI2C TSPI2C free time between STOP START condition Pulse width spikes suppressed input filter
Document Number: 001-32159 Rev.
Page
Feedback
CY8C20142
Figure Definition Timing Fast/Standard Mode
TLOWI2C TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
Document Number: 001-32159 Rev.
Page
Feedback
CY8C20142
Ordering Information
Ordering Code CY8C20142-SX1I Package Diagram 51-85066 Package Type SOIC Operating Temperature Industrial
Thermal Impedances Package
Package SOIC
Note Power
Typical JA[1] 127.22 °C/W
Solder Reflow Peak Temperature
Package SOIC Minimum Peak Temperature[2] Maximum Peak Temperature
Note Higher temperatures required based solder melting point. Typical temperatures solder with Sn-Pb with Sn-Ag-Cu paste. Refer solder manufacturer specifications.
Package Diagram
Figure (150-Mil) SOIC
DIMENSIONS INCHES[MM] MIN. MAX. OPTIONAL, ROUND SINGLE LEADFRAME RECTANGULAR MATRIX LEADFRAME REFERENCE JEDEC MS-012
0.230[5.842] 0.244[6.197]
0.150[3.810] 0.157[3.987]
PACKAGE WEIGHT 0.07gms
PART S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG.
0.189[4.800] 0.196[4.978]
SEATING PLANE
0.010[0.254] 0.016[0.406]
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249]
0.0138[0.350] 0.0192[0.487]
51-85066-*C
Document Number: 001-32159 Rev.
Page
Feedback
CY8C20142
Document History Page
Document Title: CY8C20142 CapSenseLITE Configurable Document Number: 001-32159 REV. ECN. 1494145 1773608 Issue Date Orig. Change TUP/AESA Datasheet TUP/AESA Removed table General Purpose Specifications Updated Logic Block Diagram Updated table Specifications Updated table Chip Level Specifications Updated table 3.3V General Purpose Specifications Updated table 2.7V General Purpose Specifications Updated table GPIO Specifications split into tables 5V/3.3V 2.7V Added section CapSenseLITE Software tool Description Change
Cypress Semiconductor Corporation, 2007. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. Source Code (software and/or firmware) owned Cypress Semiconductor Corporation (Cypress) protected subject worldwide patent protection (United States foreign), United States copyright laws international treaty provisions. Cypress hereby grants licensee personal, non-exclusive, non-transferable license copy, use, modify, create derivative works compile Cypress Source Code derivative works sole purpose creating custom software firmware support licensee product used only conjunction with Cypress integrated circuit specified applicable agreement. reproduction, modification, translation, compilation, representation this Source Code except specified above prohibited without express written permission Cypress. Disclaimer: CYPRESS MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Cypress reserves right make changes without further notice materials described herein. Cypress does assume liability arising application product circuit described herein. Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress' product life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. limited subject applicable Cypress software license agreement.
Document Number: 001-32159 Rev.
Revised November 2007
Page
PSoC DesignerTM, Programmable System-on-ChipTM, PSoC Expressare trademarks PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations. Purchase components from Cypress sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. products company names mentioned this document trademarks their respective holders.
Feedback
Other recent searches
TC94A29FAG - TC94A29FAG TC94A29FAG Datasheet
TC94A29FB - TC94A29FB TC94A29FB Datasheet
MPC823 - MPC823 MPC823 Datasheet
MAX3737 - MAX3737 MAX3737 Datasheet
KBP404G - KBP404G KBP404G Datasheet
KBP410G - KBP410G KBP410G Datasheet
CD4051B - CD4051B CD4051B Datasheet
CD4052B - CD4052B CD4052B Datasheet
CD4053B - CD4053B CD4053B Datasheet
AN2056 - AN2056 AN2056 Datasheet
2SK2503 - 2SK2503 2SK2503 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
