Target Application: Buses Interfaces Family: FLEX Vendor: Fe

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Target Application: Buses Interfaces Family: FLEX Vendor: Fe

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Master/Target Interface Megafunction
Target Application:
Buses Interfaces Family: FLEX Vendor:
Features
Optimized Altera® FLEX® device architecture Fully compliant with peripheral component interconnect Special Interest Group (PCI-SIG) Local Specification, Rev. Fully synchronous design Fully hardware tested Supports full-speed burst support Mbytes/second Supports zero-wait state data transfer rate
Applications Soleillet 75971 Paris Cedex France Tel. (33) 01-40-33-79-98 Fax. (33) 01-43-58-14-15 plda@worldnet.fr http://www.plda.com
General Description
master/target interface megafunction 32-bit interface that used high-speed data transfers real-time computing applications such fast data-intensive projects migration ISA-based designs designs. Figure shows block diagram megafunction.
Figure Block Diagram Master/Target Interface Megafunction
Master/Target Megafunction
ncbe[3.0] nframe nirdy ndevsel ntrdy nstop rst_hard sm_out[9.0] pci_rw m_data_valid s_data_valid s_disco
Master/Target State Machine
m_access m_hold m_gnt m_end
ngnt
m_abort t_abort
nserr nperr
Parity Calculation Reporting
Access Decoder
idsel ad[31.0]
Configuration Space Support
m_en data_out[31.0]
32-Bit Data Path
data_in[31.0] interrupt int_reset int_en m_req
ninta
Interrupt Support
nreq
Support
m_reg[1.0] m_reg_in[31.0] m_reg_cs
Altera Corporation
A-SB-026-02
ALTERA MEGAFUNCTION PARTNERS PROGRAM
Master/Target Interface Megafunction
Functional Description
master/target interface megafunction provides simple flexible interface between user-developed design. megafunction comes with Altera Hardware Description Language (AHDLTM) reference designs that designers customize their projects. These reference designs include interface that uses FLEX embedded array blocks (EABs) synchronous SRAM buffer another interface that based external SRAM buffer. addition, megafunction built-in direct-memory access (DMA) controller that interfaces with either internal memory external memory. operations programmed through software user's application logic. megafunction also support alternative back-end interfaces, such external firstin first-out (FIFO) buffer.
Performance
megafunction operates MHz. Table provides typical utilization results megafunction.
Table Typical Utilization Results Master/Target Interface Megafunction
Implementation
32-bit master/target
Target Device
EPF10K20-3 EPF10K30-3 EPF10K40-3
Clock (fMAX)
EABs
Logic Cells
1,152 1,728 2,304 1,152 1,728 2,304
Logic Cells Used
32-bit master/target with internal SRAM
EPF10K20-3 EPF10K30-3 EPF10K40-3
Customization
master/target interface megafunction fully parameterizable, allowing designer customize memory space location size (between bytes Mbytes); device, vendor, class code, revision registers; MAX_LAT MIN_GNT master registers.
Hardware Testing
master/target interface megafunction been developed tested using PCI_GEN02 evaluation board (available from Applications). PCI_GEN02 contains either EPF10K20 EPF10K30 device that implements megafunction. Because megafunction uses EPF10K30, remaining logic EABs device available user-defined custom logic. Figure shows block diagram PCI_GEN02 evaluation board.
Altera Corporation
Master/Target Interface Megafunction
Figure Block Diagram PCI_GEN02 Evaluation Board
PCI_GEN02 Hardware Prototyping Evaluation Board EPC1 BitBlaster/ByteBlaster Download Cable Connector
External Power Connector
EPF10K10
Component Prototyping Area
50-Pin External Connect (Optional)
Three 50-Pin Connectors
FLEX device configured using EPC1Configuration EPROM, BitBlasterdownload cable, ByteBlasterdownload cable. These options allow designer choose between variety configuration techniques. Three 50-pin headers provided daughter card, 50-pin off-card connector supported PCI_GEN02 solder mask.
Reference
Special Interest Group. Local Specification. Rev.2.1 Hillsboro, Oregon: Special Interest Group, 1995.
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com
Copyright 1997 Altera Corporation. Altera, AHDL, AMPP, BitBlaster, ByteBlaster, EPC1, FLEX, FLEX 10K, EPF10K40, EPF10K30, EPF10K20, EPF10K10 trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.
Altera Corporation

Target Application: Buses Interfaces Family: FLEX Vendor: Fe

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