Target Application: Buses Interfaces Family: FLEX FLEX 8000 Vendo

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Target Application: Buses Interfaces Family: FLEX FLEX 8000 Vendo

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Target Interface Megafunction
Target Application:
Buses Interfaces Family: FLEX FLEX 8000 Vendor:
Features
Optimized Altera® FLEX® FLEX 8000 device architectures Fully compliant with peripheral component interconnect Special Interest Group (PCI-SIG) Local Specification, Rev. Fully synchronous design Fully hardware tested Supports full-speed burst support Mbytes/second Provides zero-wait state data transfer rate
Applications Soleillet Paris 75020 France Tel. (33) 01-40-33-79-98 Fax. (33) 01-43-58-14-15 plda@worldnet.fr http://www.plda.com
General Description
target interface megafunction 32-bit interface that used high-speed data transfers real-time computing applications such fast dataintensive projects migration ISA-based designs designs. Figure shows block diagram megafunction. Figure Target Interface Megafunction Block Diagram
Target Megafunction
ncbe[3.0] nframe nirdy ndevsel ntrdy nstop rst_hard nserr nperr sm_out[6.0] pci_rw
Target State Machine
s_data_valid s_disco
Parity Calculation Reporting
Access Decoder
idsel ad[31.0] ninta
Configuration Space Support
data_out[31.
32-Bit Data Path
data_in[31. s_interrupt
Interrupt Support
int_reset int_en comm_in[15.0]
Communication Registers
comm_out[15.0]
Altera Corporation
A-SB-025-01
ALTERA MEGAFUNCTION PARTNERS PROGRAM
Target Interface Megafunction
Functional Description
target interface megafunction provides simple flexible interface between user-developed back-end application. megafunction maintains high performance accuracy through full parity calculation reporting. handling implemented with full support disconnect retry events; megafunction handles interrupt.
Performance
target interface megafunction operates MHz. Table provides typical utilization results megafunction.
Table Typical Utilization Results Target Interface Megafunction
Implementation
32-bit target
Target Device
EPF10K10-3 EPF10K20-3 EPF10K30-3 EPF10K40-3 EPF10K10-3
Clock (fMAX)
EABs
Logic Cells
1152 1728 2304 1152 1728 2304
Logic Cells Used
32-bit target with internal SRAM
EPF10K20-3 EPF10K30-3 EPF10K40-3
Customization
target interface megafunction fully parameterizable, allowing designer customize memory space location size (between bytes Mbytes), device, vendor, class code, revision registers.
Hardware Testing
target interface megafunction been developed tested using PCI_GEN02 evaluation board (available from Applications). PCI_GEN02 contains EPF10K10 device that implements megafunction. megafunction uses only EPF10K10 device, remaining logic resources available user-defined custom logic. Figure shows block diagram PCI_GEN02 evaluation board.
Altera Corporation
Target Interface Megafunction
Figure Block Diagram PCI_GEN02 Evaluation Board
PCI_GEN02 Hardware Prototyping Evaluation Board EPC1 BitBlaster/ByteBlaster Download Cable Connector
External Power Connector
EPF10K10
Component Prototyping Area
50-Pin External Connect (Optional)
Three 50-Pin Connectors
EPF10K10 device configured using Configuration EPROM, download cable, download cable. These options allow designer choose between variety configuration techniques. Three 50-pin headers provided daughter card, 50-pin off-card connector supported PCI_GEN02 solder mask. target applications also developed tested using PCI_GEN01 evaluation board. PCI_GEN01 used implement custom hardware bus. PCI_GEN01 contains EPM7256S device that implements target interface EPF10K50 device that used user-defined custom logic. EPF10K50 device configured using EPC1 Configuration EPROM target interface. Figure shows block diagram PCI_GEN01 evaluation board.
Figure Block Diagram PCI_GEN01 Evaluation Board
PCI_GEN01 Hardware Prototyping Evaluation Board EPC1
EPM7256S
128K SRAM (Shared)
EPF10K50
Status LEDs
SRAM (PCI Signal Sampling) 32-Pin External Interface
Altera Corporation
Target Interface Megafunction
EPF10K50 device provides significant logic resources implementing evaluating hardware bus. EPM7256S EPF10K50 devices share common 128-Kbyte SRAM space. EPM7256S device controls separate 64-Kbyte SRAM buffer that captures control signals provides signal analyzer bus. EPF10K50 device drives four status LEDs, connected external 32-pin interface.
Reference
Special Interest Group. Local Specification. Rev.2.1 Hillsboro, Oregon: Special Interest Group, 1995.
2610 Orchard Parkway Jose, 95134-2020 (408) 544-7000 http://www.altera.com
Copyright 1997 Altera Corporation. Altera, AHDL, AMPP, BitBlaster, ByteBlaster, EPC1, FLEX, FLEX 10K, FLEX 8000, EPF10K50, EPF10K30, EPM7256, EPM7256S trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.
Altera Corporation

Target Application: Buses Interfaces Family: FLEX FLEX 8000 Vendo

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