Target Application: Interface Family: FLEX Vendor: Features

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Target Application: Interface Family: FLEX Vendor: Features

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Master/Target MegaCore Function
Target Application:
Interface Family: FLEX Vendor:
Features
Optimized Altera® FLEX® EPF10K30RC240-3 device Includes 32-bit peripheral component interconnect (PCI) that support 33-MHz operation Supports zero-wait state burst mode
General Description
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master/target (pci_a) MegaCorefunction offers flexibility high performance programmable logic device (PLD) implementation board space benefits single-chip integration. function perform zero-wait state read throughput rate Mbytes/second zero-wait state write throughput rate Mbytes/second. function easily "dropped design that designer quickly implement entire design onto single PLD. pci_a MegaCore function optimized EPF10K30RC240-3 device. Since function takes less than usable gates EPF10K30RC240-3 device, there ample room user implement custom logic single-chip integration entire design. prototype board also available with function implementing testing designs. prototype board contains EPF10K30RC240-3 device, which configured with design. board provides connector socket interface other sockets accessing EPF10K30RC240-3 device pins. board also Kbytes SRAM target address space interface that displays function.
Functional Description
pci_a MegaCore function following functional components:
master/target interface Master functions Kbyte address space single cycle read write burst read write Target functions Header type configuration target read write Parity generation parity error detection Disconnect, retry, abort functions Embedded control engine with internal 64-byte buffer 32-bit customer logic support interface configuration registers
Figure shows block diagram pci_a MegaCore function.
Altera Corporation
A-SB-020-01
MegaCore
Master/Target MegaCore Function
Figure pci_a MegaCore Function Block Diagram
pci_a MegaCore Function
rstn l_adr[18.0] idsel Configuration Registers Local Side Target Access Control l_csn l_rdn l_wrn ad[31.0] cben[3.0] Address/ Data Buffering Local Side Access Control
l_ackn l_clk l_reset l_holdn l_req l_irqn l_dat_in[31.0] l_dat_out[31.0]
reqn gntn intan framen irdyn devseln trdyn stopn Master Interface
Local Data Buffering
Registers Target Interface
perrn serrn
Parity Checking Generation
64-Byte Buffer (EAB)
pci_a MegaCore function contains control engine that supports burst read write data transfers. transfer data bus, system software loads internal registers. function then ready accept local request signal that enables master initiate data transfers bus. example, burst read, master stores read information buffer from bus. After burst transaction completed, pci_a MegaCore function indicates local side that will transfer data from buffer local side memory. Similarly, burst write, function indicates local side that ready transfer data from local side buffer. When buffer full, pci_a MegaCore function last data word, function requests access bus. After arbiter grants function access, function will transfer data from buffer bus. pci_a MegaCore function, target capability used single data phase accesses. Target accesses typically used accessing configuration registers, internal registers, external target memory space.
additional information pci_a MegaCore function, refer Master/Target MegaCore Function with Data Sheet.
Altera Corporation
Master/Target MegaCore Function
OpenCore Evaluation
designer evaluate pci_a MegaCore function before purchase using OpenCorefeature that provided with MAX+PLUS® development software. This pre-purchase evaluation system allows designers instantiate simulate pci_a MegaCore function.
Performance Implementation
pci_a MegaCore function offers high data bandwidth zero-wait state burst data transfers. also supports 256-byte, header type-0 configuration. Table shows performance characteristics pci_a MegaCore function.
Table pci_a MegaCore Function Performance Characteristics
Characteristic
Clock rate Read data burst transfer rate Write data burst transfer rate
Values
Mbytes/second Mbytes/second
pci_a MegaCore function uses less than logic elements (LEs) available EPF10K30RC240-3 device. remaining logic elements (LEs) used user-defined local-side customization. Table shows typical device utilization pci_a MegaCore function EPF10K30RC240-3 device with 1,728 available.
Table Typical Device Utilization
Function pci_a MegaCore function (includes complete circuit)
Local side with custom logic
Compliance
Table describes timing elements EPF10K30RC240-3 device that compliant with Special Interest Group's (PCI-SIG) Local Specification, revision 2.1.
Table Timing Elements EPF10K30RC240-3 Device
Timing Element
Clock-to-output time Set-up time Maximum clock rate
Specification
Reference
Special Interest Group. Local Specification. Rev. 2.1. Hillsboro, Oregon: Special Interest Group, 1995.
Copyright 1997 Altera Corporation. Altera, MegaCore, OpenCore, MAX, MAX+PLUS, MAX+PLUS FLEX, FLEX 10K, EPF10K30 trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. rights reserved.
2610 Orchard Parkway Jose, 95134-2020 (408) 544-7000 http://www.altera.com
Altera Corporation

Target Application: Interface Family: FLEX Vendor: Features

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