Using APEX APEX 20KE PLLs Quartus Software APEXdevices support Cl

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Using APEX APEX 20KE PLLs Quartus Software APEXdevices support Cl

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Using APEX APEX 20KE PLLs Quartus Software
APEXdevices support ClockLockTM, ClockBoostTM, ClockShiftclock management features, which implemented with phase-locked loops (PLLs). ClockLock circuitry uses synchronizing that reduces clock delay skew within device. This reduction minimizes clock-to-output setup times while maintaining zero hold times. ClockBoost circuitry, which provides clock multiplier, allows designers scale, multiply, input clock integers fractional ratios. ClockShift circuitry provides programmable clock delay phase shift applications clock delay control meeting strict timing requirements. ClockLock, ClockBoost, ClockShift features work conjunction with APEX device's high-speed clock provide significant improvements system performance bandwidth. altclklock megafunction within Quartussoftware enable ClockLock, ClockBoost, ClockShift features APEX devices (see Figure This document describes implement these clock management features using altclklock megafunction Quartus software.
Figure altclklock Megafunction
APEX Devices
APEX devices have that features ClockLock ClockBoost circuitry. This instantiated using altclklock megafunction. APEX devices support ClockBoost multiplication circuitry, offering clock multiplication. Figure shows ClockLock ClockBoost circuitry block diagrams within altclklock megafunction ports.
M-WP-APQUARTUS-01
January 2000, ver.
Using APEX APEX 20KE PLLs Quartus Software
Altera Corporation
Figure altclklock Port-to-PLL Relationship APEX Devices
single output clock combination output clocks. altclklock clock outputs 50/50 duty cycle. Table describes clock multiplication combinations that altclklock megafunction supports APEX devices.
Table Multiplication Factor Combinations
Clock0
Clock1
InputFrequency(MHz)
dedicated clock (CLK2) supplies clock altclklock megafunction. usage guidelines altclklock megafunction when used APEX devices are:
inclock port only directly dedicated clock input without inversion. altclklock only used clock positive negative edge-triggered registers LEs, IOEs, ESBs. CLK2 that directly feeds inclock port also drive other registers without PLL. However, doing makes CLK1 clock1 port unavailable. When clock outputs generated, other clock (CLK1) cannot used.
Connect board clock trace CLK2 only designs that require outputs from altclklock megafunction. Figure illustrates valid clock connections global clock lines.
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Using APEX APEX 20KE PLLs Quartus Software
Figure APEX Dedicated Global Clock Connections Dedicated Clock Lines
APEX 20KE Devices
APEX 20KE devices incorporate multiple ClockLock circuits with advanced features. These features include ClockLock, advanced ClockBoost, low-voltage differential signaling (LVDS) support, ClockShift circuitry, external clock outputs with optional external feedback inputs. Each APEX 20KE includes circuitry that provides clock synthesis using m/(n m/(n scaling. These scaling factors chosen Quartus software according multiplication division scaling parameter values altclklock instantiation. Figure shows ClockLock ClockBoost circuitry APEX 20KE devices.
Figure ClockLock ClockBoost Circuitry APEX 20KE Devices
Each dedicated global clock pins EP20K300E, EP20K400E, EP20K600E, EP20K1000E, EP20K1500E devices (CLK1p, CLK2p, CLK3p, CLK4p) supplies clock PLL. Each altclklock instance represents
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single instantiation. altclklock clock outputs 50/50 duty cycle. other general APEX 20KE usage guidelines altclklock are:
only directly dedicated clock input without inversion. only used clock positive negative edge-triggered registers logic elements (LEs), input/output elements (IOEs), embedded system blocks (ESBs). allowable frequency input range MHz. allowable frequency output range clock0 MHz. allowable frequency output range clock1 MHz. Phase shifting only possible multiplied clock input output frequency have integer multiple relationship, i.e. fin/fout fout/fin must integer. Phase shifting, using degree time units, will delay, lag, output clock with respect input clock (see Figure ratio clock_boost clock_divide cannot greater than 160. There also special scaling ratio 256/193 193/256 that respectively allowed T1/E1 E1/T1 clock rate conversion.
Figure Phase Delay Shifting Using APEX 20KE PLLs
There several conditional equalities between input frequency, phase shift values. altclklock MegaWizardautomatically sets dividers satisfy these equalities accommodate clock multiplication division phase shift entered. MegaWizard should used verify validity settings; MegaWizard reports multiplication/division frequency ratio possible. Each driven dedicated clock also bypassed simultaneously. CLK3p CLK4p pins feed PLLs each, altclklock instances. This useful applications that need phase shifted nonphase shifted versions clock. Because eight outputs shared among four possible dedicated global clock lines, certain combinations multiple altclklock instances their output connections possible. Quartus software associates numbers based assignments made dedicated global clock that feed altclklock megafunction. Figure illustrates valid clock connections dedicated global clock lines these devices. This figure should used determine whether design clocking scheme valid terms APEX 20KE clock connections. example, CLK4p feed PLL4 PLL2 simultaneously, only single output from each used since four possible outputs feed global clock lines.
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Using APEX APEX 20KE PLLs Quartus Software
Figure Dedicated Global Clock Connections Dedicated Clock Lines EP20K300E, EP20K400E, EP20K600E, EP20K1000E EP20K1500E Devices
Notes: These connections used only LVDS mode apply ALTLVDS megafunction. LVDSTXINCLK, LBDSRXINCLK, LVDSTXOUTCLK designated dual purpose pins that used LVDS clocks PLLs LVDS mode. PLL3 PLL4 configured general purpose LVDS use. This high-speed CMOS/LVDS interface clock that feeds LVDS transmitter block. This high-speed LVDS/CMOS interface that feeds LVDS receiver block.
EP20K60E, EP20K100E, EP20K160E, EP20K200E devices, CLK4p CLK2p dedicated clock pins supply clock possible PLLs. These PLLs have same usage guidelines EP20K400E larger devices' PLLs, with exception some connections. four possible output clocks that shared among four dedicated clock lines. outputs, CLK3p CLK1p pins cannot used. Figure illustrates valid clock connections global clock lines these devices. Figure determine whether design clocking scheme valid terms clock connections. altclklock megafunction port connections should follow usage guidelines illustrated Figures
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Figure Dedicated Global Clock Connections Dedicated Clock Lines EP20K60E, EP20K100E, EP20K160E EP20K200E Devices
altclklock Megafunction
ClockShift ClockBoost features, well other feature settings, controlled altclklock parameters. This section describes ports parameters altclklock megafunction shows function prototype component declarations. following sample script shows AHDL Function Prototype (port name order also apply Verilog HDL). FUNCTION altclklock (inclock, inclocken, fbin) WITH (INCLOCK_PERIOD, INCLOCK_SETTINGS, VALID_LOCK_CYCLES, INVALID_LOCK_CYCLES, VALID_LOCK_MULTIPLIER, INVALID_LOCK_MULTIPLIER, OPERATION_MODE, CLOCK0_BOOST, CLOCK0_DIVIDE, CLOCK0_SETTINGS, CLOCK1_BOOST, CLOCK1_DIVIDE, CLOCK1_SETTINGS, OUTCLOCK_PHASE_SHIFT) RETURNS (clock0, clock1, locked); VHDL Component Declaration: COMPONENT altclklock GENERIC (INCLOCK_PERIOD: NATURAL; INCLOCK_SETTINGS: STRING "UNUSED"; VALID_LOCK_CYCLES: NATURAL
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Using APEX APEX 20KE PLLs Quartus Software
INVALID_LOCK_CYCLES: NATURAL VALID_LOCK_MULTIPLIER: NATURAL INVALID_LOCK_MULTIPLIER: NATURAL OPERATION_MODE: STRING "NORMAL"; CLOCK0_BOOST: NATURAL CLOCK0_DIVIDE: NATURAL CLOCK1_BOOST: NATURAL CLOCK1_DIVIDE: NATURAL CLOCK0_SETTINGS: STRING "UNUSED"; CLOCK1_SETTINGS: STRING "UNUSED"; OUTCLOCK_PHASE_SHIFT: NATURAL PORT (inclock, inclocken: STD_LOGIC; fbin STD_LOGIC '0'; clock0, clock1, locked STD_LOGIC); COMPONENT; Tables through list altclklock input port, output port, parameter descriptions.
Table altclklock Input Port Descriptions
Port Name
inclock inclocken
Required
Description
Clock port that drives ClockLock enable signal
Comments
When inclocken port high, drives clock0 clock1 ports. When inclocken port low, clock0 clock1 ports driven goes lock. When inclocken port goes high again, must relock. This port must unconnected APEX devices. complete feedback loop, there must board-level connection between fbin external clock output PLL. Phase shifting either clock output possible when external feedback used. Division still possible both clock outputs, multiplication only possible clock output, clock0/clock1, which must unconnected APEX devices.
fbin
External feedback input
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Table altclklock Output Port Descriptions
Port Name
clock0
Required
Description
First output clock
Comments
APEX devices, driving inclock port used somewhere else design, only clock0 output port. deterministic no-fit occurs simultaneously clock0 port, clock1 port, driving inclock port PLL. APEX 20KE devices, clock0 port, clock1 port, driving inclock port order improve fitting PLL. However, generate only clock signal, clock1 port give Compiler added flexibility when fitting PLL. APEX devices, driving inclock port used elsewhere design only clock0 output port PLL. deterministic no-fit occurs simultaneously clock0 port, clock1 port, driving inclock port PLL. APEX 20KE devices, clock0 port, clock1 port, driving inclock port order improve fitting PLL. However, generate only clock signal, clock1 port give Compiler added flexibility when fitting PLL. When locked, this signal VCC; when lock, this signal GND. locked port pulse high while process achieving lock.
clock1
Second output clock
locked
Status
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Using APEX APEX 20KE PLLs Quartus Software
Table altclklock Parameter Descriptions (Part
Port Name
INCLOCK_PERIOD
Type
Integer
Required
Description
Specifies period inclock port frequency MHz. must specified since default. This parameter required clock setting specified inclock port. Specifies clock setting assignment used with inclock port. INCLOCK_SETTINGS parameter specified, INCLOCK_PERIOD parameter required ignored. INCLOCK_SETTINGS parameter omitted, default unused. Specifies number half-clock cycles that clock0 clock1 ports must locked before locked goes high. This parameter only used third-party functional simulation. output file from MegaWizard Plug-In Manager calculate value this parameter. enter value VALID_LOCK_CYCLES, default This parameter available only APEX 20KE devices. Specifies number half clock cycles that clock0 clock1 ports must lock before locked goes low. This parameter used only third-party functional simulation. output file from MegaWizard Plug-In Manager calculate value this parameter. enter value INVALID_LOCK_CYCLES, default This parameter available only APEX 20KE devices. Specifies multiplier used along with internal configuration information generate VALID_LOCK_CYCLES parameter. actual VALID_LOCK_CYCLES value displayed Compiler informational messages MegaWizard output file. This parameter required locked port connected, values range from enter value VALID_LOCK_MULTIPLIER, default This parameter available only APEX 20KE devices. Specifies multiplier used along with internal configuration information generate INVALID_LOCK_CYCLES parameter. actual INVALID_LOCK_CYCLES value displayed Compiler informational messages MegaWizard output file. This parameter required locked port connected, values range from enter value INVALID_LOCK_MULTIPLIER, default This parameter available only APEX 20KE devices. normal mode, only feeds internal clock network, phase alignment occurs between network dedicated inclock pin. only feeds external CLKLK_OUT pin, phase alignment occurs between external CLKLK_OUT dedicated inclock pin. feeds both internal clock network external clock CLKLK_OUT pin, compensates output pin, phase alignment occurs between external CLKLK_OUT dedicated inclock pin. result, phase error introduced internal clock network. NO_COMPENSATION mode, does compensate external CLKLK_OUT clock pin. Therefore, there always phase error external CLKLK_OUT pin, regardless whether drives internal clock network. Values OPERATION_MODE parameter NORMAL NO_COMPENSATION. enter value, default NORMAL. This parameter available only APEX 20KE devices. Also, LVDS allowable operation mode cannot specified this megafunction-it with altlvds megafunction. Specifies integer-multiplication factor clock0 port with respect input clock frequency. only specify this parameter, which must greater than clock0 port used. However, required clock setting specified clock0 port. value this parameter must APEX devices; APEX 20KE devices, MegaWizard Plug-In Manager calculate value. specify value, default
INCLOCK_SETTINGS
String
VALID_LOCK_CYCLES
Integer
INVALID_LOCK_CYCLES
Integer
VALID_LOCK_MULTIPLIER
Integer
INVALID_LOCK_MULTIPLIE
Integer
OPERATION_MODE
String
CLOCK0_BOOST
Integer
Using APEX APEX 20KE PLLs Quartus Software
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Table altclklock Parameter Descriptions (Part
Port Name
CLOCK0DIVIDE
Type
Integer
Required
Description
Specifies integer division factor clock0 port with respect input clock frequency. specify this parameter, which must greater than only clock0 port used. However, required clock setting specified clock0 port. setting this parameter must APEX devices. MegaWizard Plug-In Manager calculate value this parameter APEX 20KE devices. specify value, default Specifies clock setting assignment used with clock0 port. this parameter specified, CLOCK0_BOOST, CLOCK0_DIVIDE, OUTCLOCK_PHASE_SHIFT parameters required ignored. both CLOCK0_SETTINGS CLOCK1_SETTINGS specified, they must have same phase shift. this parameter specified, default UNUSED. Specifies integer multiplication factor clock1 port with respect input clock frequency. only specify this parameter, which must greater than clock1 port used. However, required clock setting specified clock1 port. setting this parameter must APEX devices. MegaWizard Plug-In Manager calculate value this parameter APEX 20KE devices. this parameter specified, default Specifies integer division factor clock1 port with respect input clock frequency. only specify this parameter, which must greater than clock1 port used. However, required clock setting specified clock1 port. this parameter specified, default Specifies clock setting assignment used with clock1 port. this parameter specified, CLOCK1_BOOST, CLOCK1_DIVIDE, OUTCLOCK_PHASE_SHIFT parameters ignored. both CLOCK0_SETTINGS CLOCK1_SETTINGS specified, they must have same phase shift. this parameter specified, default UNUSED. Specifies phase shift output clocks relative input clock, expressed time unit. Phase shifts 0.0, 0.25, 0.5, 0.75 times input period degrees) implemented precisely. allowable range phase shift between input clock period. phase shift outside this range, Compiler adjusts fall within this range. other phase shifts, Compiler chooses closest allowed value. fbin port used, programmable phase shift available. This parameter required clock settings used clock0 clock1 ports. this parameter specified, default This parameter only available APEX 20KE devices.
CLOCK0_SETTINGS
String
CLOCK1_BOOST
Integer
CLOCK1_DIVIDE
Integer
CLOCK1_SETTINGS
String
OUTCLOCK_PHASE_SHIFT
Integer
MegaWizard Interface
MegaWizard Plug-In Manager automatically sets appropriate parameters. options page MegaWizard window only apply APEX 20KE PLLs, shown Figure Table lists options available page altclklock MegaWizard Plug-In Manager.
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Figure Page altclklock MegaWizard Plug-In Manager
Table altclklock MegaWizard Plug-In Options
Option
external feedback
Description
external feedback used, programmable phase shift allowed. phase shift entered causes output clock input clock. enter external feedback degrees, using pull-down list. smallest resolution that implemented between depending voltage-controlled oscillator (VCO) frequency, which controlled user. external feedback used, programmable phase shift clock outputs disabled. Also, multiplication disabled clock output that chosen external feedback. example, clock0 chosen external feedback output, then clock0 output cannot multiplied, clock1 multiplied used internal clock. Clock division still possible both clock outputs when external feedback used.
external feedback from following output clock
Place higher priority matching This sets Operation Mode parameter normal. Operation Mode description phase shift Table external pins being Place higher priority matching This sets Operation Mode parameter no_compensation. internal network phase shift always aligned input; external output does have phase compensation, internal network regardless whether internal clock used. Operation Mode description Table
Page MegaWizard Plug-In Manager (see Figure input frequency, clock multiplication, clock division. Estimated Performance displays actual multiplication, division, phase shift. circuits that constructed, actual multiplication division factors differ from values enter, ratio multiplication/division given clock output will same. circuits that cannot constructed, closest achievable multiplication division factors displayed. closest possible phase shift estimated performance ratios also given. inability achieve desired phase shift does prevent circuit construction; compiler achieves closest possible shift, shown under Actual phase shift Estimated Performance box.
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Figure Page altclklock MegaWizard Plug-In Manager
Page MegaWizard Plug-In Manager (see Figure provides options user control lock indication latency clock enable port. radio button choices Lock indication determined internal configuration parameters that effected user-desired multiplication, division frequency from previous wizard pages. These options automatically VALID_LOCK_CYCLES, INVALID_LOCK_CYCLE, VALID_LOCK_MULTIPLIER, INVALID_LOCK_MULTIPLIER parameters.
Figure Page altclklock MegaWizard Plug-In Manager
Figures examples instantiations configurations.
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Using APEX APEX 20KE PLLs Quartus Software
Figure APEX APEX 20KE altclklock Instantiation with Clocks Clock Inversion
Figure APEX 20KE altclklock Instantiation with Clock Multiplication, Phase Shift External Clock Output
Reporting
ClockLock section compilation report displays information regarding usage (i.e., altclklock megafunction usage) device. This section omitted design does include PLLs. more information ClockLock Section, Quartus Help. compilation information message displays whether requested clock_boost clock_divide factors and/or requested phase shift could achieved. This information useful MegaWizard Plug-In Manager verify configuration constructed. unachievable clock_boost clock_divide factors, compilation will fail with error message displaying closest achievable factors. unachievable phase shift, compilation displays closest-achievable implemented phase shift. Actual valid invalid lock cycle indication also displayed.
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Timing Analysis
Multi-clock timing analysis causes timing analyzer report results using slack. input clocks output clocks different clocks that require multi-clock analysis. This true even case because clock coming generated from (not clock pin), reduced-clock delay exists output clock. Another important fact that tuned frequency specify want. will function reliably when above below specified frequency (except 2.5% frequency tolerance). runs according your specified settings maximum clock frequency (fMAX). Because this multi-clock analysis, fMAX reported. fMAX calculation necessary, derive from reported slack. micro tCO, tSU, path delay given list path command Actual Maximum timing Slack Report window. These added inverted find fMAX that path. When using external feedback input, External Input Delay option used specify amount board delay from external clock output back external feedback input. This assignment made through Tools menu Assignment Organizer Timing.
Clock Domain Transfers
data transfer across clock domains, specific design considerations should made when using clocks with synchronous asynchronous transfers. next sections describe these considerations.
Synchronous Transfers
clocks domain transfer come from single PLL, then synchronous register-to-register transfers, (i.e. MHz), work across conditions, special design considerations need made. clocks come from different PLLs, (i.e., same clock with ClockShift), then must insert least logic element (LE) data path guarantee data transfer between registers that connected local interconnect. other register-to-register transfers (e.g., across MegaLABinterconnects) work without special design considerations. Figure shows LCELL insertion multiple clock source register-to-register transfer local interconnect.
Figure LCELL Insertion Multiple Clock Source Register-to-Register Transfer Local Interconnect
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Asynchronous Transfers
asynchronous register-to-register transfer, (i.e., MHz), appropriate asynchronous design techniques transfer data from clock domain other. example, DCFIFO first-in first-out (FIFO) function used buffer data transfer. Figure shows DCFIFO that used buffer data transfer.
Figure Using DCFIFO Interface Between Asynchronous Clock Domains
ClockShifted non-ClockShifted clocks used register-to-register transfer, fMAX reduced hold time violation occur, depending direction magnitude shift (any positive shift past degrees considered negative shift) whether destination source register's clock shifted.
Simulation
altclklock behavioral model used simulate both APEX20K APEX20KE generating clock signal based upon reference clock. APEX APEX 20KE behavioral models' instantiation should follow same guidelines restrictions design entry. altclklock behavioral timing models simulate jitter. simulate External Feedback Input pin, user provides waveform expected that pin. This waveform must have frequency that equal external output frequency (the input frequency divided clock0/1 division factor, whichever used external feedback) with delay that corresponds total delay from output External Feedback Input pin. This delay includes output External Clock Output delay (which obtained from Timing Analysis), well anticipated board delay. This delay should exceed input clock period, whichever less. When External Feedback Input being used, there compensation output delay. behavioral models altclklock reside \quartus\eda\sim_lib directory. APEX20KE_MF.VHD contains VHDL behavioral models used altclklock both APEX APEX20KE devices. APEX20KE_MF.v contains Verilog behavioral models used altclklock both APEX APEX 20KE devices. behavioral model does perform error checking, user must only specify valid values parameters altclklock. When targeting APEX devices, sure only APEX 20K-applicable parameters with appropriate values. order simulate model successfully, resolution VHDL simulator must larger resolution will result calculation rounding thus create incorrect multiplication division.
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Sample VHDL Instantiation altclklock Model Design
following shows sample VHDL instantiation altclklock model design. library ieee; ieee.std_logic_1164.all; entity pll_design port (inclock std_logic; inclocken std_logic; data_in1 std_logic_vector(7 downto clock0 std_logic; r_out: std_logic_vector(7 downto locked: std_logic); pll_design; architecture apex pll_design component my_dff port clock STD_LOGIC; data: STD_LOGIC_VECTOR(7 DOWNTO STD_LOGIC_VECTOR(7 DOWNTO 0)); component; component altclklock generic inclock_period natural; inclock_settings string "UNUSED"; valid_lock_cycles natural invalid_lock_cycles natural valid_lock_multiplier natural invalid_lock_multiplier natural operation_mode string "NORMAL"; clock0_boost natural clock0_divide natural clock1_boost natural clock1_divide natural clock0_settings string "UNUSED"; clock1_settings string "UNUSED"; outclock_phase_shift natural port (inclock std_logic; inclocken std_logic; fbin std_logic '0'; clock0 std_logic; clock1: std_logic; locked: std_logic); component; signal clock1_sig: begin std_logic;
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Using APEX APEX 20KE PLLs Quartus Software
altclklock generic inclock_period 40000, clock1_boost clock1_divide clock0_boost clock0_divide operation_mode "NORMAL", valid_lock_cycles invalid_lock_cycles valid_lock_multiplier invalid_lock_multiplier outclock_phase_shift 10000 port (inclock inclock, inclocken inclocken, clock0 clock0, clock1 clock1_sig, locked locked); process(clock1_sig) begin clock1_sig'event clock1_sig then r_out data_in1; process; apex;
Sample Testbench VHDL Design
following shows sample testbench VHDL design. library ieee; ieee.std_logic_1164.all; entity plltest2 plltest2; architecture behave2 plltest2 signal signal signal signal signal signal inclock std_logic '0'; inclocken std_logic; data_in1 std_logic_vector(7 downto "10101010"; clock0 std_logic; locked std_logic; r_out std_logic_vector(7 downto
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component pll_design port inclock std_logic; inclocken std_logic; data_in1 std_logic_vector(7 downto clock0 std_logic; r_out std_logic_vector(7 downto locked std_logic) component; begin inclocken after pll_design port inclock inclock, inclocken inclocken, data_in1 data_in1, clock0 clock0, r_out r_out, locked locked); process(inclock) begin loop inclock inclock after loop; process; behave2; configuration pllconfig plltest2 behave2 pll_design entity work.pll_design(apex); for; for; pllconfig;
Example Verilog Instantiation altclklock Model Design
following shows example Verilog instantiation alkclklock model design. module pllsource (inclock, inclocken, data_in1, clock0, r_out, locked); input inclock, inclocken; input [7:0] data_in1; output clock0, locked; output [7:0] r_out; wire clock1_sig; [7:0] r_out; altclklock PLL_1 .inclock(inclock), .inclocken(inclocken), .clock0(clock0),
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.clock1(clock1_sig), .locked(locked)); defparam PLL_1.inclock_period 50000, PLL_1.inclock_settings "UNUSED", PLL_1.clock0_settings "UNUSED", PLL_1.clock1_settings "UNUSED", PLL_1.valid_lock_cycles PLL_1.invalid_lock_cycles PLL_1.valid_lock_multiplier PLL_1.invalid_lock_multiplier PLL_1.clock0_boost PLL_1.clock1_boost PLL_1.clock0_divide PLL_1.clock1_divide PLL_1.outclock_phase_shift PLL_1.operation_mode "NORMAL"; always @(posedge clock1_sig) begin r_out data_in1;
Sample Testbench Verilog Design
following shows sample testbench Verilog design. timescale ns/100ps module plltest; parameter 10101010; inclock, inclocken; [7:0] data_in1; wire clock0, locked; wire [7:0] r_out; pllsource .inclock(inclock), .inclocken(inclocken), .data_in1(data_in1), .clock0(clock0), .r_out(r_out), .locked(locked)); initial data_in1 tmp; initial inclock always inclock ~inclock; initial begin inclocken inclocken
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initial begin #100 data_in1 11110000; #200 data_in1 00110011; endmodule
Sample Waveform
Figure shows example waveform dual clock outputs APEX 20KE PLL. this example, clock0 clock clock1 clock; both shifted/lag degrees. simulation, |altclklock|<instance>|pll clock0 output PLL, |altclklock|<instance>|pll~CLK1 clock1 output PLL, locked output indication. timing simulation, output clocks have slight negative shift because they output flipflop clock ports. positive delay added they reach clock ports RAMs flip-flops.
Figure Timing Simulation Output Waveform Dual-Output Clocks with Shift
Summary
advanced feature APEX APEX 20KE PLLs, such ClockLock, ClockBoost ClockShift, controlled with altclklock megafunction Quartus software. ClockLock, ClockBoost, ClockShift features work conjunction with APEX devices' high-speed clocks provide significant improvements system performance bandwidth.
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Copyright 2000 Altera Corporation. Altera, APEX, ClockLock, ClockBoost, ClockShift, EP20K60E, EP20K100E, EP20K160E, EP20K200E, EP20K300E, EP20K400E, EP20K600E, EP20K1000E, EP20K1500E, MegaWizard, MegaLAB, Quartus, trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders

Using APEX APEX 20KE PLLs Quartus Software APEXdevices support Cl

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