November 1999, ver. 3.02 Features pci_a MegaCorefunction imp
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Master/Target MegaCore Function with
November 1999, ver. 3.02
Features
pci_a MegaCorefunction implementing 32-bit peripheral component interconnect (PCI) master/target interface Optimized FLEX® architecture Extensive hardware testing using: E2925A Exerciser Analyzer FLEX prototype board Validated against common chipsets such Intel chipsets, PCI-to-PCI bridges Dramatically shortens design cycles FLEX prototype board included Includes test vectors user simulation OpenCorefeature allows designers instantiate simulate designs MAX+PLUS® software prior licensing Uses approximately 1,000 FLEX logic elements (LEs), e.g., capacity EPF10K50 device master features: Memory read/write parking Fully integrated engine including address counter register, byte counter register, control status register, interrupt status register Configurable interrupt source, including terminal count, master abort, target abort, local side interrupt 64-byte double words DWORDs) buffer implemented FLEX embedded array blocks (EABs) Zero-wait-state read write burst transactions target features: Type zero configuration space Parity error detection Memory read/write configuration read/write Target retry disconnect Mbyte Gbytes parameterized target memory space Configuration registers: Parameterized: device vendor class code, revision base address zero, subsystem subsystem vendor Non-parameterized: command, status, header type, latency timer, interrupt pin, interrupt line
Altera Corporation
A-DS-PCI1-03.02
Master/Target MegaCore Function With
Introduction
This data sheet provides operating information pci_a MegaCore function includes following topics: Version 2.0. General Description Compliance Summary. Signals. Local Side Signals. Function Prototype Parameters. Functional Description Sustained Tri-State Signal Operation Master Device Signals Signal Assertion Target Device Signals Signal Assertion Parity Signal Operation. Master Commands Configuration Registers Vendor Register (Offset Hex) Device Register (Offset Hex) Command Register (Offset Hex) Status Register: (Offset Hex) Revision Register (Offset Hex) Class Code Register (Offset Hex) Latency Timer Register (Offset Hex) Header Type Register (Offset Hex) Base Address Register Zero (Offset Hex). Subsystem Vendor Register (Offset Hex) Subsystem Register (Offset Hex) Interrupt Line Register (Offset Hex) Interrupt Register (Offset Hex). Minimum Grant Register (Offset Hex) Maximum Latency Register (Offset Hex) Transactions Target Transactions. Configuration Transactions Master Transactions. Operation. Target Address Space Internal Target Registers Memory Map. Registers Initializing Transfers from Local Side Transactions General Programming Guidelines. Applications Protocol Checklists. Test Bench Summary References.
Altera Corporation
Master/Target MegaCore Function With
Version
pci_a function version includes following enhancements:
Additional device support Local-side initiated Parameterized base address registers (BARs) Byte-wide selection during external target write transfers l_holdn during external target transactions Larger byte counter register
More Device Support
pci_a function supports wide range devices packages including following FLEX devices:
EPF10K30RC240 EPF10K30RC208 EPF10K30AQC240 EPF10K30AQC208 EPF10K40RC240 EPF10K40RC208 EPF10K50RC240 EPF10K100ARC240 EPF10K30BC356 EPF10K50BC356 EPF10K100ABC356 Additional device support will become available devices released. Please check Altera world-wide site http://www.altera.com latest device support.
Local-Side Initiated
perform burst transfer using pci_a function, appropriate values must written registers setup transfer. prior versions pci_a function, host master device required write registers. However, pci_a version also allows read write transactions directly from local side device. "Initializing Transfers from Local Side" page more information.
Altera Corporation
Master/Target MegaCore Function With
Parameterized BARs
BAR0 parameterized provide optimum efficiency memory allocation.In pci_a version 1.3, BAR0 address space constant Mbyte contiguous address space divided into Kbytes memory space. However, pci_a version later, users vary BAR0 address space from Mbyte Gbytes contiguous memory. "Base Address Register Zero (Offset Hex)" page more information.
Byte-Wide Selection during Target Write Transfers
During target transfers, cben[3.0] signals byte enable signals, indicating which byte carries meaningful data. cben[3.0] applies byte applies byte Likewise pci_a version 2.0, additional local-side l_ben[3.0] signals buffer cben[3.0] signals inform local-side logic which byte carries meaningful data during external target write transactions.
l_holdn External Target Write Transactions
pci_a version local application required supply accept data within clock cycles. version 2.0, slower application assert l_holdn extend period necessary transfer data.
Larger Byte Counter Register
byte counter register increased from bits bits. result, master engine initiate memory transfers Kbytes each transaction.
General Description
pci_a MegaCore function provides timely solution integrating 32-bit peripheral devices, fully tested meet requirements specification. pci_a function optimized FLEX device family, reducing design task enabling designers focus efforts custom logic surrounding interface (ordering code: PLSM-PCI/A). Figure shows pci_a symbol.
Altera Corporation
Master/Target MegaCore Function With
Figure pci_a Symbol
BAR0_RW_BITS=12 CLASS _CODE=H"FF0000" DEVICE_ID=H"0001" DEVICE_VEND_ID=H"1172" REVISION_ID=H"02" SUBSYSTEM_ID=H"0000" SUBSYSTEM_VEND_ID=H"0000" TARGET_DEVICE="EPF10K30RC240" PCI_A Signals Local Signals
L_IRQN L_HOLDN RSTN L_REQ REQN L_CLK GNTN L_RESET IDSEL L_ADR[30-BAR0_RW_BITS.0] AD[31.0] L_DAT_OUT[31.0] CBEN[3.0] L_DAT_IN[31.0] L_BEN[3.0] FRAMEN_IN L_ACKN FRAMEN_OUT L_CSN IRDYN L_RDN DEVSELN L_WRN TRDYN_IN TRDYN_OUT L_DMA_ACR_WR STOPN_IN L_DMA_BCR_WR STOPN_OUT L_DMA_CSR_WR INTAN L_DMA_DAT_IN[31.0] PERRN L_DMA_CSR_OUT[6.0] SERRN L_DMA_ACR_OUT[31.0] L_DMA_BCR_OUT[16.0] L_DMA_ISR_OUT[4.0]
Compliance Summary
pci_a function compliant with requirements specified Special Interest Group's (SIG) Local Specification, Revision 2.1, Compliance Checklist, Revision 2.1. pci_a function successfully completed extensive hardware validation testing ensure robustness compliance. testing performed using following hardware software:
Altera FLEX prototype board BlueWater Systems WinDK (Windows NT-based) software driver E2925A Exerciser Analyzer
testing performed fully-loaded bus. addition E2925A Exerciser Analyzer Altera prototype board, agents such host bridge, Ethernet network adapter, video card tested function using data-intensive applications. extensive testing ensures that pci_a function operates flawlessly under most stringent conditions.
Altera Corporation
Master/Target MegaCore Function With
pci_a function performs master target transactions from Altera prototype board. Along with typical burst single-cycle transactions, pci_a function runs various interrupt cycles initiates different abnormal terminations. addition checking data integrity, E2925A Exerciser Analyzer used ensure that free protocol violation. Each iteration test program transfers over billion data bytes between host memory pci_a-based EPF10K30 device. test procedure done overnight, thus accounting hundreds iterations. tests were repeated across multiple platforms ensure compatibility with various chipsets. Table shows list hardware platforms with which pci_a function tested time this document printing.
Table pci_a Hardware Verified Platforms
Platform
Dell OptiPlex 5166 Dell OptiPlex Dell OptiPlex 5166 U-tron (Pentium/MMX) Intel Intel 440FX PCISet (Bus DEC21052-AB PCI-PCI bridge (Bus Intel PCISet Intel PCISet
Chipset
Speed (MHz)
Speed (MHz)
addition hardware testing, pci_a function verified using applicable scenarios listed Table detailed listing tests performed, "PCI Test Bench Summary" page
Table Tests Performed pci_a Function (Part
Test Scenario Number
1.10 1.11 device speed single data phase target abort cycles single data phase target retry cycles single data phase target disconnect cycles multi-data phase target abort cycles multi-data phase target retry cycles multi-data phase target disconnect cycles multi-data phase trdyn cycles data parity error single cycles data parity error multi-data phase cycles master time-out
Test Scenario Description
Simulation File Name Note
pcicc101 pcicc102 pcicc103 pcicc104 pcicc105 pcicc106 pcicc107 pcicc108 pcicc109 pcicc110 pcicc111 Altera Corporation
Master/Target MegaCore Function With
Table Tests Performed pci_a Function (Part
Test Scenario Number
1.13 1.14 2.10
Test Scenario Description
Simulation File Name, Note
pcicc113 pcicc114 pcicc205 pcicc206 pcicc208 pcicc209 pcicc210 dma_rd dma_wr trg_xrw
master parking master arbitration Target ignores reserved commands (including dual address) Target reception configuration cycles Target receives configuration cycles with address data parity errors Target receives memory cycles Target receives memory cycles with address data parity errors Programming registers burst read transfers. Programming registers burst write transfers. External target read/write transfers
Note Note Note
Note:
file extension depends type simulation file used, e.g., Simulator Channel File (.scf), Vector File (.vec), VHDL file. This test required Local Specification, Revision 2.1, therefore does have test number.
Signals
following signals used pci_a function:
Input-Standard input-only signal. Output-Standard output-only signal. Bidirectional-Tri-state input/output signal. Sustained tri-state-Signal that driven agent time (e.g., device host operating bus). agent that drives sustained tri-state must actively drive high clock cycle before tri-stating Another agent cannot drive sustained tristate signal sooner than clock cycle after released previous agent. Open-drain-Signal that wire-ORed with other agents. signaling agent asserts open-drain signal, weak pull-up resistor deasserts open-drain signal. pull-up resistor take three clock cycles restore open-drain signal inactive state.
Altera Corporation
Master/Target MegaCore Function With
Table summarizes signals interfacing pci_a function bus. "Local Side Signals" page information local side signals.
Table Signals Interfacing pci_a (Part
Name
rstn
Type
Input Input
Polarity
Description
Clock. input provides reference signal other interface signals, except rstn intan. Reset. rstn input initializes FLEX interface circuitry, asserted asynchronously edge. When active, output signals tri-stated open-drain signals, such serrn, float. Grant. gntn input indicates master device that control bus. Every master device pair arbitration lines (gntn reqn) that connect directly arbiter. Request. reqn output indicates arbiter that master wants gain control perform transaction. Address/data bus. ad[31.0] time-multiplexed address/data bus; each transaction consists address phase followed more data phases. Each data phase completes when irdyn trdyn both asserted. Command/byte enable. cben[3.0] timemultiplexed command/byte enable bus. During address phase this indicates command; during data phase this indicates byte enables. Parity. signal tri-stated output even parity. number ad[31.0], cben[3.0], even number. Frame. framen output from current master that indicates beginning duration operation. When framen initially asserted, address command signals present ad[31.0] cben[3.0] buses. framen signal remains asserted during data operation deasserted identify transaction. Initiator ready. irdyn signal output from master target indicates that master complete data transaction. write transaction, irdyn indicates that valid data ad[31.0] bus. read transaction, irdyn indicates that master ready accept data ad[31.0] bus. Device select. Target asserts devseln indicate that target decoded address.
gntn
Input
reqn ad[31.0]
Output Tri-State
cben[3.0] Tri-State Master: Output Target: Input Tri-State
framen Note
Sustained Tri-State Master: Output Target: Input
irdyn
Sustained Tri-State Master: Output Target: Input Sustained Tri-State Master: Input Target: Output
devseln
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Master/Target MegaCore Function With
Table Signals Interfacing pci_a (Part
Name
trdyn Note
Type
Sustained Tri-State Master: Input Target: Output Sustained Tri-State Master: Input Target: Output Input Sustained Tri-State Open-Drain Open-Drain
Polarity
Description
Target ready. trdyn signal indicates that target complete current data transaction. read operation, trdyn indicates that target providing data ad[31.0] bus. write operation, trdyn indicates that target ready accept data ad[31.0] bus. Stop. stopn signal target device request that indicates master stop current transaction.
stopn Note
idsel perrn serrn intan
High
Initialization device select. idsel input chip select configuration read write operations. Parity error. perrn signal indicates data parity error. System error. serrn signal indicates system address parity errors. Interrupt intan signal active-low interrupt host, must used single-function device requiring interrupt capability.
Note:
allow pci_a function pass set-up time requirement, framen, trdyn, stopn signals split into unidirectional (input, output) signals. example, signal trdyn connected input trdyn_in output trdyn_out. input trdyn_in connected dedicated input FLEX device, output trdyn_out connected FLEX device.
FLEX devices allow IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan testing (BST). IEEE Std. 1149.1 BST, designers should connect JTAG pins with FLEX device JTAG pins. Table
Table Optional IEEE Std. 1149.1 Signals
Name
Type
Input Input Input Output
Polarity
High High High High
Description
Test clock. input used clock test mode test data device. Test mode select. input used control state Test Access Port (TAP) control device. Test data. input used shift test data instruction into device. Test data. output used shift test data instruction device.
Altera Corporation
Master/Target MegaCore Function With
Local Side Signals
Table summarizes pci_a function signals that interface pci_a function local side peripheral device(s).
Table pci_a Signals Interfacing pci_a Function Local Side (Part
Name
l_irqn
Type
Input
Polarity
Description
Local side interrupt request. local side peripheral device asserts l_irqn signal interrupt. example, when local side peripheral device requires transfer, could l_irqn input request servicing from host. Local hold. During master transactions, l_holdn suspends current transfer. long l_holdn active, data transfers cannot occur between pci_a function local side peripheral device. During target transactions, assertion l_holdn extends external target transfers. l_holdn asserted, pci_a function expects data supplied received from local side second clock after l_csn asserted. Local request. After been loaded with valid data, local side peripheral device asserts l_req, which signals pci_a function start operation. Local data input. l_dat_in[31.0] input driven active local side peripheral device during pci_a-initiated write transactions (i.e., local side read transactions) target read transactions. Local data output. pci_a function drives l_dat_out[31.0] output during pci_a-initiated read transactions (i.e., local side write transactions) target write transactions. Local byte enable. l_ben[3.0] outputs driven pci_a function indicate byte select during target write transfers. Local target address. l_adr[30BAR0_RW_BITS.0] outputs represent address target transaction local side peripheral device. Local target chip select. When active, l_csn notifies peripheral device impending target transaction. l_ackn l_csn outputs never asserted same time.
l_holdn
Input
l_req
Input
High
l_dat_in[31.0]
Input
l_dat_out[31.0]
Output
l_ben[3.0]
Output
l_adr[30-BAR0_RW_BITS.0] Output
l_csn
Output
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Master/Target MegaCore Function With
Table pci_a Signals Interfacing pci_a Function Local Side (Part
Name
l_rdn
Type
Output
Polarity
Description
Read. pci_a function asserts l_rdn signal read access local side peripheral device. pci_a function uses l_rdn reading from peripheral device target registers write transactions. target read operations, pci_a function asserts l_csn l_rdn signals. write operations, pci_a function asserts l_ackn l_rdn signals. Write. pci_a function asserts l_wrn signal write access local side peripheral device. pci_a function uses l_wrn output writing peripheral device target registers read transactions. write operation local side, pci_a asserts either l_csn l_wrn target accesses, l_ackn l_wrn read accesses. Local acknowledge. When low, l_ackn notifies local side peripheral device that been granted read write transaction. peripheral device then transfer data from through pci_a function. Local clock. l_clk buffered version clock used local side peripheral device synchronize control logic pci_a function. Local reset. pci_a function asserts l_reset output reset local side peripheral device. l_reset output active during master reset follows state l_rst (bit control status register). Local address counter register write. local side asserts l_dma_acr_wr signal write access address counter register. When l_dma_acr_wr high, data l_dma_in[31.0] written into dma_acr register. Local byte counter register write. local side asserts l_dma_bcr_wr signal write access byte counter register. When l_dma_bcr_wr high, data l_dma_dat_in[31.0] written into dma_bcr register.
l_wrn
Output
l_ackn
Output
l_clk
Output
l_reset
Output
High
l_dma_acr_wr
Input
High
l_dma_bcr_wr
Input
High
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Master/Target MegaCore Function With
Table pci_a Signals Interfacing pci_a Function Local Side (Part
Name
l_dma_csr_wr
Type
Input
Polarity
High
Description
Local control status register write. local side asserts l_dma_csr_wr signal write access control/status registers. When l_dma_csr_wr high, data l_dma_dat_in[31.0] written into dma_csr register. Local data While write signals (l_dma_acr_wr, l_dma_bcr_wr, l_dma_csr_wr) asserted, l_dma_dat_in[31.0] supplies data written corresponding register. Local control status registers out. Direct output control/status register. Local address counter registers out. Direct output address counter registers. Local byte counter registers out. Direct output byte counter register. Local interrupt status registers out. Direct output interrupt status register.
l_dma_dat_in[31.0]
Input
l_dma_csr_out[6.0] l_dma_acr_out[31.0] l_dma_bcr_out[16.0] l_dma_isr_out[4.0]
Output Output Output Output
Function Prototype
Altera Hardware Description Language (AHDL) Function Prototype pci_a function shown below: FUNCTION pci_a (clk, framen_in, gntn, idsel, l_dat_in[31.0], l_holdn, l_irqn, l_req, rstn, stopn_in, trdyn_in, l_dma_acr_wr, l_dma_bcr_wr, l-dma_csr_wr, l_dma_dat_in[31.0]) WITH (SUBSYSTEM_ID, SUBSYSTEM_VEND_ID, DEVICE_ID, DEVICE_VEND_ID, CLASS_CODE, REVISION_ID, BAR0_RW_BITS, TARGET_DEVICE) RETURNS (framen_out, l_ackn, l_adr[30-BAR0_RW_BITS.0], l_clk, l_csn, l_dat_out[31.0], rdn, l_reset, l_wrn, stopn_out, trdyn_out, ad[31.0], cben[3.0], devseln, intan, irdyn, par, perrn, reqn, serrn; l_dma_csr_out[6.0], l_dma_acr_out[31.0], l_dma_bcr[16.0], l_dma_isr_out[4.0], l_ben[3.0]);
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Master/Target MegaCore Function With
Parameters
pci_a parameters-except BAR0_RW_BITS TARGET_DEVICE-set read-only configuration registers pci_a function; these registers called device identification registers. "Configuration Registers" page more information device registers. BAR0_RW_BITS parameter controls number read/write bits instantiated BAR0, according specification, number read/write bits instantiated BAR0 controls memory address range reserved BAR0. value BAR0_RW_BITS parameter must between TARGET_DEVICE parameter ensures that most optimized design used particular device package, which ensures timing compliance target device. most updated list support devices packages, refer readme.htm file included with pci_a function. Table describes parameters pci_a function.
Table Parameters
Name
BAR0_RW_BITS TARGET_DEVICE CLASS_CODE DEVICE_ID DEVICE_VEND_ID REVISION_ID SUBSYSTEM_ID SUBSYSTEM_VEND_ID
Format
Decimal String 24-bit 16-bit 16-bit 8-bit 16-bit 16-bit
Default Value
"EPF10K30RC240" H"FF0000" H"0001" H"1172" H"02" H"0000" H"0000"
Description
address space size Device selection Class code register Device register Device vendor register Revision register Subsystem register Subsystem vendor register
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Master/Target MegaCore Function With
Functional Description
pci_a function consists three main components:
defined 64-byte configuration register space master control logic target interface control logic, including target decode register read/write signals Embedded control engine, which operates with four registers includes 64-byte DWORD) buffer, local side interface control logic, including read/write control arbitration master/target accesses
Figure shows pci_a function's block diagram.
Figure pci_a Function Block Diagram
pci_a
rstn l_adr[18.0] idsel Configuration Registers Local Side Target Access Control l_csn l_rdn l_wrn ad[31.0] cben[3.0] Address/ Data Buffering Local Side Access Control
reqn gntn intan framen irdyn devseln trdyn stopn Master Interface
l_ackn l_clk l_reset l_holdn l_req l_irqn l_dat_in[31.0] l_dat_out[31.0] l_ben[3.0] l_dma_acr_wr l_dma_bcr_wr l_dma_csr_wr l_dma_dat_in[31.0] l_dma_csr_out[6.0] l_dma_acr_out[31.0] l_dma_bcr_out[16.0] l_dma_isr_out[4.0]
Local Data Buffering
Target Interface
Registers
perrn serrn
Parity Checking Generation
64-Byte Buffer (EAB)
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Master/Target MegaCore Function With
Sustained Tri-State Signal Operation
specification defines signals that constantly sampled different agents driven agent time sustained tri-state signals. example, framen constantly sampled different targets detect start transaction), driven master time. sustained tri-state signals, specification requires clock cycle drive signals inactive before being tri-stated. specification also requires that sustained tri-state signal being released, such master device releasing ad[31.0] after asserting address read operation, given full clock cycle tri-state before another device drive specification defines turn-around cycle clock cycle where sustained tri-state signal being tri-stated that another agent drive Turn-around cycles prevent contention bus.
Master Device Signals Signal Assertion
Figure illustrates PCI-compliant master device signals interfacing pci_a with bus. signals grouped functionality, signal directions illustrated from perspective pci_a function operating master bus. pci_a master sequence begins with assertion reqn request mastership bus. After receiving gntn from arbiter (usually host bridge) after idle state detected, pci_a function initiates address phase asserting framen driving both address ad[31.0] command cben[3.0]for clock cycle. When pci_a master ready present data bus, asserts irdyn. this point, pci_a function's master logic monitors control signals driven target device. target device determined decoding address command signals presented during address phase transaction.) target device drives control signals devseln, trdyn, stopn indicate following:
data transaction been decoded accepted. target device ready data operation. (When both trdyn irdyn active, data DWORD clocked from sending receiving device.) master device should stop current transaction.
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Master/Target MegaCore Function With
Figure pci_a Master Device Signals
System Signals
rstn idsel framen
Interface Control Signals
irdyn trdyn stopn devseln pci_a PCI-Compliant Master Device
perrn serrn
Error Reporting Signals Interrupt Request Signal
intan
Arbitration Signals
gntn reqn
Address, Data Command Signals
ad[31.0] cben[3.0]
Target Device Signals Signal Assertion
Figure illustrates PCI-compliant target device signals interfacing pci_a function with bus. signals grouped functionality, signal directions illustrated from perspective pci_a function operating target bus. pci_a target sequence begins when master device asserts framen drives address target command bus. When target device decodes address bus, asserts devseln indicate master that accepted transaction. master will then assert irdyn indicate target device that:
read operation, master device complete data transaction. write operation, valid data ad[31.0] bus.
When pci_a functions selected target device, will drive control signals devseln, trdyn, stopn discussed "Master Device Signals Signal Assertion" page
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Master/Target MegaCore Function With
target device, pci_a function only supports single-cycle accesses; therefore, pci_a function simultaneously drives stopn trdyn active. When qualified active irdyn signal, data word clocked from sending receiving device.
Figure pci_a Target Device Signals
System Signals
rstn
idsel
Interface Control Signals
framen irdyn trdyn stopn devseln pci_a PCI-Compliant Target Device
perrn serrn
Error Reporting Signals Interrupt Request Signal
intan
Address, Data Command Signals
ad[31.0] cben[3.0]
Parity Signal Operation
cycles include parity. Every device that transmits ad[31.0] must also drive signal, including master devices outputting address. Because parity even, number logic ad[31.0], cben[3.0], must even. Parity checking required, enabled through agent's command register. Address parity errors presented serrn output, data parity errors presented perrn output. lags ad[31.0]bus clock cycle, parity error signals clock cycle; thus, parity error signals
address data clock cycles.
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Master/Target MegaCore Function With
Commands
Table summarizes commands that supported pci_a function.
Table Command Support Summary
cben[3.0] Value
0110 0111 1010 1011
Command Cycle
Memory read Memory write Configuration read Configuration write
Target Support Master Support
pci_a function supports memory read/write configuration read/write commands. When operating master device, pci_a function executes standard memory read write operations. When operating target, pci_a function responds standard memory read write transactions. pci_a function also responds configuration read write operations.
Configuration Registers
Each logical device includes block configuration DWORDs reserved implementation configuration registers. format first DWORDs defined SIG's Compliance Checklist, Revision 2.1, which defines header formats, type type zero. Header type used PCI-to-PCI bridges; header type zero used other devices, including pci_a function. Table displays defined 64-byte configuration space. registers within this range used identify device, control functions, provide status. shaded areas indicate registers that supported pci_a function.
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Master/Target MegaCore Function With
Table Configuration Registers
Address
Maximum Latency Subsystem Reserved Reserved Minimum Grant Interrupt Interrupt Line BIST Device Status Register Class Code Header Type Latency Timer Base Address Register Base Address Register Base Address Register Base Address Register Base Address Register Base Address Register Card Pointer Subsystem Vendor Expansion Base Address Register
Byte
Vendor Command Register Revision Cache Line Size
Table summarizes pci_a-supported configuration registers address map. Read/write refers status time, i.e., from perspective other agents. Designers some read-only registers design time setting parameters when pci_a function instantiated MAX+PLUS software. example, device register value modified from default value changing DEVICE_ID parameter MAX+PLUS software. specified default state defined state register when reset.
Table pci_a-Supported Configuration Registers Address (Part
Address Offset (Hexadecimal)
Altera Corporation
Range Reserved (Hexadecimal)
00-01 02-03 04-05 06-07 08-08
Bytes Used/ Reserved
Read/Write
Mnemonic
Register Name
Read Read Read/Write Read/Write Read
ven_id dev_id comd status rev_id
Vendor Device Command Status Revision
Master/Target MegaCore Function With
Table pci_a-Supported Configuration Registers Address (Part
Address Offset (Hexadecimal)
Range Reserved (Hexadecimal)
09-0B 0D-0D 0E-0E 10-13 2C-2D 2E-2F 3C-3C 3D-3D 3E-3E 3F-3F
Bytes Used/ Reserved
Read/Write
Mnemonic
Register Name
Read Read/Write Read Read/Write Read Read Read/Write Read Read Read
class lat_tmr header bar0 sub_ven_id sub_id int_ln int_pin min_gnt max_lat
Class code Latency timer Header type Base address register zero Subsystem vendor Subsystem Interrupt line Interrupt Minimum grant Maximum latency
Vendor Register (Offset Hex)
Vendor 16-bit read-only register that identifies manufacturer device (e.g., Altera pci_a function). value this register assigned SIG; default value this register Altera vendor value, which 1172 hex. However, setting DEVICE_VEND parameter (see Table designers change value vendor register their SIG-assigned vendor value. Table
Table Vendor Register Format
Data
15.0
Mnemonic
ven_id
Read/Write
Read
Definition
vendor
Device Register (Offset Hex)
Device 16-bit read-only register that identifies type device. value this register assigned manufacturer (e.g., Altera assigned value device register pci_a function). default value device register 0001 hex; however, designers change value device register setting parameter DEVICE_ID (see Table page 13).
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Master/Target MegaCore Function With
Command Register (Offset Hex)
Command 16-bit read write register that provides basic control over ability pci_a function respond and/or perform accesses. Table
Table Command Register Format
Data
Mnemonic
Unused mem_ena
Read/Write
Read/Write
Definition
Memory access enable. When high, mem_ena enables pci_a function respond memory accesses target. Because registers memory target accesses, mem_ena must part initialization operation pci_a function perform transfers. Master enable. When high, mstr_ena enables pci_a function acquire mastership bus. pci_a function perform transfers, mstr_ena must part initialization operation. Parity error enable. When high, perr_ena enables pci_a function report parity errors perrn output. System error enable. When high, serr_ena enables pci_a function report address parity errors serrn output. However, signal system error, perr_ena must also high.
mstr_ena
Read/Write
Unused perr_ena
Read/Write
Unused serr_ena
15.9
Unused
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Master/Target MegaCore Function With
Status Register: (Offset Hex)
Status 16-bit register that provides status bus-related events. Read transactions status register behave normally. However, write transactions different from typical write transactions that bits status register cleared set. status register cleared writing logic that bit. example, writing value 4000 status register clears number leaves rest bits unchanged. default value status register 0400 hex. Table
Table Status Register Format
Data
Mnemonic
Unused dat_par_rep
Read/Write
Read/Write
Definition
Data parity reported. When high, dat_par_rep indicates that during read transaction pci_a function asserted perrn output master device, that during write transaction perrn asserted target device. This high only when perr_ena (bit command register) also high. Device select timing. devsel_tim bits indicate target access timing pci_a function devseln output. pci_a function designed slow target device. Target abort. When high, tar_abrt indicates that current target device transaction been terminated. Master abort. When high, mstr_abrt indicates that current master device transaction been terminated. Signaled system error. When high, serr_set indicates that pci_a function drove serrn output active, i.e., address phase parity error occurred. Detected parity error. When high, det_par_err indicates that pci_a detected either address data parity error. Even parity error reporting disabled (via perr_ena), pci_a function will det_par_err bit.
10.9
devsel_tim
Read
Unused tar_abrt mstr_abrt
Read/Write Read/Write
serr_set
Read/Write
det_par_err
Read/Write
Altera Corporation
Master/Target MegaCore Function With
Revision Register (Offset Hex)
Revision 8-bit read-only register that identifies revision number device. value this register assigned manufacturer (e.g., Altera pci_a function). Therefore, default value revision register revision number pci_a function. Table However, designers change value revision register setting REVISION_ID parameter (see Table
Table Revision Register Format
Data
Mnemonic
rev_id
Read/Write
Read
Definition
revision
Class Code Register (Offset Hex)
Class code 24-bit read-only register divided into three sub-registers: base class, sub-class, programming interface. Refer Local Specification, Revision detailed information. Table default value class code register FF0000 hex; however, designers change value setting CLASS_CODE parameter (see Table
Table Class Code Register Format
Data
23.0
Mnemonic
class
Read/Write
Read
Definition
Class code
Latency Timer Register (Offset Hex)
latency timer register 8-bit register with bits tied GND. register defines maximum amount time, clock cycles, that pci_a function retain ownership bus. After initiating transaction, pci_a function decrements latency timer rising edge each clock. default value latency timer register hex. Table
Table Latency Timer Register Format
Data
Mnemonic
lat_tmr lat_tmr
Read/Write
Read Read/Write
Definition
Latency timer register Latency timer register
Altera Corporation
Master/Target MegaCore Function With
Header Type Register (Offset Hex)
Header type 8-bit read-only register that identifies pci_a function single-function device. default value header type register hex. Table
Table Header Type Register Format
Data
Mnemonic
header
Read/Write
Read
Definition
header type
Base Address Register Zero (Offset Hex)
Depending value BAR0_RW_BITS parameter, base address register zero (BAR0) consists registers ranging from bit. BAR0_RW_BITS when pci_a function instantiated, determines base memory address pci_a target space. This process done accordance with Local Specification, Revision 2.1., which states that number bits implemented read/write registers defines amount memory address space reserved BAR. Power-up software determine much address space device requires writing value then reading value back. specify required address space, pci_a function will return lower bits. amount required address space generally function value BAR0_RW_BITS parameter, i.e., assuming BAR0_RW_BITS reserved address space 2(32-n) bytes. example, when BAR0_RW_BITS reserved address space (32-4) bytes, Mbytes. Table
Table Base Address Register Format (Part
Data
Mnemonic Read/Write
mem_ind Read
Definition
Memory indicator. mem_ind indicates whether register memory address decoder. pci_a function, mem_ind tied GND, which indicates memory address decoder. Memory type. mem_type bits indicate type memory that implemented pci_a function memory address space. These bits tied GND, which indicates that memory block located anywhere 32-bit address space. Memory prefetchable. pre_fetch indicates whether block memory defined BAR0 prefetchable host bridge. pci_a function, address space prefetchable, i.e., reads low. Altera Corporation
mem_type
Read
pre_fetch Read
Master/Target MegaCore Function With
Table Base Address Register Format (Continued) (Part
Data
31-BAR0_RW_BITS
Mnemonic Read/Write
Unused Read/write
Definition
Base address register
31.(32-BAR0_RW_BITS) bar0
Subsystem Vendor Register (Offset Hex)
Subsystem vendor 16-bit read-only register that identifies add-in cards designed different vendors with same functional device card. value this register assigned SIG. Table default value subsystem vendor register 0000 hex; however, designers change value setting SUBSYSTEM_VEND_ID parameter (see Table
Table Subsystem Vendor Register Format
Data
15.0
Mnemonic
sub_vend_id
Read/Write
Read
Definition
subsystem/vendor
Subsystem Register (Offset Hex)
Subsystem register identifies subsystem; value this register defined subsystem vendor, i.e., designer. Table default value subsystem register 0000 hex; however, designers change value setting SUBSYSTEM_ID parameter (see Table
Table Subsystem Register Format
Data
15.0
Mnemonic
sub_id
Read/Write
Read
Definition
subsystem
Interrupt Line Register (Offset Hex)
interrupt line register consists 8-bit register that defines which system interrupt request line system interrupt controller) intan output routed. interrupt line register written system software power-up; default value hex. Table
Table Interrupt Line Register Format
Data
Altera Corporation
Mnemonic
int_ln
Read/Write
Read/write
Definition
Interrupt line register
Master/Target MegaCore Function With
Interrupt Register (Offset Hex)
interrupt register consists 8-bit read-only register that defines pci_a function's interrupt request line intan. default value interrupt register hex. Table
Table Interrupt Register Format
Data
Mnemonic
int_pin
Read/Write
Read
Definition
Interrupt register
Minimum Grant Register (Offset Hex)
Minimum grant register consists 8-bit read-only register that defines length time pci_a function would like retain mastership bus. value this register indicates required burst period length 250-ns increments. pci_a function requests timeslice microseconds. default state minimum grant register hex. Table
Table Minimum Grant Register Format
Data
Mnemonic
min_gnt
Read/Write
Read
Definition
Minimum grant register
Maximum Latency Register (Offset Hex)
maximum latency register 8-bit read-only register that defines frequency which pci_a function would like gain access bus. value maximum latency register hex, which indicates that pci_a function major requirements maximum latency. Table
Table Maximum Latency Register Format
Data
Mnemonic
max_lat
Read/Write
Read
Definition
Maximum latency register
Altera Corporation
Master/Target MegaCore Function With
Transactions
This section describes pci_a transactions. following items should considered when reading diagrams this section:
pci_a accesses quad-byte, 32-bit transfers; therefore, byte enables active duration master data transfers. During pci_a external target write accesses, transfers byte selectable. Although Figures through show signals tri-stated when driven pci_a function, they actually high pull-up resistors used keep sustained tri-state signals logic high while signals being driven agent.
pci_a function accesses three types transactions:
Target Configuration Master
Target Transactions
sequence events beginning target transfers exactly same. target read write transaction begins after master acquires mastership bus. master device then asserts framen drives address ad[31.0] command cben[3.0] bus. pci_a function latches address command signals first clock edge when framen asserted starts decoding address.
Target Read Transactions
pci_a function supports types target read transactions:
Internal target read-Target read transaction from internal registers External target read-Target read transaction from local side target memory space
sequence events both target read transactions identical; however, timing not. (See "External Target Read Transaction" page more information.) target read transaction from local side target memory space requires more time because pci_a function must wait local side supply with data.
Altera Corporation
Master/Target MegaCore Function With
Internal Target Read Transaction Immediately after address phase (clock four), master deasserts framen asserts irdyn, indicating both following:
transaction contains single data phase. master device ready read data that pci_a function presented ad[31.0] bus.
master device tri-states ad[31.0]bus clock five after pci_a function latches address. pci_a function drive ad[31.0] beginning clock six. master attempting burst access, will keep both framen irdyn signals asserted. However, because pci_a function does support target bursts, will assert stopn indicate disconnect master. master will subsequently transaction deasserting framen asserting irdyn clock cycle. Figure pci_a function asserts devseln clock seven, which indicates master device that pci_a claimed transaction. devseln then sampled master device rising-edge clock eight, which slow decode, defined specification. Figure shows timing pci_a internal target read transaction.
Figure Internal Target Read Transaction
reqn (Master) gntn (Arbiter) ad[31.0] (pci_a) cben[3.0] (Master) (pci_a) perrn (Master) framen (Master) irdyn (Master) devseln (pci_a) trdyn (pci_a) stopn (pci_a)
Address 0110 Add-Par Byte Enable
Par-D0 Perr
Altera Corporation
Master/Target MegaCore Function With
Figure pci_a asserts trdyn stopn clock eight indicate that valid data ad[31.0] disconnect desired. Data transferred during clock eight when irdyn trdyn active latched master device rising-edge clock nine. case attempted burst transfer, specification requires that target device that does support burst transfers must issue disconnect during first data phase. Because specification, pci_a function always asserts stopn trdyn same time. master drives active clock five address parity, pci_a function drives active clock nine data parity. target read transaction, master device drives perrn signal indicate data parity errors. clock nine, because data been sampled, pci_a function releases ad[31.0]bus master releases cben[3.0]. devseln, trdyn, stopn signals driven high clock nine released pci_a clock later. Thus, sustained tri-state signal requirement met, i.e., driving signal high clock cycle before releasing External Target Read Transaction sequence events external target read transaction identical internal target read transaction. However, because access local side takes precedence over other access local side, external target read transaction allowed complete only when idle. external target read transaction received pci_a function while idle, pci_a function signals retry. Because pci_a function must wait local side supply with data, target read transaction from local side target memory space (external target read) requires more time. local logic cannot supply data within clock after l_csn l_rdn asserted, l_holdn asserted halt data transfers. l_holdn signal driven until data presented l_dat_in[31.0] bus. specification requires that first data phase target transaction completes within clock cycles. local device must ensure that specification violated excessively long l_holdn assertion.
Altera Corporation
Master/Target MegaCore Function With
Figures shows timing pci_a external target read transaction.
Figure External Target Read Transaction
ad[31.0] cben[3.0] perrn framen irdyn devseln trdyn stopn
Address 0110 Add-Par Byte Enable Par-D0 Perr
l_adr[18.0]
l_dat_in[31.0] l_csn l_rdn
Valid Address
Figure illustrates external target read transfer where l_holdn used insert additional wait states local side. Unable supply data immediately when l_csn l_rdn asserted, local logic asserts l_holdn clock eight clock cycles. local side supplies data l_dat_in[31.0] clock deasserts l_holdn. pci_a function latches data internally rising edge clock deasserts l_rdn. l_csn deasserted clock later. pci_a drives data clock after latches from local side (clock 13). Because l_holdn registered, local side must follow timing requirements (provided MAX+PLUS Timing Analyzer) when drives l_holdn. avoid excessive latency, specification requires that target devices complete initial data transaction within clocks after framen asserted. (The local logic must ensure that this specification met.) Therefore, l_holdn cannot held active more than clock cycles.
Altera Corporation
Master/Target MegaCore Function With
Figure External Target Read Transaction with l_holdn Asserted
framen ad[31.0] cben[3.0] perrn irdyn devseln trdyn stopn
Address 0110
Add-Par
Byte Enable Par-D0
l_adr[18.0]
l_dat_in[31.0] l_holdn l_csn l_rdn
Valid Address
Target Write Transactions
pci_a function supports types target write transactions:
Internal target write: Target write internal registers External target write: Target write local side target memory space
sequence events both target write transactions identical; however, timing Internal Target Write Transaction Immediately after address phase, master deasserts framen asserts irdyn, indicating following:
transaction contains single data phase. master device ready write data ad[31.0]bus target device receive.
master device ready data phase begin, irdyn delayed framen deasserted until clock where irdyn goes active. master attempting burst access, will keep both framen irdyn signals asserted. However, because pci_a function does support target bursts, will assert stopn indicate disconnect master. master will subsequently transaction deasserting framen asserting irdyn clock cycle.
Altera Corporation
Master/Target MegaCore Function With
Figure shows typical waveform internal target write transaction. address phase occurs during clock four, data phase begins clock five. pci_a function claims transaction clock eight asserting devseln. rising edge clock nine, data transferred from master device pci_a function because both irdyn trdyn asserted. same time when pci_a function asserts trdyn, also asserts stopn indicate that unable receive more data. pci_a function always asserts stopn trdyn same time ensure that only data phase occurs during each target transaction. master device drives active clock five parity address bits, clock parity data bits. parity error occurs, pci_a function will drive perrn clock cycle later. clock nine, because data been sampled, pci_a function releases ad[31.0] cben[3.0] buses. clock later released master device. pci_a drives devseln, trdyn, stopn high clock nine releases them clock later.
Figure Internal Target Write Transaction
reqn (Master) gntn (Arbiter) ad[31.0] (Master) cben (Master) (Master) perrn (pci_a) framen (Master) irdyn (Master) devseln (pci_a) trdyn (pci_a) stopn (pci_a)
Data-Perr
Address 0111 Adr-Par Data0 Byte Enable Data-Par
External Target Write Transaction sequence events external target write transaction identical internal target write transaction. However, timing different.
Altera Corporation
Master/Target MegaCore Function With
allow external target write transaction complete faster, pci_a function provides single address single data holding register. When external target write access takes place, pci_a stores address data internal holding registers completes transfer bus. pci_a function will subsequently assert l_csn signal indicate local side that there pending target access; clock later (clock 10), l_wrn asserted data driven l_dat_out[31.0] byte enables driven l_ben[3.0] bus. Figure shows timing external target write transaction.
Figure External Target Write Transaction
ad[31.0] cben[3.0] perrn framen irdyn devseln trdyn stopn l_adr[18.0] l_dat_out[31.0] l_ben[3.0] l_csn l_wrn
Address 0111
Byte Enable
Add-Par
Par-D0 Perr-D0
Valid Address Byte Enable
Similar external target read transaction, local logic unable receive 32-bit data from l_dat_out[31.0] bus, l_hold applied delay data transfer. Figure page depicts external target write transaction where l_holdn asserted extend time required local side transfer data.
Altera Corporation
Master/Target MegaCore Function With
When pci_a drives l_csn low, l_wrn driven clock cycle later. Because local logic unable receive write data, drives l_holdn clock local side detect that local target data transfer write cycle because clock eight, when l_csn asserted, l_rdn asserted.
Because pci_a detects assertion l_holdn, continues drive data0 (D0) l_dat_out[31.0] well l_csn l_wrn until l_holdn deasserted. local application must assert l_holdn clock extend data cycle. local logic latches data clock l_wrn signal asserted until clock after l_holdn deasserted; l_csn then deasserted clock after l_wrn deasserted. pci_a function finishes data transfers before data presented local side. During external target write transaction, l_holdn held active many clock cycles without affecting performance. However, generally good practice deassert l_holdn soon possible. Otherwise, agent attempts access pci_a function again while function valid data, pci_a function issues retry.
Figure External Target Write Transaction with l_holdn Asserted
framen ad[31.0] cben[3.0] perrn irdyn devseln trdyn stopn l_adr[18.0] l_dat_out[31.0] l_ben[3.0] l_holdn l_csn l_wrn Altera Corporation
Valid Address Byte Enable 0111 Add-Par Byte Enable Par-D0 Perr-D0
Master/Target MegaCore Function With
Configuration Transactions
configuration transaction generated either host-to-PCI bridge PCI-to-PCI bridge access. address phase configuration transaction, bridge will drive idsel signal agent that wants access. agent decodes configuration command detects idsel high, agent will claim configuration access assert devseln.
Configuration Read Transaction
Figure shows timing pci_a configuration read transaction. protocol identical protocol discussed "Target Read Transactions" page except idsel signal, which active during address phase configuration transaction.
Figure Configuration Read Transaction
reqn (Host) gntn (Arbiter) framen (Host) idsel (Host) ad[31.0] (pci_a) cben (Host) irdyn (Host) trdyn (pci_a) stopn (pci_a) devseln (pci_a) (pci_a) perrn (Host)
Address 1010 Byte Enable Data0
Address Parity
Data Parity Data Parity Error
Configuration Write Transaction
Figure shows timing pci_a configuration write transaction. protocol identical protocol discussed "Target Write Transactions" page except idsel signal, which active during address phase configuration transactions.
Altera Corporation
Master/Target MegaCore Function With
Figure Configuration Write Transaction
reqn (Host) gntn (Arbiter) framen (Host) idsel (Host) ad[31.0] (Host) cben (Host) irdyn (Host) trdyn (pci_a) stopn (pci_a) devseln (pci_a) (Host) perrn (Host)
1011
Data0 Byte Enable
Address Parity
Data Parity
Data Parity Error
Master Transactions
Master transactions pci_a function controlled engine. pci_a master transaction begins after user loads appropriate values register (see "General Host Programming Guidelines" page more detailed information register loading). pci_a function waits local side assert l_req, which indicates pci_a function that begin operation. read (PCI local side) transaction, pci_a function immediately asserts reqn acquire mastership bus. After arbiter asserts gntn, pci_a function begins address phase asserting framen driving address ad[31.0] command cben[3.0] bus.
Altera Corporation
Master/Target MegaCore Function With
write (local side PCI) transaction, pci_a function first reads DWORDs from local side stores them internal buffer. this point, asserts reqn acquire mastership bus. After arbiter asserts gntn, pci_a function begins address phase.
Master Read Transactions
pci_a function supports types master read transactions:
Single-cycle master read Master burst read
Single-Cycle Master Read Transaction master read transaction, data being transferred from side local side. Assuming pci_a function acquired mastership bus, start master read transaction indicated when pci_a function asserts framen. After master read transaction initiated, target devices latch address command clock edge when framen active start address decode. pci_a function ready read data until clock five; therefore, framen deasserted irdyn asserted until clock five. selected target device asserts devseln clock three, devseln sampled pci_a function rising-edge clock four, which depicts fast decode target device. indicate that ready send data, target device simultaneously asserts trdyn drives data ad[31.0] beginning clock four. data phase begins clock five when irdyn trdyn active finishes rising edge clock with data latched pci_a function. pci_a function drives signal active clock three parity address command bits, selected target drives active clock parity data byte enable bits. pci_a function releases ad[31.0] clock three, cben[3.0]bus clock six, signal clock four. Figure shows timing pci_a function master read transaction. figure assumes pci_a function already acquired mastership bus.
Altera Corporation
Master/Target MegaCore Function With
Figure Single-Cycle Master Read Transaction
framen (pci_a) ad[31.0] (Target) cben (pci_a) irdyn (pci_a) devseln (Target) trdyn (Target) stopn (Target) (Target) perrn (pci_a)
Address 0110
Data0 0000
Address Parity
Data Parity Data Parity Error
Master Burst Read Transaction protocol address phase master burst read transaction identical "Single-Cycle Master Read Transaction" page After address phase, protocol changes reflect additional read transactions. After master burst read transaction initiated, selected target device asserts devseln clock three, pci_a function samples devseln rising edge clock five. This example displays fast decode target. target device then signals pci_a that ready send data driving trdyn ad[31.0] active clock four. pci_a function drives active clock three parity address command bits. clock target device drives active parity first data phase (Data0). target device also drives active clocks seven, eight, nine parity second, third fourth data phases. Figure shows 16-byte data transaction, with data phases occurring four consecutive clock cycles. data phase begins clock five ends clock eight when pci_a function releases framen, which indicates start final data phase.
Altera Corporation
Master/Target MegaCore Function With
Because data been read, target device simultaneously releases devseln, trdyn, ad[31.0]bus when pci_a function releases irdyn clock nine.
Figure Master Burst Read Transaction
framen (pci_a) ad[31.0] (Target) cben (pci_a) irdyn (pci_a) trdyn (Target) stopn (Target) devseln (Target) (Target) perrn (pci_a)
Address 0110
Data0
Data1 0000
Data2
Data3
Address Parity
Data Parity Data Parity Error
Master Write Transactions
pci_a function supports types master write transactions:
Single-cycle master write Master burst write
Single-Cycle Master Write Transaction master write transaction, data transferred from local side side. Assuming pci_a function acquired mastership bus, start master device write transaction indicated when pci_a function asserts framen. After master device write transaction initiated, target devices latch address command clock edge when framen active start address decode. Data from pci_a master device write transactions available until clock five; therefore, framen deasserted irdy asserted until clock five.
Altera Corporation
Master/Target MegaCore Function With
selected target device asserts devseln clock four sampled pci_a function clock five, which depicts medium decode target device. indicate that ready receive data, target device drives trdyn active clock five. Then, pci_a function drives data ad[31.0] beginning clock five simultaneously with assertion irdyn. data phase begins clock five when irdyn trdyn active, ends rising-edge clock with data latched selected target device. pci_a function drives active clock three parity address command bits clock parity data byte enable bits. Because data phase complete, pci_a function releases ad[31.0]bus cben[3.0] clock six. clock later, released pci_a function, devseln trdyn released target device. meet requirement driving sustained tri-state signal high clock cycle before releasing pci_a function drives irdyn high clock before releasing clock seven. Figure shows timing pci_a master write transaction. figure assumes pci_a function already acquired mastership bus.
Figure Single-Cycle Master Write Transaction
framen (pci_a) ad[31.0] (pci_a) cben (pci_a) irdyn (pci_a) trdyn (Target) stopn (Target) devseln (Target) (pci_a) perrn (Target)
Address 0111 0000
Data0
Address Parity
Data Parity Data Parity Error
Altera Corporation
Master/Target MegaCore Function With
Master Burst Write Transaction protocol master burst write transactions from address phase data phase identical "Single-Cycle Master Write Transaction" page From data phase two, protocol changes reflect additional write transactions. After master burst write transaction initiated, selected target device asserts devseln clock four, pci_a function samples devseln rising edge clock five. This example depicts medium decode target. target device signals master device that ready receive data driving trdyn active clock five. master burst write transaction example Figure shows data phases occurring clocks five, six, seven, nine when irdyn trdyn both active. ensure data synchronization pci_a function's internal data path pipeline, wait state master burst write transactions inserted pci_a function clock eight. target does insert wait state during burst write transaction, pci_a will insert only wait state entire burst transfer. However, target inserts additional wait states during burst write transaction, pci_a function will insert additional wait states. final data transfer occurs when pci_a function simultaneously asserts irdyn deasserts framen clock nine. pci_a function drives active clock three parity address bits clock parity data bits. Figure shows timing pci_a burst write transaction, which depicts 16-byte data transfer.
Altera Corporation
Master/Target MegaCore Function With
Figure Master Burst Write Transaction
framen (pci_a) ad[31.0] (Target) cben (pci_a) irdyn (pci_a) trdyn (Target) stopn (Target) devseln (Target) (Target) perrn (pci_a)
Address 0111
Data0
Data1 0000
Data2
Data3
Address Parity
Data Parity Data Parity Error
Operation
This section provides operating details engine, divided into following sub-sections:
Target address space Internal target registers memory registers transactions Initializing transfers from local side General host programming guidelines
Altera Corporation
Master/Target MegaCore Function With
Target Address Space
pci_a function memory-mapped target registers (internal external) read and/or written over BAR0 memory space. Accesses from BAR0 memory space occur 32-bit transfers. Table lists pci_a function's memory space address map. pci_a function BAR0 address space ranges from Mbyte Gbytes contiguous address divided into equal-sized regions (lower upper). Each region reserves half total address space reserved BAR0. lower region (internal target address space) contains pci_a control registers, upper region (external target address space) contains user-defined memory space.
Table Memory Space Address
Memory Space
BAR0
Block Size (DWORDs)
reserved space reserved space
Address Offset Note
00000h-7FFFFh
Words Used Read/ Write
bytes Read/write
Description
registers
BAR0
80000h-FFFFFh
Read/write
User-defined memory space, ranging size from Kbytes Gbytes
Note:
These values based BAR0_RW_BITS parameter
Internal Target Registers Memory
Internal pci_a target address space used registers, including control/status register, address counter register, byte counter register interrupt status register. Table lists pci_a function's registers memory map.
Table Internal Target Registers Memory
Range Reserved Note
00000h-00003h 00004h-00007h 00008h-0000Bh 0000Ch-0000Fh Note:
These values based BAR0_RW_BITS parameter
Bytes Used/Reserved
8/32 32/32 17/32 8/32
Read/Write
Mnemonic
Default State (Hexadecimal)
00000000 00000000 00000000 00000000
Register Name
Read/write Read/write Read/write Read
dma_csr dma_acr dma_bcr dma_isr
control/status address counter byte counter interrupt status
Altera Corporation
Master/Target MegaCore Function With
Registers
This section describes registers. specified default state defined state storage element when reset. pci_a function contains following registers:
Control status Address counter Byte counter Interrupt status
Control Status Register (Offset 00000 Hex)
control status register (dma_csr) configures pci_a engine, directs pci_a function's operation, provides status current memory transfer. Table
Table Control Status Register Format (Part
Data
Mnemonic
int_ena
Read/Write
Read/write
Definition
interrupt enable. int_ena enables intan output when either err_pend dma_tc bits driven high from dma_isr, when l_irqn signal active. Flush buffer. When high, flush marks bytes internal queue invalid resets dma_tc ad_loaded (bits interrupt status register). flush also resets itself; therefore, always reads zero. flush should never while dma_on set, because transfer progress. Local reset. This serves software reset local side addon logic (see "Local Side Signals" page 10). l_reset output pci_a function active long l_rst high. (The l_reset output also active resets.) Memory read/write. write determines direction pci_a function's transfer. When write high, data flows from local side (PCI write); when write low, data flows from local device (PCI read). enable. When high, dma_ena allows pci_a respond requests from local side (l_req) long activity stopped pending interrupt, etc. Transfer complete interrupt disable. When high, tci_dis disables dma_tc (bit interrupt status register) from generating interrupts.
flush
Write
l_rst
Read/write
write
Read/write
dma_ena
Read/write
tci_dis
Read/write
Altera Corporation
Master/Target MegaCore Function With
Table Control Status Register Format (Part
Data
Mnemonic
dma_on
Read/Write
Read
Definition
When high, dma_on indicates that pci_a function request mastership (reqn) prompted local side (i.e., active l_req). dma_on high when address loaded (ad_loaded), enabled, there pending errors. transfer sequence actually begins when dma_on becomes set. Under normal conditions (i.e., enabled errors pending) dma_on becomes when write transaction address counter register occurs. dma_on becomes whether write transaction occurs from local side target access.
31.7
Unused
Address Counter Register (Offset 00004 Hex)
address counter register (dma_acr) 32-bit register consisting 30-bit counter (bits 31.2) bits (bits 1.0) tied GND. dma_acr contains address current memory transfer incremented after every data transfer bus. memory transfers initiated pci_a function must begin DWORD boundaries. monitoring progress, dma_acr read l_dma_acr_out[] ports. Table
Table Address Counter Register Format
Data
31.2
Name dma_acr dma_acr
Read/Write
Read Read/write
Definition
Bits tied 30-bit counter
Byte Counter Register (Offset 00008 Hex)
byte counter register (dma_bcr) 17-bit register consisting 15-bit counter (bits 16.2) bits (bits 1.0) tied GND. dma_bcr holds byte count current pci_a -initiated memory transfer decrements bytes) after every data transfer bus. memory transfers initiated pci_a function must DWORD transfers. Reading dma_bcr during memory transfer achieved l_dma_bcr_out[] ports. Table
Altera Corporation
Master/Target MegaCore Function With
Table Byte Counter Register Format
Data
16.2 31.17
Name
byte_cntr byte_cntr Unused
Read/Write
Read Read/write
Definition
Bits tied GND. 15-bit counter.
Interrupt Status Register (Offset 0000C Hex)
interrupt status register (dma_isr) provides interrupt source status signals interrupt handler. Table
Table Interrupt Status Register Format
Data
Mnemonic
int_pend
Read/Write
Read
Definition
pci_a function automatically asserts int_pend indicate that pci_a interrupt pending. three possible interrupt signals from pci_a err_pend, dma_tc, int_irq. When high, err_pend indicates that error occurred during pci_a-initiated memory transfer, that interrupt handler must read configuration status register clear appropriate bits. following three status register bits assert err_pend: mstr_abrt, tar_abrt, det_par_err. "Control Status Register (Offset 00000 Hex)" page When high, int_irq indicates that local side requesting interrupt, i.e., l_irqn input asserted. When high, dma_tc indicates that pci_a-initiated transfer complete. When pci_a function sets dma_tc bit, interrupt will generated intan output long interrupts enabled int_ena (bit dma_csr) disabled tci_dis (bit dma_csr). dma_tc reset three ways: read transaction dma_isr; write transaction dma_csr, which sets flush (bit dma_csr); writing dma_acr from local side. When high, ad_loaded indicates that address been loaded dma_acr. This cleared three ways: when operation complete dma_tc set; when flush set; when rstn input asserted from bus. ad_loaded triggers beginning operation because sets dma_on dma_acr register. automatically pci_a when write operation dma_acr performed. Therefore, dma_acr should written last when operation being loaded into registers. Altera Corporation
err_pend
Read
int_irq dma_tc
Read Read
ad_loaded
Read
31.5
Unused
Master/Target MegaCore Function With
Transactions
master device, pci_a function performs read write transactions system memory (typically host bridge), another agent capable accepting burst target data transfers. read transaction from memory local side consists separate transfers:
burst read from buffer equivalent number DWORD transfers local side
read transactions from pci_a memory read command. Similarly, write transaction from pci_a function system memory consists separate transfers:
sixteen DWORD transfers from local side buffer burst write from buffer agent.
(PCI bus) write transactions from pci_a function memory write command.
Read Transaction Signal Sequence
internal read transaction, data transferred from system memory local side buffer. Specifically, read transaction consists
pci_a master device read from agent pci_a buffer. write from pci_a function's buffer local side peripheral device.
following signal sequence read transaction: host sets read transfer writing appropriate values registers. transfer sequence actually begins when dma_on becomes set. Under normal conditions (i.e., enabled errors pending) dma_on becomes when write transaction address counter register occurs. local side peripheral device asserts l_req request transfer.
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Master/Target MegaCore Function With
pci_a function asserts reqn waits gntn become active before assuming mastership bus. pci_a function reads DWORDs from system memory loads data into pci_a function's buffer. Once transfer complete, pci_a function asserts l_ackn l_wrn local side peripheral device transfers DWORDs. Because pci_a does have local side address location where data written, local side responsible generating address during local side transfer. Figure address generated from pci_a. pci_a function writes data from pci_a function's buffer onto l_dat_out[31.0] bus. When last data word written, pci_a function disables l_ackn l_wrn. dma_bcr expires (i.e., specified number data bytes have been transferred), pci_a function sets dma_tc dma_isr register asserts intan, provided that interrupt enabled tci_dis Otherwise, steps through repeated until dma_bcr expiration until error occurs. Figure
Figure Read Transaction
number clock cycles depends length burst transfer.
irdyn (pci_a) l_req (local side) Local side address l_ackn (pci_a) l_holdn (pci_a) l_wrn (pci_a) l_rdn (pci_a) l_dat_out[31.0] (pci_a)
irdy signal goes high indicating that current burst read, last data phase transfer complete.
Adr+4
Adr+8
Adr+12
Local side signals pci_a begin operation.
pci_a asserts l_ackn indicate transfer local side.
Local memory address generated local side while both l_ackn l_wrn signals asserted.
Altera Corporation
Master/Target MegaCore Function With
Write Transaction Signal Sequence
internal write transaction, data transferred from local side system memory. Specifically, write consists
transfer from local side pci_a function's buffer. pci_a master write from pci_a function's buffer agent.
following steps show signal sequence write transaction: local side host sets write transfer writing appropriate values registers. transfer sequence actually begins when dma_on becomes set. Under normal conditions (i.e., enabled errors pending) dma_on becomes when write transaction address counter register occurs. local side peripheral device asserts l_req request transfer. pci_a function asserts l_ackn l_rdn response request latches DWORDs from local side peripheral device. pci_a function reads data from l_dat_in[31.0] into pci_a buffer. When last DWORD transfer read, when buffer full, pci_a function disables l_ackn l_rdn. pci_a function asserts reqn waits gntn become active before assuming mastership bus. pci_a function transfers DWORDs from buffer target device. dma_bcr expires (i.e., specified number data bytes have been transferred), pci_a sets dma_tc dma_isr register asserts intan provided that interrupt enabled tci_dis= Otherwise, steps through repeated until dma_bcr expiration until error occurs. Figure
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Master/Target MegaCore Function With
Figure Write Transaction
reqn (pci_a) l_req (local side) Local side address l_ackn (pci_a) l_holdn (pci_a) l_wrn (pci_a) l_rdn (pci_a) l_dat_in[31.0] (pci_a)
Adr+4
Adr+8
Adr+12
pci_a asserts reqn request access bus.
Local side signals pci_a begin operation.
pci_a asserts l_ackn indicate transfer local side.
Local memory address generated local side while both l_ackn l_rdn signals asserted.
l_ackn signal goes high, indicating local side transfer.
Initializing Transfers from Local Side
pci_a function version allows both local side host perform read transactions. This section discusses local side registers initiate master transfer. more information host initiate DMA, "General Host Programming Guidelines" page pci_a function's engine, which consists 64-byte buffer four programmable registers, control channel when pci_a acquires mastership bus. After configuration space registers properly set, either host local logic initiate burst transfers writing registers pci_a function. This section divided into tasks:
Initializing pci_a function read transaction Initializing pci_a function write transaction
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Master/Target MegaCore Function With
Initializing pci_a Function Read Transaction
initialize read cycle, local logic sequentially writes dma_csr, dma_bcr, dma_acr registers. After local logic writes dma_acr, ad_loaded dma_isr register set. ad_loaded will dma_on dma_csr register enabled (dma_csr errors pending (dma_isr When dma_on set, pci_a waits local device assert l_req before actually begins read transaction requesting mastership bus. important check that dma_acr written last, i.e., after proper values have been dma_bcr dma_csr registers. Table
Table Initialization pci_a Function Read Operation
Address (Hexadecimal)
BAR0: 0.0000 BAR0: 0.0008
Register Name
dma_csr dma_bcr
Data (Hexadecimal)
0000.0031 00084
Definition
value dma_csr enables interrupts engine, disables terminal count interrupt. value written this register indicates amount data bytes) transfer. value must multiples DWORDs. address where transfer should begin. This address automatically updated after every data transfer.
BAR0: 0.0004
dma_acr
00400000
Figure page shows timing local side read transaction. this example, local logic requests read DWORDs (132 bytes) from system memory starting address 00400000 hex. Figure illustrates following signal sequence: local logic asserts l_req clock one, indicating that ready transfer. assertion l_req delayed until local side ready transfer commence. clock two, local logic asserts l_dma_csr_wr while supplying data value l_dma_dat_in[31.0] bus. hexadecimal value indicates that control status register set, which enables interrupts, disables terminal count interrupt. this case, set, which indicates read transfer.
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Master/Target MegaCore Function With
clock three, local logic asserts l_dma_bcr_wr while supplying data value dma_bcr register l_dma_dat_in[31.0] bus. hexadecimal value equals decimal value bytes, indicating that pci_a going read DWORDs. Because value l_dma_csr_out[6.0] changes value written clock write dma_csr register takes effect clock local logic asserts l_dma_acr_wr while supplying data value dma_acr register l_dma_dat_in[31.0] bus. This transaction writes value 00400000 into dma_acr register. Thus, pci_a function seeks read from address value 00400000 hex. clock write transaction dma_bcr dma_acr registers take effect. Figure shows changes values l_dma_bcr_out[16.0] l_dma_acr_out[31.0] buses. Figure also shows changes values l_dma_isr_out[4.0] l_dma_csr_out[6.0] buses, which result from ad_loaded dma_on bits becoming set. Because l_req already asserted, pci_a function seeks mastership asserting reqn signal clock seven. Figure
Figure Local SIde Initiated Read Transaction
reqn l_dma_dat_in[31.0] l_req l_dma_csr_wr l_dma_bcr_wr l_dma_acr_wr l_dma_csr_out[6.0] l_acr_out_[31.0] l_dma_bcr_out[16.0] l_dma_isr_out[4.0]
00000000 00000 00400000 00084
00000031 00000084 00400000
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Master/Target MegaCore Function With
Initializing pci_a Function Write Transaction
Setting registers burst write transaction from local logic follows same steps setting read transaction. local logic sequentially writes dma_csr, dma_bcr, dma_acr registers. When local logic writes dma_csr, dma_bcr, dma_acr registers, ad_loaded (bit dma_isr) set. ad_loaded triggers beginning operation setting dma_on (bit dma_csr), which prompts pci_a start write operation asserting l_ackn reading DWORDs from local side. Therefore, important check that dma_acr written last, i.e., after proper values have been dma_bcr dma_csr registers. Table
Table Initializing pci_a Function Write Operation
Address (Hexadecimal)
BAR0: 0.0000
Register Name
dma_csr
Data (Hexadecimal)
0000.0039
Definition
value dma_csr enables interrupts, indicates that operation write operation, enables engine disables terminal count interrupt. value written this register indicates amount data bytes) transfer. value must multiples DWORDs bytes). address where transfer should begin. This address automatically updated after every data transfer.
BAR0: 0.0008
dma_bcr
00084
BAR0: 0.0004
dma_acr
00400000
Figure page shows timing local side register write transaction, illustrates following signal sequence: local logic asserts l_req clock one, indicating that ready transfer. assertion l_req delayed until local side ready transfer commence. clock two, local logic asserts l_dma_csr_wr while suppling data value l_dma_dat_in[31.0] bus. hexadecimal value written dma_csr register, which enables interrupts, disables terminal count interrupt, enables engine requests write cycle. clock three, local logic asserts l_dma_bcr_wr while supplying data value l_dma_dat_in[31.0] bus. This signal sequence writes value hexadecimal (132 bytes) into dma_bcr register. clock three, write dma_csr takes place because value l_dma_csr_out[6.0] changed value written clock two.
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Master/Target MegaCore Function With
clock four, local logic asserts l_dma_acr_wr while supplying data value l_dma_dat_in[] bus. This signal sequence writes hexadecimal value 00400000 into dma_acr register. pci_a function starts write operation hexadecimal address 00400000. clock five, write transaction dma_bcr dma_acr take effect. Figure shows changes values l_dma_bcr_out[16.0] l_dma_acr_out[31.0] buses. Figure also shows changes values l_dma_isr_out[4.0] l_dma_csr_out[6.0] buses, which ad_loaded dma_on bits. pci_a function asserts l_ackn, indicating ready accept data from local side. rising edge clock nine, local logic begins provide data l_dat_in[31.0] into buffer.
Figure Local Side Initiated Write Transaction
l_ackn l_rdn l_dma_dat_in[31.0] l_req l_dma_csr_wr l_dma_bcr_wr l_dma_acr_wr l_dma_csr_out[6.0] l_dma_acr_out[31.0] l_dma_bcr_out[16.0] l_dma_bcr_out[16.0]
00000000 00000 00400000 00084
00000039 00000084 00400000
General Host Programming Guidelines
transfers controlled host well local logic. This section provides general programming guidelines-when controlled host-and divided into following four tasks:
Initializing pci_a function operation Interrupt service operation Clearing error bits
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Master/Target MegaCore Function With
Initializing pci_a Function
initialize pci_a function: Configure pci_a-supported configuration registers. Configure dma_csr register. Table
Table Initializing pci_a Function
Step
Address (Hexadecimal)
Register Name
command/status register
Data (Hexadecimal)
0000.0146
Definition
value command register enables memory transfers, master operations, assertion perrn case data parity errors, assertion serrn case address parity errors. value dma_csr enables both interrupts engine.
BAR0: 0.0000
0000.0011
Operation
begin operation, perform steps below: Load dma_bcr. (This step optional byte count next block data same current block.) Load dma_acr. (See "Internal Target Registers Memory Map" page Configure local side peripheral device. This step will address generation process necessary local side allow local side assert l_req. However, intelligent agent (e.g., microprocessor) operating local side, this step necessary. Table
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Master/Target MegaCore Function With
this point, pci_a function generates interrupt (intan) interrupt controller byte counter expiration.
Table Operation
Step
Address Register Name (Hexadecimal)
BAR0: 0.0008 BAR0: 0.0004 dma_bcr dma_acr
Data (Hexadecimal)
User defined User defined
Definition
amount data bytes) transfer address where transfer should begin. This address automatically updated after every data transfer. This step involve several steps, e.g., setting-up local address generator; asserting l_req from local side.
BAR0: 8.0000
External target register
User defined
Interrupt Service Operation
interrupt service operation, perform steps below: Read dma_isr. dma_tc high err_pend low, indicating that operation successful that pci_a ready transfer, step "DMA Operation" page err_pend high, indicating that operation stopped error, step "Clearing Error Bits" page Clear error prior continuing. Table
Table Interrupt Service Routine
Step
Address Register Name (Hexadecimal)
BAR0: 0.000C dma_isr
Data (Hexadecimal)
User defined
Definition
value dma_isr register indicates progress operation reason operation terminated.
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Master/Target MegaCore Function With
Clearing Error Bits
clear error bits, perform following steps: Read dma_isr. err_pend active, step Configure dma_csr asserting flush clear ad_loaded (bit dma_isr). Read configuration status register determine which error asserted (i.e., 13). Configure pci_a-supported status register write logic appropriate error field. Writing status register clears bit, allowing designer read status register write same value clear error conditions.
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Master/Target MegaCore Function With
Applications
pci_a function ideal add-in applications. Figure shows typical connection intelligent local-side host. this example, target control block needed access local side. local side data bidirectional controlled l_holdn output. host asserts l_holdn whenever accessing local bus. Because address often different than local side address, host responsible generating local side address during access.
Figure Local Side Interface Intelligent Local-Side Host with Shared Memory
l_clk l_adr[18.0] l_csn l_rdn l_wrn External Target SRAM pci_a Master/Target Local Side l_dat_in[31.0 l_dat_out[31.0] Local Side Interface: Add-on Logic
l_rdn l_wrn l_holdn l_req l_irqn l_reset l_ackn
address[16. Local Side Host: Control
Figure shows typical pci_a connection dumb memory FIFO buffer. this example, target control block needed access local side. Because local side does have intelligence generate control address signals during access, designers control block accept configuration control data from target access. Figure illustrates process bidirectional signals going between control blocks.
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Master/Target MegaCore Function With
Figure Local Side Interface Dumb FIFO Buffer
l_dat_out[31.0] l_dat_in[31.0] l_clk
l_adr[18.0] l_csn pci_a Master/Target Local Side
Local Side Interface: Add-on Logic External Target Registers
FIFO Buffer
l_rdn l_wrn l_req l_holdn l_irqn l_reset l_ackn
Local Side Interface: Control Add-on Logic control Error Flags
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Master/Target MegaCore Function With
Protocol Checklists
Tables through list applicable protocol requirements from Compliance Checklist, Revision 2.1. check mark column indicates that pci_a meets requirement. Checklists applicable Altera FLEX pci_a function listed, table entries annotated with dash represent non-applicable requirements.
Table Component Configuration
Requirement
Does each resource have configuration space based byte template defined section 6.1, with predefined 64-byte header 192-byte device specific region? functions device support vendor device command, status, header type class code fields header? configuration space available access times? writes reserved registers read only bits completed normally data discarded? reads reserved unimplemented registers, bits, completed normally data value returned? vendor number allocated SIG? Does header type field have valid encoding? multi-byte transactions access appropriate registers registers "little endian" order? read-only register values within legal ranges? example, interrupt register must only contain values 0-4. class code compliance with definition appendix predefined header portion configuration space accessible bytes, words, DWORDs? device multi-function device? device multifunction, configuration space accesses unimplemented functions ignored?
Table Component Configuration Space Summary (Part
Location
00h-01h 02h-03h 04h-05h
Name
Vendor Device Command Required. Required. Required.
Required/Optional
Support
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Master/Target MegaCore Function With
Table Component Configuration Space Summary (Part
Location
06h-07h 09h-0Bh 10h-13h 14h-27h 28h-2Bh 2Ch-2Dh 2Eh-2Fh 30h-33h
Name
Status Revision Class code Cache line size Latency timer Header type BIST BAR0 BAR1-BAR5 Cardbus pointer Subsystem vendor Subsystem Expansion base address Reserved Interrupt line Interrupt Min_Gnt Max_Lat Required. Required. Required.
Required/Optional
Support
Required master devices/functions that generate Memory Write Invalidate. Required master devices/functions that burst more than data phases. device multi-functional, then must Optional. Optional. Optional. Optional. Optional. Optional. Required devices/functions that have expansion ROM.
34h-3Bh
Required devices/functions that interrupt pin. Required devices/functions that interrupt pin. Optional. Optional.
Table Device Control Summary
Location
Required/Optional
When command register loaded with 0000h, device/function logically disconnected from bus, with exception configuration accesses? (Devices boot code path exempt). device/function disabled after assertion rstn? (Devices boot code exempt.)
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Master/Target MegaCore Function With
Table Command Register Summary
10.15
Name
space Memory space master Special cycles Memory write invalidate palette snoop Parity error response Wait cycle control serrn enable Fast back-toback enable Reserved
Required/Optional
Required device/function registers mapped into space. Required device/function responds memory space accesses. Required. Required devices/functions that respond special cycles. Required devices/functions that generate Memory Write Invalidate cycles. Required graphical devices/functions that snoop palette. Required. Optional. Required device/function serrn pin. Required master device/function support fast backto-back cycles among different targets.
Target Master
Table Device Status
Requirement
implemented read/write bits status reset read/write bits exclusively device/function? read/write bits reset when rstn asserted? read/write bits reset writing bit?
Table Status Register Summary (Part
Name
Reserved Required.
Required/Optional
Target Master
66-MHz capable Required 66-MHz capable devices. supported Optional.
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Master/Target MegaCore Function With
Table Status Register Summary (Part
10.9
Name
Fast back-toback capable Data parity detected DEVSEL timing Signaled target abort Received target abort Received master abort Signaled system error Detected parity error Optional. Required. Required.
Required/Optional
Target Master
Required devices/functions that capable signaling target abort. Required. Required. Required devices/functions that capable asserting serrn. Required unless exempted section 3.7.2.
Table Component Master Checklist (Part
Requirement
sustained tri-state signals driven high clock before being tri-stated. (section 2.1) Interface under test (IUT) always asserts byte enables during each data phase memory write Invalidate cycle. (section 3.1.1) always uses linear burst ordering memory write invalidate cycles. (section 3.1.1) always drives irdyn when data valid during write transaction. (section 3.2.1) only transfers data when both irdyn trdyn asserted same rising clock edge. (section 3.2.1) Once asserts irdyn never changes framen until current data phase completes. (section 3.2.1) Once asserts irdyn never changes irdyn until current data phase completes. (section 3.2.1) never uses reserved burst ordering (ad[1.0] "01"). (section 3.2.2) never uses reserved burst ordering (ad[1.0] "11"). (section 3.2.2) always ignores configuration command unless idsel asserted ad[1.0] "00". (section 3.2.2) IUT's address lines driven stable values during every address data phase. (section 3.2.4)
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Master/Target MegaCore Function With
Table Component Master Checklist (Part
Requirement
IUT's cben[3.0] output buffers remain enabled from first clock data phase through transaction. (section 3.3.1) IUT's cben[3.0] lines contain valid byte enable information during entire data phase. (section 3.3.1) never deasserts framen unless irdyn asserted will asserted (section 3.3.3.1) never deasserts irdyn until least clock after framen deasserted. (section 3.3.3.1) Once deasserts framen never reasserts framen during same transaction. (section 3.3.3.1) never terminates with master abort once target asserted devseln. never signals master abort earlier than clocks after framen first sampled asserted. (section 3.3.3.1) always repeats access exactly original when terminated retry. (section 3.3.3.2.2) never starts cycle unless gntn asserted. (section 3.4.1) always tri-states cben[3.0] ad[31.0] within clock after gntn negation when idle framen negated. (section 3.4.3) always drives cben[3.0] ad[31.0] within eight clocks gntn assertion when idle. (section 3.4.3) always asserts irdyn within eight clocks data phases. (section 3.5.2) always begins lock operation with read transaction. (section 3.6) always releases LOCK# when access terminated target-abort master-abort. (section 3.6) always deasserts LOCK# minimum idle cycle between consecutive lock operations. (section 3.6) always uses linear burst ordering configuration cycles. (section 3.7.4) always drives within clock cben[3.0] ad[31.0] being driven. (section 3.8.1) always drives such that number "1"s ad[31.0], cben[3.0], equals even number. (section 3.8.1) always drives perrn (when enabled) active clocks after data when data parity error detected. (section 3.8.2.1) always drives PERR (when enabled) minimum clock each data phase that parity error detected. (section 3.8.2.1) always holds framen asserted cycle following DUAL command. (section 3.10.1) never generates DUAL cycle when upper 32-bits address zero. (section 3.10.1)
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Master/Target MegaCore Function With
Table Component Target Checklist (Part
Requirement
sustained tri-state signals driven high clock before being tri-stated. (section 2.1) never reports perrn until claimed cycle completed data phase. (section 2.2.5) never aliases reserved commands with other commands. (section 3.1.1) 32-bit addressable treats DUAL command reserved. (section 3.1.1) Once asserted trdyn never changes trdyn until data phase completes. (section 3.2.1) Once asserted trdyn never changes devseln until data phase completes. (section 3.2.1) Once asserted trdyn never changes stopn until data phase completes. (section 3.2.1) Once asserted stopn never changes stopn until data phase completes. (section 3.2.1) Once asserted stopn never changes trdyn until data phase completes. (section 3.2.1) Once asserted stopn never changes devseln until data phase completes. (section 3.2.1) only transfers data when both irdyn trdyn asserted same rising clock edge. (section 3.2.1) always asserts trdyn when data valid read cycle. (section 3.2.1) always signals target-abort when unable complete entire access defined byte enables. (section 3.2.2) never responds reserved encodings. (section 3.2.2) always ignores configuration command unless idsel asserted ad[31.0] "00". (section 3.2.2) always disconnects after first data phase when reserved burst mode detected. (section 3.2.2) IUT's ad[31.0] lines driven stable values during every address data phase. (section 3.2.4) IUT's cben[3.0] output buffers remain enabled from first clock data phase through transaction. (section 3.3.1) never asserts trdyn during turnaround cycle read. (section 3.3.1) always deasserts trdyn, stopn, devseln clock following completion last data phase. (section 3.3.3.2) always signals disconnect when burst crosses resource boundary. (section 3.3.3.2) always deasserts stopn cycle immediately following framen being deasserted. (section 3.3.3.2.1)
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Master/Target MegaCore Function With
Table Component Target Checklist (Part
Requirement
Once asserted stopn never deasserts stopn until framen negated. (section 3.3.3.2.1) always deasserts trdyn before signaling target-abort. (section 3.3.3.2.1) never deasserts stopn continues transaction. (section 3.3.3.2.1) always completes initial data phase within clocks. (section 3.5.1.1) always locks minimum bytes. (section 3.6) always issues devseln before other response. (section 3.7.1) Once asserted devseln never deasserts devseln until last data phase competed except signal target-abort. (section 3.7.1) never responds special cycles. (section 3.7.2) always drives within clock cben[3.0] ad[31.0] being driven. (section 3.8.1) always drives such that number "1"s ad[31.0], cben[3.0], equals even number. (section 3.8.1)
Test Bench Summary
Tables through list applicable test bench scenarios from Compliance Checklist, Revision. 2.1. check mark column indicates that pci_a function meets requirement. Checklists applicable Altera FLEX pci_a function listed.
Table Test Scenario: Device Speed indicated devsel) Tests (Part
Requirement
Data transfer after write fast memory slave. Data transfer after read from fast memory slave. Data transfer after write medium memory slave. Data transfer after read from medium memory slave. Data transfer after write slow memory slave. Data transfer after read from slow memory slave. Data transfer after write subtractive memory slave. Data transfer after read from subtractive memory slave.
Altera Corporation
Master/Target MegaCore Function With
Table Test Scenario: Device Speed indicated devsel) Tests (Part
Requirement
Master abort after write slower than subtractive memory slave. Master abort after read from slower than subtractive memory slave.
Table Test Scenario: Target Abort Cycles
Requirement
Target abort after write fast memory slave. does repeat write transaction. IUT's target abort after read from fast memory slave. does repeat read transaction. Target abort after write medium memory slave. does repeat write transaction. IUT's target abort after read from medium memory slave. does repeat read transaction. Target abort after write slow memory slave. does repeat write transaction. IUT's target abort after read from slow memory slave. does repeat read transaction. Target abort after write subtractive memory slave. does repeat write transaction. IUT's target abort after read from subtractive memory slave. does repeat read transaction.
Table Test Scenario: Target Retry Cycles (Part
Requirement
Data transfer after write fast memory slave. Data transfer after read from fast memory slave.
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Master/Target MegaCore Function With
Table Test Scenario: Target Retry Cycles (Part
Requirement
Data transfer after write medium memory slave. Data transfer after read from medium memory slave. Data transfer after write slow memory slave. Data transfer after read from slow memory slave. Data transfer after write subtractive memory slave. Data transfer after read from subtractive memory slave.
Table Test Scenario: Single Data Phase Retry Cycles
Requirement
Data transfer after write fast memory slave. Data transfer after read from fast memory slave. Data transfer after write medium memory slave. Data transfer after read from medium memory slave. Data transfer after write slow memory slave. Data transfer after read from slow memory slave. Data transfer after write subtractive memory slave. Data transfer after read from subtractive memory slave.
Table Test Scenario: Single Data Phase Disconnect Cycles (Part
Requirement
Target abort after write fast memory slave. does repeat write transaction. IUT's target abort after read from fast memory slave. does repeat read transaction. Target abort after write medium memory slave. does repeat write transaction. IUT's target abort after read from medium memory slave.
Altera Corporation
Master/Target MegaCore Function With
Table Test Scenario: Single Data Phase Disconnect Cycles (Part
Requirement
does repeat read transaction. Target abort after write slow memory slave. does repeat write transaction. IUT's target abort after read from slow memory slave. does repeat read transaction. Target abort after write subtractive memory slave. does repeat write transaction. IUT's target abort after read from subtractive memory slave. does repeat read transaction.
Table Test Scenario: Multi-Data Phase Retry Cycles
Requirement
Data transfer after write fast memory slave. Data transfer after read from fast memory slave. Data transfer after write medium memory slave. Data transfer after read from medium memory slave. Data transfer after write slow memory slave. Data transfer after read from slow memory slave. Data transfer after write subtractive memory slave. Data transfer after read from subtractive memory slave.
Table Test Scenario: Multi-Data Phase Disconnect Cycles (Part
Requirement
Data transfer after write fast memory slave. Data transfer after read from fast memory slave. Data transfer after write medium memory slave. Data transfer after read from medium memory slave.
Altera Corporation
Master/Target MegaCore Function With
Table Test Scenario: Multi-Data Phase Disconnect Cycles (Part
Requirement
Data transfer after write slow memory slave. Data transfer after read from slow memory slave. Data transfer after write subtractive memory slave. Data transfer after read from subtractive memory slave.
Table Test Scenario: Multi-Data Phase trdyn Cycles
Requirement
Verify that data written primary target when trdynis released after second rising clock edge asserted third rising clock edge after framen. Verify that data read from primary target when trdyn released after second rising clock edge asserted third rising clock edge after framen. Verify that data written primary target when trdyn released after third rising clock edge asserted fourth rising clock edge after framen. Verify that data read from primary target when trdyn released after third rising clock edge asserted fourth rising clock edge after framen. Verify that data written primary target when trdyn released after third rising clock edge asserted fifth rising clock edge after framen. Verify that data read from primary target when trdyn released after third rising clock edge asserted fifth rising clock edge after framen. Verify that data written primary target when trdyn released after fourth rising clock edge asserted sixth rising clock edge after framen. Verify that data read from primary target when trdyn released after fourth rising clock edge asserted sixth rising clock edge after framen. Verify that data written primary target when trdyn alternately released clock cycle asserted clock cycle after framen. Verify that data read from primary target when trdyn alternately released clock cycle asserted clock cycle after framen. Verify that data written primary target when trdyn alternately released clock cycles asserted clock cycles after framen. Verify that data read from primary target when trdyn alternately released clock cycles asserted clock cycles after framen.
Altera Corporation
Master/Target MegaCore Function With
Table Test Scenario: Data Parity Error Single Cycles
Requirement
Verify sets data parity error detected when primary target asserts perrn memory write. Verify that perrn active clocks after first data phase (which parity) memory read. Verify sets parity error detected when parity detected memory read.
Table Test Scenario: 1.10 Data Parity Error Multi-Data Phase Cycles
Requirement
Verify sets parity error detected when primary target asserts perrn multi-data phase memory write. Verify that perrn active clocks after first data phase (which parity) multi-data phase memory read. Verify sets parity error detected when odd.
Table Test Scenario: 1.11 Master Time-Out
Requirement
Memory write transaction terminates before data phases completed. Memory read transaction terminates before data phases completed.
Table Test Scenario: 1.13 Master Parking
Requirement
drives ad[31.0] stable values within eight clocks gntn. drives cben[3.0] stable values within eight clocks gntn. drives clock cycle after drives ad[31.0] tri-states ad[31.0] cben[3.0] when gntn released.
Table Test Scenario: 1.14 Master Arbitration
Requirement
completes transaction when deasserting gntn coincident with asserting framen.
Altera Corporation
Master/Target MegaCore Function With
Table Test Scenario: Target Ignores Reserved Commands
Requirement
does respond RESERVED COMMANDS. Initiator detects master abort each transfer. does respond 64-bit cycle (dual address).
Table Test Scenario: Target Receives Configuration Cycles
Requirement
responds configuration cycles type read/write cycles appropriately. does respond configuration cycles type with idsel inactive.
Table Test Scenario: Target Receives Configuration Cycles with Address Data Parity Errors
Requirement
reports address parity error serrn during configuration read/write cycles. reports data parity error PERR during configuration write cycles.
Table Test Scenario: Target Receives Memory Cycles
Requirement
completes single memory read write cycles appropriately.
Table Test Scenario: 2.10 Target Receives Memory Cycles with Address Data Parity Errors
Requirement
reports address parity error serrn during memory read write cycles. reports data parity error PERR during memory write cycles.
Altera Corporation
Master/Target MegaCore Function With
References
Reference documents pci_a function include:
Special Interest Group. Local Specification. Revision 2.1. Portland, Oregon: Special Interest Group, June 1995. Special Interest Group. Compliance Checklist. Revision 2.1. Portland, Oregon: Special Interest Group, June 1995. Altera Corporation. 1996 Data Book. Jose, California: Altera Corporation, June 1996. Institute Electrical Electronics Engineers, Inc.IEEE Standard VHDL Language Reference Manual (ANSI/IEEE 1076-1993). York: Institute Electrical Electronics Engineers, Inc., June 1994.
Revision History
information contained Master/Target MegaCore Function with Data Sheet version 3.02 supersedes information published previous versions.
Version 3.02
Figures were updated version 3.02 Master/Target MegaCore Function with Data Sheet.
Version 3.01
Version 3.01 contains updated waveforms Figures
Altera Corporation
Master/Target MegaCore Function With
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: (408) 544-7144 lit_req@altera.com
Altera, FLEX, FLEX 10K, EPF10K130V, MegaCore, OpenCore, MAX, MAX+PLUS, MAX+PLUS trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 1998 Altera Corporation. rights reserved.
Printed Recycled Paper.
Altera Corporation
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