2004 2005 Debugging FT232BM FT245BM Designs Table Contents

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

2004 2005 Debugging FT232BM FT245BM Designs Table Contents

Datasheet Thumbnail

Top Searches for this datasheet

AN232B-06 Debugging FT232BM FT245BM Designs
2004 2005
Debugging FT232BM FT245BM Designs
Table Contents
Part Introduction Part Clock Circuit
Background
Clock Debugging Clock Problems
Reasons Oscillation Possible Reasons Device Oscillating, Working Checking Internal Chip Frequency
Part Signals
USBDP USBDM Vusb, Signal Ground Cable Shield
Part RESET Circuit Part Enumeration Part Suspend Resume Part EEPROM Interface Part VIII Signals Unique FT232BM
RESET#
Enumeration
Suspend. Resume Process
EECS, EESK, EEDATA
TXDEN, RXLED# TXLED# SLEEP#, PWRCTL, PWREN#
Part Signals Unique FT245BM
TXE# RXF# PWREN#. SI/WU# Data Loss Data Corruption Problems with FT245BM
Part Document Revision History, Disclaimer Contact Information
2004 2005
Contents
Document Revision History Disclaimer Contact Information
Index
2004 2005
Debugging FT232BM FT245BM Designs
Introduction
Background
Universal Serial some developers. information contained this document provided help debug designs which FTDI's FT232BM FT245BM Integrated Circuit devices. Oscilloscope traces provided help with this.
2004 2005
Clock Circuit
Clock Circuit
Clock
crystal ceramic resonator used with FT232BM FT245BM chips XTIN XTOUT pins. Figure shows output XTOUT. This shows what clock should look like when oscillating normally. this mode EECS (pin does need pulled high pulled high internal 200K resistor.
Figure 6MHz Clock signal
2004 2005
Debugging FT232BM FT245BM Designs
2.2.1
Debugging Clock Problems
Reasons Oscillation Lack voltage powered designs ensure that cable plugged Volts seen chip. self powered designs ensure that Volts applied FT232BM FT245BM chip. Communication Enumeration chip will stop oscillator device into suspend host. system does this stopping Start Frame (SOF) packets which normally sent every millisecond. check that oscillator circuit working correctly RESET# should held (0V). This will stop chip going into suspend that circuit looked with oscilloscope. Crystal Oscillating crystal resonator) without internal loading capacitors being used, they should fitted. Consult manufacturers specification suitable capacitor value. Please note that high value capacitor also prevent crystal oscillating.
2004 2005
Clock Circuit
2.2.2
Possible Reasons Device Oscillating, Working RESET# being held floating. While RESET# held low, RSTOUT# signal will drive prevent 1.5K pull resistor USBDP from going high. This pull resistor USBDP Volts RSTOUT# used system detect that device present. system detect that high speed device been connected looking USBDP being pulled high (USBDM pulled high speed device). RESET# tied then RSTOUT# will high when oscillator become stable. tell when chip come reset RTSOUT# will high (3.0 3.6V). chip will continue stay reset milliseconds after RSTOUT# goes high. This shown Figure
Figure RSTOUT# will high milliseconds after applied. After millisecond delay time chip will start talk external EEPROM. This seen looking signal EESK, Figures below.
2004 2005
Debugging FT232BM FT245BM Designs
Figure EESK seen talking EEPROM after chip comes reset.
2004 2005
Clock Circuit
Figure EESK seen talking EEPROM after chip comes reset. Chip responds first SETUP packet always NAKs response. This generally because there fault EEPROM interface. Usually pull resistor EEDATA (pin missing, EEDATA held GND. This seen continuous clocking EESK pin. (NAK handshake packet indicating negative acknowledgement) APLL bypass wrong value speed. order chip with resonator crystal EECS should high. First generation devices required 100K pull resistor fitted EECS. Second generation chips have incorporate this pull resistor onto chip. chip's APLL turned fitting pull down resistor EECS. This allow chips used with crystal, instead resonator crystal. check correct speed, measure clock period EESK line. EESK used interrogate EEPROM when device comes reset. should have period just less than microseconds. Figure next section.
2004 2005
Debugging FT232BM FT245BM Designs
2.2.3
Checking Internal Chip Frequency
Figure clock signal EESK should have period microseconds
combination faults been seen where FT232BM device appeared work properly, baud rate selection factor This came about wrong frequency mode being selected EECS, pins swapped around. board fitted with 6MHz crystal bypass times internal clock multiplier APLL. This made chip internally instead MHz. lines were swapped connector which caused host PC's line pulled instead line. This made host think that speed device present. frequency times over-sampling frequency internal DPLL that would used normal Speed device. Hence everything appeared correct except that device baud rate rate set. Either fault would have caused device work. When debugging, good sanity check look above waveform EESK check that period approximately microseconds.
2004 2005
Signals
Signals
USBDP USBDM
signal lines USBDP USBDM D-), should have ferrite beads inductors fitted series this will make ring oscillate. They should only have series resistors their path. These resistors should located close FT232BM FT245BM chip. keep lengths USBDP USBDM tracks same (within reason). (Start Frame) packet seen connector. signal bottom signal
Figure USBDP USBDM signals.
Some hubs appear extremely sensitive noise. glitch lines some cases cause device hang. This problem fixed adding 47pF capacitors ground lines. These should located between series resistors hub.
2004 2005
Debugging FT232BM FT245BM Designs
Vusb, Signal Ground Cable Shield
Vusb Volt supply which used supply powered designs. sourced from power designs, sourced High power designs. High power designs should follow advice given device data sheet Designers Guide. amount current sourced device should written into external EEPROM. recommended that ferrite used Vusb powered designs. Signal Ground Should connected ground FT232BM FT245BM chip, should connected cable shield. Inductors ferrites should placed between signal ground cable shield. designs where concern been seen that ceramic capacitor range 0.01uF 0.47uF between signal ground cable shield effective. Cable Shield Connect device case RS232 RS422 RS485 connector housing.
2004 2005
RESET Circuit
RESET Circuit
RESET#
chip contains voltage comparator generate internal reset signal. RESET# tied driven extend reset period required. While reset active, RSTOUT# will driven low. RSTOUT# used drive 1.5K pull USBDP. longer reset period required then RSTOUT# will prevent system detecting chip until RESET# driven high. Internal power-on reset circuit specification:1. chip will held reset while input RESET# less than 3.3V. chip will reset mode drops below 3.3V, provided remains below 3.3V period greater than 250ns. chip released from reset until RESET# input been greater than 3.3V least milliseconds. chip released from reset until clock running.
2004 2005
Debugging FT232BM FT245BM Designs
Enumeration
Enumeration
presence device it's speed detected host presence pull resistor USBDP (for full speed) USBDM (for speed). FT232BM FT245BM full speed devices. When chip detected host computer, drivers have loaded then PWREN# signal will driven order power external logic users board. This should done using soft start circuit avoid sudden glitches rail causing chip stop working. USBView utility application, which available Resources section FTDI website, used determine devices descriptors seen Vendor Product seen then hardware fault almost certainly preventing device from enumerating.
2004 2005
Suspend Resume
Suspend Resume
Suspend Resume Process
device into suspend host controller traffic stops more than milliseconds idle. FT232BM device, SLEEP# will indicate device been suspended. both FT232BM FT245BM, PWREN# signal will high when suspend. This reduce overall power consumption less than micro Amps, which requirement specification. option EEPROM configuration bits will internal pull down resistors instead pull resistors pins during suspend. This avoid powering external logic from pull ups. When device wakes external event such resume reset, will start timer wait around milliseconds before enabling chip. This delay allow time oscillator stabilise.
2004 2005
Debugging FT232BM FT245BM Designs
EEPROM Interface
EECS, EESK, EEDATA
FT232BM FT245BM devices used with optional external EEPROM. 93C46, 93C56, 93C66 EEPROMs suitable devices. external EEPROM should configured wide operation. external EEPROM used pull resistor should fitted onto EEDATA pin.
2004 2005
Signals Unique FT232BM
Signals Unique FT232BM
TXDEN, RXLED# TXLED#
TXDEN This will high whenever device transmits character. used systems where multiple devices driving cable. purpose control output enable RS485 level converter. turned same time last STOP sent. Figure oscilloscope trace showing output TXDEN. TXDEN specified follows :1.TXDEN will high time before start bit. TXDEN will stop exact length time depends baud rate selected. there consecutive bytes data TXDEN will high, stay high until data been passed through. stop bits being used, then small delay added using logic network ensure TXDEN drives single STOP bit.
2004 2005
Debugging FT232BM FT245BM Designs
Figure Example TXDEN output.
RXLED# This pulsed maximum millisecond when character Received from RS232. recovery time approximately millisecond before pulsed again. TXLED# This pulsed maximum millisecond when character Transmitted RS232. recovery time approximately millisecond before pulsed again.
2004 2005
Signals Unique FT232BM
SLEEP#, PWRCTL, PWREN#
SLEEP# This will when device suspend. When this happens oscillator will stop. This typically used power down external RS232 level converter I.C. RS232 converter designs. PWRCTL This input used tell system type power source GET_STATUS command. device will values from EEPROM data returned CONFIG_DESCRIPTOR powered Self powered remote wakeup. state PWRCTL will override EEPROM setting. PWRCTL then GET_STATUS command will device powered. PWRCTL high then GET_STATUS command will device self powered. This useful system where device Self powered powered. Config descriptor will return value indicating that device self powered, thus actual source read GET_STATUS command. PWRCTL connected external power supply with pull down, then power source will monitored system with GET_STATUS command. PWREN# This goes when device been configured over SET_CONFIGURATION command. This will high during suspend. useful system where there choice RS232 source. modem, example, there could connectors. would other normal RS232. This gives user choice which port connect RS232 lines could buffered volt side using '244 device. PWREN# signal then used select FT232BM chip's RS232 lines when connected. also used switch power external logic meet suspend enumeration current limits. internal pull down resistors option should EEPROM when using PWREN# this way.
2004 2005
Debugging FT232BM FT245BM Designs
Signals Unique FT245BM
TXE#
This input used Write data Byte D[0.7] lines into Transmit FIFO Buffer when goes from high low. TXE# Active output indicating Transmitter Empty. When high write data into FIFO. When data written into FIFO strobing high then low. oscilloscope trace Figure shows typical burst data device. data latched negative edge TXE# signal must monitored before next byte written.
Figure TXE# while writing data.
clearly seen from following trace (figure TXE# signal becomes inactive falling edge This example using clock period inactive period, which gives negative pulse approx. nanoseconds.
2004 2005
Signals Unique FT245BM
Figure TXE# becomes inactive falling edge
2004 2005
Debugging FT232BM FT245BM Designs
RXF#
This active input used Read current data byte from FIFO Receive buffer onto D[0.7] lines. data Byte available will read when taken from high. RXF# Active output indicating Receiver full. When high read data from FIFO. When data available FIFO which read strobing then high again.
Figure shows data being read from device. device indicates buffer empty
rising edge RD#. oscilloscope trace figure shows data being driven device when goes low. signal enables devices data buffer drivers. data will valid within maximum 50nS from falling edge RD#. This example using clock periods read pulse,.which gives read time approx nanoseconds.
2004 2005
Signals Unique FT245BM
Figure Data being written when goes low.
2004 2005
Debugging FT232BM FT245BM Designs
PWREN# SI/WU#
PWREN# This goes when device been configured over SET_CONFIGURATION command. This will high during suspend. also used switch power external logic meet suspend enumeration current limits. internal pull down resistors option should EEPROM when using PWREN# this way. SI/WU# Send Immediate Wake This used pass short packet data host computer avoid waiting latency timer trigger. also used resume host system remote wakeup been enabled EEPROM. Send Immediate function activated falling edge. SI/WU# wake suspended device should taken held milliseconds.
2004 2005
Signals Unique FT245BM
Data Loss Data Corruption Problems with FT245BM
Care must taken ensure that signals have ringing them. lines edge sensitive ringing these lines cause data loss data corruption. avoid this, small value series resistor Ohms lines chip that driving these lines. Another reason data loss observing RXF# TXE# lines. MUST ONLY write when TXE# MUST ONLY read when RXF# low. observing these conditions will result data loss corruption.
2004 2005
Debugging FT232BM FT245BM Designs
10.1
Document Revision History, Disclaimer Contact Information
Document Revision History Disclaimer
Document Revision History AN232B-06 Version Initial Document Created December 2003. AN232B-06 Version Updated December 2004.
Signals updated. Debugging Clock Problems updated EEPROM Interface section added.
Future Technology Devices International Limited, 2002 2005 Neither whole part information contained this document, products described, adapted reproduced material electronic form without prior written consent copyright holder. This product documentation supplied as-is basis warranty their suitability particular purpose either made implied. Future Technology Devices International Ltd. will accept claim damages howsoever arising result failure these products. Your statutory rights affected. These products, variant them, intended medical appliance, device system which failure product might reasonably expected result personal injury. This document provides preliminary information that subject change without notice.
2004 2005
Document Revision History, Disclaimer Contact Information
10.2
Contact Information
Future Technology Devices International Limited Scotland Street Glasgow 8QB, United Kingdom. )141 2777 )141 2758 E-Mail Sales sales@ftdichip.com E-Mail Support support@ftdichip.com E-Mail General Enquiries admin@ftdichip.com Site www.ftdichip.com
Agents Sales Representatives time writing Sales Network covers over different countries world-wide. Please visit Sales Network page site contact details distributor(s) your country.
2004 2005
Debugging FT232BM FT245BM Designs FIFO FT232BM FT245BM
Index
-AAPLL
-GGET_STATUS
-Bbaud rate buffer powered byte
-Hhigh power high speed host controller
-Iinternal chip frequency
-Cceramic capacitor ceramic resonator clock clock period CONFIG_DESCRIPTOR crystal
-L18 latency timer loading capacitors power speed
-DD- D[0.7] data designers guide
-NNAK
-O11 oscillator oscilliation
-EEECS EEDATA EEPROM EESK enumeration
-Ppower-on reset PWRCTL PWREN#
-RRD read receiver full
-Ffalling edge
2004 2005
Index remote wake reset RESET# RESETOUT# resonator resume RS232 RS422 RS485 RSTOUT# RWREN# RXF# RXLED#
-VVCC Vusb
-Wwake write
-Sself powered send immediate series resistor SET_CONFIGURATION setup packet SI/WU# SLEEP# Start Frame STOP suspend
-XXTIN XTOUT
-Ttransmitter empty TXDEN TXE# TXLED#
-UUSB Cable shield Signal Ground USBD- USBD+ USBDM USBDN USBDP
2004 2005

2004 2005 Debugging FT232BM FT245BM Designs Table Contents

Top Searches for this datasheet

Other recent searches