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Altera Consultants Alliance Program (ACAP) alliance created provide expert design assistance users Altera® programmable logic devices (PLDs). ACAPSM consultants provide their expertise services designers. Altera Hardware Description Language (AHDL) Altera's design entry language. high-level, modular language that integrated into Quartusand MAX+PLUS® development systems. create AHDL Text Design Files (.tdf) with Quartus MAX+PLUS Text Editors standard text editor, then compile, simulate, program your projects within Quartus MAX+PLUS software. AHDL supports Boolean equations, state machines, conditional decode logic. AHDL also allows create parameterized functions, includes full support functions library parameterized modules (LPM). Altera Megafunction Partners Program (AMPP) alliance between Altera developers synthesizable megafunctions. AMPPSM program created bring advantages megafunctions users Altera PLDs. APEX Altera embedded programmable logic device family based Advanced Programmable Embedded Matrix (APEXTM) architecture, which integrates look-up table logic, product-term logic, memory single device. This family offers complete system integration single device. APEX device family includes EP20K100, EP20K100E, EP20K160E, EP20K200,
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EP20K200E, EP20K300E, EP20K400, EP20K400E, EP20K600E, EP20K1000E devices. array clock clock signal that passes through logic array device before arriving clock input register. Assignment Configuration File (.acf) ASCII file MAX+PLUS software that stores information about probe, resource, device assignments hierarchy tree, well configuration information Compiler, Simulator, Timing Analyzer, Programmer. information that affect output files containing design information current hierarchy tree controlled ACF. ball-grid array (BGA) high-performance device package offered Altera that allows higher counts significantly less board area than quad flat pack (QFP) packages have better thermal characteristics than most packages. packages rapidly becoming preferred packages highdensity PLDs. Altera Device Package Information Data Sheet Ordering Information more information. BitBlaster cable serial download cable that allows both UNIX workstation users program configure devices in-system in-circuit. BitBlasterserial download cable provides programming support MAX® 9000, 7000S, 7000A, 7000AE, 3000A devices, configuration support APEX 20K, FLEX® 10K, FLEX 8000, FLEX 6000 devices.
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FLEX 6000 FLEX devices configured together FLEX chain; FLEX 8000 devices cannot configured same chain with other FLEX devices. ByteBlaster cable (The ByteBlaster cable obsolete replaced ByteBlasterMV cable) parallel download cable that allows users program configure devices insystem. ByteBlasterparallel port download cable provides programming support 9000, 7000S, 7000A, 3000A devices, configuration support APEX 20K, FLEX 10K, FLEX 8000, FLEX 6000 devices. FLEX 6000 FLEX devices configured together FLEX chain; FLEX 8000 devices cannot configured with other FLEX devices. ByteBlasterMV cable parallel download cable that allows users program configure devices in-system. ByteBlasterMVparallel port download cable provides programming support 9000, 7000S, 7000A, 3000A, configuration support APEX 20K, FLEX 10K, FLEX 8000, FLEX 6000 devices. FLEX 6000 FLEX devices configured together FLEX chain; FLEX 8000 devices cannot configured with other FLEX devices. carry chain dedicated architectural feature APEX 20K, FLEX 10K, FLEX 8000, FLEX 6000 device families that provides highperformance carry-forward function between logic elements (LEs). carry-in signal from lower-order moves forward into higherorder carry chain, feeds into both look-up table (LUT) next portion carry chain. This carry-forward function ideal adders, counters, comparators. cascade chain dedicated architectural feature APEX 20K, FLEX 10K, FLEX 8000,
FLEX 6000 families that allows implementation high-performance, wide fan-in functions. Adjacent LUTs used compute portions function parallel; cascade chain serially connects intermediate values. cascade chain available only FLEX 10K, FLEX 8000, FLEX 6000 devices. ceramic dual in-line package (CerDIP) device package offered Altera. Altera Device Package Information Data Sheet Ordering Information more information. Classic Altera device family based Altera's original EPROM-based EPLD architecture. Classicdevice family includes EP610, EP610I, EP910, EP910I, EP1800I, EP1810 devices. ClockBoost Altera high-density programmable logic device feature available APEX selected FLEX devices that uses phase-locked loop (PLL) increase clock frequencies much sixteen times incoming clock rate, improving system performance. Combining ClockBoostand ClockLockfeatures provides significant advantages system performance bandwidth. ClockLock Altera high-density programmable logic device feature available APEX selected FLEX devices that uses phase-locked loop (PLL) increase clock frequencies much sixteen times incoming clock rate, improving system performance. Combining ClockBoostand ClockLockfeatures provides significant advantages system performance bandwidth. configuration device Altera's family serial devices, which designed configure APEX FLEX devices. Configuration Devices APEX FLEX Devices Data Sheet more information.
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configuration scheme method used load data into FLEX devices. Five configuration schemes available APEX FLEX devices: configuration device, passive serial (PS), passive parallel asynchronous (PPA), passive parallel synchronous (PPS), IEEE Std. 1149.1 Joint Test Action Group (JTAG). complete information FLEX configuration schemes, Application Note (Configuring FLEX Devices). configuration schemes available FLEX 8000 devices: active serial (AS), active parallel (APU), active parallel down (APD), PPA, PPS, complete information FLEX 8000 configuration schemes, Application Note (Configuring FLEX 8000 Devices) Application Note (Configuring Multiple FLEX 8000 Devices). Three configuration schemes available FLEX 6000 devices: configuration device, passive serial (PS), passive serial asynchronous (PSA). complete information FLEX 6000 configuration schemes, Application Note (Configuring FLEX 6000 Devices). continuity checking test open circuits between device pins programming adapter sockets. This test verifies that device properly seated socket adapter. ceramic quad flat pack (CQFP) device package offered Altera. Altera Device Package Information Data Sheet Ordering Information more information. dedicated input that only used input device. development socket prototyping socket high-pin-count packages.
device Refers Altera programmable logic device, including APEX 20K, FLEX 10K, FLEX 8000, FLEX 6000, 9000, 7000, 3000A, 5000, Classic devices. Altera also offers configuration devices that used configure APEX 20K, FLEX 10K, FLEX 8000, FLEX 6000 devices. device family group Altera programmable logic devices with same fundamental architecture. Altera device families include APEX 20K, FLEX 10K, FLEX 8000, FLEX 6000, 9000, 7000, 3000A, 5000, Classic device families. Altera also offers configuration device family that includes devices used configuring APEX 20K, FLEX 10K, FLEX 8000, FLEX 6000 devices. dual in-line package (DIP) device package offered Altera. Altera Device Package Information Data Sheet Ordering Information more information. Ceramic (CerDIP) plastic (PDIP) versions available. dual-port APEX embedded system block (ESB) FLEX 10KE embedded array block (EAB) supports dual-port with independent read/write ports, synchronous asynchronous access, 150-MHz first-in first-out (FIFO) buffer performance. This system-level memory integration efficiently supports various requirements system-level design, such cache RAM, dual-port FIFO buffers, ROM. Electronic Design Interchange Format (EDIF) industry-standard format transmission design data. generate EDIF netlist file from schematic design from VHDL Verilog design that been processed with appropriate industry-standard synthesis tool. then import file into
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Quartus MAX+PLUS software EDIF Input File (.edf). Quartus MAX+PLUS software supports EDIF Input Files that contain functions from library parameterized modules (LPM). Quartus MAX+PLUS Compilers also generate more EDIF Output Files (.edo) either EDIF format that contain functional timing information simulation with standard EDIF simulator. EDIF Input File (.edf) EDIF version netlist file generated industrystandard EDIF netlist writer. EDIF Input Files compiled Quartus MAX+PLUS Compilers. Quartus MAX+PLUS software supports EDIF Input Files that contain functions from library parameterized modules (LPM). EDIF Output File (.edo) EDIF version netlist file generated EDIF Netlist Writer module Quartus MAX+PLUS Compiler. This file exported industry-standard UNIX workstation environment simulation. electrically erasable programmable read-only memory (EEPROM) form reprogrammable semiconductor memory which contents erased subjecting device appropriate electrical signals. Operating Requirements Altera Devices Data Sheet more information. embedded array series embedded array blocks (EABs) FLEX devices used implement variety memory functions complex logic functions, such digital signal processing (DSP), microcontroller, wide datapath manipulation, data transformation functions. embedded array block (EAB) building block embedded arrays FLEX devices. Each provides 2,048 4096 bits configurable RAM, ROM, FIFO, dual-port RAM. When
implementing logic, each contribute gates towards complex logic functions. embedded system block (ESB) embedded system block resides MultiCore architecture APEX 20K. Each contains 2,048 programmable bits that configured product-term logic, look-up table-based logic, dual-port RAM, ROM, content addressable memory (CAM). Each configured with macrocells, contain product terms, logic, D-flipflops, parallel expanders. Family signature part number that refers APEX Classic device families. APEX Programmable Logic Device Family Classic EPLD Family data sheets more information. Family signature part number that refers configuration device family. Family signature part number that refers FLEX device family. Family signature part number that refers device family. erasable programmable logic device (EPLD) Altera EPLD device families include 9000, 7000, 3000A, 5000, Classic. erasable programmable read-only memory (EPROM) form reprogrammable semiconductor memory which contents erased subjecting device proper wavelength ultraviolet light. Operating Requirements Altera Devices Data Sheet more information. expander product term single product term with inverted output that feeds back into logic array block (LAB) 9000, 7000, 3000A, 5000 device.
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uncommitted expander product term that shared with other logic cells same called shareable expander; product term that been shared this manner called shared expander. 9000, 7000, 3000A devices only, expander product term that "borrowed" from adjacent logic cell same called parallel expander. external timing parameters Factory-tested, worst-case values specified Altera. this data book, external timing parameters shown bold type. device family data sheets, external timing parameters listed under "External Timing Characteristics." extraction tool tool used extract devices from carriers. Extraction tools available from Altera 100-, 160-, 208-, 240-, 304-pin packages. Carrier Development Socket Data Sheet more information. FastFLEX FLEX 6000 family, FastFLEXI/O feature provides direct path from fast clock-to-output timing. FLEX 6000 Programmable Logic Device Family Data Sheet more information. fast logic option specify that register should implemented cell APEX 20K, FLEX 10K, FLEX 8000, FLEX 6000, 9000, 7000S, 7000A, 7000E, 3000A devices. This logic option applied individual logic functions. However, cannot incorporated into logic synthesis style applied entire project. FastTrack Interconnect Dedicated connection paths that span entire width height APEX 20K, FLEX 10K, FLEX 8000, FLEX 6000, 9000 device. FastTrack® Interconnect allows signals travel
between logic array blocks (LABs) device. FineLine FineLine BGApackages available APEX 20K, FLEX 10K, 7000 devices only half board area traditional packages offered with many pins EP20K1000E device. This package allows designs effectively implemented into higher density, higher count devices into designs while decreasing board space costs. Altera Device Package Information Data Sheet Ordering Information more information. Fitter MAX+PLUS Compiler module that fits project into more devices. Fitter selects appropriate interconnection paths well logic cell assignments. also generates part Report File (.rpt) File (.fit) project. (.fit) file used Quartus. FLEX Altera device family based Flexible Logic Element MatriX (FLEX) architecture. This SRAM-based family offers high-performance, register-intensive, highgate-count devices with embedded arrays. embedded arrays used efficiently implement memory complex logic functions. FLEX Embedded Programmable Logic Family FLEX 10KE Embedded Programmable Logic Data Sheets more information. FLEX 6000 Altera device family based OptiFLEXarchitecture. This SRAM-based family offers high-performance, registerintensive, high-gate-count devices. FLEX 6000 Programmable Logic Device Family Data Sheet more information. FLEX 8000 Altera device family based Flexible Logic Element MatriX (FLEX) architecture. This SRAM-based family offers high-performance, register-intensive, highgate-count devices.
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FLEX 8000 Programmable Logic Device Family Data Sheet more information. flipflop edge-triggered, clocked storage unit that stores single data. low-tohigh transition clock signal changes output flipflop based value data input(s). This value maintained until next low-to-high transition clock, until flipflop preset cleared. Depending architecture device family, register programmed level-sensitive flowthrough latch edge-triggered flipflop. Graphic Design File (.gdf) schematic design file created with MAX+PLUS Graphic Editor. Quartus software only read.gdf files. global clear signal from dedicated input logic element (LE) that does pass through logic array before arriving clear input register. FLEX 8000 devices, global clear come from dedicated inputs. APEX 20K, FLEX FLEX 6000 devices, global clear come from dedicated input from 9000, 7000 3000A devices have input pins that used either global clear sources dedicated inputs device. global clock signal from dedicated input that does pass through logic array before arriving clock input register. FLEX 8000 devices, global clock come from four dedicated input pins. APEX 20K, FLEX 10K, FLEX 8000, FLEX 6000, 9000, 7000, 3000A, 5000, EP1810 devices have input pins that used either global clock sources dedicated inputs device. EP910 EP610 devices have dedicated clock input pins.
FLEX FLEX 6000 devices, also generate global clock signal. Hexadecimal (Intel-Format) File (.hex) hexadecimal file Intel format. Quartus MAX+PLUS Compilers Simulators Files inputs specify initial memory contents. After compilation, also create Files that support configuration schemes APEX FLEX devices. internal timing parameters Worst-case delays based external timing parameters. Internal timing parameters cannot measured explicitly, should only used estimating device performance. Postcompilation timing simulation timing analysis required determine actual worstcase performance. this data book, internal timing parameters shown italic type. cell Also known element. register that exists periphery APEX 20K, FLEX 10K, FLEX 8000, FLEX 6000, 9000 device, fast input-type logic cell that associated with 7000E, 7000S, 7000A, 3000A devices. cells give short setup clock-to-out times. in-system programmability (ISP) capability EEPROM-based devices programmed after they have been mounted printed circuit board. Altera's 9000, 7000S, 7000A, 7000AE 3000A devices support ISP. Quartus MAX+PLUS Programmers support in-system programming BitBlaster serial, ByteBlaster parallel port (the ByteBlaster cable obsolete replaced ByteBlasterMV cable),
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ByteBlasterMV parallel port download cable. Programmer also provides capability program multiple devices JTAG chain. language open-standard language programming ISP-capable devices. Jamlanguage supported Quartus software MAX+PLUS software versions higher. interpreted language that optimized programming devices Joint Test Action Group (JTAG) interface. language platform independent, supports both existing ISP-capable devices, small interpreter code file size. File (.jam) ASCII programming test language file that stores programming data programming, verifying, blankchecking more ISP-capable devices JTAG chain. Files used embedded processor in-circuit test (ICT) equipment programming environments. Altera's APEX 20K, 9000, 7000S, 7000A 7000AE devices programmed with Files; APEX FLEX devices configured with Files. addition device(s) programmed configured, JTAG chain contain device that complies with IEEE Std. 1149.1 specification. JEDEC File (.jed) ASCII file that contains programming information. JEDEC Files provide industry-standard format transferring information between data preparation system logic device programmer. MAX+PLUS Compiler automatically generates JEDEC Files following devices during compilation: EP610, EP610I, EP910, EP910I, EP1810 devices (Classic family) well EPM5032 devices (MAX 5000 family). MAX+PLUS Programmer JEDEC File created with MAX+PLUS software platforms,
A+PLUS, PLDshell Plusto program Altera devices listed above, addition FLASHlogic devices (All FLASHLOGICdevices obsolete). Programmer also optionally save programming data plus functional test vectors JEDEC File format. Quartus software does support JEDEC files. Ceramic J-lead chip carrier (JLCC) device package offered Altera. Both JLCC plastic J-lead chip carrier (PLCC) packages available. Altera Device Package Information Data Sheet Ordering Information more information. Joint Test Action Group (JTAG) specifications that enables designer perform board- device-level functional verification board during production. JTAG boundary-scan testing Testing that isolates device's internal circuitry from circuitry. This testing made possible JTAG boundary-scan test (BST) architecture that available APEX 20K, FLEX devices, FLEX 8000 devices except EPF8452A EPF81188A, FLEX 6000, 9000, 7000S, 7000A 3000A devices. Serial data shifted into boundary-scan cells device; observed data shifted externally compared expected results. Boundary-scan testing offers efficient board testing, providing electronic substitute traditional "bed nails" test fixtures. library parameterized modules (LPM) architecture-independent library logic functions that parameterized achieve scalability adaptability. Altera implemented parameterized modules from version 2.0.1 2.1.0 that offer architecture-independent design entry Quartus MAX+PLUS II-supported devices.
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Quartus MAX+PLUS compilers include built-in compilation support functions used schematics, AHDL TDFs, EDIF Input Files. logic array series logic array blocks (LABs) that used implement general logic, such counters, adders, state machines, multiplexers. logic array performs same function sea-of-gates gate arrays. logic array block (LAB) physically grouped logic resources Altera device. consists logic cell array and, some device families, expander product term array. signal that available logic cell available entire LAB. APEX 20K, FLEX 10K, FLEX 8000, FLEX 6000, 9000 devices, FastTrack interconnect paths dedicated input bus. 7000, 3000A 5000 devices, programmable interconnect array (PIA) dedicated input bus. Classic devices, logic shares global clock signal. global dedicated input bus. EP1810 devices, LABs called quadrants. logic cell generic term basic building block Altera device. APEX 20K, FLEX 10K, FLEX 8000, FLEX 6000 devices, logic cells called logic elements. 9000, 7000, 3000A, 5000, Classic devices, logic cells called macrocells. logic element (LE) basic building block APEX 20K, FLEX 10K, FLEX 8000, FLEX 6000 devices. logic element consists look-up table (LUT)-i.e., function generator that quickly computes function four variables-and programmable register support sequential functions. register programmed flow-through latch, flipflop, bypassed entirely pure combinatorial logic.
register feed other logic cells feed back logic cell itself. Some logic elements feed output bidirectional pins device. Logic Programmer card expansion card required MAX+PLUS Programmer program Altera devices. MAX+PLUS software currently supports Programmer card with PCs. look-up table (LUT) function that generates outputs based inputs stored data. logic element FLEX 10K, FLEX 8000, FLEX 6000 devices includes four-input that configured emulate logical function four inputs. macrocell basic building block Altera 9000, 7000, 3000A, 5000, Classic devices. macrocell consists parts: combinatorial logic configurable register. combinatorial logic implement wide variety logic functions. Depending architecture device family, register programmed flow-through latch, flipflop, bypassed entirely pure combinatorial logic. register feed other macrocells feed back macrocell itself. Some macrocells feed output bidirectional pins device. APEX ESBs also implement product term based macrocells. Macrocells FLEX 10K, FLEX 8000, FLEX 6000 devices called logic elements. macrofunction high-level building block that used together with gate flipflop primitives MAX+PLUS design files. general, macrofunction lower-level design file MAX+PLUS hierarchical project. MasterBlaster Communications Cable MasterBlastercommunications cable uses serial port hardware interface. This cable provides configuration data
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APEX 20K, FLEX 10K, FLEX 8000, FLEX 6000 devices, well programming data 9000, 7000S, 7000A, 3000A devices. MasterBlaster communications cable also supports in-circuit debugging with SignalTap embedded logic analyzer APEX devices. Master Programming Unit (MPU) hardware module that works with zero-insertion-force sockets individual adapters program test Altera devices. PL-MPU base unit PLM-prefix adapters support both device programming device testing. PLE3-12 base unit, well adapters with other prefixes, support device programming only. 3000A Altera device family based Multiple Array MatriX (MAX) architecture. 3000A devices offer pin- logic-driven output enable signals, fast input setup times logic cells, multiple global clocks with optional inversion. addition, 3000A devices feature JTAG boundary-scan test circuitry. 3000A devices also optimized MultiVolt operation. 3000AProgrammable Logic Device Family Data Sheet more information. 5000 EPROM-based Altera device family based first generation Multiple Array MatriX (MAX) architecture. 5000 Programmable Logic Device Family Data Sheet more information. 7000 Altera device family based second generation Multiple Array MatriX (MAX) architecture. 7000A, 7000S, 7000E devices enhanced versions 7000 devices function-, pin-, programming file-compatible with 7000 devices. 7000A, 7000E, 7000S devices offer pin- logic-driven output enable signals, fast input setup times logic cells, multiple global clocks with optional inversion. addition,
7000S 7000A devices feature JTAG boundary-scan test circuitry. 7000A devices also optimized 3.3-V operation. 7000 Programmable Logic Device Family Data Sheet more information. 9000 Altera device family based third generation Multiple Array MatriX (MAX) architecture, with higher density than 7000 device family. 9000 Programmable Logic Device Family Data Sheet more information. MAX+PLUS Altera's Multiple Array MatriX Programmable Logic User System. MAX+PLUS software computer programs hardware support products that allow design implementation custom logic with FLEX 10K, FLEX 8000, FLEX 6000, 9000, 7000, 3000A, 5000, Classic devices. MegaCore function Altera-created megafunctions that optimized with Altera devices. MegaCorefunctions add-on products Quartus MAX+PLUS software. megafunction off-the-shelf building block that implements useful functions such processors, digital signal processing (DSP) functions, controllers, interfaces. Both MegaCore AMPP megafunctions available. MegaLAB structure APEX device family uses MegaLABstructure base MultiCore architecture. MegaLAB structure made combination logic elements (LEs). Each MegaLab structure contains LABs advanced embedded structure called embedded system block (ESB). MultiCore architecture enhances continuous metal FastTrack® Interconnect routing structure introducing fourth level routing
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hierarchy. addition global column interconnect, MegaLAB interconnect connects LABs within MegaLAB structure without requiring global routing resources. MultiCore architecture Altera's MultiCore embedded architecture (featured APEX device family) made logic array blocks (LABs) combines three different types structures: look-up tables (LUTs), product-term blocks, enhanced embedded memory blocks. Together, these structures make integration complex functions, such megafunctions, easy efficient process. MultiVolt feature interface that separates power supply from output voltage, enabling Altera devices powered specific core voltage level interface with devices using different voltage levels. example, Altera's FLEX 10KA family, which MultiVoltfeature, supports 5.0-V, 3.3-V, 2.5-V levels. OptiFLEX architecture Highly efficient programmable logic architecture, used FLEX 6000 family. OptiFLEXarchitecture targeted producing maximum performance utilization smallest possible area. FLEX 6000 Programmable Logic Device Family Data Sheet more information. parallel expander expander product term that "borrowed" from adjacent logic cell same 9000, 7000 3000A logic array block (LAB). parallel expander also logic option that apply logic function allow borrow such parallel expanders. This option reduce number shared expander product terms required
your project increase speed your project. However, project additional logic cells, more difficult fit. Parallel expanders also borrowed among APEX macrocells same ESB. passive parallel asynchronous (PPA) configuration scheme which external controller (e.g., CPU) loads design data into FLEX FLEX 8000 device common data bus. plastic dual in-line package (PDIP) device package offered Altera. Altera Device Package Information Data Sheet Ordering Information more information. peripheral component interconnect (PCI) industry-established, high-speed standard 64-bit applications. pin-grid array (PGA) ceramic device package offered Altera. Altera Device Package Information Data Sheet Ordering Information more information. plastic quad flat pack (PQFP) device package offered Altera. Altera Device Package Information Data Sheet Ordering Information more information. PLAD3-12 adapter that plugs into Master Programming Unit (MPU). This adapter allows PLE-prefix adapters originally designed with PLE3-12A programming unit. plastic J-lead chip carrier (PLCC) device package option offered Altera. Both ceramic J-lead chip carrier (JLCC) PLCC packages available. Altera Device Package Information Data Sheet Ordering Information more information. PLDshell Plus Altera's obsolete Programmable Logic Shell. PLDshell Plussoftware computer programs designing
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implementing custom logic circuits Altera FLASHlogic Classic devices. MAX+PLUS Programmer program FLASHlogic Classic devices with JEDEC Files (.jed) created PLDshell Plus. FLASHlogic devices obsolete. programmable interconnect array (PIA) portion 7000, 3000A 5000 device that routes signals between different logic array blocks (LABs). product term more factors Boolean expression combined with operator constitute product term, where "product" means "logic product". Programmer Object File (.pof) binary file generated Quartus MAX+PLUS Compiler's Assembler module. This file contains data used MAX+PLUS Programmer program Altera device. MAX+PLUS Programmer option save functional test vectors POF. programmable logic devices (PLDs) Digital, user-configurable integrated circuits used implement custom logic functions. PLDs implement Boolean expression registered function with built-in logic structures. programming file file containing data programming Altera devices. Both MAX+PLUS Compiler Programmer generate programming files. following programming file formats available. Quartus: SRAM Object File (.sof), Programmer Object File (.pof), File (.jam), ByteCode File (.jbc), Serial Vector Format File (.svf), Hexadecimal Output File (.hexout), Serial Bitstream File (.sbf), Binary File (.rbf). MAX+PLUS FLEX Chain File (.fcf), Hexadecimal (Intel-Format) File (.hex), File (.jam), JEDEC File (.jed), JTAG Chain File (.jcf),
Programmer Object File (.pof), Binary File (.rbf), Serial Bitstream File (.sbf), Serial Vector Format File (.svf), SRAM Object File (.sof), Tabular Text File (.ttf). FLEX Chain Files, JTAG Chain Files, Programmer Object Files, SRAM Object Files, JEDEC Files used program configure devices with MAX+PLUS Programmer. Test vectors functional testing saved POFs JEDEC Files. other file formats used configure FLEX 10K, FLEX 8000, FLEX 6000 devices other means. JTAG Chain Files used program configure more FLEX 10K, 9000, 7000S, 7000A 3000A devices multi-device JTAG chain. Programmer save data read from examined device JEDEC File format. quad flat pack (QFP) device package offered Altera. Windowed ceramic (CQFP), plastic (PQFP), power (RQFP), plastic thin (TQFP) packages available. Altera Device Package Information Data Sheet Ordering Information more information. Quartus Quartussoftware Altera's fourth generation development system programmable logic allows designers process multi-million gate designs APEX device family. Features Quartus software include: work group computing, integrated logic analysis functionality, electronic design automation (EDA) tool integration, multi-processor support, incremental recompilation, intellectual property (IP) integration. register flipflop.
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Report File (.rpt) ASCII text file, generated Quartus MAX+PLUS Compiler's Fitter module, that shows device resources used project. module preceding Partitioner generates error, this file generated. Partitioner generates error, Report File generated most cases. power quad flat pack (RQFP) device package offered Altera. Altera Device Package Information Data Sheet Ordering Information more information. security that prevents EPROM- EEPROM-based Altera device from being interrogated. This also prevents EPROMbased Altera devices from being inadvertently reprogrammed. security turned each device project, entire project. shared expanders shareable expanders feature 9000, 7000, 3000A 5000 device architecture that allows logic cells uncommitted product terms within same logic array block (LAB). product term that eligible shared this manner called sharable expander; product term that been shared this manner called shared expander. MAX+PLUS Compiler automatically allocates shareable expanders when project compiled. shared expander also allocated with primitive. SignalTap SignalTapis Altera's logic analysis solution that works with Quartus software. SignalTap reduces verification times allowing engineers conduct APEX verification internal signal values. SignalTap solution consists SignalTap megafunction, JTAG communications cable, Quartus waveform editor software.
small-outline integrated circuit (SOIC) device package option offered Altera. Altera Device Package Information Data Sheet Ordering Information more information. static random access memory (SRAM) readwrite memory that stores data integrated flipflops. Configuration Elements Data Sheet more information. SRAM Object File (.sof) binary file generated MAX+PLUS Compiler's Assembler module that contains data configuring Altera FLEX 10K, FLEX 8000, FLEX 6000 devices. Tabular Text File (.ttf) MAX+PLUS supported ASCII text file tabular format containing configuration data sequential passive parallel synchronous (PPS), passive parallel asynchronous (PPA), passive serial (PS) configuration schemes FLEX 8000 devices, configuration scheme FLEX devices. Text Design File (.tdf) ASCII text file written AHDL format. Text Design Export Files (.tdx) Text Design Output Files (.tdo) saved TDFs compiled with Quartus MAX+PLUS software. Text Design Output File (.tdo) ASCII text file AHDL format that optionally generated when compile design. contains cellby-cell description design MAX+PLUS software. timing simulation MAX+PLUS Simulator mode that uses timing Simulator Netlist File (.snf) simulate logical timing performance project. Because timing generated after logic synthesis, partitioning, fitting performed,
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timing simulation allows simulate only nodes project that have been removed logic optimization. thin quad flat pack (TQFP) device package offered Altera. Altera Device Package Information Data Sheet Ordering Information more information. Turbo control choosing speed power characteristics Altera device. Turbo Bitfeature speed increases; off, power consumption decreases. Turbo feature turned design file Compiler. user total number pins dedicated inputs device. Verilog hardware description language (HDL) from Cadence. create Verilog description with MAX+PLUS Text Editor standard text editor compile directly with MAX+PLUS software. also generate EDIF netlist file from Verilog design that been processed with Verilog synthesis tool. netlist file then imported into MAX+PLUS software EDIF Input File (.edf). MAX+PLUS Compiler also generate Verilog Output File (.vo). Verilog Output File (.vo) Verilog standard netlist file generated Verilog Netlist Writer module Compiler. Verilog Output File contains functional timing information simulation with standard Verilog simulator. VHDL Very High Speed Integrated Circuit (VHSIC) Hardware Description Language. create VHDL Design File (.vhd) with
MAX+PLUS Text Editor standard text editor compile directly with MAX+PLUS software. also generate EDIF netlist file from VHDL design that been processed with VHDL synthesis tool. netlist file then imported into MAX+PLUS software EDIF Input File (.edf). MAX+PLUS Compiler also generate VHDL Output File (.vho). VHDL Design File (.vhd) ASCII text file created with MAX+PLUS Text Editor another standard text editor. VHDL Design File contains design logic that defined with VHDL. VHDL Output File (.vho) VHDL standard netlist file that generated VHDL Netlist Writer module Compiler. VHDL Output File contains functional timing information simulation with standard VHDL simulator.
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