November 1998, ver. 7.01 Seamless design flow high-quality integr

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

November 1998, ver. 7.01 Seamless design flow high-quality integr

Datasheet Thumbnail

Top Searches for this datasheet

Software Support
November 1998, ver. 7.01
Seamless design flow high-quality integration third party tools essential continued success programmable logic devices (PLDs). Thus, Altera established Altera Commitment Cooperative Engineering Solutions (ACCESSSM) program. Through ACCESS program, Altera vendors jointly develop market next-generation high-level design tools methodologies. Altera provides partners with critical technical information assistance, ACCESS partners dedicate resources ensure best quality design results Altera architectures. ACCESS program provides total solution that allows designers generate verify multiple design revisions single day, greatly reducing product development cycle. Altera been leader support industry standards, such EDIF, VHDL, Verilog HDL, VITAL, library parameterized modules (LPM). Altera also made commitment support current ACCESS partner design flows.
more information software support provided Altera, MAX+PLUS Programmable Logic Development System Software Data Sheet this data book. This document identifies type product(s) available from each ACCESS partner, i.e., design entry, compilation/synthesis, timing analysis, functional simulation, timing simulation. These products either support Altera devices directly provide interface MAX+PLUS® development software. addition, MAX+PLUS software contains necessary interfaces libraries support many tools. Altera recommends contacting software manufacturers directly details product features, specific device support, product availability. Table lists third-party tool support Altera devices.
Altera world-wide site (http://www.altera.com) up-to-date information
ACCESS partner support Altera devices. MAX+PLUS ACCESS Interface Guidelines Cadence, Mentor Graphics, Synopsys, Viewlogic, other vendors.
Altera Corporation
A-GN-EDA-07.01
Software Support
Table Third-Party Tool Support Altera Devices (Part
Company
ACCEL Technologies, Inc. http://www.acceltech.com TEL: (619) 554-1000 FAX: (619) 554-1019 Accolade Design Automation, Inc. http://www.acc-eda.com TEL: (425) 844-6479 1-800-470-2686 FAX: (425) 788-3768 ACEO Technology http://www.aceo.com TEL: (510) 668-1700 FAX: (510) 668-0700 ACUGEN Software, Inc. http://www.acugen.com TEL: (603) 881-8821 FAX: (603) 881-8906 ALDEC, Inc. http://www.aldec.com TEL: (805) 499-6867 FAX: (805) 498-7945 Cadence Design Systems, Inc. http://www.cadence.com TEL: (408) 943-1234 FAX: (408) 943-0513 COMPASS Design TEL: (800) 433-4880 FAX: (408) 434-7977 Exemplar Logic, Inc. http://www.exemplar.com TEL: (510) 337-3700 FAX: (510) 337-3799 Flynn Systems Corporation http://www.flynn.com TEL: (603) 598-4444 FAX: (603) 337-3799
Design Entry
Compilation/ Synthesis
Timing Analysis
Functional Simulation
Timing Simulation
Altera Corporation
Software Support
Table Third-Party Tool Support Altera Devices (Part
Company
Technology Corporation, Ltd. (Japan) http://www.cgc.co.jp TEL: (81) 3-3464-5551 FAX: (81) 3-3464-5689 IKOS Systems, Inc. http://www.ikos.com TEL: (408) 255-4567 FAX: (408) 366-8699 i-Logix, Inc. http://www.ilogix.com TEL: (508) 682-2100 FAX: (508) 682-5995 ISDATA GmbH (Germany) http://www.intsys-europe.fr TEL: (49) 721/75 FAX: (49) 721/75 Mentor Graphics Corporation http://www.mentor.com TEL: (503) 685-7000 FAX: (503) 685-7704 MINC/Synario http://www.minc.com TEL: (719) 590-1155 FAX: (719) 590-7330 Model Technology, Inc. http://www.model.com TEL: (503) 641-1340 FAX: (503) 526-5410 OrCAD, Inc. http://www.orcad.com TEL: (503) 671-9500 1-800-671-9505 FAX: (503) 671-9501 Sophia Systems Technology http://www.sophia.com TEL: (408) 943-9300 FAX: (408) 943-9303
Design Entry
Compilation/ Synthesis
Timing Analysis
Functional Simulation
Timing Simulation
Altera Corporation
Software Support
Table Third-Party Tool Support Altera Devices (Part
Company
Summit Design, Inc. http://www.summitdesign.com TEL: (503) 643-9281 FAX: (503) 646-4954 Synopsys, Inc. http://www.synopsys.com TEL: (650) 962-5000 FAX: (650) 965-8637 Synplicity, Inc. http://www.synplicity.com TEL: (408) 617-6000 FAX: (408) 617-6001 Veda, Inc. http://www.veda.co.uk TEL: (800) 600-VEDA FAX: (408) 970-0174 VeriBest Incorporated http://www.veribest.com TEL: (650) 691-9680 1-800-837-4237 FAX: (650) 691-9016 Viewlogic Systems, Inc. http://www.viewlogic.com TEL: (508) 480-0881 FAX: (508) 480-0882
Design Entry
Compilation/ Synthesis
Timing Analysis
Functional Simulation
Timing Simulation
Interfaces
MAX+PLUS development software fully supports following design environments provides interfaces these tools:
Cadence Logic Workbench Design Framework Mentor Graphics Falcon Framework Synopsys Synplicity Viewlogic Powerview Workview Office
features supported Cadence, Mentor Graphics, Viewlogic, Synopsys interfaces with MAX+PLUS software summarized following sections.
Altera Corporation
Software Support
Altera/Cadence Interface
combining Cadence design entry, synthesis, verification tools (i.e., Logic Workbench Design Framework with MAX+PLUS software, designs implemented Altera PLD. Altera/Cadence interface supports top-down mixed-level design methodology. Designs entered mixture schematics, VHDL, Verilog HDL. Altera/Cadence interface supports following features:
Fully integrated design environment Easy-to-use, top-down design environment Schematic, Verilog HDL, VHDL design entry EDIF netlist files that contain timing information simulation LPM, version 2.1.0 Full timing simulation VITAL-compliant library RAM/ROM support Design description with architecture-independent design entry libraries Altera-provided gencklk utility, which generates simulation models Short design cycles with MAX+PLUS software's automatic device selection, fitting, multi-device partitioning
Altera/Mentor Graphics Interface
combining Mentor Graphics design entry, synthesis, verification tools (i.e., Falcon Framework) with MAX+PLUS software, designs implemented Altera PLD. Altera/Mentor Graphics design flow supports top-down mixedlevel design methodology. Designs entered mixture schematics VHDL. Altera/Mentor Graphics interface supports following features:
Fully integrated design environment Easy-to-use, top-down design environment Schematic design entry Industry-standard behavioral design entry with VHDL (supporting both IEEE Std. 1076-1987 1076-1993) Altera Hardware Description Language (AHDL), including syntax coloring templates MAX+PLUS Text Editor Full timing simulation VITAL-compliant library LPM, version 2.1.0 RAM/ROM support
Altera Corporation
Software Support
Altera-provided gencklk utility, which generates simulation models ClockLockand ClockBoostfeatures Design description with architecture-independent design entry libraries Short design cycles with MAX+PLUS software's automatic device selection, fitting, multi-device partitioning
Altera/Synopsys Interface
Altera/Synopsys interface brings high-level design methodology high-density programmable logic. This interface contains Altera synthesis simulation libraries, which describe logic functions that used implement designs Altera PLDs using FPGA Design Compiler. Altera/Synopsys interface supports following features:
Fully integrated design environment Full timing simulation VITAL-compliant library Industry-standard behavioral design entry with VHDL, Verilog HDL, AHDL Synopsys timing constraints supported MAX+PLUS Assignment Configuration File (.acf) format RAM/ROM FLEX family with Altera-provided genmem utility, which generates timing simulation models Altera-provided gencklk utility, which generates simulation models ClockLockand ClockBoostfeatures Different device speed grades FLEX 10K, FLEX 8000, FLEX 6000 devices Short design cycles with MAX+PLUS software's automatic device selection, fitting, multi-device partitioning Synopsys-provided Altera interfaces FPGA Express
Altera/Viewlogic Interface
combining Viewlogic design entry, synthesis, verification tools (i.e., Powerview Workview Office) with MAX+PLUS software, designs implemented Altera PLD. Altera/Viewlogic design flow supports top-down mixed-level design methodology. Designs entered mixture schematics, VHDL, AHDL. Altera/Viewlogic interface supports following features:
Fully integrated design environment Industry-standard behavioral design entry with VHDL AHDL Easy-to-use, top-down design environment Schematic design entry
Altera Corporation
Software Support
Full timing simulation LPM, version 2.1.0 RAM/ROM support Altera-provided gencklk utility, which generates simulation models Design description with architecture-independent design entry libraries Short design cycles with MAX+PLUS software's automatic device selection, fitting, multi-device partitioning
Revision History
information contained Software Support version 7.01 supersedes information published previous versions. Software Support version 7.01 contains following changes:
Added each vendor's world-wide address Table Modified Table reflect merger between Synario Design Automation MINC, Incorporated. Added COMPASS Design Table Split simulation/verification column Table into timing analysis, functional simulation, timing simulation columns. Made minor textual style changes throughout document.
Altera Corporation
Copyright 1995, 1996, 1997, 1998 Altera Corporation, Innovation Drive, Jose, 95134, USA, rights reserved. accessing this information, agree bound terms Altera's Legal Notice.

November 1998, ver. 7.01 Seamless design flow high-quality integr

Top Searches for this datasheet

Other recent searches