HIGH-SPEED 1.8V PRELIMINARY 256/128K IDT70P3519/99 SYNCHRONOUS DUAL-PO

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HIGH-SPEED 1.8V PRELIMINARY 256/128K IDT70P3519/99 SYNCHRONOUS DUAL-PO

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HIGH-SPEED 1.8V PRELIMINARY 256/128K IDT70P3519/99 SYNCHRONOUS DUAL-PORT STATIC WITH 3.3V/2.5V/1.8V INTERFACE
True Dual-Port memory cells which allow simultaneous access same memory location Power High-speed data access Commercial: (200MHz)/3.6ns (166MHz) Industrial: 3.6ns (166MHz) Selectable Pipelined Flow-Through output mode Dual chip enables allow depth expansion without additional logic Full synchronous operation both ports cycle time, 200MHz operation (14Gbps bandwidth) Fast 3.4ns clock data 1.5ns setup clock 0.5ns hold control, data, address inputs 200MHz Data input, address, byte enable control registers Self-timed write allows fast cycle time
Counter enable repeat features Interrupt Collision Detection Flags Separate byte controls multiplexed matching compatibility Dual Cycle Deselect (DCD) Pipelined Output Mode 1.8V (±100mV) power supply core LVTTL compatible,1.8V 3.3V power supply I/Os control signals each port Industrial temperature range (-40°C +85°C) available 166MHz Available 256-pin Ball Grid Array (BGA), 208-pin Plastic Quad Flatpack (PQFP) 208-pin fine pitch Ball Grid Array (fpBGA) Supports JTAG features compliant with IEEE 1149.1 limited count JTAG supported 208pin PQFP package Green parts available, ordering information
Functional Block Diagram
BE3L BE2L BE1L BE0L BE3R BE2R BE1R BE0R
FT/PIPEL
FT/PIPER
R/WL
R/WR
CE0L CE1L
WWWW
CE0R CE1R
Dout0-8_L Dout9-17_L Dout18-26_L Dout27-35_L
Dout0-8_R Dout9-17_R Dout18-26_R Dout27-35_R
FT/PIPER
FT/PIPE
dcba
256/128K MEMORY ARRAY
Din_L
Din_R
I/O0R I/O35R
CLKL A17L(1) REPEATL ADSL CNTENL A17R(
CLKR
Counter/ Address Reg.
ADDR_L
ADDR_R
Counter/ Address Reg.
REPEATR ADSR CNTENR
CE1L
INTERRUPT COLLISION DETECTION LOGIC
JTAG
COLR INTR
INTL
CONTROL
LOGIC NOTES: Address IDT70P3599. sleep mode shuts dynamic inputs, except JTAG inputs, when asserted. static inputs, i.e., PL/FTx sleep mode pins themselves (ZZx) affected during sleep mode.
7144
JULY 2008
7144/1
©2008 Integrated Device Technology, Inc.
IDT70P3519/99 High-Speed 1.8V 256/128K Dual-Port Synchronous Static
Preliminary Industrial Commercial Temperature Ranges
Description:
IDT70P3519/99 high-speed 256/128K synchronous Dual-Port RAM. memory array utilizes Dual-Port memory cells allow simultaneous access address from both ports. Registers control, data, address inputs provide minimal setup hold times. timing latitude provided this approach allows systems designed with very short cycle times. With input data register, IDT70P3519/99 been optimized applications having unidirectional bidirectional data flow bursts. automatic power down feature, controlled CE1, permits on-chip circuitry each port enter very standby power mode. 70P3519/99 support operating voltage 3.3V, 2.5V 1.8V both ports. power supply core device (VDD) 1.8V.
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IDT70P3519/99 High-Speed 1.8V 256/128K Dual-Port Synchronous Static
Preliminary Industrial Commercial Temperature Ranges
Configuration (2,3,4)
70P3519/99BC BC-256(5) 256-Pin View(6)
02/12/08
A17L(1) A14L
BE2L
CE1L
CNTEN
I/O18L
A15L
A12L
BE3L
CE0L R/WL REPEATL
I/O17L
I/O18R I/O19L
A16L
A13L
A10L
BE1L BE0L CLKL ADSL
I/O17R I/O16L
I/O20R I/O19R I/O20L PIPE/FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR I/O15R I/O15L I/O16R
I/O21R I/O21L I/O22L VDDQL
INTL
VDDQR I/O13L I/O14L I/O14R
I/O23L I/O22R I/O23R VDDQL
COLL
VDDQR I/O12R I/O13R I/O12L
I/O24R I/O24L I/O25L VDDQR
VDDQL I/O10L I/O11L I/O11R
I/O26L I/O25R I/O26R VDDQR
VDDQL
IO9L I/O10R
I/O27L I/O28R I/O27R VDDQL
VDDQR I/O8R I/O7R I/O8L
I/O29R I/O29L I/O28L VDDQL
VDDQR I/O6L I/O7L
I/O30L I/O31R I/O30R VDDQR
COLR
VDDQL I/O4R I/O5R
I/O32R I/O32L I/O31L VDDQR
INTR
VDDQL I/O3L I/O4L
I/O33L I/O34R PIPE/FTR DDQR VDDQR VDDQL VDDQL DDQR VDDQR VDDQL VDDQL
I/O1R I/O2R
I/O35R I/O34L
A16R
A13R
A10R
BE1R BE0R CLKR ADSR
I/O0L I/O0R
I/O1L
I/O35L
TRST
A15R
A12R
BE3R CE0R R/WR REPEAT
A17R(1) A14R
A11R
BE2R CE1R CNTENR
NOTES: IDT70P3599. pins must connected 1.8V power supply. pins must connected ground supply. Package body approximately 17mm 17mm 1.4mm, with 1.0mm ball-pitch. This package code used reference package diagram. This text does indicate orientation actual part-marking.
7144
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IDT70P3519/99 High-Speed 1.8V 256/128K Dual-Port Synchronous Static
Preliminary Industrial Commercial Temperature Ranges
Configuration (2,3,4,7) (con't.)
DDQR I/O18R I/O18L PL/FTL COLL INTL 17L(1) BE3L BE2L BE1L BE0L CE1L CE0L ADSL CNTENL REPEATL I/O17L I/O17R DDQR
02/12/08
I/O19L I/O19R I/O20L I/O20R VDDQL I/O21L I/O21R I/O22L I/O22R VDDQR I/O23L I/O23R I/O24L I/O24R VDDQL I/O25L I/O25R I/O26L I/O26R VDDQR VDDQL I/O27R I/O27L I/O28R I/O28L VDDQR I/O29R I/O29L I/O30R I/O30L VDDQL I/O31R I/O31L I/O32R I/O32L VDDQR I/O33R I/O33L I/O34R I/O34L
70P3519/99DR DR-208(5) 208-Pin PQFP View(6)
I/O16L I/O16R I/O15L I/O15R VDDQL I/O14L I/O14R I/O13L I/O13R VDDQR I/O12L I/O12R I/O11L I/O11R VDDQL I/O10L I/O10R I/O9L I/O9R VDDQR VDDQL I/O8R I/O8L I/O7R I/O7L VDDQR I/O6R I/O6L I/O5R I/O5L VDDQL I/O4R I/O4L I/O3R I/O3L VDDQR I/O2R I/O2L I/O1R I/O1L
NOTES: IDT70P3599. pins must connected 1.8V power supply. pins must connected ground supply. Package body approximately 28mm 28mm 3.5mm. This package code used reference package diagram. This text does indicate orientation actual part-marking. limited count, JTAG supported DR-208 package.
VDDQL I/O35R I/O35L PL/FTR COLR INTR A17R(1) A16R A15R A14R A13R A12R A11R A10R CNTENR REPEATR I/O0L VDDQL
7144
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IDT70P3519/99 High-Speed 1.8V 256/128K Dual-Port Synchronous Static
Preliminary Industrial Commercial Temperature Ranges
Configuration (2,3,4) (con't.)
02/12/08
I/O19L
COLL
A16L
A12L
BE1L
CLKL CNTENL
I/O20R I/O18R
A17L A13L
BE2L
CE0L
ADSL
VDDQR
VDDQL VDDQR PL/FTL
A14L
A10L
CE1L
R/WL
I/O16R
I/O22L
I/O21L I/O20L A15L
A11L
BE0L
REPEATL
I/O17R VDDQL
I/O23L VDDQR I/O21R
I/O12L I/O13R
I/O13L
VDDQL I/O23R I/O24L
I/O12R VDDQR
I/O26L
VDDQL I/O11R
VDDQR
70P3519/99BF BF-208(5) 208-Pin fpBGA View(6)
I/O9R
I/O10R
VDDQL
VDDQR
I/O27R
VDDQL I/O8R
I/O29R I/O28L VDDQR I/O27L
I/O8L
VDDQL I/O30R
I/O5R VDDQR
I/O31L
I/O31R I/O30L
VDDQL I/O4R
I/O5L
VDDQR I/O35R TRST A16R
A12R
BE1R
CLKR NTEN
I/O2L I/O3L
I/O4L
I/O34R A17R(1) A13R
CE0R
DDQL I/O1R VDDQR
I/O34L VDDQL
INTR
A14R
A10R
BE3R CE1R
R/WR
I/O0R
I/O2R
PL/FTR COLR A15R
A11R
BE0R
I/O0L
I/O1L
7144
NOTES: IDT70P3599. pins must connected 1.8V power supply. pins must connected ground supply. Package body approximately 15mm 15mm 1.4mm with 0.8mm ball pitch. This package code used reference package diagram. This text does indicate orientation actual part-marking.
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IDT70P3519/99 High-Speed 1.8V 256/128K Dual-Port Synchronous Static
Preliminary Industrial Commercial Temperature Ranges
Names
Left Port CE0L, CE1L R/WL A17L
Right Port CE0R, CE1R R/WR A17R
Names Chip Enables (Input)(6) Read/Write Enable (Input) Output Enable (Input) Address (Input) Data Input/Output Clock (Input) Pipeline/Flow-Through (Input) Address Strobe Enable (Input) Counter Enable (Input) Counter Repeat(2) Byte Enables (9-bit bytes) (Input)(6) Power (I/O Bus) (3.3V, 2.5V 1.8V)(1) (Input) Sleep Mode pin(3) (Input) Power (1.8V)(1) (Input) Ground (0V) (Input) Test Data Input Test Data Output Test Logic Clock (10MHz) (Input) Test Mode Select (Input) Reset (Initialize Controller) (Input)
I/O0L I/O35L CLKL PL/FTL ADSL CNTENL REPEATL BE0L BE3L VDDQL
I/O0R I/O35R CLKR PL/FTR ADSR CNTENR REPEATR BE0R BE3R VDDQR
TDO(4) TCK(4)
TRST INTL COLL
INTR COLR
Interrupt Flag (Output) Collision Alert (Output)
7144
NOTES: VDDQX must appropriate operating levels prior applying inputs I/Os controls that port. When REPEATX asserted, counter will reset last valid address loaded sleep mode shuts dynamic inputs, except JTAG inputs, when asserted. static inputs, i.e., PL/FTx sleep mode pins themselves (ZZx) affected during sleep mode. limited count, JTAG supported DR-208 package. Address A17x IDT70P3599. Chip Enables Byte Enables double buffered when PL/FT VIH, i.e., signals take cycles deselect.
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Preliminary Industrial Commercial Temperature Ranges
Truth Table I-Read/Write Enable Control
Byte I/O27-35 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT DOUT High-Z High-Z Byte I/O18-26 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DOUT High-Z High-Z DOUT DOUT High-Z High-Z
(1,2,3,4)
Byte I/O9-17 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DOUT High-Z High-Z DOUT High-Z DOUT High-Z High-Z Byte I/O0-8 High-Z High-Z High-Z High-Z High-Z High-Z High-Z DOUT High-Z High-Z High-Z DOUT High-Z DOUT High-Z High-Z MODE Deselected-Power Down Deselected-Power Down Bytes Deselected Write Byte Only Write Byte Only Write Byte Only Write Byte Only Write Lower Bytes Only Write Upper bytes Only Write Bytes Read Byte Only Read Byte Only Read Byte Only Read Byte Only Read Lower Bytes Only Read Upper Bytes Only Read Bytes Outputs Disabled Sleep Mode
7144
NOTES: VIL, Don't Care. ADS, CNTEN, REPEAT asynchronous input signals. possible read write combination bytes during given access. representative samples have been illustrated here.
Truth Table II-Address Counter Control
Address Previous Internal Address Internal Address Used L(4) CNTEN
(1,2)
REPEAT(6) L(4)
I/O(3) DI/O DI/O(n+1) DI/O(n+1) DI/O(n) External Address Used
MODE
Counter Enabled-Internal Address generation External Address Blocked-Counter disabled reused) Counter last valid load
7144
NOTES: VIL, Don't Care. Read write operations controlled appropriate setting R/W, CE1, Outputs configured flow-through output mode: outputs pipelined mode data will delayed cycle. REPEAT independent other memory control signals including CE0, address counter advances CNTEN rising edge CLK, regardless other memory control signals including CE0, CE1, BEn. When REPEAT asserted, counter will reset last valid address loaded ADS. This value power-up: known location should loaded during initialization desired. subsequent access during operations will update REPEAT address location.
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Preliminary Industrial Commercial Temperature Ranges
Recommended Operating Temperature Supply Voltage
Grade Commercial Industrial Ambient Temperature
1.8V 100mV 1.8V 100mV
7144 NOTES: This parameter This "instant case temperature.
Recommended Operating Conditions with VDDQ 1.8V
Symbol VDDQ Parameter Core Supply Voltage Supply Voltage Ground Input High Voltage Input High Voltage JTAG(3)
Min. VDDQ VDDQL VDDQ 0.2V -0.3(1) -0.3(1)
Typ.
Max. VDDQ 100mV
Unit
7144
VDDQL 100mV(2) VDDQ 100mV(2) VDDQ
Input High Voltage PIPE/FT Input Voltage Input Voltage PIPE/FT
NOTES: (min.) -0.75V pulse width less than tCYC/2, 5ns, whichever less. (max.) VDDQ 0.75V pulse width less than tCYC/2 5ns, whichever less. JTAG driven left port DDQL.
Recommended Operating Conditions with VDDQ 2.5V
Symbol VDDQ Parameter Core Supply Voltage Supply Voltage Ground Input High Volltage Input High Voltage JTAG(3) Input High Voltage PIPE/FT Input Voltage Input Voltage PIPE/FT Min. 0.2V -0.3(1) -0.3(1) Typ.
Max. 100mV
Unit
7144
VDDQL 100mV 100mV
NOTES: (min.) -1.0V pulse width less than tCYC 5ns, whichever less. (max.) VDDQ 1.0V pulse width less than tCYC 5ns, whichever less. JTAG driven left port VDDQL.
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Preliminary Industrial Commercial Temperature Ranges
Recommended Operating Conditions with VDDQ 3.3V
Symbol VDDQ Parameter Core Supply Voltage Supply Voltage Ground Input High Voltage Input High Voltage JTAG(3)
Min. 3.15 0.2V -0.3(1) -0.3(1)
Typ.
Max. 3.45 150mV
Unit
7144
DDQL 150mV 150mV
Input High Voltage PIPE/FT Input Voltage Input Voltage PIPE/FT
NOTES: (min.) -1.0V pulse width less than tCYC/2, 5ns, whichever less. (max.) VDDQ 1.0V pulse width less than tCYC 5ns, whichever less. JTAG driven left port VDDQL.
Absolute Maximum Ratings
Symbol VTERM (VDD) VTERM(2) (VDDQ) VTERM(2) (INPUTS I/O's) TBIAS(3) TSTG Rating Terminal Voltage with Respect VDDQ Terminal Voltage with Respect Input Terminal Voltage with Respect Temperature Under Bias Storage Temperature Junction Temperature Commercial Industrial min. 0.3, 4.2}(4) +125 +150 +150 Unit
IOUT(For 3.3V) Output Current IOUT(For 2.5V) Output Current IOUT(For 1.8V) Output Current
7144
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. This steady-state parameter that applies after power supply reached nominal operating value. Power sequencing necessary; however, voltage Input cannot exceed during power supply ramp Ambient Temperature under Bias. Conditions. Chip Deselected. VTERM (Inputs I/O's) -0.3 {VDDQ 0.3, 4.2} means that range -0.3V either +0.3V 4.2V whichever less.
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IDT70P3519/99 High-Speed 1.8V 256/128K Dual-Port Synchronous Static
Preliminary Industrial Commercial Temperature Ranges
Capacitance
Symbol COUT
+25°C, 1.0MHZ) PQFP ONLY
Parameter Input Capacitance Output Capacitance Conditions(2) VOUT Max. 10.5 Unit
7144
NOTES: These parameters determined device characterization, production tested. references interpolated capacitance when input output switch from from COUT also references CI/O.
Electrical Characteristics Over Operating Temperature Supply Voltage Range (VDD 1.8V 100mV)
70P3519/99S Symbol |ILI| |ILI| |ILO| (3.3V) (3.3V) (2.5V) (2.5V) (1.8V) (1.8V) Parameter Input Leakage Current JTAG Input Leakage Current Output Leakage Current Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage
Test Conditions VDDQ Max., VDDQ VDDQL Max., VDDQL VIL, VOUT VDDQ +4mA, VDDQ Min. -4mA, Min. +2mA, VDDQ Min. -2mA, Min. +2mA, VDDQ Min. -2mA, Min.
Min.
Max.
Unit
7144
VDDQ -0.40
NOTES: Applicable only TMS, TRST inputs. Outputs tested tri-state mode.
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Preliminary Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Supply Voltage Range (VDD 1.8V 100mV)
70P3519/99 S200 Com'l Only(8) Symbol Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports Level Inputs) Standby Current (One Port Level Inputs) Full Standby Current (Both Ports CMOS Level Inputs) Full Standby Current (One Port CMOS Level Inputs) Sleep Mode Current (Both Ports Level Inputs) CER= VIL, Outputs Disabled, fMAX(1) fMAX(1) CE"A" CE"B" VIH(5) Active Port Outputs Disabled, f=fMAX(1) Both Ports VDDQ 0.2V, VDDQ 0.2V 0.2V, 0(2) CE"A" 0.2V CE"B" VDDQ 0.2V(5) VDDQ 0.2V 0.2V Active Port, Outputs Disabled, fMAX(1) f=fMAX(1) Test Condition Version COM'L COM'L COM'L COM'L COM'L COM'L Typ.(4)
70P3519/99 S166 Com'l Ind(7) Typ.(4) Max.
7144
Max.
Unit
ISB1(6)
ISB2(6)
ISB3
ISB4(6)
NOTES: MAX, address control lines (except Output Enable) cycling maximum frequency clock cycle 1/tCYC using TEST CONDITIONS". means address, clock, control lines change. Applies only input CMOS level standby. Port either left right port. Port opposite from port "A". 1.8V, 25°C Typ, production tested. DC(f=0) 15mA (Typ). means CE0X CE1X means CE0X CE1X 0.2V means CE0X 0.2V CE1X VDDQ 0.2V VDDQ 0.2V means CE0X 0.2V CE1X 0.2V represents left port right port. ISB1, ISB4 will reach full standby levels (ISB3) appropriate port(s) and/or VIH. 166MHz I-Temp available BF-208 package. 200Mhz available BF-208 DR-208 packages.
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Preliminary Industrial Commercial Temperature Ranges
Test Conditions (VDDQ 3.3V/2.5V/1.8V)
Input Pulse Levels (Address Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 3.0V/GND 2.4V/GND 1.7V 3.0V/GND 2.4V/GND 1.7V 1.5V/1.25V/0.85V 1.5V/1.25V/0.85V Figure
7144
DATAOUT
10pF (Tester)
1.5V/1.25V/0.85V
7144
Figure Output Test load.
(Typical,
Capacitance (pF) from Test Load
7144
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Preliminary Industrial Commercial Temperature Ranges
Electrical Characteristics Over Operating Temperature Range (Read Write Cycle Timing) (2,3) (VDD 1.8V 100mV, +70°C)
70P3519/99 S200 Com'l Only(5) Symbol tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tSAD tHAD tSCN tHCN tSRPT tHRPT tOLZ(6) tOHZ tCD1 tCD2 tCKHZ
70P3519/99 S166 Com'l Ind(4) Min.
Parameter Clock Cycle Time (Flow-Through) Clock Cycle Time (Pipelined)(1) Clock High Time (Flow-Through)
Min.
Max.
Max.
Unit cycles cycles
Clock Time (Flow-Through)(1) Clock High Time (Pipelined)(2) Clock Time (Pipelined)(1) Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time Byte Enable Setup Time Byte Enable Hold Time Setup Time Hold Time Input Data Setup Time Input Data Hold Time Setup Time Hold Time CNTEN Setup Time CNTEN Hold Time REPEAT Setup Time REPEAT Hold Time Output Enable Data Valid Output Enable Output Low-Z Output Enable Output High-Z Clock Data Valid (Flow-Through)(1) Clock Data Valid (Pipelined)(1) Data Output Hold After Clock High Clock High Output High-Z Clock High Output Low-Z Interrupt Flag Time Interrupt Flag Reset Time Collision Flag Time Collision Flag Reset Time Sleep Mode Cycles Sleep Mode Recovery Cycles
tCKLZ(6) tINS tINR tCOLS tCOLR tZZSC tZZRC
Port-to-Port Delay tOFS Clock-to-Clock Offset Clock-to-Clock Offset Collision Detection
Please refer Collision Detection Timing Table Page
7144
NOTES: Pipelined output parameters (tCYC2, tCD2) apply either both left right ports when PL/FTX (1.8V). Flow-through parameters (tCYC1, tCD1) apply when PL/FT (0V) that port. input signals synchronous with respect clock except asynchronous Output Enable (OE), PL/FT OPT. PL/FT should treated signals, i.e. steady state during operation. These values valid either level VDDQ (3.3V/2.5V/1.8V). 166MHz I-Temp available BF-208 package. 200Mhz available BF-208 DR-208 packages. Guaranteed design (not production tested).
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Preliminary Industrial Commercial Temperature Ranges
Timing Waveform Read Cycle Pipelined Operation (FT/PIPE'X' VIH)(1,2)
tCYC2 tCH2
tCL2
Latency) tCD2 tCKLZ
ADDRESS
DATAOUT
tOLZ
tOHZ
7144
Timing Waveform Read Cycle Flow-through Output (FT/PIPE"X" VIL)(1,2,6)
tCYC1 tCH1
tCL1
tCD1 tCKLZ tOHZ tOLZ tCKHZ
ADDRESS
DATAOUT
7144 NOTES: asynchronously controlled; other inputs depicted above waveforms synchronous rising clock edge. VIL, CNTEN REPEAT VIH. output disabled (High-Impedance state) VIH, VIL, following next rising edge clock. Refer Truth Table Addresses have accessed sequentially since constantly loads address rising edge CLK; numbers reference only. HIGH, then appropriate Byte DATAOUT would disabled (High-Impedance state). denotes Left Right port. diagram with respect that port.
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Preliminary Industrial Commercial Temperature Ranges
Timing Waveform Multi-Device Pipelined Read
tCYC2 tCH2 ADDRESS(B1)
CE0(B1)
(1,2)
tCL2
tCD2 tCD2 tCKLZ tCKHZ tCD2 tCKHZ
DATAOUT(B1) ADDRESS(B2)
CE0(B2)
tCD2 tCKHZ tCKLZ tCKLZ
7144
tCD2
DATAOUT(B2)
Timing Waveform Multi-Device Flow-Through Read
tCH1 ADDRESS(B1) tCYC1 tCL1
(1,2)
CE0(B1)
tCD1 tCD1 tCKLZ
tCKHZ
tCD1 tCKHZ(1)
tCD1 tCKLZ
DATAOUT(B1)
ADDRESS(B2)
CE0(B2) tCD1 DATAOUT(B2) tCKLZ
tCKHZ
tCD1 tCKLZ
tCKHZ
7144
NOTES: Represents Device Represents Device Each Device consists IDT70P3519/99 this waveform, setup depth expansion this example. ADDRESS(B1) ADDRESS(B2) this situation. BEn, VIL; CE1(B1) CE1(B2) R/W, CNTEN, REPEAT VIH.
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Preliminary Industrial Commercial Temperature Ranges
Timing Waveform Left Port Write Pipelined Right Port Read
CLK"A" R/W"A
(1,2,4)
ADDRESS"A"
MATC
MATC
DATAIN"A"
VALID
tCO(3) CLK"B" tCD2 R/W"B" ADDRESS"B"
MATCH
MATC
DATAOUT"B"
VALID
7144 NOTES: CE0, BEn, VIL; CE1, CNTEN, REPEAT VIH. Port "B", which being read from. Port "A", which being written minimum specified, then data from Port read valid until following Port clock cycle (ie, time from write valid read opposite port will tCYC2 tCD2 minimum, then data from Port read available first Port clock cycle (ie, time from write valid read opposite port will CYC2 CD2). timing same Left Right ports. Port either Left Right port. Port opposite Port
Timing Waveform with Port-to-Port Flow-Through Read
ADDRESS
MATCH
(1,2,4)
MATCH
DATAIN
VALID
tCD1 ADDRESS
MATCH
MATCH
tCD1 DATAOUT
VALID VALID
7144 NOTES: CE0, BEn, VIL; CE1, CNTEN, REPEAT VIH. Right Port, which being read from. Left Port, which being written minimum specified, then data from Port read valid until following Port clock cycle (i.e., time from write valid read opposite port will tCD1 minimum, then data from Port read available first Port clock cycle (i.e., time from write valid read opposite port will CD1). timing same both left right ports. Port either left right port. Port opposite Port "A".
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Timing Waveform Pipelined Read-to-Write-to-Read tCYC2 VIL)(2)
tCH2 tCL2
ADDRESS
DATAIN
tCD2
tCKHZ
tCKLZ
tCD2
DATAOUT READ
WRITE
READ
7144 NOTES: Output state (High, Low, High-impedance) determined previous cycle control signals. BEn, VIL; CE1, CNTEN, REPEAT VIH. "NOP" Operation". Addresses have accessed sequentially since constantly loads address rising edge CLK; numbers reference only. "NOP" Operation." Data memory selected address corrupted should re-written guarantee data integrity.
Timing Waveform Pipelined Read-to-Write-to-Read Controlled)
tCH2
tCYC2 tCL2
ADDRESS
DATAIN
tCD2 tOHZ
tCKLZ
tCD2
DATAOUT
NOTES: 7144 Output state (High, Low, High-impedance) determined previous cycle control signals. BEn, VIL; CE1, CNTEN, REPEAT VIH. Addresses have accessed sequentially since constantly loads address rising edge CLK; numbers reference only. This timing does meet requirements fastest speed grade. This waveform indicates logically could done timing allows.
READ
WRITE
READ
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Timing Waveform Flow-Through Read-to-Write-to-Read VIL)(2)
tCH1 tCYC1 tCL1
ADDRESS
DATAIN
tCD1 READ tCD1 tCKHZ
tCD1
tCD1 READ
DATAOUT
tCKLZ WRITE
7144
Timing Waveform Flow-Through Read-to-Write-to-Read Controlled)(2)
tCYC1 tCH1 tCL1
ADDRESS
DATAIN tCD1 tOHZ
tCD1 tCKLZ
tCD1
DATAOUT
READ WRITE READ 7144 NOTES: Output state (High, Low, High-impedance) determined previous cycle control signals. CE0, BEn, VIL; CE1, CNTEN, REPEAT VIH. Addresses have accessed sequentially since constantly loads address rising edge CLK; numbers reference only. "NOP" Operation." Data memory selected address corrupted should re-written guarantee data integrity.
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Timing Waveform Pipelined Read with Address Counter Advance
tCH2 ADDRESS tCYC2 tCL2
tSAD tHAD
tSAD tHAD
CNTEN
tSCN tHCN tCD2
DATAOUT
1(2)
2(2)
READ EXTERNAL ADDRESS
READ WITH COUNTER
COUNTER HOLD
READ WITH COUNTER
7144
Timing Waveform Flow-Through Read with Address Counter Advance
tCYC1 tCH1 tCL1 ADDRESS
tSAD tHAD
tSAD tHAD tSCN tHCN
CNTEN
tCD1 DATAOUT Qx(2) READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER
7144
3(2)
NOTES: VIL; CE1, R/W, REPEAT there address change (loading address) CNTEN (advancing address), i.e. CNTEN VIH, then data output remains constant subsequent clocks.
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Timing Waveform Write with Address Counter Advance (Flow-through Pipelined Inputs)
tCH2 ADDRESS CYC2 tCL2
INTERNAL(3) ADDRESS tSAD tHAD
An(7)
tSCN
CNTEN
DATAIN WRITE EXTERNAL ADDRESS
WRITE WRITE WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
7144
Timing Waveform Counter Repeat
tCYC2 ADDRESS INTERNAL ADDRESS
(2,6)
tSAD tHAD An+1 An+2 An+2 An+1 An+2 An+2
tSCN tHCN
CNTEN
REPEAT
tSRPT tHRPT
DATAIN tCD1 DATAOUT WRITE ADDRESS ADVANCE COUNTER WRITE An+1 ADVANCE COUNTER WRITE An+2 HOLD COUNTER WRITE An+2 REPEAT READ LAST ADDRESS An+1 ADVANCE COUNTER READ An+1 An+2
An+2 HOLD COUNTER READ An+2
7144
ADVANCE COUNTER READ An+2
NOTES: CE0, BEn, VIL; REPEAT VIH. CE0, VIL; VIH. "Internal Address" equal "External Address" when equals counter output when VIH. dead cycle exists during REPEAT operation. READ WRITE cycle coincidental with counter REPEAT cycle: Address loaded last valid load will accessed. more information REPEAT function refer Truth Table CNTEN advances Internal Address from `An' +1'. transition shown indicates time required counter advance. +1'Address written during this cycle. Pipelined Mode user should cycle latency outputs timing waveform read cycle pipelined operations.
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Waveform Interrupt Timing
CLKL R/WL ADDRESSL(3)
3FFFF
tINS INTR tINR CER(1)
CLKR
R/WR ADDRESSR(3)
3FFFF
7144
NOTES: timing same Left Right ports. Address internal register, external bus, i.e., address needs qualified Address counter control signals.
Truth Table Interrupt Flag
Left Port CLKL R/WL
Right Port
A17L-A0L
(3,4)
INTL
CLKR
R/WR
CER(2)
A17R-A0R(3,4) 3FFFF 3FFFE
INTR
Function Right INTR Flag Reset Right INTR Flag Left INTL Flag Reset Left INTL Flag
7144
3FFFF 3FFFE
NOTES: INTR must initialized power-up Resetting flags. VIH. synchronous with respect clock need valid set-up hold times. A17X IDT70T3599, therefore Interrupt Addresses 1FFFF 1FFFE. Address internal register, external bus, i.e., address needs qualified Address counter control signals.
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Waveform Collision Timing(1,2) Both Ports Writing with Left Port Clock Leading
CLKL tOFS ADDRESSL
tCOLS COLL
tCOLR
tOFS CLKR
ADDRESSR
tCOLS COLR
tCOLR
7144
NOTES: VIL, VIH. reading port, Don't care Collision Detection Logic. Please refer Truth Table specific cases. Leading Port Output flag might output 3tCYC2 tCOLS after Address match. Address internal register, external bus, i.e., address needs qualified Address counter control signals.
Collision Detection Timing(3,4)
Cycle Time Region (ns) 7.5ns
tOFS (ns)
Region (ns) 2.81 3.81 5.31
7144
NOTES: Region Both ports show collision after cycle Addresses etc. Region Leading port shows collision after cycle addresses etc. while trailing port shows collision after cycle addresses etc. production units tested midpoint each region. These ranges based characterization typical device.
Truth Table Collision Detection Flag
Left Port CLKL R/WL(1) CEL(1) A17L-A0L(2) MATCH MATCH MATCH MATCH COLL CLKR R/WR(1) Right Port R(1) A17R-A0R(2) MATCH MATCH MATCH MATCH COLR Function Both ports reading. valid collision. flag output either port. Left port reading, Right port writing. Valid collision, flag output Left port. Right port reading, Left port writing. Valid collision, flag output Right port. Both ports writing. Valid collision. Flag output both ports.
7144
NOTES: VIH. synchronous with respect clock need valid set-up hold times. Address internal register, external bus, i.e., address needs qualified Address counter control signals.
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Timing Waveform Entering Sleep Mode (1,2)
Timing Waveform Exiting Sleep Mode
(1,2)
An+1
DATAOUT
Dn+1
NOTES: timing same Left Right ports. deactivated (CE0 VIH) three cycles prior asserting (ZZx VIH) held cycles after asserting (ZZx IH). deactivated (CE0 VIH) cycle prior de-asserting (ZZx VIL) held three cycles after de-asserting (ZZx VIL). device must Read Mode (R/W High) when exiting sleep mode. Outputs active data valid until following cycle.
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Functional Description
IDT70P3519/99 provides true synchronous Dual-Port Static interface. Registered inputs provide minimal set-up hold times address, data, critical control inputs. internal registers clocked rising edge clock signal, however, self-timed internal write pulse width independent cycle time. asynchronous output enable provided ease asynchronous interfacing. Counter enable inputs also provided stall operation address counters fast interleaved memory applications. HIGH clock cycle will power down internal circuitry reduce static power consumption. Multiple chip enables allow easier banking multiple IDT70P3519/99 depth expansion configurations. cycles required with HIGH re-activate outputs.
Interrupts
user chooses interrupt function, memory location (mail message center) assigned each port. left port interrupt flag (INTL) asserted when right port writes memory location 3FFFE (HEX), where write defined R/WR Truth Table. left port clears interrupt through access address location 3FFFE when R/WL VIH. Likewise, right port interrupt flag (INT asserted when left port writes memory location 3FFFF (HEX) clear interrupt flag (INTR), right port must read memory location 3FFFF (1FFFF 1FFFE IDT70P3599). message bits) 3FFFE 3FFFF (1FFFF 1FFFE IDT70P3599) user-defined since addressable SRAM location. interrupt function used, address locations 3FFFE 3FFFF (1FFFF 1FFFE IDT70P3599) used mail boxes, part random access memory. Refer Truth Table interrupt operation.
alert flag appropriate. event that user initiates burst access both ports with same starting address both ports both ports writing during each access (i.e., imposes long string collisions contiguous clock cycles), alert flag will asserted cleared every other cycle. Please refer Collision Detection timing waveform Page Collision detection IDT70P3519/99 represents significant advance functionality over current sync multi-ports, which have such capability. addition this functionality IDT70P3519/99 sustains features bandwidth flexibility. collision detection function very useful case bursting data, string accesses made sequential addresses, that indicates problem within burst, giving user option either repeating burst continuing watch alert flag whether number collisions increases above acceptable threshold value. Offering this function chip also allows users reduce their need arbitration circuits, typically done CPLD's FPGA's. This reduces board space design complexity, gives user more flexibility developing solution.
Sleep Mode
IDT70P3519/99 equipped with optional sleep power mode both ports. sleep mode both ports asynchronous active high. During normal operation, pulled low. When pulled high, port will enter sleep mode where will meet lowest possible power conditions. sleep mode timing diagram shows modes operation: Normal Operation, Read/Write Allowed Sleep Mode. normal operation inputs must meet setup hold times prior sleep after recovering from sleep. Clocks must also meet cycle high times during these periods. Three cycles prior asserting (ZZx VIH) three cycles after de-asserting (ZZx VIL), device must disabled chip enable pins. write read operation occurs during these periods, memory array corrupted. Validity data from cannot guaranteed immediately after asserted (prior being sleep). When exiting sleep mode, device must Read mode (R/Wx VIH)when chip enable asserted, chip enable must valid full cycle before read will result output valid data. During sleep mode automatically deselects itself. disconnects internal clock buffer. external clock continue without impacting RAMs sleep current (IZZ). outputs will remain high-Z state while sleep mode. inputs allowed toggle. will selected will perform reads writes.
Collision Detection
Collision defined overlap access between ports resulting potential either reading writing incorrect data specific address. specific cases: Both ports reading data corrupted, lost, incorrectly output, collision flag output either port. port writing, other port reading result write will still valid. However, reading port might capture data that state transition hence reading port's collision flag output. Both ports writing there risk that ports will interfere with each other, data stored memory will valid write from either port essentially random combination two). Therefore, collision flag output both ports. Please refer Truth Table above cases. alert flag (COLx) asserted rising clock edge affected port following collision, remains cycle. Please refer Collision Detection Timing table Page During that next cycle, internal arbitration engaged resetting alert flag (this avoids specific requirement part user reset alert flag). collisions occur subsequent clock cycles, second collision generate appropriate alert flag. third collision will generate
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Depth Width Expansion
IDT70P3519/99 features dual chip enables (refer Truth Table order facilitate rapid simple depth expansion with requirements external logic. Figure illustrates control various chip enables order expand devices depth. IDT70P3519/99 also used applications requiring expanded width, indicated Figure Through combining control signals, devices grouped necessary accommodate applications needing 72-bits wider.
A18/A17
IDT70P3519/99
IDT70P3519/99
Control Inputs
Control Inputs
IDT70P3519/99
IDT70P3519/99
R/W, CLK, ADS, REPEAT, CNTEN
Control Inputs
Control Inputs
7144
Figure Depth Width Expansion with IDT70P3519/99
NOTE: IDT70P3519, IDT70P3599.
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JTAG Timing Specifications
tJCL tJCYC tJCH
Device Inputs(1)/ TDI/TMS Device Outputs(2)/ TRST
7144
tJDC
tJRSR
tJCD
tJRST
Figure Standard JTAG Timing
NOTES: Device inputs device inputs except TDI, TMS, TRST. Device outputs device outputs except TDO.
JTAG Electrical Characteristics (1,2,3,4)
70P3519/99 Symbol tJCYC tJCH tJCL tJRST tJRSR tJCD tJDC Parameter JTAG Clock Input Period JTAG Clock HIGH JTAG Clock JTAG Clock Rise Time JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery JTAG Data Output JTAG Data Output Hold JTAG Setup JTAG Hold Min.
Max.
Units
7144
NOTES: Guaranteed design. 30pF loading external output signals. Refer Electrical Test Conditions stated earlier this document. JTAG operations occur speed (10MHz). base device speed specified this datasheet.
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Identification Register Definitions
Instruction Field Revision Number (31:28) Device (27:12) JEDEC (11:1) Register Indicator (Bit
NOTE: Device IDT70P3599 0x383.
Value 0x380(1) 0x33 Reserved version number Defines part number
Description
Allows unique identification device vendor Indicates presence register
7144
Scan Register Sizes
Register Name Instruction (IR) Bypass (BYR) Identification (IDR) Boundary Scan (BSR) Size Note
7144
System Interface Parameters
Instruction EXTEST BYPASS IDCODE Code 0000 1111 0010 0100 Description Forces contents boundary scan cells onto device outputs (1). Places boundary scan register (BSR) between TDO. Places bypass register (BYR) between TDO. Loads register (IDR) with vendor code places register between TDO. Places bypass register (BYR) between TDO. Forces device output drivers High-Z state except COLx INTx outputs. Uses BYR. Forces contents boundary scan cells onto device outputs. Places bypass register (BYR) between TDO. Places boundary scan register (BSR) between TDO. SAMPLE allows data from device inputs captured boundary scan cells shifted serially through TDO. PRELOAD allows data input serially into boundary scan cells TDI. Several combinations reserved. codes other than those identified above. internal only.
7144
HIGHZ CLAMP SAMPLE/PRELOAD
0011 0001
RESERVED PRIVATE
0101, 0111, 1000, 1001, 1010, 1011, 1100 0110,1110,1101
NOTES: Device outputs device outputs except TDO. Device inputs device inputs except TDI, TMS, TRST. Boundary Scan Descriptive Language (BSDL) file this device available website (www.idt.com), contacting your local sales representative.
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Ordering Information
XXXXX Device Type
Power
Speed
Package
Process/ Temperature Range
Blank
Commercial (0°C +70°C) Industrial (-40°C +85°C) Green 256-pin (BC-256) 208-pin PQFP (DR-208) 208-pin fpBGA (BF-208)
Commercial Only(2) Speed Megahertz Commercial Industrial(1)
Standard Power
70P3519 9Mbit (256K 2.5V Synchronous Dual-Port 70P3599 4Mbit (128K 2.5V Synchronous Dual-Port
NOTES: 166MHz I-Temp only available BC-256 package. 200Mhz only available BC-256 package. Green parts available. specific speeds, packages powers contact your local sales office.
7144
Clock Solution IDT70P3519/99 Dual-Port
Dual-Port Specifications Dual-Port Part Number Voltage Input Capacitance Clock Specifications Input Duty Cycle Requirement Maximum Frequency Jitter Tolerance Clock Device Non-PLL Clock Device
70P3519/99
LVTTL
3.5-6pF
75ps
5T2010 5T9010
5T905, 5T9050 5T907, 5T9070
7144
Preliminary Datasheet: Definition
"PRELIMINARY' datasheets contain descriptions products that early release.
Datasheet Document History:
07/07/08: Initial Datasheet
CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road Jose, 95138
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Tech Support: 408-284-2794 DualPortHelp@idt.com
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HIGH-SPEED 1.8V PRELIMINARY 256/128K IDT70P3519/99 SYNCHRONOUS DUAL-PO

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