Programmable Logic Development System Software January 1998, ver.

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Programmable Logic Development System Software January 1998, ver.

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MAX+PLUS
Programmable Logic Development System Software
January 1998, ver.
Introduction
Ideally, programmable logic design environment satisfies large variety design requirements: should support devices with different architectures, multiple platforms, provide easy-to-use interface, offer broad range features. Moreover, design environment should give designers freedom design entry methods tools their choice. Altera® MAX+PLUS® development system fully integrated programmable logic design environment that meets these requirements. MAX+PLUS design environment offers unmatched flexibility performance. rich graphical user interface complemented complete instantly accessible on-line documentation, which makes learning using MAX+PLUS software quick easy. MAX+PLUS development system includes following features:
Open Interfaces-Altera works closely with manufacturers link MAX+PLUS software with other industry-standard design entry, synthesis, verification tools. interfaces tools comply with EDIF library parameterized modules (LPM) 2.1.0, standard delay format (SDF) 2.0, VITAL Verilog HDL, VHDL 1987 1993, other standards. MAX+PLUS software interfaces allow designers create logic design with Altera standard design entry tools, compile design Altera device with MAX+PLUS Compiler, perform device- board-level simulation with Altera other verification tools. MAX+PLUS software currently provides interfaces tools from Cadence, Exemplar Logic, Mentor Graphics, Synopsys, Synplicity, Viewlogic, others. Architecture-Independence-The MAX+PLUS software supports Altera's FLEX® 10K, FLEX 8000, FLEX 6000, MAX® 9000, 7000, 5000, Classicprogrammable logic device families, offers industry's only truly architecture-independent programmable logic design environment. MAX+PLUS Compiler also provides powerful logic synthesis minimization efficiently designs with minimal user effort.
Altera Corporation
A-DS-MPLUS2-08
MAX+PLUS Programmable Logic Development System Software Data Sheet
Multiple Platforms-The MAX+PLUS software runs Windows 3.51 4.0, Windows 486- Pentium-based PCs, SPARCstations, 9000 Series 700/800, RISC System/6000 workstations. Full Integration-The MAX+PLUS software design entry, processing, verification features offer most fully integrated suite programmable logic development tools available, allowing faster debugging shorter development cycles. Modular Tools-Designers customize their development environment choosing from variety design entry, compilation, verification, device programming options, which described this data sheet. Additional features added needed, preserving initial tools investment. Because MAX+PLUS software supports multiple device families, designers support architectures without having learn tools. Hardware Description Languages (HDLs)-The MAX+PLUS software supports variety design entry options, including VHDL, Verilog HDL, Altera Hardware Description Language (AHDL). MegaCoreFunctions-MegaCore functions pre-verified netlists files complex system-level functions optimized FLEX 10K, FLEX 8000, FLEX 6000, 9000, 7000 devices. Created Altera, MegaCore functions reduce design task creating only custom logic surrounding commonly used system-level functions, which permits designers focus more time energy improving differentiating design final product. OpenCoreFeature-The MAX+PLUS software provides OpenCore feature, which allows designers evaluate megafunctions prior licensing.
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
MAX+PLUS Design Process
MAX+PLUS design process, shown Figure consists four phases: design entry, design compilation, design verification, device programming.
Figure MAX+PLUS Design Environment
Design Entry
Cadence Mentor Graphics edif Synopsys Standard Viewlogic Synplicity Exemplar Logic Design Others
Design Compilation
Verification Programming
Cadence Mentor Graphics Synopsys Viewlogic Others
edif
MAX+PLUS Compiler Standard Verification
Entry
Graphic Design Entry Text Design Entry (AHDL, VHDL, Verilog HDL)
Design-Rule Checking Logic Synthesis Fitting Multi-Device Partitioning Automatic Error Location TimingDriven Compilation OpenCore Evaluation
Timing Simulation Functional Simulation Multi-Device Simulation
abcde abcd
High-Level MegaCore Functions Functions Design AMPP Megafunctions Entry Waveform Design Entry Hierarchical Design Entry Floorplan Editing
Timing Analysis Device Programming
OpenCore Evaluation
Design Entry
MAX+PLUS software integrate multiple design files- generated with MAX+PLUS design entry tools with variety other industry-standard design entry tools-into single design hierarchy. extensive integration between MAX+PLUS applications allows information flow freely from each application. example, errors identified during compilation, simulation, timing analysis automatically located highlighted original design file Floorplan Editor. design (called "project" MAX+PLUS software) consists more levels hierarchy, user navigate from design file directly other design file hierarchy, regardless whether graphic-, text-, waveform-based.
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
MegaCore Functions
Altera MegaCore functions support applications such peripheral component interconnect (PCI) other interfaces, digital signal processing (DSP), communications. These functions instantiated into designs simulated with MAX+PLUS development system Altera-supported tool. MAX+PLUS design flows, designer simply instantiates function design file. design files that third-party tools, designers instantiate MegaCore functions specifying function port names hardware description language (HDL) design file. During design processing, tool includes function EDIF netlist file. MAX+PLUS software compiles resulting EDIF netlist file desired Altera device architecture. Table describes currently available Altera MegaCore functions.
MegaCore
Table MegaCore Functions
Applications
DSP/fast Fourier transform (FFT) Video/color space converter Communications/error checking Microperipheral library
Description
with internal direct memory access function. Zero-wait state burst-mode operation MHz. Fully parameterizable fast Fourier transform function. RGB2YCrCb YCrCb2RGB color space converters.
Target Devices
EPF10K30 EPF10K20 FLEX FLEX FLEX 8000 FLEX 6000 FLEX FLEX 8000 FLEX 6000 FLEX FLEX 8000 FLEX 6000 9000 7000
Cyclic redundancy code generator checker.
Programmable controller, interrupt controller, programmable communications interface, programmable peripheral interface adapter, universal asynchronous receiver/transmitter (UART), asychronous communications interface adapter.
Altera also provides wide variety megafunctions through Altera Megafunction Partners Program (AMPP). Like Altera, AMPPSM partners develop megafunctions that optimized Altera devices also facilitate high-density design. Over AMPP megafunctions that serve broad range digital signal processing (DSP), communications, interface, other applications available.
more information Altera MegaCore AMPP megafunctions, Introduction Megafunctions this data book Altera worldwide site http://www.altera.com.
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
OpenCore Feature
MegaCore AMPP megafunctions previewed before licensing MAX+PLUS OpenCore feature. This pre-purchase evaluation system allows designers instantiate simulate MegaCore functions AMPP megafunctions. However, programming files well output files third-party tool simulation only generated with authorization code provided upon licensing. information OpenCore feature, Introduction Megafunctions this data book, MAX+PLUS Help, refer Altera site.
OpenCore
Industry-Standard Functions
Users create designs using functions from industry-standard version 2.1.0. offers scalable logic functions-such RAM, counters, adders, multiplexers-and preserves high-level design information optimal implementation. MAX+PLUS Compiler automatically generates optimized, architecture-specific implementations functions. functions implemented with industry-standard design entry tools, schematic text designs created with MAX+PLUS software.
edif
more information functions, refer Quick Reference Guide MAX+PLUS Help, Altera site.
Industry-Standard Design Entry
MAX+PLUS Compiler interfaces with industry-standard tools that generate EDIF netlist files, including files that contain functions. Compiler uses Library Mapping Files (.lmf) symbol names from other tools MAX+PLUS logic functions. Altera supports LMFs with tools from companies such Cadence, Mentor Graphics, Viewlogic, others. VHDL 1987 1993 Verilog design support also available from Cadence, Exemplar Logic, Mentor Graphics, Synopsys, Synplicity, others.
edif
more information other tool vendors, Software Support this data book.
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
Schematic Capture Symbol Editing
MAX+PLUS Graphic Editor, shown Figure makes schematic design entry fast easy. Graphic Editor allows designer create edit Graphic Design File (.gdf) that includes combination megafunctions, macrofunctions, primitive symbols. MAX+PLUS software provides over 74-series, LPM, custom functions.
abcde
MAX+PLUS software allows designer automatically create symbol design file. With Symbol Editor (also shown Figure designer modify symbol customize appearance, create entirely symbol.
Figure MAX+PLUS Graphic Symbol Editors
Hardware Description Language (HDL) Entry
MAX+PLUS Text Editor ideal entering editing design files written VHDL 1987 1993, Verilog HDL, AHDL. MAX+PLUS Compiler synthesize logic from these languages Altera's FLEX, MAX, Classic device families.
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
HDLs implement state machines, truth tables, conditional logic, Boolean equations, arithmetic operations-including addition, subtraction, equality magnitude comparison. MAX+PLUS software also supports functions entered HDLs. Together, these features make easy implement complex projects concise, highlevel description.
Waveform Design Entry
MAX+PLUS Waveform Editor (shown Figure used create edit waveform design files, well input vectors simulation functional testing. Waveform Editor also functions logic analyzer that allows designer view simulation results.
Figure MAX+PLUS Waveform Editor
Waveform design entry best suited sequential repeating functions. Compiler's advanced waveform synthesis algorithms automatically generate logic from user-defined input output waveforms that represent registered, combinatorial, state machine logic. Compiler automatically assigns state bits state variables state machines.
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
Waveform Editor allows designer copy, cut, paste, repeat, stretch waveforms; create design files with internal nodes, flipflops, state machines, memory words; combine waveforms into groups that display binary, octal, decimal, hexadecimal values; compare sets simulation results superimposing waveforms another; annotate files with comments.
Floorplan Editing
MAX+PLUS Floorplan Editor (shown Figure simplifies process assigning logic device pins logic cells. graphical image each device used project allows easy logic placement. Both highlevel detailed device views available. designer assign pins logic cells before compiling design, view modify results after compilation. Floorplan Editor features allow designer view assigned unassigned logic device. Floorplan Editor provides color-coded view logic resources device, well user assignments, fan-in fan-out information, architecture-specific features. node dragged location. Logic assigned specific pins logic cells, more general regions within device. Assignments also made with menu commands MAX+PLUS application. assignments stored text-based Assignment Configuration File (.acf), which also edited MAX+PLUS Text Editor.
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
Figure MAX+PLUS Floorplan Editor
Hierarchical Design Entry
Hierarchical designs consist design files created using several different methods, including schematic capture, design entry, waveform design entry, industry-standard netlist files. MAX+PLUS software supports multiple levels hierarchy single design. This flexibility allows designers design entry method best suited each portion design. MAX+PLUS Hierarchy Display, which displays hierarchical structure project, allows designers traverse hierarchy easily, automatically opening appropriate editor each design file. Figure
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
Figure MAX+PLUS Hierarchy Display
Design Compilation
When MAX+PLUS software processes design, MAX+PLUS Compiler reads design files produces output files programming, simulation, timing analysis. Message Processor automatically locate errors detected during compilation find source design files designers. MAX+PLUS Compiler optimize design files FLEX 10K, FLEX 8000, FLEX 6000, 9000, 7000, 5000, Classic devices.
Message Processor
MAX+PLUS Message Processor communicates with MAX+PLUS applications, reporting error, information, warning messages design problems such connection syntax errors, well simulation, timing analysis, programming information. Designers Message Processor open design file that contains source error highlight location automatically. addition, Message Processor locate errors current project Floorplan Editor. Figure
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
Figure MAX+PLUS Compiler Message Processor
Logic Synthesis Fitting
Logic Synthesizer module MAX+PLUS Compiler supports numerous synthesis options. selects appropriate logic reduction algorithms minimize remove redundant logic, ensuring that device logic resources used efficiently possible target device architecture. also removes unused logic from project. Logic synthesis options help designer guide outcome logic synthesis. Altera provides three "ready-made" synthesis styles that specify settings multiple logic synthesis options. designer choose default style default synthesis options, create custom styles, specify individual synthesis options selected logic functions. Synthesis options tailored specific device family take advantage architecture. number advanced logic options further expand designer's ability control logic synthesis. Compiler's Fitter module applies heuristic rules select best possible implementation synthesized project more devices. This automatic fitting relieves designer tedious place-androute tasks. Fitter generates Report File (.rpt) that shows project implementation well unused resources device(s). Fitting results also displayed MAX+PLUS Floorplan Editor.
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
Timing-Driven Compilation
Compiler implement user-specified timing requirements propagation delays PD), clock-to-output delays CO), setup times SU), clock frequency MAX). Designers specify timing requirements selected logic functions project whole. Report File Compiler messages provide detailed information timing requirements have been implemented project.
Design-Rule Checking
MAX+PLUS Compiler includes Design Doctor, design-rule checker. Design Doctor checks each design file logic that cause system-level reliability problems that usually discovered only after design entered production. user choose three predefined sets design rules, create custom rules. Design rules based reliability guidelines that cover potential design problems such asynchronous inputs, ripple clocks, multi-level logic clocks, preset clear configurations, race conditions. Rule violations explained help designer determine which edits needed design files.
Multi-Device Partitioning
project large single device, Compiler's Partitioner module divides into multiple devices from same device family. Partitioner attempts split project into fewest possible number devices while minimizing number pins used inter-device communication. Fitter automatically fits logic into specified devices. Partitioning totally automatic, partially user-controlled, fully user-controlled. project large into target device, designer specify type number additional devices.
Industry-Standard Simulation Formats
MAX+PLUS Compiler create netlist files variety simulation environments. These netlist files contain post-synthesis functional timing information that used with standard design verification tools device- board-level simulation.
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
following interfaces available: Interface: EDIF MAX+PLUS Software Support: Creates EDIF netlist files that provide functionality timing third-party simulators. Creates Verilog netlist files that used with Verilog simulators. Creates VHDL 1987 1993 netlist files that used with VHDL simulators.
Verilog
VHDL
each interface, Compiler optionally generate version Standard Delay Output Format File (.sdo) that includes timing information simulators that require timing functional information separate files.
Programming File Generation
Both MAX+PLUS Compiler Programmer generate programming files. following programming file formats available MAX+PLUS software:
Programmer Object File (.pof) FLEX Chain File (.fcf) SRAM Object File (.sof) JEDEC File (.jed) JTAG Chain File (.jcf) Hexadecimal (Intel-format) File (.hex) Tabular Text File (.ttf) Binary File (.rbf) Serial Bitstream File (.sbf) Serial Vector Format (.svf) files JamFile (.jam)
more information programming configuring devices with these file formats, MAX+PLUS Help.
Design Verification
MAX+PLUS software offers design verification capabilities- including design simulation timing analysis-that test logical operation internal timing design. Design verification tools Altera devices also available from variety vendors.
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
Simulation
MAX+PLUS Simulator provides flexibility control modeling single- multi-device projects. Simulator uses Simulator Netlist Files (.snf) that generated during compilation perform functional, timing, multi-device simulation project. Figure shows MAX+PLUS Simulator.
Figure MAX+PLUS Simulator
designer either defines input stimuli with straightforward vector input language draws waveforms directly with MAX+PLUS Waveform Editor. Simulation results viewed Waveform Editor Text Editor printed waveform text files. designer specifies commands either interactively text-based command file perform variety tasks, such monitoring project glitches, oscillation, register setup hold time violations; halting simulation when user-defined conditions met; forcing flipflops high low; performing functional testing; defining initial memory content blocks. setup hold time, minimum pulse width, oscillation period violated, Message Processor reports problem. designer then Message Processor locate time which problem occurred Waveform Editor locate error original design file.
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
easy comparison, designer superimpose results simulations Waveform Editor. Functional Simulation MAX+PLUS Simulator supports functional simulation test logical operation project before synthesized, thereby allowing designer quickly identify correct logical errors. MAX+PLUS Waveform Editor displays results functional simulation provides easy access nodes project, including combinatorial functions. Timing Simulation timing simulation, MAX+PLUS Simulator tests project after been fully synthesized optimized. Timing simulation performed 0.1-ns resolution. Multi-Device Simulation MAX+PLUS software combine timing and/or functional information from multiple Altera devices, allowing designer simulate several devices operating together. Devices from different Altera device families used same project.
Timing Analysis
MAX+PLUS Timing Analyzer calculate matrix pointto-point device delays, determine setup hold time requirements device pins, calculate maximum clock frequency. MAX+PLUS design entry tools integrated with Timing Analyzer, allowing designer simply start points design files Floorplan Editor determine shortest longest propagation delays. addition, Message Processor locate display critical paths identified Timing Analyzer source design files Floorplan Editor. Figure
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
Figure MAX+PLUS Timing Analyzer
Device Programming
MAX+PLUS Programmer, shown Figure uses programming files program Altera devices. Programmer allows designer program, verify, examine, blank-check, functionally test devices. Altera provides hardware software necessary programming verifying devices, including Logic Programmer Card, Master Programming Unit (MPU), programming adapters. add-on Logic Programmer card (for compatible computers) drives MPU. performs continuity checking ensure adequate electrical contact between programming adapter device. With appropriate programming adapter, also supports functional testing, that vectors created simulation applied programmed device verify functionality.
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
Figure MAX+PLUS Programmer
Altera also provides ByteBlasterparallel port download cable, BitBlasterserial download cable device programming configuration. ByteBlaster download cable connects parallel port BitBlaster download cable connects standard UNIX workstation RS-232 port provide configuration/programming data. With BitBlaster ByteBlaster download cables, designers also configure program multiple devices using multi-device JTAG chain mode MAX+PLUS Programmer.
more information BitBlaster ByteBlaster download cables, Altera programming hardware software, other programming hardware manufacturers, JTAG chain programming configuration, refer following sources:
ByteBlaster Parallel Port Download Cable Data Sheet this data book BitBlaster Serial Download Cable Data Sheet this data book Altera Programming Hardware Data Sheet this data book Programming Hardware Manufacturers this data book "Setting Multi-Device JTAG Chains" MAX+PLUS Help
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
On-Line Help
On-line help provides access information about MAX+PLUS software. includes complete, up-to-date documentation MAX+PLUS applications. Altera-provided primitives, megafunctions, macrofunctions; causes suggested actions messages; references related Altera documentation; text file formats (e.g., AHDL, Vector Files); information Altera devices adapters. On-line help only keystroke mouse click away. provides instant access information dialog box, highlighted menu command, pop-up message. Typing Shift+F1 choosing contextsensitive help button toolbar turns mouse pointer into question mark pointer that allows designer click item screen-including logic function symbols names text file keywords-for context-sensitive help that item.
Software Maintenance
Altera software maintenance program ensures that designers will receive latest version MAX+PLUS development software every quarter. software maintenance program provides following benefits:
Device Support-Altera offers devices with highest density performance industry. Altera continues offer additional devices providing additional devices package options, which allows designers create systems with most advanced devices packages. Software Features-New software features enhancements make MAX+PLUS software easier improve design compilation times. Designers with maintenance agreements receive features with each MAX+PLUS upgrade, ranging from synthesis improved timing-driven compilation. Programming Methods-MAX+PLUS supports latest programming methods, (e.g., in-system programmability (ISP), incircuit reconfigurability (ICR), programming test language. Altera continues enhance programming hardware software make these programming methods easily accessible. Third-Party Interfaces-The MAX+PLUS software provides interfaces major design tools standard feature. These interfaces allow designers work most familiar design environment implement designs Altera device family. Altera continually enhances MAX+PLUS design environment keep up-to-date with third-party tool improvements upgrades.
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
Recommended System Configurations
MAX+PLUS software with optimum results, Altera recommends following system configurations:
System Configuration
200-MHz Pentium-based better Available memory shown Table Microsoft Windows version 3.51 higher, Windows Microsoft Windows-compatible graphics card 17-inch color monitor CD-ROM drive Microsoft Windows-compatible 2-button mouse Full-length 8-bit slot programmer card Parallel port (i.e., port) RS-232 serial port BitBlaster download cable
Table Memory Requirements MAX+PLUS Systems
Device Family
FLEX FLEX 8000 FLEX 6000 9000 7000
Available Memory (Mbytes)
Physical (Mbytes)
Ultra SPARCstation System Configuration
Ultra SPARCstation with color monitor Available memory shown Table OpenWindows higher Solaris higher 9660-compatible CD-ROM drive RS-232 serial port BitBlaster download cable
9000 Series 700/800 Workstation System Configuration
9000 Series 700/800 workstation with color monitor Available memory shown Table HP-UX version 10.20 higher HP-VUE 9660-compatible CD-ROM drive RS-232 serial port BitBlaster download cable
Altera Corporation
MAX+PLUS Programmable Logic Development System Software
RISC System/6000 Workstation System Configuration
RISC System/6000 workstation with color monitor Available memory shown Table page version higher 9660-compatible CD-ROM drive RS-232 serial port BitBlaster download cable most up-to-date information regarding system requirements, refer MAX+PLUS read.me file.
Software Package Options
Altera offers variety tool configurations add-on migration products UNIX-workstation-based versions MAX+PLUS software. more information, Altera site http://www.altera.com. up-to-date information MAX+PLUS software packages development systems, contact your local sales representative Altera site.
Altera Corporation
Copyright 1995, 1996, 1997, 1998, 1999 Altera Corporation, Innovation Drive, Jose, 95134, USA, rights reserved. accessing this information, agree bound terms Altera's Legal Notice.

Programmable Logic Development System Software January 1998, ver.

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