High-Density Embedded Programmable Logic Devices System-Level Integrat
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APEX Devices
High-Density Embedded Programmable Logic Devices System-Level Integration
APEX: Revolutionary Embedded Architecture
Altera® APEXprogrammable logic family offers complete systemlevel integration single device. With innovative MultiCorearchitecture, APEX family combines enhances strengths previous programmable logic device (PLD) architectures, delivers ultimate design flexibility efficiency high-performance, applications. With densities over 2.5-million system gates performance enhancements such multiple phase-locked loops (PLLs), APEX device family designed 64-bit, 66-MHz PCI-compliant capable achieving data transfer rates Mbits/second. 2.5-V APEX devices fabricated advanced 0.22-micron, six-layer-metal SRAM process. 1.8-V APEX 20KE devices, which functional superset APEX devices, utilize 0.18micron, six-layer-metal process.
enhanced embedded memory blocks FLEX 10KE devices. three structures combined into single integrated architecture, eliminating need multiple devices, saving board space, simplifying implementation complex designs. MultiCore architecture introduces level hierarchy called MegaLABstructure. Each MegaLAB structure contains logic array blocks (LABs) that consist logic elements each used
MegaLAB Structure
MegaLAB Local Interconnect
Logic Array Block (LAB)
Embedded System Block (ESB)
Logic Element (LE)
Breakthrough MultiCore Architecture
innovative APEX MultiCore architecture contains three types structures: look-up-table (LUT) logic FLEX® FLEX 6000 devices, product-term logic MAX® 7000 devices,
APEX Device Features
MultiCore Architecture
Product Term Memory
implement logic, advanced embedded structure called embedded system block (ESB). MegaLAB local interconnect ties LABs together without using valuable global routing resources. MegaLAB structures connected FastTrack® Interconnect continuous routing structure fast, predictable delays.
Embedded System Block Configuration
embedded system block heart MultiCore architecture. 2,048 programmable bits each APEX configured product-term logic, logic, three types memory: dual-port RAM, ROM, content-addressable memory (CAM). Configuring product-term logic provides powerful level integration that ideal control logic functions such address decoders complex state machines. integrating product-term logic into single device, APEX devices assure maximum efficiency optimum performance both types functions.
Embedded System Block (ESB)
Product Term Dual-Port
Features
LVDS GTL+ SSTL-3/-2 HSTL MultiVoltI/O LVTTL LVCMOS
Clock Management
PLLs ClockShiftCircuitry ClockBoostCircuitry ClockLockCircuitry
Altera Corporation
APEX Devices
Device
EP20K60E
Gates
60,000
Pin/Package Options
144-Pin TQFP, 196-Pin FBGA1, 208-Pin PQFP, 240-Pin PQFP, 324-Pin FBGA1, 356-Pin
Pins
143, 151, 183, 204, 101, 149, 159, 189, 252, 143, 151, 183, 246, 143, 175, 273, 144, 174, 279, 136, 168, 273, 376, 376, 120, 152, 408, 502, 502, 504, 498, 508, 483, 508, 716, 483, 716,
Supply Voltage
Logic Elements
2,560
Bits
32,768
Macrocells
EP20K100
100,000
144-Pin TQFP, 196-Pin FBGA1, 208-Pin PQFP, 240-Pin PQFP, 324-Pin FBGA1, 356-Pin
4,160
53,248
EP20K100E
100,000
144-Pin TQFP, 196-Pin FBGA1 208-Pin PQFP, 240-Pin PQFP, 324-Pin FBGA1, 356-Pin
4,160
53,248
EP20K160E
160,000
144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 356-Pin BGA, 484-Pin FBGA1
6,400
81,920
EP20K200 EP20K200E
200,000 200,000
208-Pin RQFP, 240-Pin RQFP, 356-Pin BGA, 484-Pin FBGA1 208-Pin PQFP, 240-Pin PQFP, 356-Pin BGA, 484-Pin FBGA1, 652-Pin BGA, 672-Pin FBGA1
8,320 8,320
106,496 106,496
EP20K300E EP20K400 EP20K400E EP20K600E EP20K1000E EP20K1500E
300,000 400,000 400,000 600,000 1,000,000 1,500,000
208-Pin RQFP, 240-Pin RQFP, 652-Pin BGA, 672-Pin FBGA1 652-Pin BGA, 655-Pin PGA, 672-Pin FBGA1 652-Pin BGA, 672-Pin FBGA1 652-Pin BGA, 672-Pin FBGA1, 1020-Pin FBGA1 652-Pin BGA, 672-Pin FBGA1, 984-Pin PGA, 1020-Pin FBGA1 652-Pin BGA, 984-Pin PGA, 1020-Pin FBGA1
11,520 16,640 16,640 24,320 38,400 54,720
147,456 212,992 212,992 311,296 327,680 466,944
1,152 1,664 1,664 2,432 2,560 3,648
Space-saving FineLine BGApackage. Preliminary. Contact Altera latest information.
Embedded Dual-Port
APEX supports dual-port with independent read/write ports, synchronous asynchronous operation, 161-MHz FIFO performance wide range widths depths (128 1,024 2,048 APEX also supports 161-MHz cache performance, performance over MHz. Multiple ESBs combined build wider deeper memories.
Each configured 32-word 32-bit CAM, ESBs cascaded build larger CAMs. integrated APEX 20KE devices offers considerable gains system performance configuration flexibility relative discrete solutions.
High-Bandwidth, Low-Voltage
demand higher system performance lower supply voltages growing. APEX 20KE devices support multiple interfacing standards, including LVTTL, LVCMOS, GTL+, SSTL-3/2, HSTL, AGP, CTT, well LVDS with performance Mbits second. APEX devices support Altera MultiVoltI/O interface, which ideal mixed-voltage systems.
High-Performance
Within APEX 20KE devices, also configured CAM, parallel processing memory that facilitates fast address search functions. operates like reverse RAM: while receives address input supplies data output, receives data input supplies address that contains input data. commonly used data communication applications. Because APEX 20KE functions high-speed parallel comparator, opens many applications designs.
Applications
Address translation Cache tagging filter address look-up Packet header identification Pattern recognition Switch address mapping VPI/VCI translation Aswitches
Enhanced Phase-Locked Loop
increase system clock rates, APEX 20KE devices feature four phase-locked loops (PLLs) with enhanced ClockLockTM, ClockBoostTM, ClockShiftcircuitry. ClockLock circuitry uses synchronizing with extended frequency range that reduces clock delay skew within device. ClockBoost circuitry provides clock multiplier that allows designer distribute low-speed clock multiply that clock device. ClockBoost circuitry also allows resource-sharing within device enhances device area efficiency. ClockShift circuitry provides programmable clock delay phase-shift capability.
Altera Corporation
Flexible Migration with FineLine Packages
APEX devices offered variety packages including space-saving FineLine BGApackages. These 1.0-mm pitch, ball-grid array packages offer designers level efficiency packaging flexibility. innovative SameFramepin-out feature FineLine packages offers footprint compatibility between packages different counts. This layout feature permits easy migration from FineLine package another without need re-layout board.
SameFrame Pin-out Example
SignalTap Logic Analysis Tool
Download Cable Quartus Software
software provides integrated logic analysis functionality (SignalTapanalysis), incremental recompilation (nSTEPCompiler), workgroup computing, tool integration, multi-processor support, intellectual property integration. Quartus Compiler analyzes design partitions functions into appropriate type LUT-based logic element, product-term based macrocell, embedded memory logic block within APEX architecture. Compiler then uses Altera's CoreSynsynthesis capability invokes appropriate synthesis technology optimize logic that architecture. Other features Quartus software, such nSTEP incremental recompilation multi-processor support, also help shorten design cycles.
Printed Circuit Board Designed 484-Pin Package
324-Pin FineLine
484-Pin FineLine
324-Pin FineLine Package (Reduced Count Logic Requirements)
484-Pin FineLine Package (Increased Count Logic Requirements)
FineLine packages feature SameFrame pin-out, allowing easy migration from FineLine package another.
Contact Altera Today
APEX device family provides completely level capability offers platform Systemon-a-Programmable-Chip applications. revolutionary three-in-one MultiCore architecture brings together power logic, product-term logic, embedded memory system-level integration. Call Altera today learn more about this multi-million-gate programmable logic family visit Altera world-wide site http://www.altera.com.
Quartus Development Software Intellectual Property Simplify Design
Programmable logic designs that require density features APEX family also need fast, powerful, efficient, easy-to-use design software. Altera's Quartusdevelopment system allows designers process multi-million gate designs using advanced features never before seen development tools. Quartus
Altera Offices
Altera Corporation Innovation Drive Jose, 95134 Telephone: (408) 544-7000 http://www.altera.com Altera U.K., Ltd. Holmers Farm High Wycombe Buckinghamshire HP12 United Kingdom Telephone: (44) Altera Japan, Ltd. Shinjuku Mitsui Bldg. 1-1, Nishi-Shinjuku, Chome Shinjuku-ku, Tokyo 163-0436 Japan Telephone: (81) 3340 9480 http://www.altera.com/japan Altera International, Ltd. Suites 908-920, Tower MetroPlaza Hing Fong Road Kwai Fong, Territories Hong Kong Telephone: (852) 2487 2030
Copyright 1999 Altera Corporation. Altera, APEX, APEX 20K, APEX 20KE, ClockLock, ClockBoost, ClockShift, CoreSyn, FastTrack, FineLine BGA, FLEX, FLEX 10K, FLEX 10KE, FLEX 6000, MAX, 7000, MegaCore, MegaLAB, MultiCore, MultiVolt, nSTEP, Quartus, SameFrame, SignalTap, System-on-a-Programmable-Chip, SOPC, specific device designations trademarks and/or service marks Altera Corporation United States other countries. Other brands products trademarks their respective holders. specifications contained herein subject change without notice. rights reserved. M-GB-APEX20K-02
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