Programmable Logic Device Family November 1999, ver. 2.05 Fe
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APEX
Programmable Logic Device Family
November 1999, ver. 2.05
Features.
Preliminary Information
Industry's first programmable logic device (PLD) incorporating MultiCorearchitecture integrating look-up table (LUT) logic, product-term logic, embedded memory Embedded system block (ESB) implementation product-term logic used combinatorial-intensive functions logic used register-intensive functions used implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, contentaddressable memory (CAM) High density 60,000 million typical gates (see Table 51,840 logic elements (LEs) 442,368 bits that used without reducing available logic 3,456 product-term-based macrocells
Table APEX Device Features
Feature
Maximum system gates Typical gates ESBs Maximum bits Maximum macrocells Maximum user pins Notes:
Notes
EP20K600E EP20K1000E EP20K1500E
EP20K60E EP20K100E EP20K160E EP20K200E EP20K300E EP20K400E EP20K100 EP20K200 EP20K400
162,000 263,000
404,000
526,000
728,000 1,052,000 1,537,000 1,771,520 2,391,552
60,000 2,560 32,768
100,000 4,160 53,248
160,000 6,400 81,920
200,000 8,320 106,496
300,000 11,520 147,456 1,152
400,000 16,640 212,992 1,664
600,000 24,320 311,296 2,432
1,000,000 1,500,000 38,400 327,680 2,560 51,840 442,368 3,456
embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes 57,000 additional gates.
Altera Corporation
A-DS-APEX20K-02.05
APEX Programmable Logic Device Family
Preliminary Information
.and More Features
Designed low-power operation 1.8-V 2.5-V supply voltage (see Table MultiVoltI/O interface support interface with 1.8-V, 2.5-V, 3.3-V devices (see Table offering programmable power-saving mode Flexible clock management circuitry with phase-locked loop (PLL) Built-in low-skew clock tree eight global clock signals ClockLockfeature reducing clock delay skew ClockBoostfeature providing clock multiplication division ClockShiftprogrammable clock phase delay shifting Powerful features Compliant with peripheral component interconnect Special Interest Group (PCI SIG) Local Specification, Revision 3.3-V operation bits Bidirectional performance (tCO tSU) Direct connection from pins local interconnect providing fast times complex logic MultiVolt interface support interface with 1.8-V, 2.5-V, 3.3-V devices (see Table Programmable clamp VCCIO Individual tri-state output enable control each Programmable output slew-rate control reduce switching noise Support advanced standards, including low-voltage differential signaling (LVDS), stub-series terminated logic (SSTL-3 SSTL-2), Gunning transceiver logic plus (GTL+) Supports hot-socketing operation Pull-up pins before during configuration
Table APEX Supply Voltages
Feature EP20K100 EP20K200 EP20K400 EP20K60E EP20K100E EP20K160E EP20K200E EP20K300E EP20K400E EP20K600E EP20K1000E EP20K1500E
Internal supply voltage (VCCINT) MultiVolt interface voltage levels (VCCIO)
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Advanced interconnect structure Four-level hierarchical FastTrack® Interconnect structure providing fast, predictable interconnect delays Dedicated carry chain that implements arithmetic functions such fast adders, counters, comparators (automatically used software tools megafunctions) Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used software tools megafunctions) Interleaved local interconnect allows drive other through fast local interconnect Advanced packaging options Available variety packages with 1,020 pins (see Tables through FineLine BGApackages maximize board space efficiency SameFramepin migration providing migration capability across device densities package sizes Advanced software support Software design support automatic place-and-route provided Altera® Quartusdevelopment system Windows-based PCs, SPARCstations, 9000 Series 700/800 workstations Altera MegaCorefunctions Altera Megafunction Partners Program (AMPPSM) megafunctions NativeLinkintegration with popular synthesis, simulation, timing analysis tools Quartus SignalTapembedded logic analyzer simplifies in-system design evaluation giving access internal nodes during device operation Supports popular revision-control software packages including PVCS, RCS, SCCS
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table APEX QFP, Package Options Count
Device 144-Pin TQFP
Notes (1), (2),
652-Pin 655-Pin 984-Pin
208-Pin PQFP RQFP
240-Pin PQFP RQFP
356-Pin
EP20K60E EP20K100 EP20K100E EP20K160E EP20K200 EP20K200E EP20K300E EP20K400 EP20K400E EP20K600E EP20K1000E EP20K1500E
Table APEX FineLine Package Options Count
Device
EP20K60E EP20K100 EP20K100E EP20K160E EP20K200 EP20K200E EP20K300E EP20K400 EP20K400E EP20K600E EP20K1000E EP20K1500E
1,020
Altera Corporation
Preliminary Information Notes tables:
APEX Programmable Logic Device Family
Contact Altera up-to-date information package availability. counts include dedicated input clock pins. APEX device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), 1.27-mm pitch ball-grid array (BGA), 1.00-mm pitch FineLine BGA, pin-grid array (PGA) packages. FineLine packages, except 196-pin 1,020-pin packages, footprint-compatible SameFrame pin-out. Therefore, designers design board support variety devices, providing flexible migration path across densities counts. Device migration fully supported Altera development tools. "SameFrame Pin-Outs" page more information. This device uses thermally enhanced package, which taller than regular package. Consult Altera Device Package Information Data Sheet detailed package size information.
Table APEX QFP, Package Sizes
Feature
Pitch (mm) Area (mm2) Length Width
144-Pin TQFP 208-Pin 240-Pin 356-Pin 652-Pin 655-Pin
0.50 0.50 30.6 30.6 0.50 1,197 34.6 34.6 1.27 1,225 1.27 2,025 3,906 62.5 62.5
Table APEX FineLine Package Sizes
Feature
Pitch (mm) Area (mm2) Length Width
1.00
1.00
1.00
1.00
1,020
1.00 1,089
General Description
APEX devices first PLDs designed with MultiCore architecture, which combines strengths LUT-based productterm-based devices with enhanced memory structure. LUT-based logic provides optimized performance efficiency data-path, registerintensive, mathematical, digital signal processing (DSP) designs. Product-term-based logic optimized complex combinatorial paths, such complex state machines. LUT- product-term-based logic combined with memory functions wide variety MegaCore AMPP functions make APEX architecture uniquely suited System-on-a-Programmable-Chip designs. Applications historically requiring combination LUT-, product-term-, memory-based devices integrated into APEX device.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
APEX 20KE devices superset APEX devices include additional features such advanced standard support, CAM, additional global clocks, enhanced ClockLock clock circuitry. addition, APEX 20KE devices extend APEX family over million gates. APEX 20KE devices denoted with suffix device name (e.g., EPF20K1000E APEX 20KE device). Table summarizes features included APEX APEX 20KE devices.
Table Comparison APEX APEX 20KE Features
Feature
MultiCore system integration Hot-socketing support SignalTap logic analysis 64-Bit, 66-MHz MultiVolt ClockLock support
APEX Devices
Full support Full support Full support Full compliance 2.5-V 3.3-V VCCIO VCCIO selected device Clock delay reduction clock multiplication
APEX 20KE Devices
Full support Full support Full support Full compliance 1.8-V, 2.5-V, 3.3-V VCCIO VCCIO selected block-by-block Clock delay reduction clock multiplication Drive ClockLock output off-chip External clock feedback LVDS support Eight 1.8-V 2.5-V 3.3-V 3.3-V Advanced Graphics Port (AGP) Center terminated (CTT) GTL+ LVCMOS LVDS data pins EP20K300E larger devices) LVDS clock pins devices) LVTTL SSTL-2 Class SSTL-3 Class Dual-port FIFO
Dedicated clock input pins standard support 2.5-V 3.3-V Low-voltage complementary metal-oxide semiconductor (LVCMOS) Low-voltage transistor-to-transistor logic (LVTTL)
Memory support
Dual-port FIFO
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
APEX devices reconfigurable 100% tested prior shipment. result, test vectors have generated fault coverage purposes. Instead, designer focus simulation design verification. addition, designer does need manage inventories different application-specific integrated circuit (ASIC) designs; APEX devices configured board specific functionality required. APEX devices configured system power-up with data stored Altera serial configuration device provided system controller. Altera offers in-system programmability (ISP)-capable EPC2 configuration devices, which configure APEX devices serial data stream. Moreover, APEX devices contain optimized interface that permits microprocessors configure APEX devices serially parallel, synchronously asynchronously. interface also enables microprocessors treat APEX devices memory configure device writing virtual memory location, making reconfiguration easy. Contact Altera information future configuration devices.
After APEX device been configured, reconfigured in-circuit resetting device loading data. Real-time changes made during system operation, enabling innovative reconfigurable computing applications. APEX devices supported Altera's Quartus development system, single, integrated package that offers schematic design entry, compilation logic synthesis, full simulation worst-case timing analysis, SignalTap logic analysis, device configuration. Quartus software runs Windows-based PCs, SPARCstations, 9000 Series 700/800 workstations. Quartus software provides NativeLink interfaces other industrystandard UNIX workstation-based tools. example, designers invoke Quartus software from within third-party design tools. Further, Quartus software contains built-in optimized synthesis libraries; synthesis tools these libraries optimize designs APEX devices. example, Synopsys Design Compiler library, supplied with Quartus development system, includes DesignWare functions optimized APEX architecture.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Functional Description
APEX devices incorporate LUT-based logic, product-term-based logic, memory into device. Signal interconnections within APEX devices well from device pins) provided FastTrack Interconnect-a series fast, continuous column channels that entire length width device. Each element (IOE) located each column FastTrack Interconnect. Each contains bidirectional buffer register that used either input output register feed input, output, bidirectional signals. When used with dedicated clock pin, these registers provide exceptional performance. IOEs provide variety features, such 3.3-V, 64-bit, 66-MHz compliance; JTAG support; slew-rate control; tri-state buffers. APEX 20KE devices offer enhanced support, including support 1.8-V I/O, 2.5-V I/O, LVCMOS, LVTTL, 3.3-V PCI, LVDS, GTL+, SSTL-2, SSTL-3, CTT, 3.3-V standards. implement variety memory functions, including CAM, RAM, dual-port RAM, ROM, FIFO functions. Embedding memory directly into improves performance reduces area compared distributed-RAM implementations. Moreover, abundance cascadable ESBs ensures that APEX device implement multiple wide memory blocks high-density designs. ESB's high speed ensures implement small memory blocks without speed penalty. abundance ESBs ensures that designers create many different-sized memory blocks system requires. Figure shows overview APEX device.
Figure APEX Device Block Diagram
Clock Management Circuitry
ClockLock
FastTrack Interconnect
Four-input data path functions. Product-term integration high-speed control logic state machines.
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
Product Term Memory
IOEs support PCI, GTL+, SSTL-3, LVDS, other standards.
Flexible integration embedded memory, including CAM, RAM, ROM, FIFO functions.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
APEX devices provide dedicated clock pins four dedicated input pins that drive register control inputs. These signals ensure efficient distribution high-speed, low-skew control signals. These signals dedicated routing channels provide short delays skews. Four dedicated inputs drive four global signals. These four global signals also driven internal logic, providing ideal solution clock divider internally generated asynchronous clear signals with high fan-out. APEX devices also include ClockLock ClockBoost clock management circuitry. APEX 20KE devices provide additional dedicated clock pins, total four dedicated clock pins.
MegaLAB Structure
APEX devices constructed from series MegaLABstructures. Each MegaLAB structure contains logic array blocks (LABs), ESB, MegaLAB interconnect, which routes signals within MegaLAB structure. EP20K1000E EP20K1500E devices, MegaLAB structures contain LABs. Signals routed between MegaLAB structures pins FastTrack Interconnect. addition, edge LABs drive pins through local interconnect. Figure shows MegaLAB structure.
Figure MegaLAB Structure
MegaLAB Interconnect
Adjacent IOEs
LE10
LE10
LE10
Local Interconnect
LABs
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Logic Array Block
Each consists LEs, LEs' associated carry cascade chains, control signals, local interconnect. local interconnect transfers signals between same adjacent LABs, IOEs, ESBs. Quartus Compiler places associated logic within adjacent LABs, allowing fast local interconnect high performance. Figure shows APEX LAB. APEX devices interleaved structure. This structure allows each drive local interconnect areas. This feature minimizes MegaLAB FastTrack interconnect, providing higher performance flexibility. Each drive other through fast local interconnect.
Figure Structure
Interconnect
MegaLAB Interconnect drive local MegaLAB, row, column interconnects.
To/From Adjacent LAB, ESB, IOEs To/From Adjacent LAB, ESB, IOEs
Local Interconnect
Column Interconnect driven local interconnect areas. These drive local interconnect areas.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Each contains dedicated logic driving control signals LEs. control signals include clock, clock enable, asynchronous clear, asynchronous preset, asynchronous load, synchronous clear, synchronous load signals. maximum control signals used time. Although synchronous load clear signals generally used when implementing counters, they also used with other functions. Each clocks clock enable signals. Each LAB's clock clock enable signals linked (e.g., particular using CLK1 will also CLKENA1). with same clock different clock enable signals either both clock signals placed into separate LABs. both rising falling edges clock used LAB, both LAB-wide clock signals used. LAB-wide control signals generated from local interconnect, global signals, dedicated clock pins. inherent skew FastTrack Interconnect enables used clock distribution. Figure shows control signal generation circuit.
Figure Control Signal Generation
Dedicated Clocks Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect SYNCLOAD LABCLKENA2 SYNCCLR LABCLK2 LABCLKENA1 LABCLR1
LABCLK1
LABCLR2
Notes:
APEX 20KE devices have four dedicated clocks. LABCLR1 LABCLR2 signals also control asynchronous load asynchronous preset within LAB. SYNCCLR signal generated local interconnect global signals.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Logic Element
smallest unit logic APEX architecture, compact provides efficient logic usage. Each contains four-input LUT, which function generator that quickly implement function four variables. addition, each contains programmable register carry cascade chains. Each drives local interconnect, MegaLAB interconnect, FastTrack Interconnect routing structures. Figure
Figure APEX Logic Element
Register Bypass
LAB-wide LAB-wide Synchronous Synchronous Load Clear Cascade-In
Carry-In
Packed Register Select Programmable Register
FastTrack Interconnect, MegaLAB Interconnect, Local Interconnect
data1 data2 data3 data4
Look-Up Table (LUT)
Carry Chain
Cascade Chain
Synchronous Load Clear Logic
CLRN FastTrack Interconnect, MegaLAB Interconnect, Local Interconnect
labclr1 labclr2 Chip-Wide Reset
Asynchronous Clear/Preset/ Load Logic
Clock Clock Enable Select labclk1 labclk2
labclkena1 labclkena2 Carry-Out Cascade-Out
Each LE's programmable register configured operation. register's clock clear control signals driven global signals, general-purpose pins, internal logic. combinatorial functions, register bypassed output drives outputs
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
outputs that drive local, MegaLAB, FastTrack Interconnect routing structure. Each output driven independently LUT's register's output. example, drive output while register drives other output. This feature, called register packing, improves device utilization because register used unrelated functions. also drive registered unregistered versions output. APEX architecture provides types dedicated high-speed data paths that connect adjacent without using local interconnect paths: carry chains cascade chains. carry chain supports high-speed arithmetic functions such counters adders, while cascade chain implements wide-input functions such equality comparators with minimum delay. Carry cascade chains connect through LABs same MegaLAB structure.
Carry Chain
carry chain provides very fast carry-forward function between LEs. carry-in signal from lower-order drives forward into higherorder carry chain, feeds into both next portion carry chain. This feature allows APEX architecture implement high-speed counters, adders, comparators arbitrary width. Carry chain logic created automatically Quartus Compiler during design processing, manually designer during design entry. Parameterized functions such library parameterized modules (LPM) DesignWare functions automatically take advantage carry chains appropriate functions. Quartus Compiler creates carry chains longer than linking LABs together automatically. enhanced fitting, long carry chain skips alternate LABs MegaLAB structure. carry chain longer than skips either from even-numbered next evennumbered LAB, from odd-numbered next oddnumbered LAB. example, last first upper-left MegaLAB structure carries first third MegaLAB structure. Figure shows n-bit full adder implemented with carry chain. portion generates bits using input signals carry-in signal; routed output register bypassed simple adders used accumulator functions. Another portion carry chain logic generates carry-out signal, which routed directly carry-in signal next-higher-order bit. final carry-out signal routed where driven onto local, MegaLAB, FastTrack Interconnect routing structures.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure APEX Carry Chain
Carry-In
Register
Carry Chain
Register
Carry Chain
Register
Carry Chain
Register
Carry-Out
Carry Chain
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Cascade Chain
With cascade chain, APEX architecture implement functions with very wide fan-in. Adjacent LUTs compute portions function parallel; cascade chain serially connects intermediate values. cascade chain logical logical (via Morgan's inversion) connect outputs adjacent LEs. Each additional provides four more inputs effective width function, with short cascade delay. Cascade chain logic created automatically Quartus Compiler during design processing, manually designer during design entry. Cascade chains longer than implemented automatically linking LABs together. enhanced fitting, long cascade chain skips alternate LABs MegaLAB structure. cascade chain longer than skips either from even-numbered next even-numbered LAB, from odd-numbered next odd-numbered LAB. example, last first upper-left MegaLAB structure carries first third MegaLAB structure. Figure shows cascade function connect adjacent form functions with wide fan-in.
Figure APEX Cascade Chain
Cascade Chain Cascade Chain
d[3.0]
d[3.0]
d[7.4]
d[7.4]
d[(4n 1).(4n
d[(4n 1).(4n
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Operating Modes
APEX operate following three modes:
Normal mode Arithmetic mode Counter mode
Each mode uses resources differently. each mode, seven available inputs LE-the four data inputs from local interconnect, feedback from programmable register, carry-in cascade-in from previous LE-are directed different destinations implement desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset, asynchronous load, synchronous clear, synchronous load, clock enable control register. These LAB-wide signals available modes. Quartus software, conjunction with parameterized functions such DesignWare functions, automatically chooses appropriate mode common functions such counters, adders, multipliers. required, designer also create special-purpose functions that specify which operating mode optimal performance. Figure shows operating modes.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Figure APEX Operating Modes
Normal Mode
Carry-In data1 data2 data3 data4 4-Input
LAB-Wide Clock Enable Cascade-In LE-Out
LE-Out
CLRN
Cascade-Out
Arithmetic Mode
Carry-In Cascade-In
LAB-Wide Clock Enable LE-Out
data1 data2
3-Input 3-Input Carry-Out
LE-Out
CLRN
Cascade-Out
Counter Mode
Cascade-In Carry-In
LAB-Wide Synchronous Load
LAB-Wide Synchronous Clear LAB-Wide Clock Enable LE-Out
data1 data2 data3 (data) 3-Input Carry-Out Cascade-Out
3-Input
LE-Out
CLRN
Notes:
normal mode support register packing. There LAB-wide clock enables LAB. When using carry-in normal mode, packed register feature unavailable. register feedback multiplexer available each LAB. DATA1 DATA2 input signals supply counter enable, down control, register feedback signals other than second LAB. LAB-wide synchronous clear wide synchronous load affect registers LAB.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Normal Mode normal mode suitable general logic applications, combinatorial functions, wide decoding functions that take advantage cascade chain. normal mode, four data inputs from local interconnect carry-in inputs four-input LUT. Quartus Compiler automatically selects carry-in DATA3 signal inputs LUT. output combined with cascade-in signal form cascade chain through cascade-out signal. normal mode support packed registers. Arithmetic Mode arithmetic mode ideal implementing adders, accumulators, comparators. arithmetic mode uses 3-input LUTs. computes three-input function; other generates carry output. shown Figure first uses carry-in signal data inputs from local interconnect generate combinatorial registered output. example, when implementing adder, this output three signals: DATA1, DATA2, carry-in. second uses same three signals generate carry-out signal, thereby creating carry chain. arithmetic mode also supports simultaneous cascade chain. arithmetic mode drive registered unregistered versions output. Quartus software implements parameterized functions that arithmetic mode automatically where appropriate; designer does need specify carry chain will used. Counter Mode counter mode offers clock enable, counter enable, synchronous up/down control, synchronous clear, synchronous load options. counter enable synchronous up/down control signals generated from data inputs local interconnect. synchronous clear synchronous load options LAB-wide signals that affect registers LAB. Consequently, counter mode, other that must used part same counter used combinatorial function. Quartus software automatically places registers that used counter into other LABs.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
counter mode uses three-input LUTs: generates counter data, other generates fast carry bit. 2-to-1 multiplexer provides synchronous loading, another gate provides synchronous clearing. cascade function used counter mode, synchronous clear load overrides signal carried cascade chain. synchronous clear overrides synchronous load. arithmetic mode drive registered unregistered versions output.
Clear Preset Logic Control
Logic register's clear preset signals controlled LAB-wide signals. directly supports asynchronous clear function. Quartus Compiler NOT-gate push-back technique emulate asynchronous preset. Moreover, Quartus Compiler programmable NOT-gate push-back technique emulate simultaneous preset clear asynchronous load. However, this technique uses three additional register. emulation performed automatically when design compiled. Registers that emulate simultaneous preset load will enter unknown state upon power-up when chipwide reset asserted. addition clear preset modes, APEX devices provide chip-wide reset (DEV_CLRn) that resets registers device. this controlled through option Quartus software that before compilation. chip-wide reset overrides other control signals. Registers using asynchronous preset preset when chip-wide reset asserted; this effect results from inversion technique used implement asynchronous preset.
FastTrack Interconnect
APEX architecture, connections between LEs, ESBs, pins provided FastTrack Interconnect. FastTrack Interconnect series continuous horizontal vertical routing channels that traverse device. This global routing structure provides predictable performance, even complex designs. contrast, segmented routing FPGAs requires switch matrices connect variable number routing paths, increasing delays between logic resources reducing performance. FastTrack Interconnect consists column interconnect channels that span entire device. interconnect routes signals throughout MegaLAB structures; column interconnect routes signals throughout column MegaLAB structures. When using column interconnect, IOE, drive other IOE, device. Figure
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure APEX Interconnect Structure
Interconnect
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
MegaLAB
Column Interconnect
Column Interconnect
MegaLAB
MegaLAB
MegaLAB
MegaLAB
line driven directly LEs, IOEs, ESBs that row. Further, column line drive line, allowing IOE, drive elements different column interconnect. interconnect drives MegaLAB interconnect drive LEs, IOEs, ESBs particular MegaLAB structure. column line directly driven LEs, IOEs, ESBs that column. column line device's left right edge also driven IOEs. column line used route signals from another. column line drive line; also drive MegaLAB interconnect directly, allowing faster connections between rows. Figure shows FastTrack Interconnect uses local interconnect drive within MegaLAB structures.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Figure FastTrack Connection Local Interconnect
MegaLAB MegaLAB Column
Column Interconnect Drives MegaLAB Interconnect
MegaLAB Interconnect
MegaLAB Interconnect Drives Local Interconnect
Column
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure shows intersection column interconnect, these forms interconnects drive each other.
Figure Driving FastTrack Interconnect
Interconnect
MegaLAB Interconnect
Column Interconnect
Local Interconnect
APEX 20KE devices include enhanced interconnect structure faster routing input signals with high fan-out. Column pins drive FastRow interconnect, which routes signals directly into local interconnect without having drive through MegaLAB interconnect. FastRow lines traverse MegaLAB structures. Also, these pins drive local interconnect directly fast setup times. EP20K300E larger devices, FastRow interconnect drives MegaLABs left corner MegaLABs bottom right corner. EP20K200E smaller devices, FastRow interconnect drives MegaLABs MegaLABs bottom device. devices, FastRow interconnect drives local interconnect appropriate MegaLABs except interconnect areas left right MegaLAB. Figure shows FastRow interconnect.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Figure APEX 20KE FastRow Interconnect
FastRow Interconnect
FastRow Interconnect Drives Local Interconnect MegaLAB Structures
Select Vertical Pins Drive Local Interconnect FastRow Interconnect
Local Interconnect
MegaLAB
LABs
MegaLAB
Table summarizes various elements APEX architecture drive each other.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table APEX Routing Scheme
Source
Column Column Local Interconnect MegaLAB Interconnect FastTrack Interconnect Column FastTrack Interconnect FastRow Interconnect Note:
This connection supported APEX 20KE devices only.
Destination
Local MegaLAB Interconnect Interconnect Column FastRow FastTrack FastTrack Interconnect Interconnect Interconnect
Product-Term Logic
product-term portion MultiCore architecture implemented with ESB. configured block macrocells ESB-by-ESB basis. Each inputs from adjacent local interconnect; therefore, driven MegaLAB interconnect adjacent LAB. Also, nine macrocells feed back into through local interconnect higher performance. Dedicated clock pins, global signals, additional inputs from local interconnect drive control signals. product-term mode, each contains macrocells. Each macrocell consists product terms programmable register. Figure shows product-term mode.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Figure Product-Term Logic
Dedicated Clocks Global Signals
MegaLAB Interconnect
Macrocell Inputs (1-16) CLK[1.0] ENA[1.0] CLRN[1.0] Column Interconnect
From Adjacent
Local Interconnect
Note:
APEX 20KE devices have four dedicated clocks.
Macrocells
APEX macrocells configured individually either sequential combinatorial logic operation. macrocell consists three functional blocks: logic array, product-term select matrix, programmable register. Combinatorial logic implemented product terms. productterm select matrix allocates these product terms either primary logic inputs gates) implement combinatorial functions, parallel expanders used increase logic available another macrocell. product term inverted: Quartus software uses this feature perform DeMorgan's inversion more efficient implementation wide functions. Quartus Compiler NOT-gate push-back technique emulate asynchronous preset. Figure shows APEX macrocell.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure APEX Macrocell
ESB-Wide ESB-Wide ESB-Wide Clears Clock Enables Clocks Parallel Logic Expanders (From Other Macrocells)
Programmable Register
ProductTerm Select Matrix
Output
Clock/ Enable Select
CLRN
Signals from Local Interconnect
Clear Select
registered functions, each macrocell register programmed individually implement operation with programmable clock control. register bypassed combinatorial operation. During design entry, designer specifies desired register type; Quartus software then selects most efficient register operation each registered function optimize resource utilization. Quartus software other synthesis tools also select most efficient register operation automatically when synthesizing designs. Each programmable register clocked ESB-wide clocks. ESB-wide clocks generated from device dedicated clock pins, global signals, local interconnect. Each clock also associated clock enable, generated from local interconnect. clock clock enable signals related particular ESB; macrocell using clock also uses associated clock enable. both rising falling edges clock used ESB, both ESB-wide clock signals used.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
programmable register also supports asynchronous clear function. Within ESB, asynchronous clears generated from global signals local interconnect. Each macrocell either choose between asynchronous clear signals choose cleared. Either clear signals inverted within ESB. Figure shows control logic when implementing product-terms.
Figure Product-Term Mode Control Logic
Dedicated Clocks Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect
CLK2
CLKENA2
CLK1
CLKENA1 CLR2
CLR1
Note:
APEX 20KE devices have four dedicated clocks.
Parallel Expanders
Parallel expanders unused product terms that allocated neighboring macrocell implement fast, complex logic functions. Parallel expanders allow product terms feed macrocell logic directly, with product terms provided macrocell parallel expanders provided neighboring macrocells ESB. Quartus Compiler allocate sets parallel expanders macrocells automatically. Each parallel expanders incurs small, incremental timing delay. Figure shows APEX parallel expanders.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure APEX Parallel Expanders
From Previous Macrocell
ProductTerm Select Matrix
Macrocell ProductTerm Logic Parallel Expander Switch
ProductTerm Select Matrix
Macrocell ProductTerm Logic Parallel Expander Switch
Signals from Local Interconnect
Next Macrocell
Embedded System Block
implement various types memory blocks, including dual-port RAM, ROM, FIFO, blocks. includes input output registers; input registers synchronize writes, output registers pipeline designs improve system performance. offers dual-port mode, which supports simultaneous reads writes different clock frequencies. Figure shows block diagram.
Figure Block Diagram
wraddress[] data[] wren inclock inclocken inaclr rdaddress[] rden outclock outclocken outaclr
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
ESBs implement synchronous RAM, which easier than asynchronous RAM. circuit using asynchronous must generate write enable (WE) signal, while ensuring that data address signals meet setup hold time specifications relative signal. contrast, ESB's synchronous generates signal self-timed with respect global clock. Circuits using ESB's selftimed must only meet setup hold time specifications global clock. inputs driven adjacent local interconnect, which turn driven MegaLAB FastTrack Interconnect. Because driven local interconnect, adjacent drive directly fast memory access. outputs drive MegaLAB FastTrack Interconnect. addition, outputs, nine which unique output lines, drive local interconnect fast connection adjacent fast feedback product-term logic. When implementing memory, each configured following sizes: 1,024 2,048 combining multiple ESBs, Quartus software implements larger memory blocks automatically. example, blocks combined form block, blocks combined form block. Memory performance does degrade memory blocks 2,048 words deep. Each implement 2,048-word-deep memory; ESBs used parallel, eliminating need external control logic associated delays. create high-speed memory block that more than 2,048 words deep, ESBs drive tri-state lines. Each tri-state line connects ESBs column MegaLAB structures, drives MegaLAB interconnect column FastTrack Interconnect throughout column. Each incorporates programmable decoder activate tri-state driver appropriately. instance, implement 8,192-word-deep memory, four ESBs used. Eleven address lines drive memory, more drive tri-state decoder. Depending which 2,048-word memory page selected, appropriate driver turned driving output tri-state line. Quartus software automatically combines ESBs with tri-state lines form deeper memory blocks. internal tri-state control logic designed avoid internal contention floating lines. Figure
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure Deep Memory Block Implemented with Multiple ESBs
Address Decoder
System Logic
implements forms dual-port memory: read/write clock mode input/output clock mode. also used bidirectional, dual-port memory applications which ports read write simultaneously. implement this type dual-port memory, ESBs used support simultaneous reads writes. also Altera megafunctions implement dual-port applications where both ports read write, shown Figure
Figure APEX Implementing Dual-Port
Port address_a[] data_a[] we_a clkena_a Clock Port address_b[] data_b[] we_b clkena_b Clock
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Preliminary Information
APEX Programmable Logic Device Family
Read/Write Clock Mode
read/write clock mode contains clocks. clock controls registers associated with writing: data input, write address. other clock controls registers associated with reading: read enable (RE), read address, data output. also supports clock enable asynchronous clear signals; these signals also control read write registers independently. Read/write clock mode commonly used applications where reads writes occur different system frequencies. Figure shows read/write clock mode.
Figure Read/Write Clock Mode
Dedicated Inputs Global Signals Dedicated Clocks
Note
data[
RAM/ROM Data 1,024 2,048 Data
MegaLAB, FastTrack Local Interconnect
rdaddress[
Read Address
wraddress[
Write Address
rden
Read Enable
wren
outclocken
Write Enable
inclocken
inclock
Write Pulse Generator
outclock
Notes:
registers cleared asynchronously local interconnect signals, global signals, chip-wide reset. APEX 20KE devices have four dedicated clocks.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Input/Output Clock Mode
input/output clock mode contains clocks. clock controls registers inputs into ESB: data input, read address, write address. other clock controls data output registers. also supports clock enable asynchronous clear signals; these signals also control reading writing registers independently. Input/output clock mode commonly used applications where reads writes occur same system frequency, require different clock enable signals input output registers. Figure shows input/output clock mode.
Figure Input/Output Clock Mode
Dedicated Inputs Global Signals Dedicated Clocks
Note
data[
RAM/ROM Data 1,024 2,048 Data
MegaLAB, FastTrack Local Interconnect
rdaddress[
Read Address
wraddress[
Write Address
rden
Read Enable
wren
outclken
Write Enable
inclken
inclock
Write Pulse Generator
outclock
Notes:
registers cleared asynchronously local interconnect signals, global signals, chip-wide reset. APEX 20KE devices have four dedicated clocks.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Single-Port Mode
APEX also supports single-port mode, which used when simultaneous reads writes required. Figure
Figure Single-Port Mode
Dedicated Inputs Global Signals Dedicated Clocks
Note
data[
RAM/ROM Data 1,024 2,048 Data
MegaLAB, FastTrack Local Interconnect
address[
Read Address
wren
outclken
Write Enable
inclken
inclock
Write Pulse Generator
outclock
Notes:
registers asynchronously cleared local interconnect signals, global signals, chip-wide reset. APEX 20KE devices have four dedicated clocks.
Content-Addressable Memory
APEX 20KE devices, implement CAM. thought inverse RAM. When read, outputs data given address. Conversely, outputs address given data word. example, data FA12 stored address outputs when FA12 driven into
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
used high-speed search operations. When searching data within block, search performed serially. Thus, finding particular data word take many cycles. searches addresses parallel outputs address storing particular word. When match found, match flag high. Figure shows block diagram.
Figure APEX 20KE Block Diagram
wraddress[] data[] wren inclock inclocken inaclr data_address[] match outclock outclocken outaclr
used application requiring high-speed searches, such networking, communications, data compression, cache management. APEX 20KE on-chip provides faster system performance than traditional discrete CAM. Integrating logic into APEX 20KE device eliminates off-chip on-chip delays, improving system performance. When mode, implements 32-word, 32-bit CAM. Wider deeper implemented combining multiple CAMs with some ancillary logic implemented LEs. Quartus software combines ESBs automatically create larger CAMs. supports writing "don't-care" bits into words memory. don't-care used mask comparisons; don't-care effect matches. output encoded unencoded. When encoded, outputs encoded address data's location. instance, data located address output When unencoded, uses outputs show location data over clock cycles. this case, data located address 12th output line goes high. When using unencoded outputs, clock cycles required read output, because 16-bit output used show status words.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
encoded output better suited designs that ensure duplicate data written into CAM. duplicate data written into locations, CAM's output will correct. contain duplicate data, unencoded output better solution; with unencoded outputs distinguish multiple data locations. pre-loaded with data during configuration, written during system operation. most cases, clock cycles required write each word into CAM. When don't-care bits used, third clock cycle required.
Driving Signals
ESBs provide flexible options driving control signals. Different clocks used inputs outputs. Registers inserted independently data input, data output, read address, write address, signals. global signals local interconnect drive signals. global signals, dedicated clock pins, local interconnect drive clock signals. Because drive local interconnect, control signals clock, clock enable, asynchronous clear signals. Figure shows control signal generation logic.
Figure Control Signal Generation
Dedicated Clocks Global Signals Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect RDEN
INCLKENA
OUTCLKENA
WREN INCLOCK
OUTCLOCK
INCLR OUTCLR
Note:
APEX 20KE devices have four dedicated clocks.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
local interconnect, which driven adjacent (for high-speed connection ESB) MegaLAB interconnect. drive local, MegaLAB, FastTrack Interconnect routing structure drive IOEs same MegaLAB structure anywhere device.
Implementing Logic
addition implementing logic with product terms, implement logic functions when programmed with read-only pattern during configuration, creating large LUT. With LUTs, combinatorial functions implemented looking results, rather than computing them. This implementation combinatorial functions faster than using algorithms implemented general logic, performance advantage that further enhanced fast access times ESBs. large capacity ESBs enables designers implement complex functions logic level without routing delays associated with linked distributed blocks. Parameterized functions such functions take advantage automatically. Further, Quartus software implement portions design with ESBs where appropriate.
Programmable Speed/Power Control
APEX ESBs offer high-speed mode that supports very fast operation ESB-by-ESB basis. When high speed required, this feature turned reduce ESB's power dissipation 50%. ESBs that power incur nominal timing delay adder. This Turbo Bitoption available ESBs that implement product-term logic memory functions. that used will powered down does consume current. Designers program each APEX device either high-speed low-power operation. result, speed-critical paths design high speed, while remaining paths operate reduced power.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Structure
APEX element (IOE) contains bidirectional buffer register that used either input register external data requiring fast setup times, output register data requiring fast clock-to-output performance. IOEs used input, output, bidirectional pins. Quartus Compiler uses programmable inversion option invert signals from column interconnect automatically where appropriate. Because APEX offers output enable pin, Quartus Compiler emulate open-drain operation efficiently. APEX includes programmable delays that activated ensure zero hold times, minimum clock-to-output times, input register-to-core register transfers, core-to-output register transfers. path which directly drives register require delay ensure zero hold time, whereas path which drives register through combinatorial logic require delay. Table describes APEX programmable delays their logic options Quartus software.
Table APEX Programmable Delay Chain
Programmable Delays
Input Core Delay Input Input Register Delay Core Output Register Delay Output register Delay
Quartus Logic Option
Decrease input delay internal cells Decrease input delay input register Decrease input delay output register Increase delay output
Quartus compiler automatically program these delays minimize setup time while providing zero hold time. Figure shows fast bidirectional I/Os implemented APEX devices. register APEX programmed power high after configuration complete. programmed power low, asynchronous clear control register. programmed power high, register cannot asynchronously cleared preset. This feature useful cases where APEX device controls active-low input another device; prevents inadvertent activation input upon power-up.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure APEX Bidirectional Registers
Row, Column, Local Interconnect Dedicated Clock Inputs Peripheral Control
Register
Dedicated Inputs
CLRN
Chip-Wide Reset
OE[7.0]
Chip-Wide Output Enable
VCCIO
Input Core Delay Core Output Register Delay Input Input Register Delay CLK[1.0] CLRN Output Register Output Register Delay
Optional Clamp
Slew-Rate Control
CLK[3.2] ENA[5.0]
CLRn[1.0]
Chip-Wide Reset Input Register
CLRN
Chip-Wide Reset
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
APEX 20KE devices include enhanced IOE, which drives FastRow interconnect. FastRow interconnect connects column directly local interconnect within MegaLAB structures. This feature provides fast setup times pins that drive high fan-outs with complex logic, such designs. APEX 20KE also includes direct support open-drain operation, giving faster clock-tooutput open-drain signals. Some programmable delays APEX 20KE offer multiple levels delay fine-tune setup hold time requirements. Quartus compiler automatically these delays minimize setup time while providing zero hold time. Table describes APEX 20KE programmable delays their logic options Quartus software.
Table APEX 20KE Programmable Delay Chains
Programmable Delays
Input Core Delay Input Input Register Delay Core Output Register Delay Output Register Delay Clock Enable Delay
Quartus Logic Option
Decrease input delay internal cells Decrease input delay input registers Decrease input delay output register Increase delay output Increase clock enable delay
register APEX 20KE programmed power high after configuration complete. programmed power low, asynchronous clear control register. programmed power high, asynchronous preset control register. Figure shows fast bidirectional I/Os implemented APEX 20KE devices. This feature useful cases where APEX device controls active-low input another device; prevents inadvertent activation input upon power-up.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure APEX 20KE Bidirectional Registers
Row, Column, FastRow, Dedicated Local Interconnect Clock Inputs Dedicated Inputs Peripheral Control
Register
CLRN
Chip-Wide Reset
OE[7.0]
Chip-Wide Output Enable
Input Core Delay Input Core Delay Core Output Register Delay Input Input Register Delay CLK[1.0] Output Register Output Register Delay
VCCIO
Optional Clamp
Open-Drain Output Slew-Rate Control
CLRN/
CLK[3.2] ENA[5.0] Clock Enable Delay CLRn[1.0]
Chip-Wide Reset Input Register
CLRN
Chip-Wide Reset
Note:
This programmable delay four settings: three levels delay.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Each drives row, column, MegaLAB, local interconnect when used input bidirectional pin. drive local, MegaLAB, row, column interconnect; column drive column interconnect. Figure shows connects interconnect.
Figure Connection Interconnect
Interconnect MegaLAB Interconnect
drive through row, column, MegaLAB interconnect.
Each drive local, MegaLAB, row, column interconnect. Each data signal driven local interconnect.
drive through local interconnect faster clock-to-output times.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure shows column connects interconnect.
Figure Column Connection Interconnect
Each drive column interconnect. APEX 20KE devices, IOEs also drive FastRow column interconnect. Each data signal driven local interconnect.
drive through local interconnect faster clock-to-output times.
drive column through row, column, MegaLAB interconnect.
Column Interconnect
Interconnect
MegaLAB Interconnect
Dedicated Fast I/Os
APEX 20KE devices incorporate enhancement support bidirectional pins with high internal fanout such control signals. These pins called Dedicated Fast I/Os (FAST1, FAST2, FAST3, FAST4) replace dedicated inputs. These pins used fast clock, clear, high fanout logic signal distribution. They also drive out. Dedicated Fast data output tri-state control driven local interconnect from adjacent MegaLAB high speed.
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Advanced Standard Support
APEX 20KE supports following standards: LVTTL, LVCMOS, 1.8-V I/O, 2.5-V I/O, 3.3-V PCI, 3.3-V AGP, LVDS, GTL+, CTT, SSTL-3 Class SSTL-2 Class APEX 20KE device contains eight banks. banks support standards except LVDS. addition, bank supports LVDS inputs, another bank supports LVDS outputs. LVDS banks support standards. LVDS banks support standards. Each bank VCCIO pins. single device support 1.8-V, 2.5-V, 3.3-V interfaces; each bank support different standard independently. Each bank also separate VREF level, that each bank support terminated standards (such SSTL-3) independently. Within bank, terminated standards supported. EP20K300E larger APEX 20KE devices support LVDS interface data pins (smaller devices support LVDS clock pins, data pins). EP20K300E larger devices support LVDS interface data pins Mbit/channel; devices with X-suffix ordering code serializer/deserializer circuit support Mbit/channel. Each bank support multiple standards with same VCCIO output pins. Each bank support voltage-referenced standard, support multiple standards with same VCCIO voltage level. example, when VCCIO bank support LVTTL, LVCMOS, 3.3-V PCI, SSTL-3 inputs outputs. When LVDS banks used LVDS I/Os, they support other standards. Figure shows arrangement APEX 20KE banks.
more information standards supported APEX 20KE devices, Application Note (Using Selectable Standards Altera Devices).
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Figure APEX 20KE Banks
Bank Bank
Bank
LVDS Output Bank
Regular Banks Support: LVTTL LVCMOS GTL+ SSTL-2 Class SSTL-3 Class Individual Power
Bank
LVDS Input Bank
Bank
Bank
Bank
Bank
Power Sequencing Socketing
Because APEX devices used mixed-voltage environment, they have been designed specifically tolerate possible power-up sequence. Therefore, VCCIO VCCINT power planes powered order. Signals driven into APEX devices before during power without damaging device. addition, APEX devices drive during power Once operating conditions reached device configured, APEX devices operate specified user.
SameFrame Pin-Outs
APEX devices support SameFrame pin-out feature FineLine packages. SameFrame pin-out feature arrangement balls FineLine packages such that lower-ballcount packages form subset higher-ball-count packages. SameFrame pin-outs provide flexibility migrate only from device device within same package, also from package another. given printed circuit board (PCB) layout support multiple device density/package combinations. example, single board layout support range devices from EP20K100 device 324-pin FineLine package EP20K400 device 672-pin FineLine package.
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Preliminary Information
APEX Programmable Logic Device Family
Quartus software provides support design PCBs with SameFrame pin-out devices. Devices defined present future use. Quartus software generates pin-outs describing board take advantage this migration (see Figure 30).
Figure SameFrame Pin-Out Example
Printed Circuit Board Designed 672-Pin FineLine Package
324-Pin FineLine
672-Pin FineLine
324-Pin FineLine Package (Reduced Count Logic Requirements)
672-Pin FineLine Package (Increased Count Logic Requirements)
ClockLock ClockBoost Features
APEX devices support ClockLock ClockBoost clock management features, which implemented with PLLs. ClockLock circuitry uses synchronizing that reduces clock delay skew within device. This reduction minimizes clock-to-output setup times while maintaining zero hold times. ClockBoost circuitry, which provides clock multiplier, allows designer enhance device area efficiency sharing resources within device. ClockBoost circuitry allows designer distribute low-speed clock multiply that clock on-device. APEX devices include high-speed clock tree; unlike ASICs, user does have design optimize clock tree. ClockLock ClockBoost features work conjunction with APEX device's high-speed clock provide significant improvements system performance bandwidth. Devices with x-suffix ordering code include ClockLock circuit. ClockLock ClockBoost features APEX devices enabled through Quartus software. External devices required these features.
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
designs that require both multiplied non-multiplied clock, clock trace board connected CLK2p. Table shows combinations supported ClockLock ClockBoost circuitry. CLK2p feed both ClockLock ClockBoost circuitry APEX device. However, when both circuits used, other clock (CLK1p) cannot used.
Table Multiplication Factor Combinations
Clock
Clock
APEX 20KE ClockLock Feature
APEX 20KE devices include enhanced ClockLock feature set. These devices include four PLLs, which used independently. PLLs designed either general-purpose LVDS devices that support LVDS pins). remaining PLLs designed general-purpose use. EP20K200E smaller devices have PLLs; EP20K300E larger devices have four PLLs. following sections describe some features offered APEX 20KE PLLs.
External Feedback
ClockLock circuit's output driven off-chip clock other devices system; further, feedback loop routed off-chip. This feature allows designer exercise fine control over interface between APEX 20KE device another high-speed device, such SDRAM.
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Preliminary Information
APEX Programmable Logic Device Family
Clock Multiplication
APEX 20KE ClockBoost circuit multiply divide clocks programmable number. clock multiplied m/(n where range from ranges from Clock multiplication division used time-domain multiplexing other functions, which reduce design requirements.
Clock Phase Delay Adjustment
APEX 20KE ClockShift feature allows clock phase delay adjusted. clock phase adjusted steps. clock delay adjusted increase decrease clock delay arbitrary amount, clock period.
LVDS Support
PLLs designed support LVDS interface. When using LVDS, clock runs slower rate than data transfer rate. Thus, PLLs used multiply clock internally capture LVDS data. example, clock 77.76 support 622.08 Million bits second (Mbps) LVDS data transfer. this example, multiplies incoming clock support high-speed data transfer. LVDS interface supported EP20K300E larger devices. APEX 20KE ClockLock circuitry supports individual LOCK signals. LOCK signal drives high when ClockLock circuit locked onto input clock. Lock signals optional each ClockLock circuit; when used, they pins.
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APEX Programmable Logic Device Family
Preliminary Information
ClockLock ClockBoost Timing Parameters
ClockLock ClockBoost circuitry function properly, incoming clock must meet certain requirements. these specifications met, circuitry lock onto incoming clock, which generates erroneous clock within device. clock generated ClockLock ClockBoost circuitry must also meet certain specifications. incoming clock meets these requirements during configuration, APEX ClockLock ClockBoost circuitry will lock onto clock during configuration. circuit will ready immediately after configuration. APEX 20KE devices, clock input standard programmable, cannot respond clock until device configured. will begin lock onto input clock soon configuration complete. Figure shows incoming generated clock specifications.
Figure Specifications Incoming Generated Clocks
parameter refers nominal input clock period; parameter refers nominal output clock period.
CLK1, CLK2 CLK4 INDUTY CLKDEV
Input Clock
OUTDUTY
INCLKSTB
ClockLock Generated Clock
JITTER
JITTER
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Preliminary Information
APEX Programmable Logic Device Family
Table summarizes ClockLock ClockBoost parameters APEX devices. APEX 20KE device specifications, contact Altera Applications.
Table APEX ClockLock ClockBoost Parameters
Symbol
INDUTY CLK1 fCLK2 fCLK4 CLKDEV
Parameter
Input rise time Input fall time Input duty cycle Input clock frequency (ClockBoost clock multiplication factor equals Input clock frequency (ClockBoost clock multiplication factor equals Input clock frequency (ClockBoost clock multiplication factor equals Input deviation from user specification Quartus software (ClockBoost clock multiplication factor equals Input clock stability (measured between adjacent clocks) Time required ClockLock ClockBoost acquire lock Jitter ClockLock ClockBoostgenerated clock Duty cycle ClockLock ClockBoost-generated clock
Condition
Unit
25,000
INCLKSTB LOCK JITTER
INCLKSTB INCLKSTB
tOUTDUTY
Notes:
implement ClockLock ClockBoost circuitry with Quartus software, designers must specify input frequency. Quartus software tunes ClockLock ClockBoost circuitry this frequency. fCLKDEV parameter specifies much incoming clock differ from specified frequency during device operation. Twenty-five thousand parts million (PPM) equates 2.5% input clock period. During device configuration, ClockLock ClockBoost circuitry configured before rest device. incoming clock supplied during configuration, ClockLock ClockBoost circuitry locks during configuration because tLOCK value less than time required configuration. tJITTER specification measured under long-term observation.
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APEX Programmable Logic Device Family
Preliminary Information
SignalTap Embedded Logic Analyzer
APEX devices include device enhancements support SignalTap embedded logic analyzer. including this circuitry, APEX device provides ability monitor design operation over period time through IEEE Std. 1149.1 (JTAG) circuitry; designer analyze internal logic speed without bringing internal signals pins. This feature particularly important advanced packages such FineLine packages, because difficult connection during debugging process after board designed manufactured. APEX devices provide JTAG circuitry that complies with IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing performed before after configuration, during configuration. APEX devices also JTAG port configuration with Quartus software with hardware using either Files (.jam) Byte-Code Files (.jbc). Finally, APEX devices JTAG port monitor logic operation device with SignalTap embedded logic analyzer. APEX devices support JTAG instructions shown Table
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
Table APEX JTAG Instructions
JTAG Instruction Description
SAMPLE/PRELOAD Allows snapshot signals device pins captured examined during normal device operation, permits initial data pattern output device pins. Also used SignalTap embedded logic analyzer. EXTEST BYPASS Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing test results input pins. Places 1-bit bypass register between pins, which allows data pass synchronously through selected devices adjacent devices during normal device operation. Selects 32-bit USERCODE register places between pins, allowing USERCODE serially shifted TDO. Selects IDCODE register places between TDO, allowing IDCODE serially shifted TDO. These instructions used when configuring APEX device JTAG port with ByteBlasterMV download cable, using File Byte-Code File embedded processor. These instructions monitor internal device operation with SignalTap embedded logic analyzer.
USERCODE IDCODE Instructions
SignalTap Instructions
APEX device instruction register length bits. APEX device USERCODE register length bits. Tables show boundary-scan register length device IDCODE information APEX devices.
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Preliminary Information
APEX Programmable Logic Device Family
Table APEX Boundary-Scan Register Length
Device
EP20K60E EP20K100 EP20K100E EP20K160E EP20K200 EP20K200E EP20K300E EP20K400 EP20K400E EP20K600E EP20K1000E EP20K1500E Note:
Contact Altera Applications up-to-date information this device.
Boundary-Scan Register Length
1,176 1,164 1,188 1,266 1,536 1,506 1,866 2,190 2,502
Table 32-Bit APEX Device IDCODE
Device Version Bits)
EP20K60E EP20K100 EP20K100E EP20K160E EP20K200 EP20K200E EP20K300E EP20K400 EP20K400E EP20K600E EP20K1000E EP20K1500E Notes:
most significant (MSB) left. IDCODE's least significant (LSB) always Contact Altera Applications up-to-date information this device.
IDCODE Bits) Part Number Bits)
1000 0000 0110 0000 0000 0100 0001 0110 1000 0001 0000 0000 1000 0001 0110 0000 0000 1000 0011 0010 1000 0010 0000 0000 1000 0011 0000 0000 0001 0110 0110 0100 1000 0100 0000 0000 1000 0110 0000 0000 1001 0000 0000 0000 1001 0101 0000 0000
Manufacturer Identity Bits)
0110 1110 0110 1110 0110 1110 0110 1110 0110 1110 0110 1110 0110 1110 0110 1110 0110 1110 0110 1110 0110 1110 0110 1110
Bit)
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Figure shows timing requirements JTAG signals.
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APEX Programmable Logic Device Family
Preliminary Information
Figure APEX JTAG Waveforms
tJPZX tJSSU Signal Captured Signal Driven tJSH JPCO JPXZ JPSU
tJSZX
tJSCO
tJSXZ
Table shows JTAG timing parameters values APEX devices.
Table APEX JTAG Timing Parameters Values
Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ clock period clock high time clock time JTAG port setup time JTAG port hold time JTAG port clock output JTAG port high impedance valid output JTAG port valid output high impedance Capture register setup time Capture register hold time Update register clock output Update register high impedance valid output Update register valid output high impedance
Parameter
Unit
more information, following documents:
Application Note (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing Altera Devices) Programming Test Language Specification
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Preliminary Information
APEX Programmable Logic Device Family
Generic Testing
Each APEX device functionally tested. Complete testing each configurable static random access memory (SRAM) logic functionality ensures 100% yield. test measurements FLEX 10KE devices made under conditions equivalent those shown Figure Multiple test patterns used configure devices during stages production flow.
Figure APEX Test Conditions
Device Power supply transients affect measurements. Simultaneous transitions Output multiple outputs should avoided accurate measurement. Threshold tests must performed under conditions. Large-amplitude, fast-ground-current Device input rise fall transients normally occur device times outputs discharge load capacitances. When these transients flow through parasitic inductance between device ground test system ground, significant reductions observable noise immunity result. Test System
(includes capacitance)
Operating Conditions
Tables through provide information absolute maximum ratings, recommended operating conditions, operating conditions, capacitance 2.5-V APEX devices.
Table APEX Device Absolute Maximum Ratings
Symbol
CCINT CCIO input voltage output current, Storage temperature Ambient temperature Junction temperature bias Under bias
Note
-0.5 -0.5 -0.5
Parameter
Supply voltage
Conditions
With respect ground
Unit
PQFP, RQFP, TQFP, packages, under bias Ceramic packages, under bias
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APEX Programmable Logic Device Family
Preliminary Information
Table APEX Device Recommended Operating Conditions
Symbol
CCINT CCIO
Parameter
Supply voltage internal logic input buffers
Conditions
(3),
2.375 (2.375) 3.00 (3.00) 2.375 (2.375) -0.5 -40°
2.625 (2.625) 3.60 (3.60) 2.625 (2.625) CCIO 100°
Unit
Supply voltage output buffers, 3.3-V (3), operation Supply voltage output buffers, 2.5-V (3), operation
Input voltage Output voltage Operating temperature Input rise time Input fall time
commercial industrial
Table APEX Device Operating Conditions (Part
Symbol
Notes (6),
0.8, VCCIO
Parameter
High-level LVTTL, CMOS, 3.3-V input voltage Low-level LVTTL, CMOS, 3.3-V input voltage 3.3-V high-level LVTTL output voltage 3.3-V high-level LVCMOS output voltage
Conditions
Unit
1.7, VCCIO -0.5 CCIO 3.00 -0.1 CCIO 3.00 CCIO VCCIO
3.3-V high-level output voltage -0.5 CCIO 3.00 3.60 2.5-V high-level output voltage -0.1 CCIO 2.30 CCIO 2.30 CCIO 2.30
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Preliminary Information
APEX Programmable Logic Device Family
Table APEX Device Operating Conditions (Part
Symbol
Notes (6),
VCCIO
Parameter
3.3-V low-level LVTTL output voltage 3.3-V low-level LVCMOS output voltage
Conditions
CCIO 3.00 (10) CCIO 3.00 (10)
Unit
3.3-V low-level output voltage CCIO 3.00 3.60 (10) 2.5-V low-level output voltage CCIO 2.30 (10) CCIO 2.30 (10) CCIO 2.30 (10) Input leakage current Tri-stated leakage current supply current (standby) (All ESBs power-down mode) -0.5 -0.5 ground, load, toggling inputs, speed grade ground, load, toggling inputs, speed grades CONF Value pull-up resistor before during configuration CCIO (11) CCIO 2.375 (11)
Table APEX Device Capacitance
Symbol
CINCLK COUT
Note (12)
Conditions
Parameter
Input capacitance Input capacitance dedicated clock Output capacitance
Unit
VOUT
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APEX Programmable Logic Device Family Data Sheet Notes tables:
Preliminary Information
Operating Requirements Altera Devices Data Sheet. Minimum input -0.5 During transitions, inputs undershoot -2.0 overshoot input currents less than periods shorter than Numbers parentheses industrial-temperature-range devices. Maximum rise time must rise monotonically. pins, including dedicated inputs, clock, I/O, JTAG pins, driven before VCCINT VCCIO powered. Typical values 25°C, CCINT CCIO These values specified under APEX device recommended operating conditions, shown Table page APEX input buffers compatible with 2.5-V 3.3-V (LVTTL LVCMOS) signals. Additionally, input buffers 3.3-V compliant when VCCIO VCCINT meet relationship shown Figure page parameter refers high-level TTL, PCI, CMOS output current. (10) parameter refers low-level TTL, PCI, CMOS output current. This parameter applies open-drain pins well output pins. (11) pull-up resistance values will lower external source drives higher than VCCIO. (12) Capacitance sample-tested only.
Tables through provide information absolute maximum ratings, recommended operating conditions, operating conditions, capacitance 1.8-V APEX 20KE devices.
Table APEX 20KE Device Absolute Maximum Ratings
Symbol
CCINT CCIO input voltage output current, Storage temperature Ambient temperature Junction temperature bias Under bias
Note
-0.5 -0.5 -0.5
Parameter
Supply voltage
Conditions
With respect ground
Unit
PQFP, RQFP, TQFP, packages, under bias Ceramic packages, under bias
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Preliminary Information
APEX Programmable Logic Device Family
Table APEX 20KE Device Recommended Operating Conditions
Symbol
CCINT CCIO
Parameter
Supply voltage internal logic input buffers
Conditions
(3),
1.71 (1.71) 3.00 (3.00) 2.375 (2.375) -0.5 -40°
1.89 (1.89) 3.60 (3.60) 2.625 (2.625) CCIO 100°
Unit
Supply voltage output buffers, 3.3-V (3), operation Supply voltage output buffers, 2.5-V (3), operation
Input voltage Output voltage Operating temperature Input rise time Input fall time
commercial industrial
Table APEX 20KE Device Operating Conditions (Part
Symbol
Notes (6),
0.8, VCCIO
Parameter
High-level LVTTL, CMOS, 3.3-V input voltage Low-level LVTTL, CMOS, 3.3-V input voltage 3.3-V high-level LVTTL output voltage 3.3-V high-level LVCMOS output voltage
Conditions
Unit
1.7, VCCIO -0.5 CCIO 3.00 -0.1 CCIO 3.00 CCIO VCCIO
3.3-V high-level output voltage -0.5 CCIO 3.00 3.60 2.5-V high-level output voltage -0.1 CCIO 2.30 CCIO 2.30 CCIO 2.30
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table APEX 20KE Device Operating Conditions (Part
Symbol
Notes (6),
VCCIO
Parameter
3.3-V low-level LVTTL output voltage 3.3-V low-level LVCMOS output voltage
Conditions
CCIO 3.00 (10) CCIO 3.00 (10)
Unit
3.3-V low-level output voltage CCIO 3.00 3.60 (10) 2.5-V low-level output voltage CCIO 2.30 (10) CCIO 2.30 (10) CCIO 2.30 (10) Input leakage current Tri-stated leakage current supply current (standby) (All ESBs power-down mode) -0.5 -0.5 ground, load, toggling inputs, speed grade ground, load, toggling inputs, speed grades CONF Value pull-up resistor before during configuration CCIO (11) CCIO 2.375 (11) CCIO 1.71 (11)
Operating Specifications APEX 20KE standards, please refer Application Note (Using Selectable Standards Altera Devices).
Table APEX 20KE Device Capacitance
Symbol
CINCLK COUT
Note (12)
Conditions
Parameter
Input capacitance Input capacitance dedicated clock Output capacitance
Unit
VOUT
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Preliminary Information Notes tables:
APEX Programmable Logic Device Family
Operating Requirements Altera Devices Data Sheet. Minimum input -0.3 During transitions, inputs undershoot -0.5 overshoot input currents less than periods shorter than Numbers parentheses industrial-temperature-range devices. Maximum rise time must rise monotonically. pins, including dedicated inputs, clock, I/O, JTAG pins, driven before VCCINT VCCIO powered. Typical values 25°C, CCINT CCIO These values specified under APEX device recommended operating conditions, shown Table page APEX input buffers compatible with 2.5-V 3.3-V (LVTTL LVCMOS) signals. Additionally, input buffers 3.3-V compliant when VCCIO VCCINT meet relationship shown Figure page Input buffers also meet specifications GTL+, CTT, AGP, SSTL-2, SSTL-3 parameter refers high-level TTL, PCI, CMOS output current. (10) parameter refers low-level TTL, PCI, CMOS output current. This parameter applies open-drain pins well output pins. (11) pull-up resistance values will lower external source drives higher than VCCIO. (12) Capacitance sample-tested only.
Figure shows relationship between VCCIO VCCINT 3.3-V compliance APEX devices. information this relationship APEX 20KE devices, contact Altera Applications.
Figure Relationship between VCCIO VCCINT 3.3-V Compliance
VCCINT
PCI-Compliant Region
VCCIO
Figure shows typical output drive characteristics APEX devices with 3.3-V 2.5-V VCCIO. output driver compatible with 3.3-V Local Specification, Revision (when VCCIO pins connected output drive characteristics APEX 20KE devices, contact Altera Applications.
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APEX Programmable Logic Device Family
Preliminary Information
Figure Output Drive Characteristics APEX Devices
Typical Output Current (mA)
VCCINT VCCIO Room Temperature
Typical Output Current (mA)
VCCINT VCCIO Room Temperature
Output Voltage
Output Voltage
Timing Model
continuous, high-performance FastTrack MegaLAB interconnect routing resources ensure predictable performance, accurate simulation, accurate timing analysis. This predictable performance contrasts with that FPGAs, which segmented connection scheme therefore have unpredictable performance. Figure shows timing model bidirectional timing.
Figure Synchronous Bidirectional External Timing
Dedicated Clock
tXZBIDIR tZXBIDIR tOUTCOBIDIR
Bidirectional
CLRN
CLRN
Register
tINSUBIDIR tINHBIDIR
CLRN
Note:
output enable input registers registers adjacent bidirectional pin.
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Preliminary Information
APEX Programmable Logic Device Family
Tables describe APEX external timing parameters.
Table APEX External Timing Parameters
Symbol
tINSU tINH tOUTCO
Note
Conditions
Clock Parameter
Setup time with global clock register Hold time with global clock register Clock-to-output delay with global clock register
Table External Bidirectional Timing Parameters
Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Note Tables:
These timing parameters sample-tested only.
Note
Condition
Parameter
Setup time bidirectional pins with global clock same-row samecolumn register Hold time bidirectional pins with global clock same-row samecolumn register Clock-to-output delay bidirectional pins with global clock register Synchronous output buffer disable delay Synchronous output buffer enable delay, slow slew rate
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Figure shows fMAX timing model APEX APEX 20KE devices.
Figure fMAX Timing Model
tLUT
Routing Delay
F1-4 F5-20 tF20+
tESBRC tESBWC tESBWESU tESBDATASU tESBADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO
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Preliminary Information
APEX Programmable Logic Device Family
Table describes fMAX timing parameters shown Figure
Table APEX APEX 20KE fMAX Timing Parameters
Symbol
tLUT tESBRC tESBWC tESBWESU tESBDATASU tESBADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO tF1-4 tF5-20 tF20+ tCLRP tPREP tESBCH tESBCL tESBWP tESBRP
register setup time before clock register hold time before clock register clock-to-output delay delay data-in Asynchronous read cycle time Asynchronous write cycle time setup time before clock when using input register data setup time before clock when using input register ESAB address setup time before clock when using input registers clock-to-output delay when using output registers clock-to-output delay without output registers data-in data-out delay mode Macrocell input non-registered output Macrocell register setup time before clock Macrocell register clock-to-output delay Fanout delay using Local Interconnect Fanout delay using MegaLab Interconnect Fanout delay using FastTrack Interconnect Minimum clock high time from clock Minimum clock time from clock clear Pulse Width preset pulse width Clock high time Clock time Write pulse width Read pulse width
Parameter
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Tables through show fMAX timing parameters EP20K100, EP20K200, EP20K400, EP20K400E, EP20K600E devices.
Table EP20K100 fMAX Timing Parameters
Symbol Speed Grade
tLUT tESBRC tESBWC tESBWESU tESBDATASU tESBADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO tF1-4 tF5-20 tF20+ tCLRP tPREP tESBCH tESBCL tESBWP tESBRP
Speed Grade
Speed Grade
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Preliminary Information
APEX Programmable Logic Device Family
Table EP20K200 fMAX Timing Parameters
Symbol Speed Grade
tLUT tESBRC tESBWC tESBWESU tESBDATASU tESBADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO tF1-4 tF5-20 tF20+ tCLRP tPREP tESBCH tESBCL tESBWP tESBRP
Speed Grade
Speed Grade
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APEX Programmable Logic Device Family
Preliminary Information
Table EP20K400 fMAX Timing Parameters
Symbol Speed Grade
tLUT tESBRC tESBWC tESBWESU tESBDATASU tESBADDRSU tESBDATACO1 tESBDATACO2 tESBDD tWDSU tPTERMSU tPTERMCO tF1-4 tF5-20 tF20+ tCLRP tPREP tESBCH tESBCL tESBWP tESBRP
Speed Grade
Speed Grade
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Preliminary Information
APEX Programmable Logic Device Family
Table EP20K400E fMAX Timing Parameters
Symbol Speed Grade
tLUT tESBRC tESBWC tESBWESU tESBDATASU tESBADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO tF1-4 tF5-20 tF20+ tCLRP tPREP tESBCH tESBCL tESBWP tESBRP
Speed Grade
Speed Grade
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APEX Programmable Logic Device Family
Preliminary Information
Table EP20K600E fMAX Timing Parameters
Symbol Speed Grade
tLUT tESBRC tESBWC tESBWESU tESBDATASU tESBADDRSU tESBDATACO1 tESBDATACO2 tESBDD tPTERMSU tPTERMCO tF1-4 tF5-20 tF20+ tCLRP tPREP tESBCH tESBCL tESBWP tESBRP
Speed Grade
Speed Grade
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Preliminary Information
APEX Programmable Logic Device Family
Tables through show timing parameter values APEX devices.
Table EP20K100 External Timing Parameters
Symbol Speed Grade
tINSU tINH tOUTCO tINSU tINH tOUTCO tPCISU tPCIH tPCICO
Speed Grade
Speed Grade
Unit
Table EP20K100 External Bidirectional Timing Parameters
Symbol Speed Grade
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR
Speed Grade
Speed Grade
Unit
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APEX Programmable Logic Device Family
Preliminary Information
Table EP20K200 External Timing Parameters
Symbol Speed Grade
tINSU tINH tOUTCO tINSU tINH tOUTCO tPCISU tPCIH tPCICO
Speed Grade
Speed Grade
Unit
Table EP20K200 External Bidirectional Timing Parameters
Symbol Speed Grade
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR
Speed Grade
Speed Grade
Unit
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Preliminary Information
APEX Programmable Logic Device Family
Table EP20K400 External Timing Parameters
Symbol Speed Grade
tINSU tINH tOUTCO tINSU tINH tOUTCO tPCISU tPCIH tPCICO
Speed Grade
Speed Grade
Unit
Table EP20K400 External Bidirectional Timing Parameters
Symbol Speed Grade
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Notes tables:
This parameter measured without using ClockLock ClockBoost circuits. This parameter measured using ClockLock ClockBoost circuits.
Speed Grade
Speed Grade
Unit
10.3 10.3
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APEX Programmable Logic Device Family
Preliminary Information
Table EP20K400E External Timing Parameters
Symbol Speed Grade
tINSU tINH tOUTCO tINSU tINH tOUTCO tPCISU tPCIH tPCICO
Speed Grade
Speed Grade
Unit
Table EP20K400E External Bidirectional Timing Parameters
Symbol Speed Grade
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR
Speed Grade
Speed Grade
Unit
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Preliminary Information
APEX Programmable Logic Device Family
Table EP20K600E External Timing Parameters
Symbol Speed Grade
tINSU tINH tOUTCO tINSU tINH tOUTCO tPCISU tPCIH tPCICO
Speed Grade
Speed Grade
Unit
Table EP20K600E External Bidirectional Timing Parameters
Symbol Speed Grade
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR Notes tables:
This parameter measured without using ClockLock ClockBoost circuits. This parameter measured using ClockLock ClockBoost circuits. ClockShift used this measurement. ClockShift used adjust setup clock-to-output times achieve desired results.
Speed Grade
Speed Grade
Unit
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APEX Programmable Logic Device Family
Preliminary Information
Tables show selectable standard input output adder delays APEX 20KE devices.
Table Selectable Standard Input Adder Delays
Symbol Speed Grade
LVCMOS LVTTL GTL+ SSTL-3 Class SSTL-3 Class SSTL-2 Class SSTL-2 Class LVDS
Speed Grade
-0.4 -0.5 -0.5 -0.3 -0.3 -0.3 -0.3
Speed Grade
-0.5 -0.6 -0.6 -0.4 -0.4 -0.4 -0.4
Unit
-0.3 -0.4 -0.4 -0.3 -0.3 -0.2 -0.3
Table Selectable Standard Output Adder Delays
Symbol Speed Grade
LVCMOS LVTTL GTL+ SSTL-3 Class SSTL-3 Class SSTL-2 Class SSTL-2 Class LVDS
Speed Grade
-0.3 -0.5 -0.2 -0.8 -0.5 -1.0 -0.3 -0.5
Speed Grade
-0.4 -0.6 -0.2 -1.0 -0.6 -1.2 -0.4 -0.7
Unit
-0.2 -0.4 -0.1 -0.6 -0.4 -0.8 -0.2 -0.4
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Preliminary Information
APEX Programmable Logic Device Family
Power Consumption Configuration Operation
estimate device power consumption, interactive power estimator Altera site http://www.altera.com.
APEX architecture supports several configuration schemes. This section summarizes device operating modes available device configuration schemes.
Operating Modes
APEX architecture uses SRAM configuration elements that require configuration data loaded each time circuit powers process physically loading SRAM data into device called configuration. During initialization, which occurs immediately after configuration, device resets registers, enables pins, begins operate logic device. pins tri-stated during power-up, before during configuration. Together, configuration initialization processes called command mode; normal device operation called user mode. Before during device configuration, I/Os pulled VCCIO built-in weak pull-up resistor. SRAM configuration elements allow APEX devices reconfigured in-circuit loading configuration data into device. Real-time reconfiguration performed forcing device into command mode with device pin, loading different configuration data, reinitializing device, resuming usermode operation. In-field upgrades performed distributing configuration files.
Configuration Schemes
configuration data APEX device loaded with five configuration schemes (see Table 45), chosen basis target application. EPC2 configuration device, intelligent controller, JTAG port used control configuration APEX device. When EPC2 configuration device used, system configure automatically system power-up.
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APEX Programmable Logic Device Family
Preliminary Information
Multiple APEX devices configured five configuration schemes connecting configuration enable (nCE) configuration enable output (nCEO) pins each device.
Table Data Sources Configuration
Configuration Scheme
Configuration device Passive serial (PS) Passive parallel asynchronous (PPA) Passive parallel synchronous (PPS) JTAG EPC2 configuration device ByteBlasterMV MasterBlaster download cable serial data source Parallel data source Parallel data source ByteBlasterMV MasterBlaster download cable microprocessor with File
Data Source
more information configuration, Application Note (Configuring APEX 20K, FLEX 10K, FLEX 6000 Devices.)
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Preliminary Information
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Device Pin-Outs
Table shows names numbers EP20K100 devices 144-pin TQFP, 208-pin PQFP, 240-pin PQFP, 324-pin FineLine packages.
Table EP20K100 Device Pin-Outs (Part
Name
MSEL0 MSEL1 NSTATUS NCONFIG DCLK CONF_DONE INIT_DONE nCEO RDYnBSY CLKUSR DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 (4), TRST Dedicated Inputs LOCK CLK2 CLK1 124,
Note
240-Pin PQFP
209,
144-Pin TQFP
208-Pin PQFP
181,
324-Pin FineLine
D10,
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Preliminary Information
Table EP20K100 Device Pin-Outs (Part
Name
DEV_CLRn DEV_OE VCCINT
Note
240-Pin PQFP
122, 145, 179, 120, 148, 177, 199, G11, H12, K11, K12, L10, M13, F12, G13, H10, J11, L12, M11, N14, D15, E14, F13, G12, H11, J10, K10, L11, M12, N13, P14,
144-Pin TQFP
208-Pin PQFP
324-Pin FineLine
125, 108, 182, 156, 126, 105, 144, 116, 136, 208, 189,
VCCIO
VCC_CKLK (10) GNDINT
126,
183, 143, 127, 118,
137, 146, 162,
GNDIO GND_CKLK (10) Connect (N.C.) Total User Pins (11) Notes:
134, 106, 199, 169, 149, 114,
108, 132, 165, 188, 218,
pins that listed user pins. EP20K100 devices 208-pin packages pin-compatible with EP20K200 devices same package pins 154, 148, 121, 109, tri-stated connected VCCINT, pins 153, 147, 110, tri-stated connected GNDINT. Quartus software performs this function automatically when future migration set. EP20K100 devices 240-pin packages pin-compatible with EP20K200 devices same package pins 176, 168, 140, 127, tri-stated connected VCCINT, pins 175, 167, 128, tri-stated connected GNDINT. Quartus software performs this function automatically when future migration set. This dedicated pin; available user pin. This used user used device-wide configuration function. This used user after configuration. This tri-stated user mode. This shows status ClockLock ClockBoost circuitry. When ClockLock ClockBoost circuitry locked incoming clock generates internal clock, LOCK driven high. LOCK remains high periodic clock stops clocking. LOCK function optional; LOCK output used, this user pin. This drives ClockLock ClockBoost circuitry. (10) This power ground ClockLock ClockBoost circuitry. ensure noise resistance, power ground supply ClockLock ClockBoost circuitry should isolated from power ground rest device. ClockLock ClockBoost circuitry used, this power ground should connected VCCINT GNDINT, respectively. (11) user count includes dedicated input pins, dedicated clock pins, pins.
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Preliminary Information
APEX Programmable Logic Device Family
Table shows names numbers EP20K200 devices 208-pin RQFP, 240-pin RQFP, 484-Pin FineLine packages.
Table EP20K200 Device Pin-Outs (Part
Name
MSEL0 MSEL1 NSTATUS NCONFIG DCLK CONF_DONE INIT_DONE nCEO RDYnBSY CLKUSR DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 (4), TRST Dedicated Inputs Dedicated Clock Pins LOCK CLK2 DEV_CLRn DEV_OE 181,
Note
240-Pin RQFP
209,
208-Pin RQFP
484-Pin FineLine
D11, F12, V11,
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Preliminary Information
Table EP20K200 Device Pin-Outs (Part
Name
VCCINT
Note
240-Pin RQFP
122, 127, 140, 145, 168, 176, 179, 120, 148, 177, 199,
208-Pin RQFP
105, 109, 121, 126, 148, 154, 156, 136, 172, 189,
484-Pin FineLine
AA1, AA22, B22, J13, K11, K14, L10, M13, M14, M22, N12, P10, P15, H14, J10, J15, K12, L13, L22, M10, N11, N14, P13, R16, A11, A22, AA2, AA21, AB1, AB11, AB22, B21, F17, G16, H15, J11, J14, K10, K13, L11, L12, M11, M12, M21, N10, N13, P14, R15, T16,
VCCIO
VCC_CKLK (10) GNDINT
110, 118, 127, 143, 147, 153,
128, 137, 146, 162, 167, 175,
GNDIO GND_CKLK (10) Connect (N.C.)
114, 149, 169,
108, 132, 165, 188, 218, A10, A12, A13, A14, AB9, AB10, AB12, AB13, AB14
Total User Pins (11)
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Preliminary Information Notes:
APEX Programmable Logic Device Family
pins that listed user pins. EP20K100 devices 208-pin packages pin-compatible with EP20K200 devices same package pins 154, 148, 121, 109, tri-stated connected VCCINT, pins 153, 147, 110, tri-stated connected GNDINT. Quartus software performs this function automatically when future migration set. EP20K100 devices 240-pin packages pin-compatible with EP20K200 devices same package pins 176, 168, 140, 127, tri-stated connected VCCINT, pins 175, 167, 128, tri-stated connected GNDINT. Quartus software performs this function automatically when future migration set. This dedicated pin; available user pin. This used user used device-wide configuration function. This used user after configuration. This tri-stated user mode. This shows status ClockLock ClockBoost circuitry. When ClockLock ClockBoost circuitry locked incoming clock generates internal clock, LOCK driven high. LOCK remains high periodic clock stops clocking. LOCK function optional; LOCK output used, this user pin. This drives ClockLock ClockBoost circuitry. (10) This power ground ClockLock ClockBoost circuitry. ensure noise resistance, power ground supply ClockLock ClockBoost circuitry should isolated from power ground rest device. ClockLock ClockBoost circuitry used, this power ground should connected VCCINT GNDINT, respectively. (11) user count includes dedicated input pins, dedicated clock pins, pins.
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Preliminary Information
Table shows names numbers EP20K400 devices 652-pin BGA, 655-pin PGA, 672-pin FineLine packages.
Table EP20K400 Device Pin-Outs (Part
Name
MSEL0 MSEL1 NSTATUS NCONFIG DCLK CONF_DONE INIT_DONE nCEO RDYnBSY CLKUSR DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 (2), TRST Dedicated Inputs Dedicated Clock Pins LOCK CLK2 DEV_CLRn DEV_OE AN17 AM17 AN19 AM19 B17, B19, AP17, AP19
Note
655-Pin
AE41 BA23 AC47 BE25 BF14 AY20 BB20 BD20 BG13 BB16 BE23 BG23 AC45 AD40 AB4, AC5, AC43, AE43 H24, AY24 BG29 AY24 AY22 BF26
652-Pin
672-Pin FineLine
AA13 AA12 AA14 AA15 F13, H14, Y13,
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APEX Programmable Logic Device Family
Table EP20K400 Device Pin-Outs (Part
Name
VCCINT
Note
655-Pin
A45, B24, C11, C19, C29, C37, C47, D24, G47, L45, N47, W45, AA1, AA47, AD4, AD44, AG1, AG47, AJ3, AJ45, AR1, AR47, AU3, AU45, AY8, BA1, BA47, BD24, BE1, BE11, BE19, BE29, BE37, BE47, BG3, BG45 E15, E21, E27, E33, E39, G41, J43, R43, AA5, AA43, AG5, AG43, AN5, AN43, AW5, AW43, BA7, BA41, BC9, BC15, BC21, BC27, BC33, BC39 BD28 A47, C13, C21, C27, C35, C45, F24, J47, N45, R47, W47, AA3, AA45, AD6, AD8, AD42, AG3, AG45, AJ1, AJ47, AN1, AN47, AR3, AR45, AW1, AW47, BB24, BE3, BE13, BE21, BE27, BE35, BE45, BG1, BG47
652-Pin
A17, A19, D12, D24, E12, E24, F35, G30, K31, M30, R34, U34, W31, W33, AA4, AA31, AC3, AC32, AE2, AE33, AG1, AH4, AH31, AH35, AK33, AL2, AL12, AL24, AM12, AM24, AR17, AR19 AL3, AL4, AL17, AL19, AL31, AL32, AM5, AN4, AN32, AN33, C32, D31, E17, E19, F30, F31, U30, W30, A18, A35, B18, B34, B35, C18, C33, C34, C35, D17, D18, D32, D33, D34, E18, E30, E31, E32, E33, F18, V30, V31, V32, V33, V34, V35, AK18, AL5, AL6, AL18, AL30, AM18, AM2, AM3, AM4, AM31, AM32, AM33, AM34, AN1, AN2, AN3, AN18, AN34, AN35, AP1, AP2, AP18, AP34, AP35, AR1, AR18, AR35,
672-Pin FineLine
A24, B19, B24, C25, C26, D24, K11, L10, L15, M13, M16, N12, P15, P16, P24, P25, R11, R14, T12, T17, U16, AC3, AC24, AD1, AD2, AD25, AD26, AE3, AE8, AE19, AE24, AF3, AF24 A13, A21, J10, K16, L12, L17, M11, M14, N15, N24, P12, R13, R16, T10, T15, U11, U18, V10, V17, AF6, AF13, AF21 A14, A19, A25, B21, B25, B26, C13, C24, D23, H19, J18, K10, K17, L11, L13, L16, M12, M15, N13, N14, N25, N26, P13, P14, P23, P26, R12, R15, T11, T16, U10, U17, V18, W19, AC4, AC23, AD3, AD13, AD24, AE1, AE2, AE6, AE21, AE25, AE26, AF2, AF8, AF14, AF19, AF25
VCCIO
VCC_CKLK GNDINT
GNDIO
E13, E19, E29, E35, E41, G43, H40, N43, W43, AJ5, AJ43, AR5, AR43, AY40, BA5, BA43, BC7, BC13, BC19, BC29, BC35, BC41, BF46 BD26
GND_CKLK
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Preliminary Information
Table EP20K400 Device Pin-Outs (Part
Name
Connect (N.C.)
Note
655-Pin
652-Pin
672-Pin FineLine
A15, A16, B13, B14, B15, B16, C11, C12, C14, C15, C16, AD11, AD12, AD14, AD15, AD16, AE12, AE13, AE14, AE15, AF12, AF15,
Total User Pins Notes:
pins that listed user pins. This dedicated pin; available user pin. This used user used device-wide configuration function. This used user after configuration. This tri-stated user mode. This shows status ClockLock ClockBoost circuitry. When ClockLock ClockBoost circuitry locked incoming clock generates internal clock, LOCK driven high. LOCK remains high periodic clock stops clocking. LOCK function optional; LOCK output used, this user pin. This drives ClockLock ClockBoost circuitry. This power ground ClockLock ClockBoost circuitry. ensure noise resistance, power ground supply ClockLock ClockBoost circuitry should isolated from power ground rest device. ClockLock ClockBoost circuitry used, this power ground should connected VCCINT GNDINT, respectively. user count includes dedicated input pins, dedicated clock pins, pins.
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Table shows information EP20K100E devices 144pin TQFP, 208-pin RQFP, 240-pin RQFP packages.
Table EP20K100E Pin-Outs (Part
VREF Bank
Note
208-Pin RQFP 240-Pin RQFP
Number Orientation
Pin/Pad Function
144-Pin TQFP
VCCIO VCCINT VCCIO I/O, DATA6 GNDINT I/O, DATA7 GNDIO I/O, I/O, I/O, VCCINT VCC_CKLK3 GND_CKLK3
VCCIO8 VCCINT VCCIO8 VCCINT
VCCIO8 VCCINT VCCIO8 VCCINT
VCCIO8 VCCINT VCCIO8 VCCINT
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Preliminary Information
Table EP20K100E Pin-Outs (Part
VREF Bank
Note
208-Pin RQFP 240-Pin RQFP
Number Orientation
Pin/Pad Function
144-Pin TQFP
GND_CKLK3 I/O, I/O, DEV_CLRn VCCIO CLKLK_FB2p I/O, CLK4n CLK4p I/O, CLK2n DATA0 DCLK CLK2p VCCIO GND_CKLK1 GND_CKLK1 GNDINT VCC_CKLK1 I/O, DEV_OE VCC_CKOUT1 GND_CKOUT1 GNDIO CLKLK_OUT2p I/O, CLKLK_OUT2n I/O, LOCK2 VCCINT I/O, LOCK4
VCCIO8 VCCIO7 VCCINT
VCCIO8 VCCIO7 VCCINT
VCCIO8 VCCIO7 VCCINT
I/O, CLKLK_FB2n
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APEX Programmable Logic Device Family
Table EP20K100E Pin-Outs (Part
VREF Bank
Note
208-Pin RQFP 240-Pin RQFP
Number Orientation
Pin/Pad Function
144-Pin TQFP
VCCIO GNDINT GNDIO VCCINT VCCIO VCCIO GNDIO
VCCIO7 VCCINT VCCIO7 VCCIO6
VCCIO7 VCCINT VCCIO7 VCCIO6
VCCIO7 VCCINT VCCIO7 VCCIO6
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Preliminary Information
Table EP20K100E Pin-Outs (Part
VREF Bank
Note
208-Pin RQFP 240-Pin RQFP
Number Orientation
Pin/Pad Function
144-Pin TQFP
VCCIO VCCIO CONF_DONE nSTATUS FAST4 VCCIO GNDINT GNDINT VCCINT VCCINT GNDINT GNDINT GNDIO FAST3
VCCIO6 VCCIO6 VCCIO5 VCCINT VCCINT
VCCIO6 VCCIO6 VCCIO5 VCCINT VCCINT
VCCIO6 VCCIO6 VCCIO5 VCCINT VCCINT
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Preliminary Information
APEX Programmable Logic Device Family
Table EP20K100E Pin-Outs (Part
VREF Bank
Note
208-Pin RQFP 240-Pin RQFP
Number Orientation
Pin/Pad Function
144-Pin TQFP
VCCIO GNDIO VCCIO VCCIO VCCIO
VCCIO5 VCCIO5 VCCIO5 VCCIO4
VCCIO5 VCCIO5 VCCIO5 VCCIO4
VCCIO5 VCCIO5 VCCIO5 VCCIO4
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table EP20K100E Pin-Outs (Part
VREF Bank
Note
208-Pin RQFP 240-Pin RQFP
Number Orientation
Pin/Pad Function
144-Pin TQFP
GNDINT GNDIO VCCINT VCCIO GNDINT I/OI/O GNDIO I/O, CLK3n CLK3p I/O, CLK1n
VCCINT VCCIO4
VCCINT VCCIO4
VCCINT VCCIO4
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Table EP20K100E Pin-Outs (Part
VREF Bank
Note
208-Pin RQFP 240-Pin RQFP
Number Orientation
Pin/Pad Function
144-Pin TQFP
VCCINT nCONFIG CLK1p MSEL1 MSEL0 VCCIO GNDINT GNDIO VCCINT VCCIO
VCCINT VCCIO3 VCCINT VCCIO3
VCCINT VCCIO3 VCCINT VCCIO3
VCCINT VCCIO3 VCCINT VCCIO3
CLKLK_ENA (6),
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table EP20K100E Pin-Outs (Part
VREF Bank
Note
208-Pin RQFP 240-Pin RQFP
Number Orientation
Pin/Pad Function
144-Pin TQFP
VCCIO GNDINT VCCIO GNDIO VCCIO VCCIO
VCCIO3 VCCIO3 VCCIO2 VCCIO2
VCCIO3 VCCIO3 VCCIO2 VCCIO2
VCCIO3 VCCIO3 VCCIO2 VCCIO2
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Table EP20K100E Pin-Outs (Part
VREF Bank
Note
208-Pin RQFP 240-Pin RQFP
Number Orientation
Pin/Pad Function
144-Pin TQFP
GNDIO VCCIO TRST NCEO FAST1 GNDINT GNDINT VCCINT VCCINT GNDINT VCCIO FAST2 GNDINT I/O, INITDONE I/O, RDYnBSY I/O, CLKUSR I/O, DATA1
VCCIO2 VCCINT VCCINT VCCIO1
VCCIO2 VCCINT VCCINT VCCIO1
VCCIO2 VCCINT VCCINT VCCIO1
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table EP20K100E Pin-Outs (Part
VREF Bank
Note
208-Pin RQFP 240-Pin RQFP
Number Orientation
Pin/Pad Function
144-Pin TQFP
GNDIO VCCIO I/O, DATA2 VCCIO I/O, DATA3 I/O, DATA4 I/O, DATA5(2) GNDIO VCCINT VCCIO8 VCCIO7 VCCIO6 VCCIO5 VCCIO4 VCCIO3 VCCIO2 VCCIO1
VCCIO1 VCCIO1 108,
VCCIO1 VCCIO1 105, 126, 156, 42,53 8,189
VCCIO1 VCCIO1 122, 145, 179, 97,120
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Table EP20K100E Pin-Outs (Part
VREF Bank Number Orientation Pin/Pad Function
Note
208-Pin RQFP 240-Pin RQFP
144-Pin TQFP
106, 126,
114, 118, 127, 143, 149, 169, 183,
108, 132, 137, 146, 162, 165, 188, 211, 218,
Total User I/Os (10)
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table shows configuration power information EP20K100E devices 144-pin TQFP, 208-pin RQFP, 240-pin RQFP packages.
Table EP20K100E Configuration Power Pins (Part
Name
MSEL0 MSEL1 NSTATUS NCONFIG DCLK CONF_DONE INIT_DONE nCEO RDYnBSY CLKUSR DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 (6), (11) TRST Dedicated Fast I/Os CLK1p CLK2p CLK3p CLK4p 124,
144-Pin TQFP
208-Pin RQFP(1)
240-Pin RQFP
181,
209,
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Table EP20K100E Configuration Power Pins (Part
Name
LOCK2 LOCK4 CLKLK_ENA (6), CLKLK_OUT2p CLKLK_FB2p DEV_CLRn DEV_OE VCCINT VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCC_CKLK1 (12) VCC_CKLK3 (12) VCC_CKOUT1
144-Pin TQFP
208-Pin RQFP(1)
240-Pin RQFP
108, 105, 126, 156, 8,189 42,53
122, 145, 179, 97,120
106, 126, 114, 118, 127, 143, 108, 132, 137, 146, 162, 149, 169, 183, 165, 188, 211, 218,
GND_CKLK1 (12) GND_CKLK3 GND_CKOUT1 Connect (N.C.) Total User Pins (10)
Altera Corporation
APEX Programmable Logic Device Family Data Sheet Notes tables:
Preliminary Information
144-pin, 208-pin, 240-pin packages, Four unique VCCIO levels supported. VCCIOs bank must same level; VCCIOs banks must same level; VCCIOs banks must same level. However, unique VREF settings supported each banks. This used user after configuration. CLKLK_OUT CLKLK_FBIN pins powered VCC_CKOUT GND_CKOUT pins. This used user used device-wide configuration function. This complementary signal LVDS pair dedicated inputs outputs that configured LVDS standard. used LVDS pair, these pins regular I/Os. Pins with suffix carry negative signal LVDS channel. Pins with suffix carry positive signal LVDS channel. This dedicated pin; available user pin. This power ground ClockLock ClockBoost circuitry PLL. ensure noise resistance, power ground supply ClockLock ClockBoost circuitry should isolated from power ground rest device. used, this power ground should connected VCCINT GNDINT, respectively. This shows status ClockLock ClockBoost circuitry. When ClockLock ClockBoost circuitry locked incoming clock generates internal clock, LOCK driven high. LOCK goes periodic clock stops clocking. LOCK function optional; LOCK output used, this user pin. This active high enable circuits device. When de-asserted, PLLs reset their default, unlocked state will stop clocking. Once re-asserted, PLLs will begin lock again start clocking. this function needed, should connected VCCINT. (10) user count includes dedicated inputs dedicated clock inputs. does include dedicated clock feedback output pins. (11) This tri-stated user mode. (12) This power ground external output feedback input PLL. These pins should VCCIO level/standard desired external clock output feedback input used). ensure noise resistance, power ground supply external output should isolated from power ground rest VCCIO GNDIO pins. external output used, this power ground should connected VCCIO GNDIO, respectively.
Table shows information EP20K200E devices 208-pin RQFP, 240-pin RQFP, 484-pin FineLine BGA, 672-pin FineLine BGA, 652-pin packages.
Table EP20K200E Pins (Part
VREF Bank
Note
240-Pin RQFP
VCCINT
Number Orientation
Pin/Pad Function
208-Pin RQFP
484-Pin FineLine
VCCINT
652-Pin
672-Pin FineLine
VCCINT
VCCINT
VCCINT
VCCINT
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Table EP20K200E Pins (Part
VREF Bank
Note
240-Pin RQFP
VCCIO8 VCCINT VCCIO8
Number Orientation
Pin/Pad Function
208-Pin RQFP
484-Pin FineLine
VCCIO8 VCCINT VCCIO8
652-Pin
VCCIO8 VCCINT VCCIO8
672-Pin FineLine
VCCIO8 VCCINT VCCIO8
VCCIO GNDINT GNDIO I/O, DATA6 VCCINT I/O, DATA7 VCCIO I/O, GNDINT
VCCIO8 VCCINT VCCIO8
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table EP20K200E Pins (Part
VREF Bank
Note
240-Pin RQFP
VCCINT VCCIO8 VCCIO8
Number Orientation
Pin/Pad Function
208-Pin RQFP
484-Pin FineLine
VCCINT VCCIO8
652-Pin
672-Pin FineLine
VCCINT VCCIO8
VCCINT VCCIO8 VCCIO8
GNDIO I/O, VCCINT I/O, VCCIO GNDINT
VCCINT VCCIO8
VCC_CKLK3 GND_CKLK3 GND_CKLK3 I/O,
I/O, DEV_CLRn VCCIO GNDIO I/O, CLKLK_FB2n CLKLK_FB2p VCCIO8
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Table EP20K200E Pins (Part
VREF Bank
Note
240-Pin RQFP
VCCINT VCCIO7
Number Orientation
Pin/Pad Function
I/O, CLK4n CLK4p I/O, CLK2n VCCINT DATA0 (7), DCLK CLK2p VCCIO
208-Pin RQFP
484-Pin FineLine
VCCINT
652-Pin
672-Pin FineLine
VCCINT
VCCINT VCCIO7
VCCINT VCCIO7
GND_CKLK1 GND_CKLK1 GNDINT VCC_CKLK1 I/O, DEV_OE VCC_CKOUT1 GND_CKOUT1 CLKLK_OUT2p I/O, CLKLK_OUT2n VCCIO VCCINT GNDIO
VCCIO7 VCCINT
VCCIO7 VCCINT
VCCIO7 VCCINT
VCCIO7 VCCINT
VCCIO7 VCCINT
I/O, LOCK2 (10)
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table EP20K200E Pins (Part
VREF Bank
Note
240-Pin RQFP
VCCIO7 VCCINT
Number Orientation
Pin/Pad Function
208-Pin RQFP
VCCIO7 VCCINT
484-Pin FineLine
VCCIO7 VCCINT
652-Pin
VCCIO7 VCCINT
672-Pin FineLine
VCCIO7 VCCINT
I/O, LOCK4 (10)
GNDINT VCCIO VCCINT GNDIO GNDINT
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Table EP20K200E Pins (Part
VREF Bank
Note
240-Pin RQFP
VCCIO7 VCCINT VCCIO7 VCCIO6
Number Orientation
Pin/Pad Function
VCCIO
208-Pin RQFP
VCCIO7 VCCINT VCCIO7 VCCIO6
484-Pin FineLine
VCCIO7 VCCINT AA11 AA10 VCCIO7 VCCIO6
652-Pin
VCCIO7 VCCINT VCCIO7 VCCIO6 AN11 AP10 AL13 AM13 AN12 AP11 AL14 AR10
672-Pin FineLine
VCCIO7 VCCINT VCCIO6
VCCINT GNDIO GNDINT VCCIO VCCIO
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table EP20K200E Pins (Part
VREF Bank
Note
240-Pin RQFP
VCCIO6 VCCIO6 VCCIO5 VCCINT VCCINT
Number Orientation
Pin/Pad Function
GNDIO
208-Pin RQFP
VCCIO6 VCCIO6 VCCIO5 VCCINT VCCINT
484-Pin FineLine
VCCIO6 VCCINT VCCINT
652-Pin
AN13 AP12 AM14 AR11 AL15 AN14 AP13 AR12 AR13 AM15 VCCIO6 AN15 AL16 AP14 AR14 AP15 AR15 VCCIO6 AM16 AN16 AP16 AR16 AM17 AN17 AP17 VCCIO5 VCCINT VCCINT AP19
672-Pin FineLine
AA10 AB11 AB10 AA11 VCCIO6 AB12 VCCIO6 AA12 AA13 VCCIO5 VCCINT VCCINT
VCCIO VCCIO NSTATUS FAST4 VCCIO GNDINT GNDINT VCCINT VCCINT GNDINT GNDINT GNDIO FAST3
CONF_DONE
Altera Corporation
Preliminary Information
APEX Programmable Logic Device Family
Table EP20K200E Pins (Part
VREF Bank
Note
240-Pin RQFP
VCCIO5 VCCIO5
Number Orientation
Pin/Pad Function
VCCIO GNDIO VCCIO
208-Pin RQFP
VCCIO5 VCCIO5
484-Pin FineLine
VCCIO5
652-Pin
AN19 AM19 AR20 AP20 AN20 AM20 AR21 AP21 AR22 AP22 AL20 AN21 VCCIO5 AM21 AR23 AR24 AP23 AN22 AL21 AR25 AM22 AP24 AN23 VCCIO5 AR26 AL22 AP25 AN24 AM23 AL23 AR27 AP26 AN25 AR28
672-Pin FineLine
AA14 AA15 AB13 AB14 AB15 AB16 VCCIO5 AA16 AB17 AA17 AB18 AA18 VCCIO5 AA19 AB20 AB19 AA20
Altera Corporation
APEX Programmable Logic Device Family
Preliminary Information
Table EP20K200E Pins (Part
VREF Bank
Note
240-Pin RQFP
VCCIO5 VCCIO4 VCCINT VCCIO4 VCCINT
Number Orientation
Pin/Pad Function
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