Altera Devices October 1999, ver. Introduction High-per

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Using Selectable Standards
Altera Devices
October 1999, ver.
Introduction
High-performance, low-voltage standards have been introduced keep pace with increasing clock speeds, higher data rates, lowvoltage devices. These standards used interface with memory, microprocessors, backplanes, peripheral devices. Designers want these standards with programmable logic need flexible, high-performance, multi-standard buffers. Altera's revolutionary APEX20KE devices offer highest density, highest performance programmable logic solution with necessary standards communication computer industries. Altera® MAX® 7000B devices product-term leader standard support: 7000B devices only macrocell-based devices support Gunning transceiver logic plus (GTL+), stub series terminated logic (SSTL-2), 3.3-V SSTL-3. With programmable standards supported APEX 20KE 7000B devices, single device simultaneously support multiple standards, well interface with high-speed, low-voltage memory buses backplanes. These standards include low-voltage differential signaling (LVDS), which supports data rates 622.08 million bits second (Mbps). Programmable standards simplify board design. Dedicated circuitry like LVDS integrated into programmable logic devices (PLDs), saving board space, reducing usage, improving performance. This application note provides guidelines designing with selectable standards Altera devices covers following topics:
Overview Standards Applications APEX 20KE 7000B Standards Operating Conditions Using LVDS Board Termination Schemes
Overview Standards Applications
ability PLDs support industry standards gives customers quick time-to-market design solution. This section provides overview typical applications selectable standards supported Altera devices. specifications each standard listed this section.
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117: Using Selectable Standards Altera Devices
LVTTL
low-voltage transistor-transistor logic (LVTTL) standard singleended, general-purpose standard 3.3-V applications. LVTTL interface defined JEDEC Standard JESD 8-A, Interface Standard Nominal V/3.3 Supply Digital Integrated Circuits. maximum recommended input voltage APEX 7000B devices which exceeds 3.9-V requirement this specification. LVTTL output buffer push-pull driver. This standard requires output buffer drive (minimum does require input reference voltages termination. APEX 7000B devices compliant with this standard.
LVCMOS
low-voltage CMOS (LVCMOS) standard defined JEDEC Standard JESD 8-A, Interface Standard Nominal V/3.3 Supply Digital Integrated Circuits. LVCMOS single-ended general-purpose standard also used 3.3-V applications. input buffer requirements same LVTTL requirements, output buffer required drive rail (minimum VCCIO APEX 7000B devices fully compliant with LVCMOS standard. This standard requires 3.3-V supply voltage (VCCIO), input reference voltages termination.
2.5-V standard documented JEDEC Standard JESD 8-5, ±0.2 (Normal Range) (Wide Range) Power Supply Voltage Interface Standard Nonterminated Digital Integrated Circuit. This standard similar LVCMOS used 2.5-V power supply levels. APEX 7000B devices compliant with this standard, which requires 2.5-V VCCIO, input reference voltages termination.
1.8-V standard documented JEDEC Standard JESD 8-7, ±0.15 (Normal Range) 1.95 (Wide Range) Power Supply Voltage Interface Standard Nonterminated Digital Integrated Circuit. This standard similar LVCMOS used 1.8-V power supply levels reduced input output thresholds. APEX 7000B devices compliant with this standard, which requires 1.8-V VCCIO, input reference voltages termination.
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117: Using Selectable Standards Altera Devices
3.3-V
APEX devices compliant with Local Specification, Revision 3.3-V operation. 7000B devices compliant with aspects this standard except that they offer clamps VCCIO. standard supports 64-bit width operation MHz. This standard uses LVTTL-type input output buffers requires 3.3-V VCCIO, input reference voltages termination.
LVDS
LVDS standard used very high-performance, low-powerconsumption data transfer. industry standards define LVDS: IEEE 1596.3 SCI-LVDS ANSI/TIA/EIA-644. Both standards have similar features, IEEE standard supports maximum data transfer Mbps. APEX 20KE devices designed meet ANSI/TIA/EIA-644 requirements Mbps. LVDS standard requires 3.3-V VCCIO 100- termination resistor between traces input buffer. input reference voltage required. more information LVDS, "Using LVDS" page Altera site (http://www.altera.com).
GTL+
GTL+ standard high-speed standard first used Intel Corporation interfacing with Pentium processor. GTL+ voltage-referenced standard requiring 1.0-V input reference voltage (VREF) board termination voltage (VTT) Because GTL+ open-drain standard, does require particular VCCIO supply voltage. APEX 20KE 7000B devices compliant with this standard. GTL+ often used processor interfacing communication across backplane.
SSTL-2 Class
SSTL-2 standard, specified JEDEC Standard JESD 8-9, Stub-Series Terminated Logic Volts (SSTL-2), voltage-referenced standard requiring 1.125-V VREF, 2.5-V VCCIO, 1.125-V VTT. APEX 20KE 7000B devices compliant with this standard. SSTL-2 used high-speed SDRAM interfaces.
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117: Using Selectable Standards Altera Devices
SSTL-3 Class
SSTL-3 standard, specified JEDEC Standard JESD 8-8, Stub-Series Terminated Logic Volts (SSTL-3), voltage-referenced standard requiring 1.5-V VREF, 3.3-V VCCIO, 1.5-V VTT. APEX 20KE 7000B devices compliant with this standard. SSTL-3 used high-speed SDRAM interfaces.
advanced graphics port (AGP) standard specified Advanced Graphics Port Interface Specification Revision introduced Intel Corporation graphics applications. voltage referenced standard requiring 1.32-V VREF, 3.3-V VCCIO, does require termination. APEX 20KE devices support interface.
center-tap-terminated (CTT) standard specified JEDEC Standard JESD 8-4, Center-Tap-Terminated (CTT) Low-Level, High-Speed Interface Standard Digital Integrated Circuits. voltage referenced standard requiring 1.5-V VREF, 3.3-V VCCIO, 1.5-V VTT. standard superset LVTTL LVCMOS. receivers compatible with LVCMOS LVTTL standards. drivers, when unterminated, compatible with specifications LVCMOS LVTTL.
Software Support
Selectable standards programmable block basis both APEX 20KE 7000B devices. APEX 20KE devices have total blocks including LVDS blocks. LVDS blocks also used other standards when used LVDS. 7000B devices have blocks; standards supported 7000B devices shown Table page Quartusand MAX+PLUS® software tools define standard used each block. Software support selectable standards provided Quartus MAX+PLUS software. Quartus software versions 1999.10 higher supports selectable standards APEX 20KE devices, MAX+PLUS software versions higher supports standards 7000B devices. information Quartus MAX+PLUS software tools will support these standards, contact Altera Applications.
Altera Corporation
117: Using Selectable Standards Altera Devices
APEX 20KE 7000B Standards
APEX 20KE blocks support standards only PLDs industry with LVDS. 7000B family support GTL+, SSTL-2, SSTL-3 unique among product-term-based PLDs. programmable input/output element (IOE) blocks both APEX 20KE 7000B devices have individual power planes with separate supply voltage (VCCIO) pins each block. VCCIO supply supports 3.3-V, 2.5-V, 1.8-V levels.
APEX 20KE 7000B Standards
APEX 20KE 7000B buffers meet voltage, drive strength, characteristics necessary comply with standards listed Table
Table APEX 20KE 7000B Supported Standards
Standard Device APEX 20KE 7000B v(2) Type Input Output Supply Board Reference Voltage Termination Voltage (VCCIO) Voltage (VREF) (VTT)
1.125 1.32 1.125
LVTTL LVCMOS LVDS GTL+ SSTL-2 Class SSTL-3 Class Notes:
Single-ended Single-ended Single-ended Single-ended Single-ended Differential Voltage referenced Voltage referenced Voltage referenced Voltage referenced Voltage referenced
values shown VREF, VCCIO, typical values. 7000B devices have diode clamp VCCIO. These devices comply with other 64-bit/66-MHz 3.3-V specifications.
Each standard different VREF, VTT, VCCIO requirements. more information, refer "Board Termination Schemes" page
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117: Using Selectable Standards Altera Devices
APEX 20KE devices FineLine BGApackages have eight programmable blocks LVDS blocks. Figure shows representation blocks. APEX 20KE designs that LVDS, LVDS blocks used other standard.
Figure APEX 20KE Blocks
Block Block
Block Block Regular Blocks Support LVTTL LVCMOS GTL+ SSTL-2 Class SSTL-3 Class Individual Power LVDS Input Block
LVDS Output Block Block
Block
Block
Block
Note:
first pins that border LVDS blocks only used input maintain acceptable noise level VCCIO plane. LVDS input output blocks used LVDS, they support standards used input, output, bidirectional pins with VCCIO
7000B Standards
Each 7000B device programmable blocks. Each block configured independently utilize standards supported 7000B devices. Additionally, standards with common VCCIO voltages simultaneously within single block. Each programmable block power supply with separate VCCIO pins support 3.3-V, 2.5-V, 1.8-V voltage levels. Figure shows representation 7000B programmable blocks.
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Figure 7000B Blocks
Notes (1), (2),
Programmable Blocks LVTTL LVCMOS 3.3-V GTL+ SSTL-2 Class SSTL-3 Class Individual Power
Notes:
input referenced available VREF levels. 7000B devices have VREF pins that referenced both blocks. output drivers dependent VCCIO. VCCIO pins each block powered different voltage.
standards supported 7000B devices listed Figure
Operating Conditions
Tables through list operating specifications supported standards. These tables list minimal specifications only. APEX 20KE 7000B devices exceed these specifications. Consult individual device data sheets details.
Table LVTTL Input Specifications
Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
-0.3
Maximum
VCCIO
Units
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Table LVCMOS Input Specifications
Symbol
VCCIO
Parameter
Power supply voltage range High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
-0.3
Maximum
VCCIO
Units
VCCIO 3.0, -0.1 VCCIO 3.0, VCCIO
Table 2.5-V Specifications
Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage
Conditions
Minimum
2.375 -0.3
Maximum
2.625 VCCIO
Units
-0.1
Low-level output voltage
Table 1.8-V Specifications
Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
Maximum
0.35 VCCIO
Units
0.65 VCCIO VCCIO VCCIO 0.45 0.45
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Table 3.3-V LVDS Specifications
Symbol
VCCIO
Parameter
supply voltage Differential output voltage Change between high Output offset voltage Change between high
Conditions
Minimum
Typical
Maximum
Units
1.125
1.25
1.375
Differential input threshold Receiver input voltage range Receiver differential input resistor (external APEX devices)
-100
Table 3.3-V Specifications
Symbol
VCCIO
Parameter
supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
VCCIO -0.5
Typical
Maximum
VCCIO VCCIO
Units
VCCIO IOUT -500 IOUT 1,500 VCCIO
VCCIO
Table GTL+ Specifications
Symbol
VREF
Parameter
Termination voltage Reference voltage High-level input voltage Low-level input voltage Low-level output voltage
Conditions
Minimum
1.35 0.88 VREF
Typical
Maximum
1.65 1.12 VREF
Units
0.65
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Table SSTL-2 Class Specifications
Symbol
VCCIO VREF
Parameter
supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VREF 0.04 1.15 VREF 0.18 -0.3
Typical
VREF 1.25
Maximum
VREF 0.04 1.35 VCCIO VREF 0.18 0.57
Units
-7.6
0.57
Table SSTL-2 Class Specifications
Symbol
VCCIO VREF
Parameter
supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VREF 0.04 1.15 VREF 0.18 -0.3
Typical
VREF 1.25
Maximum
VREF 0.04 1.35 VCCIO VREF 0.18 0.76
Units
-15.2 15.2
0.76
Table SSTL-3 Class Specifications
Symbol
VCCIO VREF
Parameter
supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VREF 0.05 VREF -0.3
Typical
VREF
Maximum
VREF 0.05 VCCIO VREF
Units
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Table SSTL-3 Class Specifications
Symbol
VCCIO VREF
Parameter
supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VREF 0.05 VREF -0.3
Typical
VREF
Maximum
VREF 0.05 VCCIO VREF
Units
Table 3.3-V Input Specifications
Symbol
VCCIO VREF Note:
VREF specifies center point switching range.
Parameter
supply voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input leakage current
Conditions
Minimum
3.15 0.39 VCCIO VCCIO
Typical
Maximum
3.45 0.41 VCCIO VCCIO VCCIO VCCIO
Units
IOUT IOUT VCCIO
VCCIO
Table Specifications
Symbol
VCCIO VTT/VREF
Parameter
supply voltage Termination reference voltage High-level input voltage Low-level input voltage
Conditions
Minimum
1.35 VREF
Typical
Maximum
1.65
Units
VREF VREF VREF
Input leakage current VCCIO High-level output voltage Low-level output voltage Output leakage current (when output high
VOUT VCCIO
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Using LVDS
LVDS standard high-speed, low-voltage swing, low-power, general-purpose interface standard. LVDS requires differential input does need input reference voltage. Typical uses LVDS interfaces high-bandwidth data transfer, backplane driver, clock distribution applications.
Efficiency
LVDS power-efficient standard. Because contains low-switching voltage (typically current channel, power dissipation signal small. load power dissipation 1.225 channel
Electromagnetic Interference
low-voltage swing LVDS standard, electromagnetic interference (EMI) effects much smaller than with CMOS, TTL, even PECL. radiated noise created from acceleration electric charges within device across transmission medium between devices. Device-generated dependent frequency, outputvoltage swing, slew rate. Figure shows that system powersupply noise affect signal quality because they coupled equally both LVDS signals.
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Figure LVDS Rejects System-Level Noise
Common Mode Noise from Power Supply Rejected
APEX 20KE LVDS Interface
APEX 20KE devices have dedicated circuitry LVDS block manage 622.08-Mbps data transfer. example, LVDS phase-locked loop (PLL) used boost LVDS input clock from 77.76 622.08 SONET OC-12 applications. also phase-aligns clock with incoming data. Figure shows block diagram LVDS circuitry.
Figure Dedicated LVDS Circuitry
APEX 20KE LVDS
Serial Data 622.08 Mbps data[7.0] Built-In Serial-to-Parallel Converter
CLK_LVDS2 77.76 Clock
622.08 LVDS Dedicated Clock 77.76
incoming serial LVDS channels either bypass serial-toparallel converter. serial-to-parallel converter built into dedicated silicon, does consume LEs. parallel converter operate different data-conversion modes: 8-to-1, 7-to-1, 4-to-1, 1-to-1. LVDS clocked input clock frequency 8-to-1, 7-to-1, 4-to-1, 1-to-1 data conversion, respectively. 8-to-1 conversion mode shown Figure LVDS also clock internal logic within device.
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Data synchronization necessary 8-to-1, 7-to-1, 4-to-1 modes. example, with 8-to-1 data conversion 77.76-MHz clock frequency, external clock multiplied phase-aligned with data ensure successful data capture serial-to-parallel converter. Figure shows data synchronization timing diagram 8-to-1 data conversion mode.
Figure Internal Data Synchronization
Signal Changes Here Signal Stable Sampling
Clock (77.76 MHz) LVDS Signal Internal LVDS Clock
input LVDS channels input block, together with LVDS PLL, clock serial-to-parallel converter receiver. parallel-toserial converter clocked separate drives output LVDS channels transmitter. LVDS transmitter converts maximum CMOS data bits on-chip into LVDS data streams using 8-to-1 parallel-to-serial converter. Similarly, LVDS receiver converts LVDS data streams back into CMOS data bits. Figure
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Figure LVDS Receiver Transmitter Interface
Loadable Shift Register Loadable Shift Register
lvdsin1 lvdsin1a
lvdsout1 lvdsout1a
User Logic
clklvds_out clk_lvds2 clk_lvds2a
clklvds_outa
clk_lvds3 clk_lvds3a
internal clocks have maximum multiplication rate LVDS transmitter ability drive locked clock off-chip. external clock transmits signals phase with LVDS data streams. Every cycle, LVDS channels sample bits input output data. LVDS input pins pins located right side device. Each LVDS input channel interfaces with dedicated shift registers drives lines. Similarly, LVDS output pins pins located left side device. Each LVDS output channel interfaces with dedicated shift registers, driven peripheral LEs.
APEX 20KE LVDS Features
LVDS standard offers fast pins registers improved setup clock-to-output times. LVDS standard also supports hot-socketing operation; pins driven before device powered
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Board Termination Schemes
various standards supported APEX 20KE 7000B devices require specific termination schemes achieve their high speeds. Each standard individual termination scheme. diagram Figure shows series parallel termination resistors that used with standards.
Figure Board Termination Diagram
Driving Device Receiving Device
VREF
LVDS standard requires termination resistor between signals receiving device shown Figure termination resistor should match differential load impedance ranging from typically
Figure LVDS Board Termination Receiver
Transmitting Device Receiving Device
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Table shows board termination values reference voltages that each APEX 20KE standard uses.
Table Board Termination Values
Standard
GTL+ SSTL-2 Class SSTL-2 Class SSTL-3 Class SSTL-3 Class
Output Driver
Open-drain Push-pull Push-pull Push-pull Push-pull Push-pull Push-pull
VREF
1.125 1.32
1.125 1.125
Conclusion
programmable features standards simplify board design minimizing number devices used interface with memory, microprocessors, backplanes. APEX 20KE devices 64-bit, 66-MHz compliant offer increased performance with standards features like LVDS (622.08-Mbps data transfer), programmable delays, fast APEX I/O.
References
Interface Standard Nominal V/3.3 Supply Digital Integrated Circuits, JESD8-A, Electronic Industries Association, June 1994. Stub-Series Terminated Logic Volts (SSTL-3), EIA/JESD8-8, Electronic Industries Association, August 1996. Stub-Series Terminated Logic Volts (SSTL-2), EIA/JESD8-9, Electronic Industries Association, September 1998. Electrical Characteristics Voltage Differential Signaling (LVDS) Interface Circuits, ANSI/TIA/EIA-644, American National Standards Institute/Telecommunication Industry Association/Electronic Industries Association. ±0.2 (Normal Range) (Wide Range) Power Supply Voltage Interface Standard Nonterminated Digital Integrated Circuit, EIA/JESD8-5, Electronic Industries Association, October 1995. ±0.15 (Normal Range) 1.95 (Wide Range) Power Supply Voltage Interface Standard Nonterminated Digital Integrated Circuit, EIA/JESD8-7, Electronic Industries Association, February 1997. Local Specification, Revision 2.2, Special Interest Group, December 1998.
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Altera Devices October 1999, ver. Introduction High-per

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