December 1999, ver. 1.02 Introduction APEX20K, FLEX® 10K, FL
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Configuring APEX 20K, FLEX FLEX 6000 Devices
December 1999, ver. 1.02
Introduction
APEX20K, FLEX® 10K, FLEX 6000 devices configured using configuration schemes, which ideal variety systems. configuration schemes either microprocessor configuration device. Table
Table Configuration Schemes
Configuration Scheme
Configuration Device
Device Family
APEX FLEX FLEX 6000 APEX FLEX FLEX 6000 APEX FLEX APEX FLEX FLEX 6000 APEX FLEX
Typical
Configuration with EPC2, EPC1, EPC1441 configuration devices. Configuration with serial synchronous microprocessor interface MasterBlastercommunications cable, ByteBlasterMVparallel port download cable, BitBlasterserial download cable. (1), (2), Configuration with parallel synchronous microprocessor interface. Configuration with parallel asynchronous microprocessor interface. this scheme, microprocessor treats target device memory. Configuration with serial asynchronous microprocessor interface. Configuration through IEEE Std. 1149.1 (JTAG) pins.
Passive Serial (PS)
Passive Parallel Synchronous (PPS) Passive Parallel Asynchronous (PPA) Passive Serial Asynchronous (PSA) Joint Test Action Group (JTAG) Notes:
MasterBlaster communications cable uses standard serial universal serial (USB) hardware interface that downloads configuration data APEX 20K, FLEX 10K, FLEX 6000 devices. supports operation with supported Quartussoftware MAX+PLUS® software versions higher. more information MasterBlaster cable, MasterBlaster Serial/USB Communications Cable Data Sheet. ByteBlasterdownload cable obsolete replaced ByteBlasterMV parallel port download cable. Although cannot configure FLEX 6000 devices through JTAG pins, perform JTAG boundary-scan testing. BitBlaster serial download cable supported Quartus software used configure APEX devices.
Altera Corporation
A-AN-116-01.02
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
This application note discusses configure more APEX (including APEX 20KE), FLEX (including FLEX 10KE FLEX 10KA), FLEX 6000 devices. This application note should used together with following documents:
APEX Programmable Logic Device Family Data Sheet FLEX Embedded Programmable Logic Family Data Sheet FLEX 10KE Embedded Programmable Logic Family Data Sheet FLEX 6000 Programmable Logic Device Family Data Sheet Configuration Devices APEX FLEX Devices Data Sheet appropriate, illustrations this application note show devices with generic "APEX 20K", "FLEX 10K", "FLEX 6000" labels indicate they valid APEX 20K, FLEX 10K, FLEX 6000 devices.
Contents
This application note provides information following topics: Device Configuration Overview. Configuration Schemes Configuration Device Configuration with Download Cable Configuration with Microprocessor Configuration (APEX FLEX Devices Only). Configuration (FLEX 6000 Devices Only). Configuration (APEX FLEX Devices Only). JTAG Programming Configuration (APEX FLEX Devices Only). JTAG Programming Configuration Multiple Devices (APEX FLEX Devices Only). Programming Test Language Combining Different Configuration Schemes Device Options Device Configuration Pins. Device Configuration Files Device Configuration Configuration Reliability Board Layout Tips.
Device Configuration Overview
During device operation, APEX 20K, FLEX 10K, FLEX 6000 devices store configuration data SRAM cells. Because SRAM memory volatile, SRAM cells must loaded with configuration data each time device powers After APEX 20K, FLEX 10K, FLEX 6000 device configured, registers pins must initialized. After initialization, device enters user mode in-system operation. Figure shows state device during configuration, initialization, user modes.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure APEX 20K, FLEX FLEX 6000 Configuration Cycle
nCONFIG nSTATUS CONF_DONE DCLK DATA High-Z User I/Os INIT_DONE MODE Configuration Configuration Initialization User High-Z High-Z
User
Notes:
During initial power-up configuration, CONF_DONE low. After configuration, CONF_DONE goes high. device reconfigured, CONF_DONE goes after nCONFIG driven low. User pins tri-stated during configuration. APEX FLEX 10KE devices also have weak pull-up resistor pins during configuration. After initialization, user pins perform function assigned user's design. When used, optional INIT_DONE signal high when nCONFIG before configuration during approximately first clock cycles configuration. DCLK should left floating. should driven high low, whichever more convenient. DATA (FLEX 6000 devices) DATA0 (APEX FLEX devices) should left floating. should driven high low, whichever more convenient.
configuration data APEX 20K, FLEX 10K, FLEX 6000 devices loaded using active passive configuration scheme. When using active configuration scheme with configuration device, both target device configuration device generate control synchronization signals. When both devices ready begin configuration, configuration device sends data APEX 20K, FLEX 10K, FLEX 6000 device. When using passive configuration scheme, APEX 20K, FLEX 10K, FLEX 6000 device incorporated into system with intelligent host, such microprocessor, that controls configuration process. host supplies configuration data from storage device (e.g., hard disk, RAM, other system memory). When using passive configuration, change target device's functionality while system operation reconfiguring also perform in-field upgrades distributing programming file system users. select APEX FLEX device's configuration scheme driving MSEL0 MSEL1 pins either high shown Table
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table APEX FLEX Configuration Schemes
MSEL1
Note:
Note
MSEL0
Configuration Scheme
Configuration device passive serial. Passive parallel synchronous. Passive parallel asynchronous.
MSEL1 MSEL0 pins used change configuration modes between configurations. However, they generally connected ground.
FLEX 6000 devices, MSEL controls configuration, shown Table
Table FLEX 6000 Configuration Schemes
MSEL
Note:
Note
Configuration Scheme
Configuration device passive serial scheme, using MasterBlaster, ByteBlasterMV, BitBlaster cables. Passive serial asynchronous.
MSEL used change configuration modes between configurations. However, generally connected ground.
Device option bits device configuration pins discussed further "Device Options" page "Device Configuration Pins" page respectively.
Table summarizes approximate configuration file size required each APEX 20K, FLEX 10K, FLEX 6000 device. calculate amount storage space required multi-device configurations, simply each device's file size together.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table APEX 20K, FLEX FLEX 6000 Configuration File Sizes Note
Device
EP20K1000E EP20K600E EP20K400, EP20K400E EP20K200 EP20K100 EPF10K250A EPF10K200E EPF10K130E EPF10K130V EPF10K100E EPF10K100, EPF10K100A, EPF10K100B EPF10K70 EPF10K50E EPF10K50, EPF10K50V EPF10K40 EPF10K30E EPF10K30A EPF10K30 EPF10K20 EPF10K10A EPF10K10 EPF6024A EPF6016, EPF6016A EPF6010A Note:
Binary Files (.rbf) were used determine these file sizes.
Data Size (Bits)
8,938,000 5,564,000 3,878,000 1,950,000 985,000 3,300,000 2,757,000 1,840,000 1,600,000 1,336,000 1,200,000 892,000 785,000 621,000 498,000 470,000 406,000 376,000 231,000 120,000 118,000 398,000 260,000 260,000
Data Size (Kbytes)
1,092
numbers Table should only used estimate file size before design compilation. exact file size vary because different MAX+PLUS Quartus software versions slightly different number padding bits during programming. However, specific version MAX+PLUS Quartus software, design targeted same device same configuration file size.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table lists Altera configuration devices that used configure APEX 20K, FLEX 10K, FLEX 6000 devices.
Table Configuration Devices
Device
EPC2 EPC1 EPC1441
Description
1,695,680 1-bit device with 5.0-V 3.3-V operation 1,046,496 1-bit device with 5.0-V 3.3-V operation 440,800 1-bit device with 5.0-V 3.3-V operation
data from Tables determine number configuration devices required configure your device. example, configure EPF10K100 device, need EPC1 devices only EPC2 device. Similarly, EP20K400 device requires three EPC2 devices.
Configuration Schemes
This section describes configure APEX 20K, FLEX 10K, FLEX 6000 devices with following configuration schemes:
Configuration Device Configuration with Download Cable Configuration with Microprocessor Configuration (APEX FLEX Devices Only) Configuration (FLEX 6000 Devices Only) Configuration (APEX FLEX Devices Only) JTAG Programming Configuration (APEX FLEX Devices Only) JTAG Programming Configuration Multiple Devices (APEX FLEX Devices Only)
Configuration Device
configuration device scheme uses Altera-supplied serial configuration device supply data APEX 20K, FLEX 10K, FLEX 6000 device serial bitstream. Figure
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Configuration Device Scheme Circuit
APEX FLEX Devices APEX FLEX Device
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1 nCEO N.C.
Configuration Device
DCLK DATA nINIT_CONF
FLEX 6000 Devices
FLEX 6000 Device
DCLK DATA nSTATUS CONF_DONE nCONFIG nCEO
Configuration Device
DCLK DATA nINIT_CONF
N.C.
MSEL
Notes:
pull-up resistor should connected same supply voltage configuration device. pull-up resistors EPC2 device's nCS, nINIT_CONF pins have internal, user-configurable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. nINIT_CONF available EPC2 devices only. nINIT_CONF available (i.e., EPC1 devices) used, nCONFIG must pulled either directly through resistor. nCEO left unconnected.
configuration device scheme, nCONFIG usually tied EPC2 devices, nCONFIG connected nINIT_CONF). Upon device power-up, target APEX 20K, FLEX 10K, FLEX 6000 device senses low-to-high transition nCONFIG initiates configuration. target device then drives open-drain CONF_DONE low, which in-turn drives configuration device's low. When exiting power-on reset (POR), both target configuration device release open-drain nSTATUS pin.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Before configuration begins, configuration device issues delay (maximum) allow power supply stabilize; during this time, configuration device drives low. This signal delays configuration because connected target device's nSTATUS pin. When both devices complete POR, they release nSTATUS, which then pulled high pull-up resistor. When configuring multiple devices, configuration does begin until devices release their nSTATUS pins. When devices ready, configuration device clocks data serially target devices using internal oscillator. After successful configuration, configuration device starts clocking target device initialization. CONF_DONE released target device then pulled high pull-up resistor. When initialization complete, configuration device enters user mode. error occurs during configuration, target device drives nSTATUS low, resetting itself internally resetting configuration device. Auto-Restart Configuration Frame Error option-available MAX+PLUS Global Project Device Options dialog (Assign menu)-is turned device reconfigures automatically error occurs. Quartus software provides similar option APEX devices. this option turned off, external system must monitor nSTATUS errors then pulse nCONFIG restart configuration. external system pulse nCONFIG nCONFIG under system control rather than tied VCC. When configuration complete, target device releases CONF_DONE, which disables configuration device driving high. configuration device drives DCLK before after configuration. addition, configuration device sends data then detects that CONF_DONE gone high, recognizes that target device configured successfully. this case, configuration device pulses microseconds, driving target device's nSTATUS low. Auto-Restart Configuration Frame Error option software, target device resets then pulses nSTATUS low. When nSTATUS returns high, configuration device reconfigures target device. When configuration complete, configuration device drives DCLK low.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
When CONF_DONE driven after device configuration, configuration device recognizes that target device configured successfully; therefore, should this scheme delay initialization. Instead, should MAX+PLUS Quartus software's User-Supplied Start-Up Clock option synchronize initialization multiple devices that same configuration chain. Devices same configuration chain will initialize together. more information this option, "Device Options" page Figure shows configure multiple devices with configuration device. This circuit similar configuration device circuit single device, except APEX 20K, FLEX 10K, FLEX 6000 devices cascaded multi-device configuration.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Multi-Device Configuration Circuit
APEX FLEX Devices
Note
APEX FLEX Device
MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG nCEO
APEX FLEX Device
MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Configuration Device
DCLK DATA nCASC nINIT_CONF N.C.
Configuration Device
DCLK DATA nINIT_CONF
nCEO
FLEX 6000 Devices
FLEX 6000 Device
MSEL DCLK DATA nSTATUS CONF_DONE nCONFIG
FLEX 6000 Device
MSEL DCLK DATA nSTATUS CONF_DONE nCONFIG
Configuration Device
DCLK DATA nCASC nINIT_CONF N.C.
Configuration Device
DCLK DATA nINIT_CONF
nCEO
nCEO
Notes:
When performing multi-device active serial configuration, must generate EPC1 EPC2 device's Programmer Object File (.pof) from each project's SRAM Object File (.sof). combine multiple SOFs using MAX+PLUS software's Combine Programming Files dialog (File menu). APEX devices, Quartus software provides similar option. more information create configuration programming files, "Device Configuration Files" page pull-up resistor should connected same supply voltage configuration device. pull-up resistors EPC2 device's nCS, nINIT_CONF pins have internal, user-configurable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. nINIT_CONF available EPC2 devices only. nINIT_CONF available (i.e., EPC1 devices) used, nCONFIG must pulled either directly through resistor. nCEO left unconnected last device chain.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
After first device completes configuration during multi-device configuration, nCEO activates second device's pin, prompting second device begin configuration. Because device CONF_DONE pins tied together, devices initialize enter user mode same time. addition, nSTATUS pins tied together; thus, device (including configuration devices) detects error, configuration stops entire chain. Also, first configuration device does detect CONF_DONE going high configuration, resets chain pulsing microseconds. This pulse drives second configuration device drives nSTATUS APEX 20K, FLEX 10K, FLEX 6000 devices, causing them enter error state; this state similar APEX 20K, FLEX 10K, FLEX 6000 device detecting error. Auto-Restart Configuration Frame Error option software, APEX 20K, FLEX 10K, FLEX 6000 devices release their nSTATUS pins after reset time-out period. When nSTATUS pins released pulled high, configuration devices reconfigure chain. Auto-Restart Configuration Frame Error option set, APEX 20K, FLEX 10K, FLEX 6000 devices drive nSTATUS until they reset with pulse nCONFIG. also cascade several configuration devices configure multiple APEX 20K, FLEX 10K, FLEX 6000 devices. When data from first configuration device sent, drives nCASC low, which turn drives subsequent configuration device. Because configuration device requires less than clock cycle activate subsequent configuration device, data stream uninterrupted. Figure shows timing waveform configuration device scheme.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Configuration Device Scheme Timing Waveform
VCC/nCONFIG OE/nSTATUS nCS/CONF_DONE
tPOR
tDSU
DCLK DATA User INIT_DONE
tOEZX
User Mode
Tri-State
Tri-State
Notes:
DATA should left floating. should driven high low, whichever more convenient. APEX devices, device enters user mode clock cycles after CONF_DONE goes high. FLEX FLEX 6000 devices, device enters user mode clock cycles after CONF_DONE goes high.
single configuration chain configure multiple APEX 20K, FLEX 10K, FLEX 6000 devices. this scheme, nCEO first device connected second device chain. configure properly, device CONF_DONE nSTATUS pins must tied together. Figure shows examples configuring multiple APEX 20K, FLEX 10K, FLEX 6000 devices using configuration device.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Multi-Device Configuration with APEX 20K, FLEX FLEX 6000 Devices
Configuring APEX FLEX 6000 Device
FLEX 6000 Device
MSEL DCLK DATA nSTATUS CONF_DONE nCONFIG nCEO
APEX Device
MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Configuration Device
DCLK DATA nCASC nINIT_CONF
Configuration Device
DCLK DATA nINIT_CONF
N.C.
nCEO
Configuring FLEX FLEX 6000 Device
FLEX 6000 Device
MSEL DCLK DATA nSTATUS CONF_DONE nCONFIG nCEO
FLEX Device
MSEL0 MSEL1 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Configuration Device
DCLK DATA nCASC nINIT_CONF
Configuration Device
DCLK DATA nINIT_CONF
N.C.
nCEO
Notes:
pull-up resistor should connected same supply voltage configuration device. pull-up resistors EPC2 device's nCS, nINIT_CONF pins have internal, user-configurable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. nCEO left unconnected last device chain. nINIT_CONF available EPC2 devices only. nINIT_CONF available (i.e., EPC1 devices) used, nCONFIG must pulled either directly through resistor.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table defines APEX 20K, FLEX 10K, FLEX 6000 timing parameters when using EPC2 devices
Table APEX 20K, FLEX FLEX 6000 Timing Parameters using EPC2 Devices Note
Symbol
tPOR tOEZX tDSU tOEW fCLK Notes:
more information regarding configuration device timing parameters, Configuration Devices APEX FLEX Devices Data Sheet. configuration device imposes delay upon initial power-up allow voltage supply stabilize. Subsequent reconfigurations incur this delay.
Parameter
delay high DATA output enabled DCLK high time DCLK time Data setup time before rising edge DCLK Data hold time after rising edge DCLK DCLK DATA pulse width guarantee counter reset DCLK frequency
Units
12.5
Table defines APEX 20K, FLEX 10K, FLEX 6000 timing parameters when using EPC1 EPC1441 devices
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table APEX 20K, FLEX FLEX 6000 Timing Parameters using EPC1 EPC1441 Devices Note
Symbol
tPOR tOEZX tDSU tOEW fCLK Notes:
more information regarding configuration device timing parameters, Configuration Devices APEX FLEX Devices Data Sheet. configuration device imposes delay upon initial power-up allow voltage supply stabilize. Subsequent reconfigurations incur this delay.
Parameter
delay high DATA output enabled DCLK high time DCLK time Data setup time before rising edge DCLK Data hold time after rising edge DCLK DCLK DATA pulse width guarantee counter reset DCLK frequency
Units
Table defines APEX 20K, FLEX 10K, FLEX 6000 timing parameters when using EPC2, EPC1, EPC1441 devices
Table APEX 20K, FLEX FLEX 6000 Timing Parameters using EPC2, EPC1 EPC1441 Devices Note
Symbol
tPOR tOEZX tDSU tOEW fCLK Notes:
more information regarding configuration device timing parameters, Configuration Devices APEX FLEX Devices Data Sheet. configuration device imposes delay upon initial power-up allow voltage supply stabilize. Subsequent reconfigurations incur this delay.
Parameter
delay high DATA output enabled DCLK high time DCLK time Data setup time before rising edge DCLK Data hold time after rising edge DCLK DCLK DATA pulse width guarantee counter reset DCLK frequency
Units
16.7
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
pins tri-stated after power during configuration. user mode, these pins perform their programmed function.
Table shows status device DATA pins before after configuration. (APEX FLEX devices have DATA[7.0] bus, while FLEX 6000 devices have DATA only.)
Table DATA Status Before After Configuration
Pins APEX FLEX Device Before
DATA DATA0 DATA[7.1] Notes:
status shown configuration with configuration device. function these pins depends upon settings specified MAX+PLUS software's Global Project Device Options dialog box. APEX devices, Quartus software provides similar option. more information, refer MAX+PLUS Quartus Help.
FLEX 6000 Device Before
Tri-state
After
Tri-state User defined
After
Tri-state
Tri-state User defined
information create configuration programming files this configuration scheme, "Device Configuration Files" page
Configuration with Download Cable
configuration with download cable, intelligent host transfers data from storage device APEX 20K, FLEX 10K, FLEX 6000 device MasterBlaster, ByteBlasterMV, BitBlaster cable. initiate configuration this scheme, download cable generates lowto-high transition nCONFIG pin. programming hardware then places configuration data time device's DATA (the DATA0 APEX FLEX devices, DATA FLEX 6000 devices). data clocked into target device until CONF_DONE goes high. When using programming hardware APEX 20K, FLEX 10K, FLEX 6000 devices, setting Auto-Restart Configuration Frame Error option does affect configuration cycle because MAX+PLUS Quartus software must restart configuration when error occurs. Figure shows configuration APEX 20K, FLEX 10K, FLEX 6000 devices using MasterBlaster, ByteBlasterMV, BitBlaster cable.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Configuration Circuit with MasterBlaster, ByteBlasterMV, BitBlaster Cable
APEX Device
MSEL0 MSEL1 CONF_DONE nSTATUS
nCEO
N.C.(2)
MasterBlaster ByteBlasterMV 10-Pin Male Header
DCLK DATA0 nCONFIG
FLEX Device
MSEL0 MSEL1 CONF_DONE nSTATUS
Shield
nCEO
N.C.(2)
DCLK DATA0 nCONFIG
MasterBlaster, ByteBlasterMV BitBlaster 10-Pin Male Header
Shield
FLEX 6000 Device
MSEL CONF_DONE nSTATUS
DCLK DATA nCONFIG
nCEO
N.C.(2)
MasterBlaster, ByteBlasterMV BitBlaster 10-Pin Male Header
Shield
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices Notes figure:
pull-up resistor should connected same supply voltage MasterBlaster, ByteBlasterMV, BitBlaster cable. nCEO left unconnected last device chain. Power supply voltage: MasterBlaster cable. ByteBlasterMV cable. BitBlaster cable. header reference voltage MasterBlaster output driver. should match device's VCCIO. This connect ByteBlasterMV BitBlaster header.
programming hardware configure multiple APEX 20K, FLEX 10K, FLEX 6000 devices connecting each device's nCEO subsequent device's pin. other configuration pins connected each device chain. Because CONF_DONE pins tied together, devices chain initialize enter user mode same time. addition, because nSTATUS pins tied together, entire chain halts configuration device detects error. this situation, MAX+PLUS Quartus software must restart configuration; AutoRestart Configuration Frame Error option does affect configuration cycle. Figure shows schematic configuring multiple FLEX FLEX 6000 devices with MasterBlaster, ByteBlasterMV, BitBlaster download cable.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Multi-Device Configuration FLEX FLEX 6000 Devices with Cable
MasterBlaster, ByteBlasterMV, BitBlaster 10-Pin Male Header (Passive Serial Mode)
FLEX Device
MSEL0 MSEL1
CONF_DONE nSTATUS DCLK
nCEO
DATA0 nCONFIG
FLEX 6000 Device
MSEL
CONF_DONE nSTATUS DCLK nCEO N.C.(4)
DATA nCONFIG
Notes:
pull-up resistor should connected same supply voltage MasterBlaster, ByteBlasterMV, BitBlaster cable. Power supply voltage: MasterBlaster cable. ByteBlasterMV cable. BitBlaster cable. reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. nCEO left unconnected last device chain.
Figure shows schematic configuring multiple FLEX devices with MasterBlaster, ByteBlasterMV, BitBlaster download cable.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Multi-Device Configuration Multiple FLEX Devices with Cable
MasterBlaster, ByteBlasterMV, BitBlaster 10-Pin Male Header (Passive Serial Mode)
FLEX Device
MSEL0
MSEL1
CONF_DONE nSTATUS DCLK
DATA0 nCONFIG
nCEO
FLEX Device
MSEL0 MSEL1
CONF_DONE nSTATUS DCLK
nCEO
N.C.
DATA0 nCONFIG
Notes:
pull-up resistor should connected same supply voltage MasterBlaster, ByteBlasterMV, BitBlaster cable. Power supply voltage: MasterBlaster cable. ByteBlasterMV cable. BitBlaster cable. reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. nCEO left unconnected last device chain.
Figure shows schematic configuring multiple APEX FLEX devices with MasterBlaster, ByteBlasterMV, BitBlaster cable.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Multi-Device Configuration APEX FLEX Devices with Cable
MasterBlaster ByteBlasterMV 10-Pin Male Header (Passive Serial Mode)
APEX Device
MSEL0
MSEL1
CONF_DONE nSTATUS DCLK
nCEO
DATA0 nCONFIG
FLEX Device
MSEL0 MSEL1
CONF_DONE nSTATUS DCLK
nCEO
N.C.
DATA0 nCONFIG
Notes:
pull-up resistor should connected same supply voltage MasterBlaster, ByteBlasterMV, BitBlaster cable. Power supply voltage: MasterBlaster cable. ByteBlasterMV cable. BitBlaster cable. reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. nCEO left unconnected last device chain.
using MasterBlaster, ByteBlasterMV, BitBlaster cable configure device(s) board that also configuration devices, should electrically isolate configuration device from target device(s) cable. isolate configuration device logic, such multiplexer, that select between configuration device cable. Another option switches five common signals (i.e., CONF_DONE, nSTATUS, DCLK, nCONFIG, DATA0) between cable configuration device. last option remove configuration device from board when configuring with cable. Figure shows combination configuration device MasterBlaster, ByteBlasterMV, BitBlaster cable configure FLEX device.
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116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Configuring with Combined Configuration Device Scheme
MasterBlaster (2), ByteBlasterMV, BitBlaster 10-Pin Male Header (Passive Serial Mode)
FLEX Device
MSEL0 MSEL1 DATA0 nCONFIG nCEO N.C. CONF_DONE nSTATUS DCLK
Configuration Device
DCLK DATA nINIT_CONF
Notes:
pull-up resistor should connected same supply voltage configuration device. Refer MasterBlaster Serial/USB Communications Cable Data Sheet more information MasterBlaster cable. Power supply voltage: MasterBlaster cable. ByteBlasterMV cable. BitBlaster cable. header reference voltage MasterBlaster output driver. should match target device's VCCIO. This connect ByteBlasterMV BitBlaster header. nCEO left unconnected. should attempt configuration with MasterBlaster, ByteBlasterMV, BitBlaster cable while configuration device connected APEX 20K, FLEX 10K, FLEX 6000 device. Instead, should either remove configuration device from socket when using download cable place switch five common signals between download cable configuration device. nINIT_CONF available EPC2 devices only. nINIT_CONF available (i.e., EPC1 devices) used, nCONFIG must pulled either directly through resistor.
more information MasterBlaster, ByteBlasterMV, BitBlaster cables, following documents:
MasterBlaster Serial/USB Communications Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet BitBlaster Serial Download Cable Data Sheet information create configuration programming files this configuration scheme, "Device Configuration Files" page
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116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Configuration with Microprocessor
configuration with microprocessor, microprocessor transfers data from storage device target APEX 20K, FLEX 10K, FLEX 6000 device programming hardware. initiate configuration this scheme, microprocessor must generate low-to-high transition nCONFIG target device must release nSTATUS. microprocessor programming hardware then places configuration data time DATA target device (the DATA0 APEX FLEX devices, DATA FLEX 6000 devices). least significant (LSB) each data byte must presented first. Data clocked continuously into target device until CONF_DONE goes high. After data transferred, DCLK must clocked additional times FLEX FLEX 6000 devices additional times APEX devices initialize device. device's CONF_DONE goes high show successful configuration start initialization. configuration files created MAX+PLUS Quartus software incorporate extra bits initialization. Driving DCLK device after configuration does affect device operation. Therefore, sending entire configuration file device sufficient configure initialize Handshaking signals used configuration modes. Therefore, configuration clock speed must below specified frequency ensure correct configuration. maximum DCLK period exists. pause configuration halting DCLK. target device detects error during configuration, drives nSTATUS alert microprocessor. microprocessor then pulse nCONFIG restart configuration process. Alternatively, Auto-Restart Configuration Frame Error option MAX+PLUS Quartus software, target device releases nSTATUS after reset time-out period. After nSTATUS released, microprocessor reconfigure target device without needing pulse nCONFIG low. microprocessor also monitor CONF_DONE INIT_DONE pins ensure successful configuration. microprocessor sends data initialization clock starts CONF_DONE gone high, must reconfigure target device. Figure shows circuit configuration with microprocessor.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Configuration Circuit with Microprocessor
APEX FLEX Devices
Memory
ADDR DATA0
APEX FLEX Device
MSEL1 CONF_DONE nSTATUS nCEO MSEL0 N.C.
Microprocessor
DATA0 nCONFIG DCLK
FLEX 6000 Devices
Memory
ADDR DATA
FLEX 6000 Device
MSEL CONF_DONE nSTATUS nCEO N.C.
Microprocessor
DATA nCONFIG DCLK
Notes:
pull-up resistor should connected that meets device high-level input voltage (VIH) specification. nCEO left unconnected.
multi-device configuration with microprocessor, first device's nCEO cascaded second device's pin. second device chain begins configuration within clock cycle; therefore, transfer data destinations transparent microprocessor. Because device CONF_DONE pins tied together, devices initialize enter user mode same time.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
addition, nSTATUS pins tied together; thus, device detects error, entire chain halts configuration drives nSTATUS low. microprocessor then pulse nCONFIG restart configuration process. Alternatively, Auto-Restart Configuration Frame Error option MAX+PLUS Quartus software, target devices release nSTATUS after reset time-out period. After nSTATUS released, microprocessor reconfigure target devices. Figure shows multi-device configuration with microprocessor.
Figure Multi-Device Configuration with Microprocessor
APEX FLEX Devices
Memory
ADDR DATA0
APEX FLEX Device
MSEL1 CONF_DONE nSTATUS nCEO MSEL0
APEX FLEX Device
MSEL1 CONF_DONE nSTATUS nCEO N.C. MSEL0
Microprocessor
DATA0 nCONFIG DCLK DATA0 nCONFIG DCLK
FLEX 6000 Devices
Memory
ADDR DATA
FLEX 6000 Device
MSEL CONF_DONE nSTATUS nCEO
FLEX 6000 Device
MSEL CONF_DONE nSTATUS nCEO N.C.
Microprocessor
DATA nCONFIG DCLK DATA nCONFIG DCLK
Notes:
pull-up resistor should connected supply that provides acceptable power level devices chain. example, when device chain contains mixture 5.0-V FLEX devices 2.5-V FLEX 10KE devices, pull-up resistor should connected should this scenario because FLEX 10KE pins 5.0-V tolerant. nCEO left unconnected last device chain.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure shows configuration timing waveform APEX 20K, FLEX 10K, FLEX 6000 devices.
Figure Timing Waveform APEX 20K, FLEX FLEX 6000 Devices
tCF2ST1 tCFG
nCONFIG
tCF2CK
nSTATUS
tSTATUS tCF2ST0 tCF2CD ST2CK
CONF_DONE
DCLK
DATA
tDSU
User INIT_DONE High-Z User Mode
tCD2UM
Notes:
Upon power-up, nSTATUS held more than when reaches minimum requirement. Upon power-up before configuration, CONF_DONE low. DATA should left floating. should driven high low, whichever more convenient.
Tables contain preliminary timing information APEX 20K, FLEX 10K, FLEX 6000 devices.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table Timing Parameters APEX Devices
Symbol
tCF2CD tCF2ST0 tCF2ST1 tCFG tSTATUS tCF2CK tST2CK tDSU tCLK fMAX tCD2UM
Parameter
nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG nSTATUS high nCONFIG pulse width nSTATUS pulse width nCONFIG high first rising edge DCLK nSTATUS high first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK DCLK high time DCLK time DCLK period DCLK maximum frequency CONF_DONE high user mode
Units
16.7
Table Timing Parameters FLEX FLEX 6000 Devices
Symbol
tCF2CD tCF2ST0 tCF2ST1 tCFG tSTATUS tCF2CK tST2CK tDSU tCLK fMAX tCD2UM
Parameter
nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high nCONFIG pulse width nSTATUS pulse width nCONFIG high first rising edge DCLK nSTATUS high first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK DCLK high time DCLK time DCLK period DCLK maximum frequency CONF_DONE high user mode
Units
16.7
Notes tables:
configuration stopped reinitiated before CONF_DONE goes high, this value applies when internal oscillator selected clock source. configuration stopped reinitiated before CONF_DONE goes high clock source CLKUSR DCLK, multiply clock period APEX devices FLEX FLEX 6000 devices. minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR DCLK, multiply clock period APEX devices FLEX FLEX 6000 devices obtain this value.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure shows multi-device configuration circuit with APEX 20K, FLEX 10K, FLEX 6000 devices using microprocessor.
Figure Multi-Device Configuration APEX 20K, FLEX FLEX 6000 Devices with Microprocessor
Memory
ADDR DATA0
FLEX 6000 Device
MSEL CONF_DONE nSTATUS nCEO
APEX FLEX Device
MSEL1 MSEL0 CONF_DONE nSTATUS DATA0 nCEO N.C.
Microprocessor
DATA nCONFIG DCLK
nCONFIG DCLK
Notes:
pull-up resistor should connected supply that provides acceptable power level devices chain. example, when device chain contains mixture 5.0-V FLEX devices 2.5-V FLEX 10KE devices, pull-up resistor should connected should this scenario because FLEX 10KE pins 5.0-V tolerant. nCEO left unconnected last device chain.
information create configuration programming files this configuration scheme, "Device Configuration Files" page
Configuration (APEX FLEX Devices Only)
passive parallel synchronous (PPS) configuration scheme, intelligent host drives target APEX FLEX device. host system outputs parallel data serializing clock device. target device latches byte-wide data DATA[7.0] pins, serializes internally.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
DCLK, CONF_DONE, nCONFIG, nSTATUS, DATA[7.0] pins connected port intelligent host, such microprocessor. begin configuration, nCONFIG given low-to-high transition host places 8-bit configuration word target device's data inputs. host clocks target device; data should presented host latched target device every eight clock cycles. first rising clock edge, byte configuration data latched into target device; subsequent eight falling clock edges serialize data device. ninth rising clock edge, next byte configuration data latched serialized into target device. status (RDYnBSY) target device indicates when serializing data when ready accept next data byte. error occurs during configuration, nSTATUS drives low. host senses this signal begins reconfiguration issues error. Once target device configures successfully, releases CONF_DONE pin. When CONF_DONE goes high, indicates that configuration complete. After last data byte, DCLK must clocked times APEX devices times FLEX devices release CONF_DONE initialize device. Figure
Figure Configuration Circuit
Note
APEX FLEX Device
MSEL0
Memory
ADDR DATA[7.0]
MSEL1 CONF_DONE nSTATUS
Microprocessor
DATA[7.0] DCLK nCONFIG
Note:
FLEX devices, configuration word Tabular Text File (.ttf), Binary File (.rbf), Hexadecimal (.hex) format; APEX devices, configuration word format. information create configuration programming files, "Device Configuration Files" page
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
configure multiple APEX FLEX devices mode cascading devices. Once first device configured, drives nCEO low, driving second device's low. second device begins configuration within clock cycle. Because device CONF_DONE pins tied together, devices initialize enter user mode same time. addition, nSTATUS pins tied together; thus, device detects error, entire chain reset automatic reconfiguration. Figure
Figure Multi-Device Configuration Circuit
APEX FLEX Device Memory
ADDR DATA[7.0] MSEL0
APEX FLEX Device
MSEL0
MSEL1 CONF_DONE nSTATUS nCEO
MSEL1 CONF_DONE nSTATUS DATA[7.0] DCLK nCONFIG
Microprocessor
DATA[7.0] DCLK nCONFIG
Figure shows timing waveforms configuration APEX FLEX devices.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Timing Waveform APEX FLEX Devices
tCFG
nCONFIG nSTATUS DCLK DATA[7.0] RDYnBSY CONF_DONE INIT_DONE User
High High User Mode
tCF2CK
Cycles
tCLK
tDSU
Byte
tCH2B
Byte
Byte
User Mode User Mode
tCD2UM
Tables define timing parameters configuration APEX FLEX devices.
Table Timing Parameters APEX Devices
Symbol
tCF2CK tDSU tCH2B tCFG tCLK fMAX tCD2UM Notes:
This parameter depends DCLK frequency. RDYnBSY signal goes high clock cycles after rising edge DCLK. This value calculated with DCLK frequency MHz. This value applies only internal oscillator selected clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value. minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value.
Parameter
nCONFIG high first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK First rising DCLK first rising RDYnBSY nCONFIG pulse width DCLK high time DCLK time DCLK period DCLK frequency CONF_DONE high user mode
0.75
Units
16.7
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table Timing Parameters FLEX Devices
Symbol
tCF2CK tDSU tCH2B tCFG tCLK fMAX tCD2UM Notes:
This parameter depends DCLK frequency. RDYnBSY signal goes high clock cycles after rising edge DCLK. This value calculated with DCLK frequency MHz. This value applies only internal oscillator selected clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value. minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this number.
Parameter
nCONFIG high first rising edge DCLK Data setup time before rising edge DCLK Data hold time after rising edge DCLK First rising DCLK first rising RDYnBSY nCONFIG pulse width DCLK high time DCLK time DCLK period DCLK frequency CONF_DONE high user mode
0.75
Units
information create configuration programming files this configuration scheme, "Device Configuration Files" page
Configuration (FLEX 6000 Devices Only)
passive serial asynchronous (PSA) configuration, microprocessor drives data FLEX 6000 device download cable. When mode, should pull DCLK high using pull-up resistor prevent unused configuration pins from floating. begin configuration, microprocessor drives nCONFIG high then pulls FLEX 6000 device's high. microprocessor places configuration FLEX 6000 device's DATA input pulses write data FLEX 6000 device. next rising edge nWS, FLEX 6000 device latches configuration data. Next, FLEX 6000 device drives RDYnBSY signal low, indicating that processing configuration data. microprocessor then perform other system functions while FLEX 6000 device processing data bit.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Afterward, microprocessor checks nSTATUS CONF_DONE. device asserts nSTATUS low, encountered error microprocessor should restart configuration. nSTATUS configuration data been received, FLEX 6000 device ready initialization. beginning initialization, CONF_DONE goes high indicate that configuration complete. both nSTATUS CONF_DONE low, microprocessor sends next data bit. microprocessor also monitor CONF_DONE INIT_DONE pins ensure successful configuration. microprocessor sent configuration data started initialization CONF_DONE high, microprocessor must reconfigure FLEX 6000 device. MAX+PLUS II-generated programming files include extra bits required initialize device configuration. However, configuration, FLEX 6000 device initialize itself. Therefore, FLEX 6000 device asserts CONF_DONE high initializes itself before data sent. microprocessor stop sending configuration data when CONF_DONE asserted high. FLEX 6000 device's pins toggled during configuration design meets specifications specified tCSSU, tWSP, tCSH Table page Figure shows configuration FLEX 6000 devices.
Figure Configuration Circuit FLEX 6000 Devices
FLEX 6000 Device
CONF_DONE nSTATUS nCEO MSEL
Microprocessor
DATA nCONFIG RDYnBSY
Notes:
pull-up resistor should connected same supply voltage FLEX 6000 device. nCEO left unconnected.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
optional address decoder control device's pins. This decoder allows microprocessor select FLEX 6000 device accessing particular address, simplifying configuration process. microprocessor also control signals directly. signals active state (i.e., tied low) other signal toggled control configuration. FLEX 6000 device process data internally without microprocessor. When device ready next configuration data, pulls RDYnBSY high, causing microprocessor strobe next configuration data into FLEX 6000 device. Alternatively, signal strobed low, causing RDYnBSY signal appear DATA. simplify configuration, microprocessor wait tBUSY time (the maximum RDYnBSY pulse time) before sending next data bit. Because RDYnBSY does need monitored, strobing read state configuration data saves system port. should drive data onto DATA while because causes contention. used monitor configuration, should tied high. After configuration, nCS, nRS, nWS, RDYnBSY pins user pins. However, when using scheme, these pins tri-stated user mode should driven microprocessor. FLEX 6000 device detects error during configuration, drives nSTATUS alert microprocessor. microprocessor then pulse nCONFIG restart configuration process. Alternatively, Auto-Restart Configuration Frame Error option MAX+PLUS Quartus software, FLEX 6000 device releases nSTATUS after reset time-out period. After nSTATUS released, microprocessor reconfigure FLEX 6000 device. this point, microprocessor does need pulse nCONFIG low. mode also used configure multiple FLEX 6000 devices. Multi-device configuration similar single-device configuration, except that FLEX 6000 devices cascaded. After first FLEX 6000 device configured, nCEO asserted low, which asserts second device's low, causing begin configuration. second FLEX 6000 device begins configuration within write cycle first device; therefore, transfer data destinations transparent microprocessor. FLEX 6000 device CONF_DONE pins tied together, FLEX 6000 devices initialize enter user mode same time. more than five FLEX 6000 devices used, Altera recommends using buffers split fan-out DCLK signal. Figure
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Multi-Device Configuration Circuit FLEX 6000 Devices
FLEX 6000 Device
MSEL CONF_DONE nSTATUS DATA nCONFIG RDYnBSY nCEO
FLEX 6000 Device
MSEL CONF_DONE nSTATUS nCEO N.C.
Microprocessor
DATA nCONFIG RDYnBSY
Notes:
pull-up resistor should connected same supply voltage FLEX 6000 device. nCEO left unconnected last device chain.
Figure shows FLEX 6000 timing waveforms configuration.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Timing Waveforms FLEX 6000 Devices
tCFG
nCONFIG
tST2WS
nSTATUS
tSTATUS
CONF_DONE DATA
tCSH
tCSSU
tWSP tCSSU
tRDY2WS
tWS2B tBUSY
RDYnBSY User INIT_DONE
Notes:
Upon power-up, nSTATUS held more than when reaches minimum requirement. DATA should left floating. should driven high low, whichever more convenient. After configuration, state nCS, nWS, RDYnBSY depends design programming FLEX 6000 device. Device pins user mode.
Figure shows FLEX 6000 timing waveforms when using strobed signal.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Timing Waveforms Using FLEX 6000 Devices
tCFG tCF2WS
nCONFIG nSTATUS CONF_DONE DATA (Microprocessor)
tCSSU tCF2ST1 tST2WS tDSU
tRDY2WS tWSP tCSH
tWS2RS tRSD7 tRS2WS tCSSU
DATA (FLEX 6000)
tSTATUS tCF2ST0 tCF2CD
Notes:
Upon power-up, nSTATUS held more than when reaches minimum requirement. DATA should left floating. should driven high low, whichever more convenient. After configuration, state nCS, nWS, nRS, RDYnBSY depends design programming FLEX 6000 device. Device pins user mode.
Table summarizes timing parameters configuration.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table Timing Parameters FLEX 6000 Devices
Symbol
tCFG tSTATUS tCF2ST1 tST2WS tCF2WS tDSU tCSSU tCSH tWSP tWS2B tBUSY tRDY2WS tWS2RS tRS2WS tRSD7 tCF2CD tCF2ST0 Note:
This value applies only internal oscillator selected clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value.
Parameter
nCONFIG pulse width nSTATUS pulse width nCONFIG high nSTATUS high nSTATUS high first rising edge nCONFIG high first rising edge Data setup time before rising edge Data hold time after rising edge Chip select setup time before rising edge Chip select hold time after rising edge pulse width rising edge RDYnBSY RDYnBSY pulse width RDYnBSY rising edge falling edge rising edge falling edge rising edge falling edge falling edge DATA7 valid with RDYnBSY signal nCONFIG CONF_DONE nCONFIG nSTATUS
Units
information create configuration programming files this configuration scheme, "Device Configuration Files" page
Configuration (APEX FLEX Devices Only)
passive parallel asynchronous (PPA) schemes, microprocessor drives data APEX FLEX device download cable. When using scheme, should pull DCLK high through pull-up resistor prevent unused configuration pins from floating.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
begin configuration, microprocessor drives nCONFIG high then asserts target device's high. Next, microprocessor places 8-bit configuration word target device's data inputs pulses low. rising edge nWS, target device latches byte configuration data then drives RDYnBSY signal low, indicating that processing byte configuration data. microprocessor then perform other system functions while APEX FLEX device processing byte configuration data. Next, microprocessor checks nSTATUS CONF_DONE. both nSTATUS CONF_DONE low, microprocessor sends next data byte. nSTATUS low, device signaling error microprocessor should restart configuration. However, nSTATUS configuration data been received, device ready initialization. beginning initialization, CONF_DONE goes high indicate that configuration complete. Figure shows configuration circuit. optional address decoder controls device pins. This decoder allows microprocessor select APEX FLEX device accessing particular address, simplifying configuration process.
Figure Configuration Circuit APEX FLEX Devices
Address Decoder ADDR
Memory
ADDR DATA[7.0]
APEX FLEX Device CONF_DONE nSTATUS MSEL1 MSEL0
nCEO
Microprocessor
DATA[7.0] nCONFIG RDYnBSY
Note:
nCEO left unconnected.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
device's pins toggled during configuration design meets specifications specified tCSSU, tWSP, tCSH Tables page signals also controlled directly microprocessor. signals active state (i.e., tied low) other signal toggled control configuration. APEX FLEX devices serialize data internally without microprocessor. When APEX FLEX device ready next byte configuration data, drives RDYnBSY high. microprocessor senses high signal when polls RDYnBSY, microprocessor strobes next byte configuration data into device. Alternatively, signal strobed, causing RDYnBSY signal appear DATA7. Because RDYnBSY does need monitored, reading state configuration data strobing saves system port. Data should driven onto data while because causes contention DATA7. used monitor configuration, should tied high. simplify configuration, microprocessor wait tBUSY time (the maximum RDYnBSY pulse time) before sending next data bit. After configuration, nCS, nRS, nWS, RDYnBSY pins user pins. However, when scheme chosen MAX+PLUS Quartus software, these pins tri-stated user mode should driven microprocessor. APEX FLEX device detects error during configuration, drives nSTATUS alert microprocessor. microprocessor then pulse nCONFIG restart configuration process. Alternatively, Auto-Restart Configuration Frame Error option been MAX+PLUS Quartus software, APEX FLEX device releases nSTATUS after reset time-out period. After nSTATUS released, microprocessor reconfigure APEX FLEX device. this point, microprocessor does need pulse nCONFIG low. microprocessor also monitor CONF_DONE INIT_DONE pins ensure successful configuration. CONF_DONE must monitored microprocessor detect errors determine when programming completes. microprocessor sends configuration data starts initialization CONF_DONE asserted, microprocessor must reconfigure APEX FLEX device.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
mode also used configure multiple APEX FLEX devices. Multi-device configuration similar single-device configuration, except that APEX FLEX devices cascaded. After first APEX FLEX device configured, nCEO asserted, which asserts second device, causing begin configuration. second APEX FLEX device begins configuration within write cycle first device; therefore, transfer data destinations transparent microprocessor. APEX FLEX device CONF_DONE pins tied together, devices initialize enter user mode same time. Figure
Figure Multi-Device Configuration Circuit APEX FLEX Devices
Address Decoder ADDR Memory
ADDR DATA[7.0] APEX FLEX Device DATA[7.0] CONF_DONE nSTATUS Microprocessor nCONFIG RDYnBSY
APEX FLEX Device DATA[7.0] CONF_DONE nSTATUS nCEO N.C. MSEL1 nCONFIG RDYnBSY MSEL0
nCEO
MSEL1 MSEL0
Notes:
used, connected directly. nCEO left unconnected last device chain. When CONF_DONE goes high, RDYnBSY triggered low. Because CONF_DONE does high until devices chain configured, device RDYnBSY pins high same time after devices have been configured.
Figure shows APEX FLEX timing waveforms configuration.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Timing Waveforms APEX FLEX Devices
tCFG tCF2ST1
nCONFIG nSTATUS CONF_DONE DATA[7.0]
tRDY2WS tST2WS
Byte
tDSU tCSSU tCF2WS
Byte
Byte
Byte
tCSSU
tWSP tCSH
tSTATUS tCF2ST0 tCF2CD tWS2B tBUSY tCD2UM
RDYnBSY
User I/Os INIT_DONE
tCFL2WS
High-Z
Notes:
Upon power-up, nSTATUS held more than when reaches minimum requirement. Upon power-up, CONF_DONE low. After configuration, state nCS, nWS, RDYnBSY depends design programmed into APEX FLEX device. Device pins user mode.
Figure shows APEX FLEX timing waveforms when using strobed signal.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Timing Waveforms Using
tCFG
nCONFIG nSTATUS CONF_DONE
tCSSU
tCSH
DATA[6.0]
tWSP tRS2WS tWS2RS tRDY2WS
Byte
tDSU
Byte
Byte
tCF2WS
INIT_DONE User
tWS2B tRSD7
tBUSY tCD2UM
DATA7/RDYnBSY
Notes:
user toggle during configuration design meets specification tCSSU, tWSP, tCSH. Device pins user mode. DATA0 should left floating. should driven high low, whichever more convenient.
Tables define APEX FLEX timing parameters configuration.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table Timing Parameters APEX Devices
Symbol
tCF2WS tDSU tCSSU tCSH tWSP tCFG tWS2B tBUSY tWS2RS tRS2WS tRSD7 tCD2UM
Note
Parameter
nCONFIG high first rising edge Data setup time before rising edge Data hold time after rising edge Chip select setup time before rising edge Chip select hold time after rising edge pulse width nCONFIG pulse width rising edge RDYnBSY RDYnBSY pulse width rising edge falling edge rising edge rising edge falling edge DATA7 valid with RDYnBSY signal CONF_DONE high user mode
Units
tRDY2WS RDYnBSY rising edge rising edge
Table Timing Parameters FLEX Devices
Symbol
tCF2WS tDSU tCSSU tCSH tWSP tCFG tWS2B tBUSY tRDY2WS tWS2RS tRS2WS tRS2D7 tCD2UM
Parameter
nCONFIG high first rising edge Data setup time before rising edge Data hold time after rising edge Chip select setup time before rising edge
Units
Chip select hold time after rising edge pulse width nCONFIG pulse width rising edge RDYnBSY RDYnBSY pulse width RDYnBSY rising edge rising edge rising edge falling edge rising edge rising edge falling edge DATA7 valid with RDYnBSY signal CONF_DONE high user mode
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices Notes tables:
This information preliminary. This value applies only internal oscillator selected clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value. minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value. This parameter value applies EPF10K10, EPF10K20, EPF10K40, EPF10K50, FLEX 10KA, FLEX 10KE devices. This parameter value applies EPF10K70 EPF10K100 devices only. minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR DCLK, multiply clock period obtain this value.
information create configuration programming files this configuration scheme, "Device Configuration Files" page
JTAG Programming Configuration (APEX FLEX Devices Only)
Joint Test Action Group (JTAG) developed specification boundary-scan testing. This boundary-scan test (BST) architecture offers capability efficiently test components PCBs with tight lead spacing. architecture test connections without using physical test probes capture functional data while device operating normally. JTAG circuitry also used shift configuration data into device.
more information JTAG boundary-scan testing, Application Note (IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices). device operating JTAG mode uses four required pins, TDI, TDO, TMS, TCK, optional pin, TRST. other pins tri-stated during JTAG configuration. should begin JTAG configuration until other configuration complete. Table shows each JTAG pin's function.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table JTAG Descriptions
Description
Test data input Test data output
Function
Serial input instructions well test programming data. Data shifted rising edge TCK. Serial data output instructions well test programming data. Data shifted falling edge TCK. tri-stated data being shifted device.
Test mode select Input that provides control signal determine transitions controller state machine. Transitions within state machine occur rising edge TCK. Therefore, must before rising edge TCK. evaluated rising edge TCK. Test clock input clock input circuitry. Some operations occur rising edge, while others occur falling edge. Active-low input asynchronously reset boundary-scan circuit. TRST optional according IEEE Std. 1149.1.
TRST Test reset input (optional) Note:
FLEX devices 144-pin thin quad flat pack (TQFP) packages have TRST pin. Therefore, TRST ignored when using these devices.
During JTAG configuration, data downloaded device through MasterBlaster, ByteBlasterMV, BitBlaster header. Configuring devices through cable similar programming devices in-system, except TRST should connected VCC; this connection ensures that controller reset. Figure
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure JTAG Configuration Single APEX FLEX Device
TRST nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1
APEX FLEX Device
MasterBlaster, ByteBlasterMV, BitBlaster 10-Pin Male Header (Top View)
Notes:
pull-up resistor should connected same supply voltage MasterBlaster, ByteBlasterMV, BitBlaster cable. FLEX devices 144-pin TQFP packages have TRST pin. Therefore, TRST ignored when configuring FLEX devices 144-pin TQFP packages. nCONFIG, MSEL0, MSEL1 pins should connected support FLEX configuration scheme. only JTAG configuration used, connect nCONFIG VCC, MSEL0 MSEL1 ground. reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. BitBlaster serial download cable supported Quietus software used configure APEX devices.
configure single device JTAG chain, programming software places other devices BYPASS mode. BYPASS mode, devices pass programming data from through single bypass register without being affected internally. This scheme enables programming software program verify target device. Configuration data driven into device appears clock cycle later.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
APEX FLEX devices have dedicated JTAG pins that always function JTAG pins. JTAG testing performed APEX 20K, FLEX 10K, FLEX 6000 devices both before after configuration, during configuration. chip-wide reset output enable pins APEX 20K, FLEX 10K, FLEX 6000 devices affect JTAG boundary-scan programming operations. Toggling these pins does affect JTAG operations (other than usual boundary-scan operation). When designing board JTAG configuration APEX FLEX devices, regular configuration pins should considered. Table shows these pins should connected during JTAG configuration.
Table Descriptions
Signal
nSTATUS CONF_DONE nCONFIG MSEL0, MSEL1 DCLK DATA0 TRST Note:
nSTATUS pulling middle JTAG configuration indicates that error occured; CONF_DONE pulling high JTAG configuration indicates successful configuration.
Description
APEX FLEX devices chain should driven connecting ground, pulling down resistor, driving some control circuitry. Pulled resistor. When configuring multiple devices same JTAG chain, each nSTATUS should pulled individually. Pulled resistor. When configuring multiple devices same JTAG chain, each CONF_DONE should pulled individually. Driven high connecting VCC, pulling resistor, driven some control circuitry. These pins must left floating. These pins support whichever non-JTAG configuration used production. only JTAG configuration used, should both pins ground. Should left floating. Drive high, whichever more convenient. Should left floating. Drive high, whichever more convenient. This JTAG connected download cable. should driven logic high.
information create configuration programming files this configuration scheme, "Device Configuration Files" page
JTAG Programming Configuration Multiple Devices (APEX FLEX Devices Only)
When programming JTAG device chain, JTAG-compatible header, such ByteBlasterMV BitBlaster header, connected several devices. number devices JTAG chain limited only drive capability download cable. However, when more than five devices connected JTAG chain, Altera recommends buffering TCK, TDI, pins with on-board buffer.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
JTAG-chain device programming ideal when contains multiple devices, when testing using JTAG circuitry. Figure shows multi-device JTAG configuration.
Figure Multi-Device JTAG Configuration
MasterBlaster, ByteBlasterMV, BitBlaster 10-Pin Male Header
Notes (1),
APEX
FLEX Device
nSTATUS nCONFIG MSEL0 CONF_DONE MSEL1
APEX FLEX Device
nSTATUS nCONFIG MSEL0 CONF_DONE MSEL1
APEX FLEX Device
nSTATUS nCONFIG MSEL0 CONF_DONE MSEL1
Notes:
APEX 20K, FLEX 10K, devices placed within same JTAG chain device programming configuration. more information configuration pins connected this mode, refer Table page pull-up/pull-down resistors nCONFIG, MSEL0, MSEL1 pins should connected support FLEX configuration scheme. only JTAG configuration used, connect nCONFIG VCC, MSEL0 MSEL1 ground. reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. BitBlaster serial download cable supported Quietus software used configure APEX devices.
Successful JTAG configuration verified automatically MAX+PLUS Quartus software JTAG configuration. software checks state CONF_DONE through JTAG port configuration. CONF_DONE correct state, MAX+PLUS Quartus software indicates that configuration failed. CONF_DONE correct state, software indicates that configuration successful. When using JTAG pins configuration, VCCIO tied both pins JTAG port will drive 3.3-V levels. meets JTAG requirements specified voltage level.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
JTAG non-JTAG configuration should attempted simultaneously. When configuring JTAG, allow non-JTAG configuration complete first. Figure shows JTAG configuration APEX FLEX device with microprocessor.
Figure JTAG Configuration APEX FLEX Device with Microprocessor
Memory
ADDR DATA
APEX FLEX Device Microprocessor
nCONFIG CONF_DONE
Programming Test Language
In-circuit configuration embedded processor enables easy design prototyping, streamlines production, allows quick efficient in-field upgrades. Jamprogramming test language, standard file format using IEEE Std. 1149.1 (JTAG) interface, further simplifies in-circuit configuration providing small file sizes increased flexibility. Files Byte-Code Files (.jbc) contain both programming algorithm data required upgrade more devices. language supported MAX+PLUS software versions higher. estimate size using following equation: Size Where:
Data
Space used algorithm (see Table Data Space used compressed programming data (see Table Index representing family type(s) being targeted Number target devices chain
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table FLEX Algorithm Constants
Device Family Typical Algorithm Size (Kbytes) ASCII File
FLEX FLEX 10KE
Byte-Code File
Table FLEX Data Constants
Device Typical Data Size (Kbytes) Compressed ASCII
EPF10K10, EPF10K10A EPF10K20 EPF10K30, EPF10K30A, EPF10K30E EPF10K40 EPF10K50, EPF10K50E, EPF10K50V EPF10K70 EPF10K100, EPF10K100A, EPF10K100B, EPF10K100E EPF10K130E, EPF10K130V EPF10K200E EPF10K250A
more information configure devices using programming test language, Application Note (Using Language Embedded Processor). future version application note will contain File Byte-Code File sizes APEX devices. This section shows configure APEX 20K, FLEX 10K, FLEX 6000 devices using multiple configuration schemes same board. Figure shows schematic configuring APEX 20K, FLEX 10K, FLEX 6000 device using download cable configuration device.
Combining Different Configuration Schemes
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Device Configuration with Download Cable Configuration Device
MasterBlaster ByteBlasterMV 10-Pin Male Header
APEX 20K, FLEX 10K, FLEX 6000 Device MSEL1 MSEL0
EPC2 Device (10) DATA DCLK VCCSEL VPPSEL nCASC nINIT_CONF
DCLK CONF_DONE nCONFIG nSTATUS DATA0
VCCINT VCCIO nCEO N.C.
Notes:
should connected same supply voltage configuration device. pull-up resistors pull-up resistor should connected same supply voltage configuration device. download cable programs configuration device. reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. VCCINT VCCIO should applied according target device's VCCINT VCCIO. FLEX 6000 devices have single MSEL pin, which tied ground, DATA0 named DATA. nCEO left unconnected. 3.3-V supply voltage used, VCC, VCCSEL, VPP, VPPSEL pins should connected 3.3-V supply. 5.0-V supply voltage used, pins should connected 5.0-V supply, VCCSEL VPPSEL pins should connected ground. improve in-system programming times, connect VPPSEL ground. more information these pins, Table page (10) configuration device configures APEX 20K, FLEX 10K, FLEX 6000 device. This figure shows connections EPC2 configuration device. other configuration device, connect pins appropriately.
Figure shows schematic configuring APEX 20K, FLEX 10K, FLEX 6000 devices using download cables EPC2 device.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Device Configuration with Download Cables EPC2 Device
MasterBlaster JTAG ByteBlasterMV 10-Pin Male Header 10-Pin Male Header
APEX 20K, FLEX 10K, FLEX 6000 Device MSEL1 MSEL0
EPC2 Device
DCLK CONF_DONE nCONFIG nSTATUS DATA0
(10)
VCCINT VCCIO nCEO
N.C.
DATA DCLK
VCCSEL VPPSEL nCASC nINIT_CONF
Notes:
should connected same supply voltage configuration device. target APEX FLEX device configured either configuration device download cable. pull-up resistors download cable programs configuration device through JTAG circuitry. reference voltage MasterBlaster output driver. should match device's VCCIO. Refer MasterBlaster Serial/USB Communications Cable Data Sheet this value. VCCINT VCCIO should applied according target device's VCCINT VCCIO. FLEX 6000 devices have single MSEL pin, which tied ground, DATA0 named DATA. nCEO left unconnected. should attempt configuration with download cable while configuration device connected APEX FLEX device. perform this operation, should either remove configuration device from socket when using download cable, place switch five common signals between download cable configuration device. (10) 3.3-V supply voltage used, VCC, VCCSEL, VPP, VPPSEL pins should connected 3.3-V supply voltage. 5.0-V supply voltage used, pins should connected 5.0-V supply voltage, VCCSEL VPPSEL pins should connected ground. improve in-system programming times, connect VPPSEL ground. more information these pins, Table page
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
external memory configure APEX 20K, FLEX 10K, FLEX 6000 device using 7000 device. Figure shows schematic this configuration scheme. sample design 7000 device, called promldr.txt, available Altera site http://www.altera.com.
Figure Device Configuration using External Memory 7000 Device
Oscillator 7000 Device
nSTATUS APEX 20K, FLEX 10K,
FLEX 6000 Device
MSEL0 nSTATUS INIT_DONE CONF_DONE DCLK DATA0 nCONFIG nCEO
Memory
DATA[] DATAIN ADDR[] RESTART ADDR[] RESTART DATA[]
MSEL1
INIT_DONE CONF_DONE DCLK DATA0 nCONFIG
APEX 20K, FLEX 10K, FLEX 6000 Device
MSEL0 nSTATUS INIT_DONE CONF_DONE DCLK DATA0 nCONFIG nCEO MSEL1
Notes:
FLEX 6000 devices have single MSEL pin, which tied ground, DATA0 named DATA. nCEO left unconnected last device chain.
Figure shows timing waveform configuring APEX 20K, FLEX 10K, FLEX 6000 device using external memory 7000 device.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Figure Timing Waveform Configuration using External Memory 7000 Device
nSTATUS nCONFIG DCLK DATA0 D[7.0] ADDR[15.0] CONF_DONE RESTART INIT_DONE
Device Options
FLEX FLEX 6000 device options Altera's MAX+PLUS development software choosing Global Project Device Options (Assign menu). APEX device options using similar dialog Quartus software. Table summarizes each these options.
Table APEX 20K, FLEX FLEX 6000 Configuration Option Bits
Device Option
User-supplied start-up clock (FLEX FLEX 6000 devices only.)
(Part
Modified Configuration (Option
Option Usage
complete initialization, device must clocked times after data transferred. CONF_DONE goes high after initialization process begun. select which clock source initialization choosing CLKUSR rather than DCLK.
Default Configuration (Option Off)
configuration schemes, device's internal oscillator supplies initialization clock.
user provides clock CLKUSR pin. This clock synchronize initialization multiple devices. clock should supplied when configuration device, last data byte transferred. schemes, internal Supplying clock during oscillator disabled. Thus, configuration will affect external circuitry, such configuration process. configuration device download operation CLKUSR cable, must provide during user mode selected initialization clock DCLK MAX+PLUS software. pin. configuration device scheme, configuration device supplies clock; schemes, microprocessor supplies clock.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table APEX 20K, FLEX FLEX 6000 Configuration Option Bits
Device Option
User-supplied start-up clock (APEX devices only.)
(Part
Modified Configuration (Option
user provides clock CLKUSR DCLK pin. Quartus software specifies which used. This clock synchronizes initialization multiple devices. clock should supplied when last data byte transferred. Supplying clock CLKUSR will affect configuration process. Quartus software specifies CLKUSR pin's operation mode. When using configuration device, CLKUSR synchronize initialization; DCLK used passive configuration only. configuration process restarts automatically. nSTATUS drives releases. nSTATUS then pulled pull-up resistor, indicating that configuration restart. configuration device scheme, target device's nSTATUS tied configuration device's pin, nSTATUS reset pulse resets configuration device automatically. configuration device releases (which pulled high) reconfiguration begins. error occurs during passive configuration, device reconfigured without system having pulse nCONFIG. After nSTATUS goes high, reconfiguration begin.
Option Usage
Default Configuration (Option Off)
begin initialization, device's internal oscillator device must clocked supplies start-up clock. times after data transferred. CONF_DONE goes high after initialization process begins. device initialized internal oscillator external clocks provided DCLK CLKUSR.
Auto-restart data error occurs during configuration configuration, frame error choose restart configuration.
configuration process stops until direct device restart configuration. nSTATUS driven when error occurs. When nCONFIG pulled then high, device begins reconfigure.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table APEX 20K, FLEX FLEX 6000 Configuration Option Bits
Device Option Option Usage Default Configuration (Option Off)
(Part
Modified Configuration (Option
Release clears During configuration, before tridevice pins states tri-stated. During initialization, choose order releasing tri-states clearing registers. Enable chipwide reset Enables single reset device registers.
device releases tri-states device releases clear pins before releasing signals registers before clear signal registers. releasing tri-states. this option allow design operate before drives out, outputs start low. Chip-wide reset enabled. Chip-wide reset enabled DEV_CLRn available registers device. user pin. registers cleared when DEV_CLRn driven low. Chip-wide output enable enabled device tri-states. After configuration, user pins tri-stated when DEV_OE low. INIT_DONE signal available open-drain INIT_DONE pin. This drives during configuration. After initialization, released pulled high externally. INIT_DONE must connected pull-up resistor. INIT_DONE output used, INIT_DONE cannot used user pin. JTAG boundary-scan testing performed before after device configuration four JTAG pins (TDI, TDO, TMS, TCK); however, cannot performed during configuration. When JTAG boundary-scan testing performed before device configuration, nCONFIG must held low.
Enable chipwide output enable
Enables single Chip-wide output enable control device tri-states. enabled. DEV_OE available user pin.
Enable INIT_DONE output
Enables drive INIT_DONE signal signal when available. INIT_DONE initialization process available user pin. complete device entered user mode.
Enable JTAG support (FLEX 6000 devices only. APEX FLEX devices, JTAG support always enabled.)
Enables post-configuration JTAG boundary-scan testing support FLEX 6000 devices.
JTAG boundary-scan testing performed before configuration; however, cannot performed during after configuration. During JTAG boundary-scan testing, nCONFIG must held low.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Device Configuration Pins
Table summarizes APEX 20K, FLEX 10K, FLEX 6000 device configuration pins.
Table Functions (Part
Name
MSEL0 MSEL1 MSEL
Device Family
APEX FLEX FLEX 6000
User Configuration Mode Scheme
Type
Input
Description
2-bit configuration input. Sets APEX FLEX device configuration scheme. Table page 1-bit configuration input. Sets FLEX 6000 device configuration scheme. Table page
Input
nSTATUS
APEX FLEX FLEX 6000
Bidirectional device drives nSTATUS immediately open-drain after power-up releases within (When using configuration device, configuration device holds nSTATUS ms.) nSTATUS must pulled with resistor. error occurs during configuration, nSTATUS pulled target device. external source drives nSTATUS during configuration initialization, target device enters error state. Driving nSTATUS after configuration initialization does affect configured device. However, configuration device used, driving nSTATUS will cause that device attempt configure APEX FLEX device. Input Configuration control input. resets target device; low-to-high transition begins configuration.
nCONFIG
APEX FLEX FLEX 6000
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table Functions (Part
Name
CONF_DONE
Device Family
APEX FLEX FLEX 6000
User Configuration Mode Scheme
Type
Description
Bidirectional Status output. target device drives open-drain CONF_DONE before during configuration. Once configuration data received without error initialization clock cycle starts, target device releases CONF_DONE. Status input. After data received CONF_DONE goes high, target device initializes enters user mode. CONF_DONE must pulled with resistor. external source drive this delay initialization process, except when configuring with configuration device. Driving CONF_DONE after configuration initialization does affect configured device.
DCLK
APEX FLEX FLEX 6000 APEX FLEX FLEX 6000
Configuration device
Input
Clock input used clock data from external source into target device. schemes, DCLK should held prevent this from floating. Active-low chip enables. activates device with signal allow configuration should tied single device configuration. must held during configuration, initialization, user mode. Output that drives when device configuration complete. During multidevice configuration, this feeds subsequent device's pin. Write strobe input. APEX FLEX devices, low-to-high transition causes device latch byte data DATA[7.0] pins. FLEX 6000 devices, low-to-high transition causes device latch data DATA pin.
Input
nCEO
APEX FLEX FLEX 6000
Multi-device
Output
APEX FLEX FLEX 6000
Input
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116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table Functions (Part
Name
Device Family
User Configuration Mode Scheme
Type
Input
Description
Read strobe input. APEX FLEX devices, input directs device drive RDYnBSY signal DATA7 pin. FLEX 6000 devices, input directs device drive RDYnBSY signal DATA pin. used, should tied high. Ready output. high output indicates that target device ready accept another data byte. output indicates that target device ready receive another data byte. Chip-select inputs. high select target device configuration. only chip-select input used, other must tied active value (e.g., tied ground used). pins must held active during configuration initialization. Optional user-supplied clock input. Synchronizes initialization more devices. Data inputs. Bit-wide configuration data presented FLEX 6000 device DATA pin. configuration scheme, DATA presents RDYnBSY signal after signal been strobed, which more convenient microprocessors than using RDYnBSY pin. Data inputs. Byte-wide configuration data presented target device DATA[7.0]. Data input. serial configuration modes, bit-wide configuration data presented target device DATA0 pin.
APEX FLEX FLEX 6000
RDYnBSY
APEX FLEX FLEX 6000
Output
APEX FLEX FLEX 6000
Input
CLKUSR
APEX FLEX FLEX 6000 FLEX 6000
Input
DATA
Configuration device
Input
DATA[7.1] APEX FLEX DATA0 APEX FLEX
Configuration device
Inputs
Input
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table Functions (Part
Name
DATA7
Device Family
User Configuration Mode Scheme
Type
Output
Description
configuration scheme, DATA7 presents RDYnBSY signal after signal been strobed, which more convenient microprocessors than using RDYnBSY pin. Status pin. used indicate when device initialized user mode. INIT_DONE drives during configuration. Before after configuration, INIT_DONE released pulled external pull-up resistor. Because INIT_DONE tri-stated before configuration, pulled high external pull-up resistor. Thus, monitoring circuitry must able detect low-to-high transition. This option MAX+PLUS Quartus software. Optional that allows user override tri-states device. When this driven low, I/Os tri-stated; when this driven high, I/Os behave programmed. This option MAX+PLUS Quartus software. Optional that allows override clears device registers. When this driven low, registers cleared; when this driven high, registers behave programmed. This option MAX+PLUS Quartus software. JTAG pins. When used user pins, JTAG pins must kept stable before during configuration. JTAG stability prevents accidental loading JTAG instructions.
APEX FLEX
INIT_DONE
APEX FLEX FLEX 6000
Output open-drain
DEV_OE
APEX FLEX FLEX 6000
Input
DEV_CLRn
APEX FLEX FLEX 6000
Input
APEX FLEX JTAG FLEX 6000 pins
Input Output Input Input
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table describes EPC2, EPC1, EPC1441 functions during APEX 20K, FLEX 10K, FLEX 6000 device configuration.
Table EPC2, EPC1 EPC1441 Functions During APEX 20K, FLEX FLEX 6000 Configuration (Part
Name Number 8-Pin 20-Pin 32-Pin PDIP PLCC TQFP
DATA
Type
Description
Output
Serial data output. DATA tri-stated before configuration when high, after configuration device finishes sending configuration data. This operation independent device's position cascade chain. DCLK clock output when configuring with single configuration device when configuration device first device configuration device chain. DCLK clock input subsequent configuration devices configuration device chain. Rising edges DCLK increment internal address counter present next data DATA pin. counter incremented only input held high, input held low, configuration data been transferred target device. When configuring with first EPC2 EPC1 device configuration device chain with single EPC1441 device, DCLK drives after configuration complete when low. Output enable (active high) reset (active low). logic level resets address counter. high logic level enables DATA permits address counter count. this (reset) during configuration, internal oscillator becomes inactive DCLK drives low. Chip select input (active low). input allows DCLK increment address counter enables DATA drive out. EPC1 EPC2 reset with low, device initializes first device configuration chain. EPC1 EPC2 device reset with high, device initializes subsequent device chain. Cascade select output (active low). This output goes when address counter reached maximum value. chain EPC1 EPC2 devices, nCASC device connected next device, which permits DCLK clock data from next EPC1 EPC2 device chain.
DCLK
Opendrain
Input
nCASC
Output
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Table EPC2, EPC1 EPC1441 Functions During APEX 20K, FLEX FLEX 6000 Configuration (Part
Name Number 8-Pin 20-Pin 32-Pin PDIP PLCC TQFP
nINIT_CONF (3), (5),
Type
Description
Output Opendrain
Allows INIT_CONF JTAG instruction initiate configuration. This connected nCONFIG FLEX APEX device initiate configuration from EPC2 JTAG instruction. chain EPC2 devices used, only first EPC2 nINIT_CONF tied FLEX device's nCONFIG pin. JTAG data input pin. Connect this JTAG circuitry used. JTAG data output pin. connect this JTAG circuitry used. JTAG mode select pin. Connect this JTAG circuitry used. JTAG clock pin. Connect this ground JTAG circuitry used. Mode select supply. VCCSEL must connected ground device uses 5.0-V power supply (i.e., VCCSEL must connected device uses 3.3-V power supply (i.e., Mode select VPP. VPPSEL must connected ground uses 5.0-V power supply (i.e., VPPSEL must connected uses 3.3-V power supply (i.e, Programming power pin. EPC2 device, this normally tied VCC. EPC2 tied improve in-system programming times. EPC1 EPC1441 devices, must tied VCC. Power pin.
VCCSEL
Input Output Input Input Input
VPPSEL
Input
Power
Power
Ground Ground pin. 0.2-µF decoupling capacitor must placed between pins.
Notes table:
This package available EPC1 EPC1441 devices only. This package available EPC2 EPC1441 devices only. nCS, nINIT_CONF pins EPC2 devices have internal, user-configurable pull-up resistors. internal pull-up resistors used, external pull-up resistors should used these pins. This EPC2 feature available MAX+PLUS software version higher. earlier versions MAX+PLUS software, internal pull-up resistors these pins disabled. EPC1441 device does support data cascading. EPC2 EPC1 devices support data cascading. This applies EPC2 devices only. This instruction supported MAX+PLUS software versions higher.
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116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Device Configuration Files
Altera's MAX+PLUS Quartus development tools create more configuration programming files support configuration schemes discussed this application note. This section describes these files.
SRAM Object File (.sof)
should during configuration when data downloaded directly from Altera programming hardware with MasterBlaster, ByteBlasterMV, BitBlaster cable. APEX 20K, FLEX 10K, FLEX 6000 devices, MAX+PLUS Quartus Compiler's Assembler module automatically creates each device your design. MAX+PLUS Quartus software controls configuration sequence automatically inserts appropriate headers into configuration data stream. other configuration files created from SOF.
Programmer Object File (.pof)
Programmer Object File (.pof) used Altera programming hardware program configuration device. generated automatically when APEX 20K, FLEX 10K, FLEX 6000 project compiled. smaller FLEX devices (e.g., EPF10K20 devices), multiple POFs into configuration device; larger devices (e.g., APEX devices), multiple configuration devices required hold configuration data.
Binary File (.rbf)
Binary File (.rbf) binary file, e.g., byte data configured bits 10000101 Hex), containing APEX 20K, FLEX 10K, FLEX 6000 configuration data. Data must stored that least significant (LSB) each data byte loaded first. converted image stored mass storage device. microprocessor then read data from binary file load into APEX 20K, FLEX 10K, FLEX 6000 device. also microprocessor perform realtime conversion during configuration. configuration schemes, target device receives information parallel from data bus, data port microprocessor, some other byte-wide channel. configuration schemes, data shifted serially, first. following steps explain create file FLEX FLEX 6000 devices using MAX+PLUS software. follow similar procedure Quartus software generate RBFs APEX devices.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
MAX+PLUS Compiler Programmer, choose Convert SRAM Object Files command (File menu.) Convert SRAM Object Files dialog box, specify which files combine then select .rbf (Sequential) File Format box. Click
more information creating RBFs, search "RBF" MAX+PLUS Quartus Help.
Hexadecimal (Intel-Format) File (.hex)
File ASCII file Intel format. This file used third-party programmers program Altera's serial configuration devices. Files also used program parallel configuration devices with third-party programming hardware. parallel configuration devices PPS, PPA, configuration schemes, which microprocessor uses parallel configuration device data source. following steps explain create file FLEX FLEX 6000 devices using MAX+PLUS software. follow similar procedure Quartus software generate files APEX devices. MAX+PLUS Programmer Compiler, choose Convert SRAM Object Files command (File menu). Convert SRAM Object Files dialog box, specify which files combine then select .hex File Format box. Click
more information creating Files, search "Hex File" MAX+PLUS Quartus Help.
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116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Tabular Text File (.ttf)
Tabular Text File (.ttf) tabular ASCII file that provides commaseparated version configuration data PPA, PPS, PSA, bit-wide configuration schemes. some applications, storage device containing FLEX FLEX 6000 configuration data neither dedicated connected directly target device. example, configuration device also contain executable code system (e.g., BIOS routines) other data. allows include configuration data part microprocessor's source code using include source commands. microprocessor access this data from configuration device mass-storage device load into target device. imported into nearly assembly language high-level language compiler. TTFs supported MAX+PLUS software only.
following steps explain create file FLEX FLEX 6000 devices using MAX+PLUS software. MAX+PLUS Programmer Compiler, choose Convert SRAM Object Files command (File menu). Convert SRAM Object Files dialog box, specify which files combine then select .ttf (Sequential) File Format box. Click
more information creating TTFs, search "TTF" MAX+PLUS Quartus Help.
Serial Bitstream File (.sbf)
Serial Bitstream File (.sbf) used schemes configure FLEX FLEX 6000 devices in-system with BitBlaster cable. SBFs supported MAX+PLUS software only.
following steps explain create file FLEX FLEX 6000 devices using MAX+PLUS software. MAX+PLUS Programmer Compiler, choose Convert SRAM Object Files command (File menu). Convert SRAM Object Files dialog box, specify which files combine then select .sbf (Sequential) File Format box. Click
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116: Configuring APEX 20K, FLEX FLEX 6000 Devices
more information creating SBFs, search "SBF" MAX+PLUS Help.
File (.jam)
File ASCII text file device programming language that stores device programming information. These files used program, verify, blank-check more devices MAX+PLUS Quartus Programmer embedded processortype environment.
Byte-Code File (.jbc)
Byte-Code File (.jbc) binary file File byte-code representation. files store device programming information used program, verify, blank-check more devices MAX+PLUS Programmer embedded processor-type environment.
Device Configuration
configure APEX 20K, FLEX 10K, FLEX 6000 devices using data stored either configuration device MAX+PLUS Quartus software.
Configuration with Configuration Device
program configuration devices using MAX+PLUS Quartus software, Master Programming Unit (MPU), appropriate configuration device programming adapter. Table shows which programming adapter with each configuration device.
Table Programming Adapters
Device
EPC2 EPC1 EPC1441
Package
20-pin J-Lead 32-pin TQFP 8-pin 20-pin J-Lead 8-pin 20-pin J-Lead 32-pin TQFP
Adapter
PLMJ1213 PLMT1213 PLMJ1213 PLMJ1213 PLMJ1213 PLMJ1213 PLMT1064
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
following steps explain program Altera configuration devices using MAX+PLUS software: Open MAX+PLUS Programmer. Load appropriate using Select Programming File dialog (File menu). default, Programmer loads current project's POF. Device field displays appropriate device current programming file. Insert blank configuration device into programming adapter's socket. Click Program button.
After successful programming, place configuration device configure APEX 20K, FLEX 10K, FLEX 6000 device.
more information configuration devices, Configuration Devices APEX FLEX Devices Data Sheet.
Configuration with MasterBlaster, ByteBlasterMV, BitBlaster Cable
more information MasterBlaster, ByteBlasterMV, BitBlaster cable, following documents:
MasterBlaster Serial/USB Communications Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet BitBlaster Serial Download Cable Data Sheet
Configuration Reliability
APEX 20K, FLEX 10K, FLEX 6000 architecture been designed minimize effects power supply data noise system, ensure that configuration data corrupted during configuration normal user-mode operation. number circuit design features provided ensure highest possible level reliability from this SRAM technology. Cyclic redundancy code (CRC) circuitry used validate each data frame (i.e., sequence data bits) loaded into target device. generated APEX FLEX device does match data stored data stream, configuration process halted, nSTATUS pulled held indicate error condition. circuitry ensures that noisy systems will cause errors that yield incorrect incomplete configuration.
Altera Corporation
116: Configuring APEX 20K, FLEX FLEX 6000 Devices
APEX 20K, FLEX 10K, FLEX 6000 architecture also provides very high level reliability low-voltage brown-out conditions. These devices' SRAM cells require certain level maintain accurate data. This voltage threshold significantly lower than voltage required activate device's circuitry. Therefore, target device stops operating starts fail, indicates operation error pulling holding nSTATUS low. device must then reconfigured before resume operation logic device. active configuration schemes which nCONFIG tied VCC, reconfiguration begins soon returns acceptable level. pulse nSTATUS resets configuration device driving low. passive configuration schemes, host system starts reconfiguration process. These device features ensure that APEX 20K, FLEX 10K, FLEX 6000 devices have highest possible reliability wide variety environments, provide same high level system reliability that exists other Altera programmable logic devices (PLDs).
Board Layout Tips
Even though DCLK signal (used configuration device, configuration schemes) fairly low-frequency, drives edge-triggered pins APEX 20K, FLEX 10K, FLEX 6000 device. Therefore, overshoot, undershoot, ringing, other noise affect configuration. When designing board, DCLK trace using same techniques laying clock line, including appropriate buffering. more than five devices used, Altera recommends using buffers split fan-out DCLK signal. information contained Application Note (Configuring APEX 20K, FLEX FLEX 6000 Devices) version 1.02 supersedes information published previous versions.
Revision History
Version 1.02 Changes
Version 1.02 contains following changes:
Corrected notes Figures Corrected Figures Corrected note Table Added note Table
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116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Version 1.01 Changes
Version 1.01 contained following changes:
Added note Table Updated information Tables Corrected minimum tCFG value Tables Corrected Figures Added note Figures
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116: Configuring APEX 20K, FLEX FLEX 6000 Devices
Notes:
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116: Configuring APEX 20K, FLEX FLEX 6000 Devices
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Altera, APEX, APEX 20K, APEX 20KE, FLEX, FLEX 10K, FLEX 10KA, FLEX 10KE, FLEX 6000, BitBlaster, ByteBlaster, ByteBlasterMV, MasterBlaster, Jam, MAX, MAX+PLUS, MAX+PLUS Quartus trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 1999 Altera Corporation. rights reserved.
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