Application Note 1999, ver. Introduction APEX20K device

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Application Note 1999, ver. Introduction APEX20K device

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Using ClockLock ClockBoost Features APEX Devices
Application Note
1999, ver.
Introduction
APEX20K devices have ClockLockand ClockBoostfeatures, which PLLs increase performance provide clock-frequency synthesis. ClockLock feature minimizes clock delay clock skew within device, reducing clock-to-output setup times while maintaining zero hold times. ClockBoost feature allows designers internal logic device faster slower rate than input clock frequency. This technique simplifies board design because clock path board does have distribute high-speed signal. Through time-domain multiplexing, ClockBoost feature allows designer improve device area efficiency sharing resources within device. APEX 20KE devices include PLLs with enhanced ClockLock feature set, such advanced ClockBoost capability m/(n multiplication, voltage differential signaling (LVDS) support, external clock outputs feedback ability, ClockShiftcircuitry more complex clockfrequency synthesis applications. These enhanced features permit systemlevel clock management skew control APEX 20KE devices. ClockLock ClockBoost features provide significant improvements system performance, bandwidth, This application note explains APEX APEX 20KE ClockLock ClockBoost features. also describes common applications these features.
Clock Delay Skew
delay from clock register, especially large devices, significant enough degrade both off-chip performance. equation pin-to-pin clock-to-output delay (tCO) shown Figure clock delay (tCLOCK) clock skew (tSKEW) parameters account significant portion total clock-to-output delay larger devices. reducing clock delay clock skew, ClockLock ClockBoost circuitry improves clock-to-output times device.
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115: Using ClockLock ClockBoost Features APEX Devices
Figure APEX APEX 20KE Hold, Setup Clock-to-Output Times
data1 clock Clock Delay Data Delay Output Delay
Skew
data2
Data Delay
Output Delay
tREG_H tCLOCK tSKEW tDATA tREG_SU tDATA tCLOCK tSKEW tCLOCK tSKEW tREG_CO tOUTPUT
Clock skew-the difference between clock delays different registers- also increases setup time indirectly. ensure zero hold time (tH), data delay must added account longest clock delay register. This delay must large enough ensure zero hold time under fast process, voltage, temperature conditions. However, added data delay also increases register's setup time under slow process, voltage, temperature conditions. When ClockLock signal feeds register, data delay element register bypassed, resulting decreased setup time. Because clock skew delay reduced, register maintains zero hold time. programmable devices become larger, clock delay skew become problem. Also, clock skew affect board design. address these issues, designers either phase-locked loops (PLLs) delaylocked loops (DLLs). Although both used reduce skew within system clocks, PLLs more flexible than DLLs frequency synthesis system clocks. Additionally, DLLs capable performing scaling. PLLs ideal clock multiplication division applications because they perform scaling.
ClockLock ClockBoost Features
ClockLock ClockBoost circuitry locks onto rising edge incoming clock. circuit output drives clock port registers. Both negative- positive-edge-triggered registers ClockLock and/or ClockBoost output APEX device.
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115: Using ClockLock ClockBoost Features APEX Devices
Table shows features APEX APEX 20KE devices.
Table APEX APEX 20KE ClockLock Features
Device Number PLLs ClockBoost Feature
Note
LVDS LVDS Clock Data
T1/E1 Number Number ClockShift Conversion External Feedback Inputs Clock Outputs
EP20K100 EP20K200 EP20K400 EP20K100E EP20K160E EP20K200E EP20K300E EP20K400E EP20K600E EP20K1000E Notes:
m/(n
m/(n m/(n m/(n m/(n m/(n m/(n
APEX devices that support ClockLock ClockBoost features denoted suffix ordering code (e.g., EP20K400FC672-1X). integers ranging from
APEX Devices
APEX offers enhanced ClockLock synchronization circuitry, with extended output frequency range from MHz. APEX devices also support enhanced ClockBoost multiplication circuitry, offering clock multiplication. Figure shows ClockLock ClockBoost circuitry block diagram.
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115: Using ClockLock ClockBoost Features APEX Devices
Figure ClockLock ClockBoost Circuitry APEX Devices
Phase Comparator
Voltage-Controlled Oscillator Locked Clock ClockBoost
Primary Clock
ClockLock
single output clock dual output clocks combination and/or ClockLock circuitry ClockBoost multiplication circuitry. Table shows clock combinations supported ClockLock ClockBoost circuitry. These outputs drive logic element (LE), element (IOE), embedded system block (ESB) device. output ClockLock ClockBoost circuits available device pins APEX devices.
Table Multiplication Factor Combinations
Clock
Clock
Quartussoftware enables ClockLock ClockBoost features APEX devices; external devices required. Designers Quartus software program these features within APEX devices.
dedicated clock (GCLK1) supplies clock PLL. While dedicated clock driving ClockLock ClockBoost circuitry, cannot drive other signals device.
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115: Using ClockLock ClockBoost Features APEX Devices
Table shows timing parameters APEX ClockLock ClockBoost features.
Table APEX ClockLock ClockBoost Parameters
Symbol
fOUT fCLK1 fCLK2 fCLK4 tOUTDUTY tLOCK tSKEW tJITTER tINCLKSTB
Notes:
Notes (1),
Minimum
Parameter
Output frequency Input clock frequency (ClockBoost clock multiplication factor equals Input clock frequency (ClockBoost clock multiplication factor equals Input clock frequency (ClockBoost clock multiplication factor equals Duty cycle ClockLock/ClockBoost-generated clock Input rise time Input fall time Time required ClockLock/ClockBoost acquire lock Skew delay between related ClockLock/ClockBoost-generated clocks Jitter ClockLock/ClockBoost-generated clock Input clock stability (measured between adjacent clocks)
Maximum
Unit
This information preliminary. input clock specifications must met. lock onto incoming clock clock specifications met, creating erroneous clock within device. During device configuration, ClockLock ClockBoost circuitry configured first. incoming clock supplied during configuration, ClockLock ClockBoost circuitry locks during configuration, because lock time less than configuration time. jitter specification measured under long-term observation. input clock stability TJITTER
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115: Using ClockLock ClockBoost Features APEX Devices
Table lists APEX ClockLock pins their function.
Table APEX Device ClockLock Pins
Name
GCLK1 LOCK
Type
Input Output
Description
Dedicated that drives ClockLock ClockBoost circuitry. Optional that shows status ClockLock ClockBoost circuitry. When ClockLock ClockBoost circuitry locked incoming clock generates internal clock, LOCK driven high. LOCK remains high long clock input remains within specification.
Standard Supported
2.5-V I/O, LVCMOS, LVTTL, 3.3-V
Note:
LVCMOS: low-voltage complementary metal-oxide semiconductor, LVTTL: low-voltage transistor-to-transistor logic, PCI: peripheral component interconnect.
APEX 20KE Devices
APEX 20KE devices incorporate multiple ClockLock circuits with advanced features. These features include ClockLock ClockBoost circuitry with m/(n scaling, LVDS support, ClockShift circuitry, external clock outputs feedback inputs, T1/E1 clock domain conversion. Figure shows ClockLock ClockBoost circuitry APEX 20KE devices.
Figure ClockLock ClockBoost Circuitry APEX 20KE Devices
Phase Comparator
Voltage-Controlled Oscillator Locked Clock Locked Clock ClockShift Circuitry
Primary Clock
ClockLock
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115: Using ClockLock ClockBoost Features APEX Devices
EP20K200E, EP20K160E, EP20K100E devices contain enhanced general-purpose PLLs with ClockLock, ClockBoost, ClockShift features, shown Figure
Figure Global Clock Diagram EP20K200E, EP20K160E EP20K100E Devices
Dedicated Clocks GCLK2 GCLK3 GCLK0 GCLK1 CLKLK_FB1 CLKLK_OUT1
APEX 20KE Device
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115: Using ClockLock ClockBoost Features APEX Devices
EP20K300E larger devices contain four enhanced, general-purpose circuits. PLLs designed either general-purpose LVDS use. remaining PLLs designed general-purpose use, shown Figure
Figure Global Clock Diagram EP20K1000E, EP20K600E, EP20K400E EP20K300E Devices
APEX 20KE Device
Dedicated Clocks
CLKLVDS_OUT3
CLK_LVDS3 GCLK3
CLK_LVDS2 GCLK2
GCLK1 CLKLK_FB1 CLKLK_OUT1
GCLK0 CLKLK_FB0 CLKLK_OUT0
Notes:
These connections only used LVDS mode. cannot configured general purpose LVDS simultaneously. CMOS/LVDS interface clock. LVDS/CMOS interface clock.
Altera Corporation
115: Using ClockLock ClockBoost Features APEX Devices
Table lists APEX 20KE ClockLock pins their function.
Table APEX 20KE Device ClockLock Pins
Name
GCLK LOCK
Type
Input Output
Description
Dedicated pins that drive clock inputs. Optional that shows status ClockLock ClockBoost circuitry. When ClockLock ClockBoost circuitry locked incoming clock generates internal clock, LOCK driven high. LOCK remains high long clock input remains within specification. Dedicated pins that allow external feedback PLLs. Dedicated clock output that allows output driven off-chip. Dedicated that drives clock input LVDS mode LVDS/CMOS data conversion. Dedicated LVDS clock output that allows drive LVDS clock off-chip LVDS mode. LVDS output data synchronized this clock. LVDS
Standard Supported
1.8-V I/O, 2.5-V I/O, AGP, CTT, HSTL, LVCMOS, LVDS, LVTTL, GTL+, 3.3-V PCI, SSTL-2, SSTL-3
CLKLK_FB CLKLK_OUT CLK_LVDS CLKLVDS_OUT
Input Output Input Output
Notes:
AGP: advanced graphics port, CTT: center-tap terminated, GTL+: Gunning transceiver logic, HSTL: high speed transceiver logic, SSTL: stub-series terminated logic. This available EP20K1000E, EP20K600E, EP20K400E, EP20K300E devices only.
Advanced ClockBoost m/(n Multiplication Division
Each APEX 20KE includes circuitry that provides clock synthesis using m/(n scaling factors. When locked, locked output clock aligns rising edge input clock. closed loop equation Figure gives output frequency fOUT (m/(n fIN. This equation allows multiplication division clocks programmable number. Variables integers ranging from over specified frequency ranges. factor used pre-scale division input before multiplied factor used post-scale division. m/(n multiplication gives wide range user-defined multiplication division ratios that possible with DLLs. example, frequency scaling factor 3.75 needed given input clock, then scale factors used. This advanced ClockBoost scaling performed with single PLL, making unnecessary cascade outputs.
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115: Using ClockLock ClockBoost Features APEX Devices
Separate division factors ensure that each PLL's voltagecontrolled oscillator (VCO) operates specified frequency range. Clock inputs that exceed maximum output frequency when multiplied should divided (pre-scaled) before multiplication. example, scale factor together with 125-MHz clock obtain 175-MHz clock output. value should used because will divide, pre-scale, input clock before multiplication multiplied rate without first dividing first exceeds maximum frequency range. reverse true when using low-frequency inputs. multiplication should performed first ensure that operates minimum frequency then division should performed with post-scale factor. example, multiply input clock value m/n, obtain frequency MHz. This value then divided desired frequency that less than using value. Quartus software helps choose appropriate scaling factors. Duty cycle correction outputs with 50/50 duty cycle also available. Setting even number will give approximately 50/50 duty cycle, chosen along with numbered clock multiplication. example, setting clock generated with 50/50 duty cycle. When configured LVDS interface, scaling factor ability changes. LVDS mode, fOUT where Tables through show ClockLock ClockBoost parameters scaling factor parameter specifications conditions.
Table APEX 20KE ClockLock ClockBoost Parameters
Symbol
fOUT fINLVDS
Parameter
Output frequency Input clock frequency (general-purpose PLL) Input clock frequency (PLL LVDS mode)
Minimum
1.25
Maximum
Unit
Table Rate Multiplication General-Purpose PLLs APEX 20KE Devices
Scale Factor
Note
(2), (2),
Parameter
Multiplication factors
Minimum
Maximum
Unit
Integer Integer
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115: Using ClockLock ClockBoost Features APEX Devices
Table Rate Multiplication PLLs used LVDS APEX 20KE Devices
Scale Factor
Note
Parameter
Multiplication factors
Value
Unit
Integer Integer
Notes tables:
Scale factor values must meet these conditions simultaneously: (fIN/n) (fIN (m/n)) These parameters preliminary. most up-to-date information, contact Altera Applications. frequency range fOUT MHz. frequency range when used LVDS fOUT MHz.
APEX 20KE devices frequencies MHz), input jitter tolerance period. Avoid high-frequency multiplication low-frequency inputs with high jitter. Otherwise, high jitter lowfrequency input reflected high frequency output substantial. example, could 1.5-MHz input frequency generate 24-MHz output frequency setting this case, input jitter allowed period, will still lock. However, output jitter 24-MHz clock output cannot expected there 13-ns input jitter. this multiplication application, results improved with less input jitter.
T1/E1 Clock Conversion
general-purpose PLLs include special circuitry support T1/E1 conversion. telecommunications standard uses 1.544-MHz clock, telecommunications standard uses 2.048-MHz clock. general-purpose LVDS PLLs EP20K1000E, EP20K600E, EP20K400E, EP20K300E devices convert clock clock, vice versa. T1/E1 conversion only available when these PLLs used general-purpose use. PLLs EP20K200E, EP20K160E, EP20K100E devices convert clock clock, vice versa.
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115: Using ClockLock ClockBoost Features APEX Devices
Configuration LVDS Interface
EP20K300E larger devices, ClockLock PLLs configured LVDS interfaces. When using LVDS, clock multiplied support high-speed data transfer rates convert between LVDS CMOS data. These PLLs interface with APEX 20KE LVDS input output blocks. clock input multiplied capture convert LVDS data. also bypassed lower-speed LVDS inputs.
External Clock Outputs
EP20K300E larger devices, low-jitter external clocks, CLKLK_OUT0 CLKLK_OUT1, available external clock sources. EP20K200E, EP20K160E, EP20K100E devices, external clock, CLKLK_OUT1, available external clock source. CLKLK_OUT0 signal originates from general-purpose CLKLK_OUT1 signal originates from general-purpose Other devices board these outputs clock sources. incorporates multiplication circuitry which used with external clock. using CLKLK_OUT with without feedback along with internal global signal from same PLL, delay occurs between internal global signal CLKLK_OUT. When using CLKLK_FB pin, adjusts CLKLK_OUT align with GCLK. When using feedback, Quartus software allows choose which signal- CLKLK_OUT global signal-is aligned GCLK. either case, both signals need aligned GCLK, PLLs should used. When using LVDS, CLKLVDS_OUT available drive LVDS clock off-chip. LVDS output data synchronized with skew margin LVDS output clock.
External Feedback Inputs
addition clock output capability, feedback inputs used align feedback clock with input clock. aligning these clocks, actively remove clock delay skew between devices. cannot phase shift capability ClockShift circuitry CLKLK_OUT signal used with external feedback input. When using CLKLK_FB pin, CLKLK_OUT frequency should divided board back APEX 20KE device. CLKLK_FB intended clock skew adjustment, frequency adjustment.
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115: Using ClockLock ClockBoost Features APEX Devices
Lock Signals
APEX 20KE ClockLock circuitry supports individual LOCK signals. LOCK signal drives high when ClockLock circuit locked onto input clock. Lock remains high long clock input remains within specification. will input specification three consecutive clock cycles. LOCK optional each used APEX 20KE devices; when used, they pins.
ClockShift Circuitry
APEX 20KE PLLs have ClockShift circuitry that provides programmable clock delay phase shift. Programmable clock delay allows step delays increments total lagging leading output clock edges with respect input. time delay setting tolerance within device, e.g., 15%), where 0.5, 1.0, 1.5, 2.0. clock phase adjusted steps phase shifting 90°, 180°, 270°. phase-adjusted non-adjusted versions same clock distributed different clock lines. Quartus software automatically configures ClockShift circuitry user-specified angle shift and/or delay shift. LVDS mode, ClockShift circuitry available. APEX APEX 20KE ClockLock circuits designed align rising edges clock input. ClockShift circuitry also adjusts clock with respect rising edges. falling edges clock signals determined duty cycle specification adjustable. setting even number (i.e., dividing even number), output clock cycle will approximately 50%.
Board Layout
Each requires pins. APEX devices have pair pins ClockLock ClockBoost circuitry. APEX 20KE devices require pair each each clock output pin. Table shows power pins required APEX APEX 20KE devices.
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115: Using ClockLock ClockBoost Features APEX Devices
Table Power Requirements APEX APEX 20KE ClockLock ClockBoost Features
Device
EP20K100 EP20K200 EP20K400 EP20K100E EP20K160E EP20K200E EP20K300E EP20K400E EP20K600E EP20K1000E
Name
VCC_CKLK GND_CKLK
Description
Power ground pins ClockLock ClockBoost circuitry. ensure noise resistance, power ground supply ClockLock ClockBoost circuitry should isolated from power ground rest device. Power ground pins ClockLock ClockBoost circuitry clock outputs. ensure noise resistance, power ground supply ClockLock ClockBoost circuitry clock outputs should isolated from power ground rest device. Power ground pins ClockLock ClockBoost circuitry clock outputs. ensure noise resistance, power ground supply ClockLock ClockBoost circuitry clock outputs should isolated from power ground rest device.
VCC_CKLK[1.0] GND_CKLK[1.0] VCC_CKOUT GND_CKOUT VCC_CKLK[3.0] GND_CKLK[3.0] VCC_CKOUT[1.0] GND_CKOUT[1.0]
Power supply noise, such ground bounce sag, directly affects clock jitter. avoid excessive jitter, proper power supply decoupling. ensure noise resistance, isolate power ground supply ClockLock ClockBoost circuitry clock outputs from power ground rest device. dedicated printed circuit board (PCB) traces power ClockLock circuits clock outputs, separate from VCCINT/GNDINT VCCIO/GNDIO planes. Each VCC_CKLK/GND_CKLK VCC_CKOUT/GND_CKOUT pairs should with wide, dedicated traces coming from power supply avoid coupling between PLLs. Each VCC_CKLK/GND_CKLK VCC_CKOUT/GND_CKOUT pairs should decoupled with 0.2-µF powersupply decoupling capacitor located close possible APEX device. Place 100-µF capacitor immediately adjacent location where power-supply lines ClockLock ClockBoost circuits come into PCB. Figure
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115: Using ClockLock ClockBoost Features APEX Devices
Figure Power Supply Decoupling
VCC_CKLK GND_CKLK VCC_CKOUT GND_CKOUT APEX 20KE Device
Note:
VCC_CKOUT GND_CKOUT pins only available APEX 20KE devices.
Applications
Various applications features APEX APEX 20KE circuits. This section describes some possible applications.
Clock Multiplication Division
ClockBoost feature allows designer reduce effects highspeed signals using low-speed clock board. ClockBoost feature used increase on-chip speed. Reducing transmission line effects allows designer simplify board layout. APEX devices, board clock multiplied within device. More complex ratios possible with APEX 20KE devices. Tables pages more information. Clock multiplication division useful communications applications. ClockBoost feature used when transfer rates must multiplied divided. multiplication division clocks also needed maintain rates when converting between parallel data streams serial data streams.
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microprocessor-based systems, system clock lower rate than other system components. example, embedded processor peripheral circuits faster rate than system clock. Embedded applications also require faster internal rates operations such synchronization counting. ClockBoost feature used multiply slower system clock embedded application APEX device. multiplication division capabilities APEX device give designers ability develop System-on-a-Programmable-Chip designs. Figure shows clock synthesis embedded application.
Figure Embedded Application Using Clock Synthesis
Clock Microprocessor System Logic Logic
Logic
Logic
ClockBoost feature used create variable-size pulse widths. using multiplied frequency counter, create pulse widths various sizes depending multiplied frequency driving counter. These pulses used interface with external SRAM DRAM. example, write enable (WE), address strobe (RAS), column address strobe (CAS) signals generated SDRAM interface, meeting appropriate address data setup times. Figure
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115: Using ClockLock ClockBoost Features APEX Devices
Figure Using Multiplication Generate Pulses
ADDR
DATA
Pulse
Removing Board Delay
APEX 20KE device feedback pins allow designer reduce clock skew between several devices board. actively aligns feedback input GCLK input clock. dynamically adjusts output during operation account delay changes that occur temperature voltage. While designing board, should match return delay containing feedback input with delay each device involved. Similar delays ensure that aligned feedback input edge also aligned destination devices, eliminating delay. Figure illustrates board delay reduced using APEX 20KE device.
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115: Using ClockLock ClockBoost Features APEX Devices
Figure Reducing Board Delay Using APEX 20KE Device
GCLK1 CLKLK_OUT1 Device
Note
CLKLK_FB1
APEX 20KE Device
Device
Device
Note:
board design, route delay from CLKLK_OUT1 each device return route delay should equal.
Minimize delays between CLKLK_OUT CLKLK_FB signals APEX 20KE devices. Because feedback path closes loop, long delay board time poles phase loop, resulting unstable output. sure clock-out time plus board time less than period CLKLK_FB.
LVDS
EP20K300E larger devices, general-purpose PLLs configured LVDS interfaces. These PLLs interface with APEX 20KE LVDS differential input output blocks. multiply clock input LVDS/CMOS data conversion using dedicated, built-in parallel-to-serial serial-to-parallel converters.
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115: Using ClockLock ClockBoost Features APEX Devices
When APEX 20KE device configured LVDS, uses multiply CLK_LVDS2 input. Serial-to-parallel conversion circuitry uses multiplied clock convert high-speed serial LVDS data lower speed parallel CMOS data. multiplication factor used should match multiplexer/de-multiplexer ratio desired. example, conversion 1-to-8 required 622-Mbps LVDS channel, multiplication factor needed with clock input 77.75 MHz. needed, serial-to-parallel converter bypassed lowspeed LVDS data inputs. Figure shows built-in LVDS input interface with LVDS serial input Mbps multiplexer/demultiplexer ratio 1-to-8.
Figure APEX 20KE LVDS PLL/Input Interface
APEX 20KE LVDS
Serial Data Mbps data[7.0] Serial-to-Parallel Converter
CLK_LVDS2 77.75 Clock
77.75 Dedicated Clock
When APEX 20KE device configured LVDS, uses multiply CLK_LVDS3 input. Parallel-to-serial conversion circuitry uses multiplied clock convert lower speed parallel CMOS data higher speed serial LVDS output data. multiplication factor should match multiplexer/de-multiplexer ratio desired. example, conversion 7-to-1 needed 462-Mbps LVDS output, multiplication factor needed with input clock MHz. needed, parallel-to-serial converter bypassed low-speed LVDS serial output. Figure shows built-in LVDS output interface that converts internal parallel data into LVDS serial data with 7-to-1 ratio Mbps.
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115: Using ClockLock ClockBoost Features APEX Devices
Figure APEX 20KE LVDS PLL/Output Interface
APEX 20KE LVDS Interface
data[6.0] Built-in Parallel-to-Serial Converter Serial Data Mbps
66-MHz CLK_LVDS3
Internal Global Clocks
Internal Global Clock CLKLVDS_OUT3
Note:
LVDS mode, CLK_LVDS3 three remaining internal global clocks.
Clock Domain Conversion
APEX 20KE devices, ClockBoost circuitry used convert clock frequency (1.544 MHz) clock frequency (2.048 MHz), vice versa. ClockLock circuit special mode perform T1/E1 conversions; this multiplication done just setting appropriate values. with type clock domain data transfer, appropriate asynchronous design techniques transfer data from clock domain other. example, DCFIFO first-in first-out (FIFO) function used buffer data transfer. Figure shows DCFIFO that interfaces between clock domains. example, DCFIFO with input data clocked input clock. output DCFIFO should clocked with converted clock from output. Output data synchronized output clock. This same practice used synchronization across other clock domains.
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115: Using ClockLock ClockBoost Features APEX Devices
Figure Using DCFIFO Interface Between Clock Domains
DCFIFO
T1_data DATA
wrreq T1_clk
WRREQ wrreq WRCLK E1_sync_data
rdreq E1_clk
with T1/E1 ClockBoost Feature
RDREQ (ACK) RDCLK
Time-Domain Multiplexing
ClockBoost feature allows designers implement time-domain multiplexed applications which given circuit used more than once clock cycle. Depending whether circuit clocked ClockBoost circuitry APEX device, operate four times, respectively, system cycle. With time-domain multiplexing, given function implemented with fewer logic cells ESBs. example, circuit using multipliers, each multiplier uses total LEs. Alternatively, could implement circuit multiplier that used twice clock cycle using clock that system clock. input multiplier multiplexed switch between sets inputs; output de-multiplexed that drive multiplication results. While some needed accomplish multiplexing, cost outweighed saved from using multiplier. Figure shows schematic timedomain multiplexed circuit.
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115: Using ClockLock ClockBoost Features APEX Devices
Figure Time-Domain Multiplexed Circuit
dataa1[15.0]
datab1[15.0] Multiplier
producta[31.0]
dataa2[15.0]
productb[31.0]
datab2[15.0]
control signal
ClockLock
ClockBoost
same example applied circuit requiring four multipliers; circuit would clock 4-to-1 multiplexers instead 2-to-1 multiplexers shown Figure control line created using one-hot counter state machine enable output register clock cycle, permitting multiplier used four times single system clock cycle. Table shows reduction resource requirements.
Table Resources Required Multipliers
Design
multipliers multipliers, time-domain multiplexed with ClockBoost Four multipliers Four multipliers, time-domain multiplexed with ClockBoost
Required
1,788
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115: Using ClockLock ClockBoost Features APEX Devices
ClockShift Applications
Phase time delay adjustments clock outputs have many interface applications. example, adjusting delay allows designer meet strict timing requirements more easily. adjusting lead clock output, known clock delay between various clocks used improve clock-to-output setup times APEX 20KE external devices. Some high-speed SDRAMs other devices have access times that require fast setup times interface device given critical path. meet this requirement, adjust external clock output SDRAM that leads input clock specified amount time. adjusting clock edge, SDRAM's clock-to-output (tCO) will sooner, meeting fast setup time. Figure shows interface timing between APEX 20KE device SDRAM. example, have APEX 20KE device reading from high-speed SDRAM with Assuming 100-MHz system speed, 10-ns period, 3-ns board propagation delay (tPD) between SDRAM APEX 20KE device, combination delays This leaves only setup time into APEX 20KE device. adjusting output clock SDRAM lead amount equal (for APEX 20KE device) minus needed, timing requirement met.
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115: Using ClockLock ClockBoost Features APEX Devices
Figure Using ClockShift Meet SDRAM Timing
APEX 20KE Device
SDRAM
clk_in feedback
with ClockShift
tPERIOD
clk_in
APEX 20KE device
sdram_clk tPERIOD
Required
addition meeting setup times, intentional clock delay improve device's clock-to-output time, similar clock-to-output time SDRAM interface improved. Using lagging clock output devices makes device's clock-to-output time faster when compared system's clock. internal leading clock used registers also produces faster clock-to-output time output registers. also clock delay control instead feedback adjust clock delay other devices based their distance from clock source. Designers manually adjust external clock output APEX device compensate board delay. also phase adjustment interface with external device. input clock phase shifted with separate ClockLock ClockBoost circuits then output external outputs. example, these external outputs used together with input 3-phase motor.
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115: Using ClockLock ClockBoost Features APEX Devices
APEX 20KE devices, programmable phase shift limited period VCO. Figure shows relationship between scaling factors VCO. When scale factor large, period much smaller than input period, i.e., tVCO much lower than tCLKIN. scale factor large well, period much smaller than output period, i.e., tVCO much lower than tCLKOUT. range phase adjustments limited period; small period compared output clock period means phase range will especially small clock output. Figure shows example waveforms scaling factors affect phase range. Choose that period long enough desired phase shift range.
Figure Scaling Factor Relationship Voltage-Controlled Oscillator
clkin clkout
ClockShift Circuitry
clkin
fVCO
clkout Phase shift limit period
Software Support
ClockLock ClockBoost features APEX devices enabled through Quartus software. software uses CLKLOCK megafunction utilize ClockLock ClockBoost features, which allows user specify operating frequency input ClockBoost clock multiplication factor.
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115: Using ClockLock ClockBoost Features APEX Devices
GCLK1 dedicated input that feeds both ClockLock ClockBoost circuitry. combinations output clocks utilized, such When outputs generated, other clock (GCLK0) cannot used. designs that require outputs from ClockLock ClockBoost circuits, clock trace board should connected GCLK1 only. When clock outputs used, input frequency parameter must same both circuits. this case, input frequency parameter must meet requirements specified highest multiplied output clock. example, both output used, input frequency must meet input frequency requirement MHz. Figure shows block diagram example enable ClockBoost circuit outputs Quartus software. example shown schematic, similar approach applies designs created Altera Hardware Description Language (AHDL), VHDL, Verilog HDL.
Figure Implementing Multiple ClockLock ClockBoost Functions
CLOCKBOOST=4 INPUT_FREQUENCY=33
CLKLOCK
outa
gclk1 CLKLOCK
CLOCKBOOST=2 INPUT_FREQUENCY=33
outb
parameterized CLKLOCK function also allows APEX 20KE devices control multiplication shifting. this function Quartus design entry editors (AHDL, VHDL, Verilog HDL, Block Editor). Quartus software includes utility generating simulation files VHDL Verilog third-party tools.
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115: Using ClockLock ClockBoost Features APEX Devices
Conclusion
advanced APEX ClockLock ClockBoost features PLLs provide significant improvements system performance design versatility. reduction clock delay elimination clock skew within device improves design speed, time-domain multiplexing improves area usage. ClockBoost feature simplifies board design running internal logic device faster rate than input clock frequency. advanced APEX 20KE ClockLock ClockBoost feature further enhanced with m/(n multiplication, LVDS interfaces, phase adjustment more complex clock synthesis applications.
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Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: (888) 3-ALTERA lit_req@altera.com
Altera, APEX, APEX 20K, APEX 20KE, ClockBoost, ClockLock, ClockShift, EP20K100, EP20K100E, EP20K160E, EP20K200, EP20K200E, EP20K300E, EP20K400, EP20K400E, EP20K600E, EP20K1000E, Quartus, System-on-a-Programmable-Chip trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 1999 Altera Corporation. rights reserved.
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Application Note 1999, ver. Introduction APEX20K device

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