PSoC Designer Version Beta Release Release Date: 2006 Thank your

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PSoC Designer Version Beta Release
Release Date: 2006 Thank your interest PSoC Designerversion 4.3. information this document lists installation requirements describes software updates changes. System Requirements Recommendations System Requirement Processor Speed Free Hard Drive Space Screen Resolution CD-ROM Drive Parallel Port Port, preferably Open Host Controller Universal Windows® 2000, (SP1) Microsoft Internet Explorer (SP1) Adobe Reader (For Viewing .pdf Documentation) Updates Check latest downloads software documentation. efficient math library routines that reduce Flash size improve performance. math library documented "PSoC Designer: Libraries User Guide". PSoC Power Estimator tool added CY8C24x94 family. Inclusion PSoC Designer service packs. Improved Filter Design Wizard User Modules Design Rule Check (DRC) that power when block placed. Design Rule Checks (DRCs) enabled default. PSoC Designer used from non-administrative account. Extensibility support enables future Service packs Extension packs incrementally installed removed. Minimum 1024x768 Recommended 1280x1024
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Defects Repaired (7219) Corrected code generation error that caused I2CCFG register reset when I2CHW EZI2C User Module unplaced deleted. (8270) Corrected code generation errors with Dynamic Reconfiguration that could leave register bank setting Bank instead Bank (6994) Corrected code generation errors that prevented generation psocgpioint.h psocgpioint.inc when names been entered user, GPIO interrupt sources been enabled. (7563/8256) Corrected code generation PRT5IE register CY8C24X94 CY7C64215 devices. Fixed CY7C63300/m8c.h, CY7C63800/m8c.h, CY7C63900/m8c.h. defines TCAPINTE TCAPINTS have been given same name TMRCR (7318) Updated boot.tpl CY7C603XX devices remove conditional code since these devices spec'ed 2.4-3.6V operation only. (8240) Updated boot.tpl CY8C29XXX devices decimator into full algorithm mode start boot sequence. This saves power consumption decimator used application. (8271) Updated boot.tpl CY8C24x94 ACB00CR0/ ACB01CR0 preferred default state. (8150) Previously, character allowed entered grid names. Some special characters caused compiler/assembler errors. Those characters have been restricted. (8246) Compiler License Agreement Dialog works properly most non-English Languages Updates That Affect Previous Projects Analog Comparator Update: Previous PSoC Designer when using dynamic re-configuration, analog comparators stayed connected from configuration configuration, manual overwrite required remove connection when moving from configuration another. PSoC Designer clears analog comparator connections between configurations. Protect Project from Unintentional Alteration: projects created before PSoC Designer 4.3, used analog comparators, aware that PSoC Designer will disconnect connected analog comparators configurations except base configuration. Check comparator connections configurations reconnect comparators that have become disconnected when upgrading PSoC Designer 4.3. Floating-Point Math: floating-point implementation been completely rewritten. Except feature, version implements IEEE-754 standard floating-point numbers (single precision). omission that denormalized numbers truncated `0'. implementation adhere IEEE standard, calculations using implementation necessary binary identical calculations using implementation.
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Updates Enhancements User Modules Datasheets most User Modules have been updated correct documentation error clarify User Module characteristics. (6492) USBFS: Several defects have been repaired. USBFS have passed (USB Spec) Chapter Chapter testing (8302) USBFS: Updated ReadOUTEndpt() function change Clock during when extracting data from Endpoint buffers. (7766) AMPINV: Changed default RTapMux values R15_1 gain R14_2 gain. (8363) I2CHW: Fixed file definition I2C_TX (7494) I2CM: Prevent assignment same pin. User Modules Details following User Modules reviewed PSoC Designer Device Editor User Module Selection View. User Modules supporting PSoC devices. Segment (LED7SEG) Light Emitting Diode (LED) User Modules supporting CY8C42XXX PSoC devices. Incremental (ADCINC) Fixed Function Counter/Timer (ATMRCTR16) Analog Comparator (CMP) Current (IDAC) Voltage (VDAC) Integrated 16-Bit with Deadband (IPWMDB8/IPWMDB16) Power Block (PBLOCK)
Reference Designs Design Browser Removal Modem 3000 Design Modem 3000 Design project been removed. found Cypress site.
PSoC Designer Project Migration Compatibility dialog boxes encountered when opening project from older release: first "Old Version" dialog box. notifies user about necessity update current project order comply with current version PSoC Designer gives option perform project update immediately postpone until later. changes made boot.tpl, such added jumps interrupt vector table, must migrated boot.tpl. second dialog "Outdated User Modules" dialog box. This dialog provides users with list outdated User Modules. update process happens automatically during source generation. When source generated, files
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will added project file will moved backup directory. interrupt files contain start/end markers user code. User code placed within user code markers will automatically carried into file. migration, make sure that user code between user code markers following first "Generate Application" invocation after upgrading 4.2. have modify source code manually after first application generation avoid compilation errors. Source must generated before closing updated project dialog order update take effect. source generated, files will remain project out-of-date status will lost. updated file generated your project time. Right-click file source tree select Remove from Project. When source generated, file will added project file will moved backup directory. When migrating projects CY8C29x66 using cloning, compiler linker will default using small memory model (SMM). Project Settings, Compiler "Enable paging" large memory model (LMM). When migrating projects CY8C29x66 using assembly language: Additional code required manage pages. small number User Module function calls need changed. AN2218 PSoC Large Memory Model Programming details. Reference Application Note AN2218 PSoC Large Memory Model Programming under .\Program Files\Cypress MicroSystems\PSoC Designer\Documentation http://www.cypress.com guidance. CY8C25xxx/26xxx CY8C27xxx Project Migration Application Note AN2131 migrating projects product family. This process mostly automatic, require some manual steps. (.\Program Files\Cypress MicroSystems\PSoC Projects CY8C27). Note that Ports have swapped pins CY8C27xxx parts with respect CY8C26xxx parts. This will affect 48-pin project. Projects from previous PSoC Designer releases will have projectname_globalparams.inc projectnameapi.h under Library Source folder. These files have been replaced with globalparams.inc psocapi.h manually removed right-clicking file icon selecting Remove from Project.
Documentation User guides documents located \Documentation subdirectory PSoC Designer installation directory. default location C:\Program Files\Cypress MicroSystems\PSoC Designer\Documentation. This directory accessed within PSoC Designer under Help Documentation. documents .pdf files that require Adobe Reader. Documents include: PSoC Designer: Integrated Development Environment User Guide PSoC Designer: Assembly Language User Guide PSoC Designer: Language Compiler User Guide PSoC Designer: ICE-4000 Adapter Installation Guide PSoC Designer: Connection Troubleshooting Guide PSoC Designer: PSoC Programmer User Guide PSoC Designer: Libraries User Guide CY8C29x66 PSoC Mixed-Signal Array Data Sheet
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CY8C27x43 PSoC Mixed-Signal Array Data Sheet CY8C25-26xxx PSoC Device Family Data Sheet CY8C24794 PSoC Mixed-Signal Array Data Sheet CY8C24x23A PSoC Mixed-Signal Array Data Sheet CY8C24x23 PSoC Mixed-Signal Array Data Sheet CY8C22x13 PSoC Mixed-Signal Array Data Sheet CY8C26xxx_Master.pdf Interface Diagram/Worksheet Help: Document Links PSoC Technical Reference Manual (TRM) Large Memory Programming Migrating Large Memory Model PSoC Devices PSoC Compatibility Guide PSoC Device Selector Guide AN2209
Supporting documents PSoC Designer's public-domain functionality, such "Find Files" text search (grep.pdf) build utility (make.pdf sed.pdf), located .\Program Files\Cypress MicroSystems\PSoC Documents.
Tele-Training recommended that first time users attend Module Introductory Module TeleTraining program. following Tele-Training modules available: PSoC Pre-Recorded Video Module Introductory Module PSoC Pre-Recorded Video Module Getting Started Designing PSoC Pre-Recorded Video Module Getting Started Debugging PSoC Pre-Recorded Video Module Dynamic Re-configuration PSoC Module Advanced Analog Design PSoC Pre-Recorded Video Module Introduction PSoC Express PSoC Pre-Recorded Video Module CY3210-ExpressDK PSoC Express Development PSoC Pre-Recorded Video Module Hands PSoC Express Capacitive Touch Sensing with PSoC Jazz-up your user interface with PSoC-enabled Capacitive Touch Sensing details.
Example Projects instructive user view test Example Projects. They located three directories product family: .\Program Files\Cypress MicroSystems\PSoC Designer\Examples\CY8C24, .\CY8C27, .\CY8C29, respectively. (This default installation path PSoC Designer.) Example projects include: Examples CY8C24x23A, CY8C27x43, CY8C29x66 parts: ASM_Example_ADC_UART_LCD ASM_Example_Blink_LED ASM_Example_DAC_ADC
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ASM_Example_Dynamic_PWM_PRS ASM_Example_LED_Logic C_Example_ADC_UART_LCD
Installation Issues Parallel Port Considerations Proper installation PSoC Designer Windows NT/2000/XP requires user have local Administrator permission. Windows Active Desktop supported. PSoC Designer function correctly Windows Active Desktop enabled. Windows compatibility mode causes problems PSoC Designer's debugging with parallel port. Compatibility mode should enabled. Upgrading from Windows 95/98/Me Windows NT/2000/XP requires uninstalling PSoC Designer before upgrade reinstalling PSoC Designer after Windows upgrade. this done, PSoC Designer's parallel port drivers will updated match operating system. Windows logging cause problems with parallel port connections ICE. This fixed execution following steps: Open Start Menu Select Settings Open Control Panel Open Administrative Tools Open Local Security Policy (may available Windows Home Edition) Open Local Policies Open Security Options Disable "Strengthen default permissions internal system objects" setting Reboot
PSoC ICE-4000 provides significant debugging functionality that requires full twoway communication over ICE-4000 operate. There several steps connection process, including both setting hardware, making communications connection software. Making software connection will likely require changes BIOS settings port. Some recent laptops support Bidirectional modes BIOS needed full two-way communication over ICE-4000. relatively easy method that bypasses need changing BIOS settings install parallel port card. This added benefit providing dedicated port without potential conflicts with other applications printers user have their computer. PSoC Designer: Troubleshooting Guide details parallel port cards both desktops laptops that have been tested compliance with ICE-4000. mode operation parallel port affected when some laptops return from sleep. Often, connection cannot resumed. Rebooting system rectifies this situation. Considerations
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have trouble connecting ICE-4000 Adapter ICE-Cube, Debugger Subsystem Debugger Error Messages PSoC Designer Help System PSoC Designer: Troubleshooting Guide more details. problems persist, contact Cypress MicroSystems. want assist with connection. information PSoC Designer Help System PSoC Designer: Troubleshooting Guide sufficient resolve issues, please following resources: TightLink Email Support System enter support request this system with guaranteed response-time four hours: Support Forums View participate discussion threads about wide variety PSoC device topics: http://www.cypress.com/forums/. Open Host Controller Interface (OHCI) allows communication with operate faster than Universal Host Controller Interface (UHCI). This improves download debugging speed. find which interface using, "Device Manager," look under "Universal Serial controllers" heading. will these three Host Controllers: Universal, Open, Enhanced. Based port which connected, Adapter will default either Universal Open. Typically, Intel motherboards have UHCI. Most hubs OHCI. Hardware Rev. Pods required emulation CY8C22x13, CY8C24x23, CY8C27x43, CY8C29x66 parts. Rev. Pods, later, required CY8C25xxx/26xxx family devices. ICECube in-circuit emulator does support CY8C25/26xxx family. ICE-4000 will continue support this family PSoC devices. YProgrammer boards required programming CY8C22x13, CY8C24x23, CY8C24x23A, CY8C25xxx/26xxx, CY8C27x43, CY8C29x66 family devices using ICE-4000. ICE-Cube, with attached ISSP cable, will enable programming without YProgrammer. Device Editor Subsystem Notes Errata Cloning from PSoC device PSoC device which number analog resources reduced (i.e., From CY8C24xxx CY8C22xxx) cause more analog User Modules un-placeable. will required delete analog User Module then same User Module back into project. Clock global resource setting PSoC devices that have SLIMO feature display Clock frequency "SysClk/N" where {1,2,4,8,16,32,64,128 256}. customers updating CY8C29x66 CY8C24x23 PSoC devices, Clock setting will default "SysClk/8" MHz) upon opening project first time this release. This change. Changing value then saving project will restore correct Clock global parameter.
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Printing project data sheet very large project result missing user module parameters. Acer TravelMate Notebook (with MOBILITY RADEON 9000 Graphics Adapter) cause schematic area Interconnect View blank when Navigation Help window appears. Closing Navigation Help window causes Interconnect View window divider moved.
Debugger Subsystem/ICE Errata Debugger does detect Flash size limits during emulation. parts that have less than Flash, user must exercise caution that designs work within memory limits. complex/sequential breakpoints offered Events feature Debugger subsystem provide means detecting stack memory overflows during development. Analog register display scrambled when Successive Approximation Register (SAR) operation enabled. Enabling operation (i.e., count Analog Synchronization Register (ASY_CR) scrambles Debugger register Bank analog register displays. Enabling will stall until analog register data ready, does stall on-chip Debugger interface used PSoC Designer. result, analog register contents displayed PSoC Designer incorrect. programs that read registers will still correct data. This only affects analog block registers. some machines, unplugging from result inability reconnect. this occurs, power cycling required. Adding Flash watch variable will default address. correct this, re-select FLASH memory space Flash Watch Variable's property dialog box. Watch variables cannot with values greater than 0x7FFFFFFF.
Debugger Subsystem/ICE Notes Debugger switches operation when halted. status shows user-selected speed while halted on-chip digital PSoC blocks will running with SysClk MHz. This affect external hardware. System clock-jitter target circuit board cause emulation fail when mode enabled. failure symptom usually Invalid Memory Reference. Debugger cannot halt immediately after instruction that puts into sleep mode. This means that cannot step over sleep, breakpoint immediately after sleep, halt event point immediately after sleep. Placing breakpoint further away from sleep instruction recommended. Clicking Halt icon exit sleep okay, assuming that sleep interrupt been enabled. sleep interrupt been enabled part goes into sleep, will disconnect when halt executed. Occasionally, with Adapter, will disconnect when debugging with sleep. breakpoint instruction immediately following SSC_Action macro will halt debugger. breakpoint will halt second instruction after SSC_Action macro. When CY8C29xxx/27xxx/24xxx/22xxx parts being debugged, enables sysclk (doubler).
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False event triggers occur. Setting event break Instruction Register (IR) with (opcode 0x40) will trigger event following "go" from reset. Setting event break when Program Counter (PC) above user code will cause halt occur following "go" from Reset. Compiler/Assembler/Build System Errata certain corner case input values (close zero infinity), following functions found math.h known return incorrect results: sinh(), cosh(), tanh(), atan2(). Internal references prevent elimination from removing certain parts functions that ought removed.
Compiler/Assembler/Build System Notes "TOP" area reserved boot code (boot.asm) special linker implications. create code within "TOP" area declared another source file, other than boot.asm. total size arrays structures limited bytes, even large memory model. code compressor makes debugging very difficult when more blocks code combined into single "subroutine." problem that debugger does know which chunk associated source code display. This partially mitigated using step assembly necessary when possible, turning code compression off.
Library Notes low-level arithmetic library routines provided. They called from well assembly language. routines faster more compact than previous implementation. routines documented PSoC Designer: Libraries User Guide.
User Module Errata ADCINCVR iGetData result data skewing interrupt occurs between handling. work around flag check mismatched data between MSB. (8362) known issue Timer8, Timer16, Timer24, Timer32 User Modules cause build error CY8C42XXX device family. This will fixed before final release PSoC Designer 4.3.
assistance http://www.cypress.com contact Application Team 425.787.4814.
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Silicon Errata CY8C25xxx/CY8C26xxx CY8C22/24/27/29xxx most up-to-date versions silicon errata available site following link navigating Software Drivers Errata Update (tab) PSoC Mixed-Signal Array http://www.cypress.com/psoc.
Cypress Semiconductor 2700 162nd Street Building Lynnwood, 98037 Phone: 425.787.4400 Fax: 425.787.4641 Application Support Hotline: 425.787.4814 http://www.cypress.com/ Copyright 2005 Cypress Semiconductor Corporation. rights reserved. "Programmable System-on-Chip," PSoC, PSoC Designer PSoC Express trademarks Cypress Semiconductor. other trademarks registered trademarks referenced herein property their respective owners. information contained herein subject change without notice. Made U.S.A.
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PSoC Designer Version Beta Release Release Date: 2006 Thank your

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