78P2241B, 78P2242, 78P2243, 78P2244, 78P7200L, 78P7202L, 78P7203L 78P7

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78P2241B, 78P2242, 78P2243, 78P2244, 78P7200L, 78P7202L, 78P7203L 78P7

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DS3/E3/STS-1 Test Board
78P2241B, 78P2242, 78P2243, 78P2244, 78P7200L, 78P7202L, 78P7203L 78P7204L DS3/E3/STS1 transceiver from Semiconductor Corporation. This application note will explain design test board using ALTERAEPM7128ALC84-6 FPGA PLCC package. When tied 78P224x 78P720xL demo board, unframed DS3/E3/STS1 signal transmitted received
Using board control switches, generate either fixed PRBS pattern. test board includes crystal oscillator accept external CMOS clock that indicates frequency operation (DS3/E3/STS1).
FEATURES
Allows easy evaluation 78P224x 78P720xL DS3/E3/STS1 transceivers. Includes necessary external components. Includes switches control pattern options. Operates DS3, STS-1 selecting oscillator applying external clock. Generate fixed PRBS pattern. Detects fixed PRBS pattern. Indicates errors errors LEDs. test board operates supply. layer board construction.
DESCRIPTION
test board generates fixed PRBS data stream. also detects similar pattern indicates errors using LEDS. When tied 78P224x 78P720xL chips DS3/E3/STS-1 transceiver demo boards, emulates some functions HP3784 ANT20.
DS3/E3/STS-1 Test Board
Clock Circuitry
Serial Interface
ALTERA Gate Array
Optional Interface
Options Select Switches
LED's Display
FIGURE Test Board block Diagram POWER SUPPLY CONNECTION test board constructed four-layer board. outer planes carry signals. internal layers ground power supply planes. power supply pins connected directly supply planes (see Layout Files Figures: 12). power supply taken from 78P224x 78P720xL demo board power placing jumper VCC2 position needed, test board 224X demo board supplied independent power supplies placing jumper VCC2 position test board requires 3.3V supply. Additionally, difference between boards should less than 0.7V prevent protection diodes from conducting clamping signals. FUNCTIONS DESCRIPTION test board will generate patterns check data integrity. seven-bit display will show error count. green will show that signal detected receive line. green will error encountered asserted. green will only back when RST1 button pushed. Transmit clock furnished either crystal oscillator external source. test board does include BLASTER connector customer load customized program into FPGA. PATTERN GENERATION ALTERA gate array provides five different patterns follow: Pseudo Random Binary Sequence (PRBS) either (DS3/STS-1) (E3) depending switch setting S1-1. fixed pattern 001, this sequence used check pulse mask STS-1. fixed pattern fixed pattern zeros. This pattern enables customer check B3ZS (Binary Three Zeros Suppression) HDB3 (High-Density Binary Three) codes. fixed pattern ones. PATTERN CHECKING data integrity checker implemented gate array, this checker will increment seven counter every time error detected. This error counter displayed LED's Depending setting S1-8, this counter will count either errors Line Code Violations (LCV).
DS3/E3/STS-1 Test Board TRANSMIT CLOCK transmit clock supplied from crystal oscillator situated This crystal oscillator either DIP. layout will accommodate both packages. transmit clock supplied from external source connector CLK1 well. drive clock input transmit clock selected from sources mentioned above placing jumper CLKI position ALTERA gate array generates transmit clock, then jumper CLKI needs position SERIAL INTERFACE male DB15 (P1) connector will connection between test board 78P224x/78P720xL demo board. signals traveling this connector are; SIGNALS allocation LOSN RPOS RNEG/LCV RCLK TPOS TNEG TCLK Table Interface Signals LINE DENSITY CODING output signal should properly coded prevent long zeros line. proper code will limit number zeros three depending rate. Table shows proper coding required rate: SPEED Mbit/s Zeros 44.736 STS-1 51.840 34.386 Table Coding names rates RATE CODE NAME B3ZS B3ZS HDB3
ERROR COUNTER error counter seven counter, will increment every time there error either error error, depending position S1-8. counter will ones asserted. DISPLAY display will reflect contents seven error counter Green will show status errors, either asserted error occurred then green will shut off. asserted will RESET power-on, reset pulse will generated; length this pulse long enough, order data travelling through 1000 feet cable have time reach data checking logic. This means that power-on, error counter will zero green will assuming that cabling done correctly. RST1 When this push button depressed error counter green will reset. INCRER1 push this switch will generate error. Only works when S1_8 OPEN. HEADER This header used customer specific needs. example, trigger function Oscilloscope. CONNECTOR (P2) Used extension software would Gate Array. PERFORMING TESTS WITH DEMO BOARD general test setup using test board shown figure this configuration demo board exercised test performance LIU. Cable flat attenuation added test sensitivity receiver. following tests performed receiver. ERROR RATE TEST test board generates pseudo-random pattern. This pattern created using shift register bits. combination 2**N-1 patterns bits created random manner. This pattern used simulate
This code setting selected with switch S1-1 (see Table 78P224x option that will either enable disable Encoder /Decoder, coding done gate array then switch S1-3 needs OPEN position demo board need have ENDEC disabled. When coding done then switch S1-3 needs CLOSED position demo board needs have ENDEC function enabled. 78P720xL does offer ENDEC function; therefore, S1-3 needs OPEN position.
DS3/E3/STS-1 Test Board TRANSMITTER TESTS pulse generated tested shape, amplitude, frequency contents over different lengths cable. demo board connected show Figure ALTERA SELF TEST contents ALTERA gate array tested with test board stand-alone. test functions test board, S1-4 open position. SWITCHES This bank switches used this board.
live traffic line. following table shows typical patterns test SPEED RANDOM PATTERN 2**15-1 STS-1 2**15-1 2**23-1 Table Test patterns. FIXED PATTERN 100100 100100 100100
When running these patterns, error ratio should lower than test repeated fixed patterns exercise pattern sensitivity. SWITCH SETTINGS CODING SELECTION (S1-1)
CODE HDB3 B3ZS
RATE DS3/STS-1
S1_1 CLOSED OPEN
S1-2 used. Leave OPEN. ENDEC (S1_3) S1_3 OPEN CLOSED ENDEC HIGH (OFF) (ON) Serial Data Interface TPOS TNEG TPOS only
ALTERA LOOP BACK (S1_4) S1_4 OPEN Loop back CLOSED loop back Generated Pattern ALTERA (S1_5,6,7) S1_5 S1-6 S1-7 PATTERN CLOSED CLOSED CLOSED CLOSED OPEN CLOSED CLOSED CLOSED OPEN Zeros CLOSED OPEN OPEN Ones OPEN PRBS SELECT ERROR COUNT COUNT (S1_8) S1_8 errors count count OPEN CLOSED
Table Switch settings
DS3/E3/STS-1 Test Board
Rxin cable 78P2241 Demo Board cable Txout
ALTERA test board
Figure Test performance testing
Rxin 78P2241 Demo Board cable Txout
ALTERA test board
Tek.
Termination Channel Oscilloscope Tektronix 784C
Pattern Pseudo Random Pattern STS-1
input channel input impedance.
scope pulse mask Checking mask STS-1
Figure Test pulse mask checking
DS3/E3/STS-1 Test Board
VCC2 DB15M SCLK1 0.1UF TXCLK SW1-1 SW1-2 SW1-3 SW1-4 SW1-5 SW1-6 SW1-7 SW1-8 SW2-1 SW2-2 SW2-3 SW2-4 SW2-5 SW2-6 SW2-7 SW2-8 CLKI LSON RPOS RNEG LPBK RCLK ENDEC MODE TNEG TPOS
IO79 CCCCCCCC IO77 IO76 IO75 IO74 IO73 IO70
MORE HEADER20
IO69 IO68 IO67 IO65 IO64 IO63 IO61 IO60 IO58 IO57 IO56 IO55 IO54 IO52 IO51 IO50 IO49 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8
VCC3
XCLK SW1-1 SW1-2 SW1-3 SW1-4 SW1-5 SW1-6 SW1-7 SW1-8 SW2-1 SW2-2 SW2-3 SW2-4 SW2-5 SW2-6 SW2-7 SW2-8 INCERB RSTB CLK1
DB15F
INCERB RSTB CLK1 CLRN
EPM7128
BLASTER1 HEADER10 DDDDDDDD NNNNNNNN GGGGGGGG
Figure Test Board Schematic.
DS3/E3/STS-1 Test Board
RST1 74AC14 10UF INCRER1 10UF 74AC00 74AC00 74AC00 INCREB 74AC14 74AC00 RSTB 74AC14 VCC1 GND1 74AC14
74AC14
74AC14
NC10 EC1145TS
CLK1 XCLK
CLKI1
10UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
Figure Test Board Schematic.
DS3/E3/STS-1 Test Board
SW1-1 SW1-2 SW1-3 SW1-4 SW1-5 SW1-6 SW1-7 SW1-8
DIP-8
SW2-1 SW2-2 SW2-3 SW2-4 SW2-5 SW2-6 SW2-7 SW2-8
DIP-8
Figure Test Board Schematic.
DS3/E3/STS-1 Test Board
Figure Layer Signal Traces.
Figure Layer plane.
DS3/E3/STS-1 Test Board
Figure Layer Ground Plane.
Figure Layer Bottom Traces.
DS3/E3/STS-1 Test Board
Figure Assembly
Figure Bottom Assemblies.
DS3/E3/STS-1 Test Board Altera contents obtained request sales offices.
responsibility assumed SEMICONDUCTOR CORPORATION this product infringements patents trademarks other rights third parties resulting from use. license granted under patents, patent rights trademarks Semiconductor Corporation company reserves right make changes specifications time without notice. Accordingly, reader cautioned verify that referencing most current data sheet before placing orders. site http://www.tsc.tdk.com contact your local Semiconductor representative. Semiconductor Corp., 2642 Michelle Dr., Tustin, 92780, (714) 508-8800, (714) 508-8877, http://www.tsc.tdk.com Semiconductor Corporation 01/05/01
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78P2241B, 78P2242, 78P2243, 78P2244, 78P7200L, 78P7202L, 78P7203L 78P7

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