S19252 STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with Clock

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

S19252 STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with Clock

Datasheet Thumbnail

Top Searches for this datasheet

S19252
STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with Clock
Features
Operational from Gbps 11.3 Gbps Built-In Self Test (BIST) with Error Counter On-chip High-Frequency PLLs Clock Recovery Clock Gen. 16-bit LVDS Parallel Data Path Lock Detect Indicators Reference Loop Timing Modes Line Diagnostic Loopback Mode Faulty Node Identification -40°C 85°C Industrial Temperature Range Supports MDIO, serial interface Complies with applicable SFI-4 Phase Telcordia/ITU-T, 300-pin MSA, IEEE 802.3ae Standards 2000 rating speed pins, 1000 high speed I/Os mm2, pitch package with Green RoHS compliant lead free option. typical JTAG support
Description
S19252 MUX/DeMux chip fully integrated serialization/de-serialization SONET STS-192/10 Ethernet/Fiber Channel transceiver with Electronic Dispersion Compensation (EDC). This device used compensate channel impairments caused Single Mode Fiber (SMF) copper medium. chip performs necessary parallel-to-serial serial-to-parallel functions conformance with SONET/SDH, Gigabit Ethernet GbE) Gigabit Fibre Channel transmission standards. figure below shows typical network application. other application block diagrams shown page On-chip clock synthesis components contained S19252 chip, allowing slower external transmit clock reference. chip used with 155.52 622.08 equivalent FEC/10 GbE/10 rates) reference clocks, support existing system clocking schemes. low-jitter LVDS interface guarantees compliance with bit-error rate requirements Telcordia ITU-T standards.
AMCC Suggested Interface Devices GANGES (S19202) Rubicon/Niagara HUDSON (S19203) STS-192 POS/ASONET/SDH Mapper OC-192/48/12/3 DW/FEC/PM ASYNC Mapper Device Variable Rate Digital Wrapper Framer/Deframer, Performance Monitor, Device STS-192 Pointer Processor STS-192c SONET/SDH Framer/Mapper with Integrated Dual imbedded module
MEKONG (S19204) KHATANGA (S19205) S19233
Transmitter Features
Ref. Freq. 155.52 622.08 rate); Common GbE/10 Ref. 156.25 159.375 Divide rates Internal, Self-Initializing FIFO Decouple Transmit Clocks Programmable Output Differential Swing Transmitter Serial Clock Output Binary Encoding
sequence operations follows: Transmitter Operations
16-bit parallel input Parallel-to-serial conversion Serial data output Serial clock output Serial input post-Amplifier compensation RSSI Threshold phase adjustment improved Clock data recovery Serial-to-parallel conversion 16-bit parallel data clock output
Receiver Operations
Receiver Features
LOS/RSSI compensation. Tolerates additional chromatic dispersion with OSNR penalty 1.0dB over traditional demux Tolerates Standard FR-4 Material Adaptive Post-Amplifier Offset Adjust Phase Adjust -0.11 +0.085 Ref. Freq. 155.52 622.08 rate); Common ref. 156.25 GbE/10 159.375 GFC; Divide rates Capability Interface with Single-Ended Differential TIAs (Center Option) Input Sensitivity (one wire wire) 10-12
Overview
S19252 transceiver incorporates SONET/ SDH/10 GbE/10 Fibre Channel serialization deserialization functions. This chip used implement front SONET/10 GbE/10 Fibre Channel equipment, which consists primarily serial transmit interface serial receive interface. chip includes parallel-to-serial, serial-to-parallel conversion system timing.
Internal clocking control functions transparent user.
Applications
SONET/SDH 10GbE-Based Transmission Systems Modules Section Repeaters Drop Multiplexers (ADM) Broad-Band Cross-Connects Fiber Optic Test Equipment
AMCC
GANGES HUDSON MEKONG KHATANGA RUBICON
AMCC S19252 data
AMCC S19252
AMCC
GANGES HUDSON MEKONG KHATANGA RUBICON
data
System Block Diagram with S19252
SPECIFIC IONS
S19252
Enable Adaptive Post-Amplifier Offset Control Compensates FR-4
MDIO/I2C /SPI
ASIC
AMCC S19252
MDIO/I2C /SPI
AMCC S19252
ASIC
Enable Adaptive Mitigation
Figure Mid-Plane Application Block Diagram
Enable Adaptive Post-Amplifier Offset Control Enable Adaptive Mitigation Disable Clock
MDIO/I2C /SPI
ASIC FRAMER
AMCC S19252
MODULE
Compensates FR-4 (Improves Performance extends reach standard Module)
Figure Application Block Diagram
ASIC FRAMER
Control
MODULE
Laser
AMCC S19252
Laser Driver
Post Amplifier Required
Figure Application Block Diagram
6290 Sequence Diego, 92121 9333 9885 www.amcc.com
technical support, please call 1-800-840-6055 858-535-6517, email support@amcc.com. AMCC reserves right make changes products, datasheets, related documentation, without notice warrants products solely pursuant terms conditions sale, only substantially comply with latest available datasheet. Please consult AMCC's Term Conditions Sale warranties other terms, conditions limitations. AMCC discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information current. AMCC does assume liability arising application product circuit described herein, neither does convey license under patent rights rights others. AMCC reserves right ship devices higher grade place those lower grade. AMCC SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. AMCC registered trademark Applied Micro Circuits Corporation. PowerPC PowerPC logo registered trademarks Corporation. other trademarks property their respective holders. Copyright 2006 Applied Micro Circuits Corporation. Rights Reserved. S19252_PB2028_v1.01_20061031

S19252 STS-192 SONET/SDH/FEC/GbE/FC 16-bit Transceiver with Clock

Top Searches for this datasheet

Other recent searches