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INTRODUCTION following design considerations outline applications gene


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Design Considerations FlashFlex51 Family Microcontroller
INTRODUCTION following design considerations outline applications generally accepted design practices prevent data corruption issues that could encountered when using single power-supply microcontrollers with embedded EEPROM such SST89F54/58 devices. types data corruption encountered described below: False Write occurs during intentional write cycle, when either data loaded address loaded incorrect. Inadvertent Write occurs when valid write command issued unintentionally. wide traces VDD. SST89F54/58 devices with maximum minimum trace width mils. Trace widths should twice that VDD. Keep bypass capacitors close power pins device possible. socket used, additional 1-10 capacitor between VSS. Specifically SST89F54/58 devices, high quality grade capacitors. recommends high frequency ceramic capacitor placed close possible between VSS, i.e. less than away from device. Additionally, frequency electrolytic capacitor from should placed within pin. Ensure that power supply does have more than peak-to-peak noise device's pins. Make this check while sending random data, both during power-on ramp steady state operation.
causes these problems described below: noisy circuit cause False Writes well Inadvertent Writes. These errors minimized using generally accepted board layout decoupling practices. Incorrect power-up power-down sequence cause Inadvertent Writes. Correct power-up power-down sequences minimize these errors. inadequate power-on ramp rate cause Inadvertent Writes. Considering ramp rate when tuning external power-on reset circuit minimize these errors.
EXTERNAL POWER-ON RESET CIRCUIT When powering microcontroller, power supply voltage must traverse full voltage range VDD) before power supply voltage reaches final operating level. Some circuits device (e.g., logic) will start operating voltage levels lower than other circuits chip (e.g., flash memory); therefore, some circuits power unknown state. Powering device without valid reset could cause microcontroller start executing instructions from indeterminate location. Such undefined states cause inadvertent write flash. guarantee that SST89F54/58 devices start known state, system application must contain power-on reset circuit. When power applied SST89F54/58 devices, must held high long enough external oscillator start addition required machine cycles valid power-on Reset. common method extend signal implement circuit connecting through capacitor through resistor shown Figure Provisions must made ensure rise time, does exceed external oscillator with slow startup time, reset signal must extended order account delay. time taken oscillator start often varies depending manufacturer, e.g.
following sections discuss application considerations address these specific issues. GENERAL BOARD LAYOUT GUIDELINES Reliable operation high-frequency analog digital environment requires that some basic board layout rules followed. recommends implementing generally accepted design practices order minimize noise. They include: preferred method designing high-speed application printed circuit board, where user control layout power ground planes. Many high-speed applications that laid wire wrap board will work reliably. board with separate planes. Ensure that connection between each supply corresponding power/ground plane short possible (less than mm).
1999 Silicon Storage Technology, Inc. 216-01 8/99
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. FlashFlex, In-Application Programming trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Design Considerations FlashFlex51 Family Microcontroller
Application Note start times varied from tests various manufacturer's frequency crystals. system reset initializes SST89F54/58 devices begins program execution program memory location 0000h. reset input SST89F54/58 devices pin. order reset SST89F54/58 devices, logic level high must applied least machine cycles clock cycles), after external oscillator becomes stable. PSEN# internally pulled high during reset. During reset, PSEN# output high level order perform correct reset; therefore, PSEN# pins must driven while reset active. Driving PSEN#
10µF
could cause device into indeterminate state. circuit described above maintains maximum delay time allowed between ramp, shown Figure recommends power-up sequence asserting logic level high RST, PSEN#, well asserting logic prior ramp, machine cycles after oscillator becomes stable, shown Figure recommended power-down sequence shown Figure recommended power-up power-down sequences will provide maximum protection against effects external factors, such noisy power supply.
SST89F54/58 8.2K
12MHz
XTAL2 XTAL1
PSEN#
F05.1
FIGURE RECOMMENDED POWER-ON RESET CIRCUIT
PSEN#
osc. start time min. clock cycles
F02.2
FIGURE POWER-UP SEQUENCE
1999 Silicon Storage Technology, Inc.
216-01 8/99
Design Considerations FlashFlex51 Family Microcontroller
Application Note
osc. start time min. clock cycles
F03.2
PSEN#
FIGURE RECOMMENDED POWER-UP SEQUENCE
F04.1
PSEN#
FIGURE RECOMMENDED POWER-DOWN SEQUENCE
avoid many data corruption issues that could encountered when using single power-supply microcontrollers with embedded EEPROM.
SUMMARY recommends implementing generally accepted design practices recommended power-up/ power-down sequences when using SST89F54/58 devices design. These recommendations help
1999 Silicon Storage Technology, Inc.
216-01 8/99
Design Considerations FlashFlex51 Family Microcontroller
Application Note
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Revised 8-9-99
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com Literature FaxBack 888-221-1178, International 732-544-2873
1999 Silicon Storage Technology, Inc.
216-01 8/99

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