MBYTES/SEC ALDC DATA COMPRESSION COPROCESSOR AHA3520 single-chip
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AHA3520
MBYTES/SEC ALDC DATA COMPRESSION COPROCESSOR
AHA3520 single-chip CMOS lossless compression decompression integrated circuit. device implements ALDC compression algorithm defined various industry standards. This algorithm also known Adaptive Lossless Data Compression. device compresses, decompresses passes data through. Flexible interface connects directly with various microprocessors devices used tape drive systems. Content Addressable Memory within ALDC engine eliminates external SRAMs typically required dictionary storage compression system. Other system features include compatibility ALDC1-20S-HA device.
FEATURES
PERFORMANCE:
MBytes/sec data compression, decompression pass-through rate average compression ratio Multiple byte transfers without microprocessor intervention Error checking decompression mode reportable interrupt
FLEXIBILITY:
In-line look-aside system architectures supported Polled interrupt driven independent ports programmable 16-bit transfers handshaking modes
SYSTEM INTERFACE:
Single-chip data compression solution Programmable interrupts Interfaces directly with industry standard SCSI chips
ADDR[0] ADDR[1] ADDR[2] TESTN1 BCIN TESTN0 ADDR[3] ADDR[4] TRISTATEN RESETN BCOUT WAITN BPCS IREQ
APARITY[1] APARITY[0] ADATA[8] ADATA[9] ADATA[10] ADATA[11] ADATA[12] ADATA[13] ADATA[14] ADATA[15] ADATA[0] ADATA[1] APCS ADATA[2] ADATA[3] ADATA[4] ADATA[5] TESTN2 ADATA[6] ADATA[7] ACIN
MDATA[7] TESTN3 TESTN4 MDATA[6] MDATA[5] MDATA[4] MDATA[3] ACOUT MCIN[0] MCIN[1] MDATA[2] MDATA[1] MDATA[0] MMODE TESTN5 TESTN6
OTHERS:
AHA3520A-040 PQC-G
YYWWD COUNTRY ORIGIN LLLLL
Industry standard ALDC adaptive lossless compression algorithm Complies QIC-154, ECMA 222, ANSI X3.280-1996 15200 standard specifications Compatible ALDC1-20S-HA Specification package PQFP RoHS compliant
BDATA[7] BDATA[6] BDATA[5] BDATA[4] BDATA[3] BDATA[2] BDATA[1] BDATA[0] BDATA[15] BDATA[14] BDATA[13] BDATA[12] BDATA[11] BDATA[10] BDATA[9] BDATA[8] BPARITY[0] BPARITY[1] IREQN
APPLICATIONS
Tape drives Printers copiers
NOTE: YYWWD DATE CODE; LLLLL NUMBER
comtech corporation
*Request AHA3520 Product Specification complete details.
comtech corporation Figure AHA3520 Block Diagram AHA3520 Compression Chip
ADATA[15:0] APARITY[1:0] ACOUT APCS ACIN PORT INTERFACE PORT STATE MACHINE PORT TRANSFER COUNTER PORT INTERFACE PORT STATE MACHINE PORT TRANSFER COUNTER BDATA[15:0] BPARITY[1:0] BCOUT BPCS BCIN
ALDC ENGINE
PASS THROUGH CONTROLLER CLOCK CLOCK GENERATION
PROCESSOR INTERFACE
PROCESSOR INTERFACE STATE MACHINE
INTERRUPT LOGIC
MCIN[1:0]
MMODE
ADDR[4:0]
MDATA[7:0]
FUNCTIONAL DESCRIPTION
Major blocks this device Microprocessor Interface, Port Interface, Port Interface, Compression/Decompression Engine. Microprocessor Interface provides status control information register access. Port Port Interfaces ports configurable width, polarity, handshaking modes, other options. operating mode establishes direction both Port Port Interfaces. Compression Compression Pass Through sets Port Interface input Port Interface output. Conversely Decompression Decompression Pass Through sets Port Interface output Port Interface input. Decompression Output Disabled mode allows device decompress block data predetermined point while dumping uncompressed data, then automatically begin outputting remaining uncompressed data that block record. four byte Transfer Size counter allows user partition data into blocks four gigabytes less process. Compression Pass
Through mode Decompression Pass Through modes allow data transfers through device without changing data. Both Port Interface Port Interface have 16-byte FIFO with Almost Empty Almost Full signal pins programmable thresholds. Both interfaces, Port Port have programmable wait states addition four selectable transfer modes: asynchronous request/acknowledge pair, asynchronous burst mode, peripheral access modes that correlate with microprocessor modes.
RESETN
WAITN
IREQN
IREQ
comtech corporation
ALDC COMPRESSION ALGORITHM
ALDC (Adaptive Lossless Data Compression) algorithm variant (Lempel-Ziv class data compression algorithms, first proposed Abraham Lempel Jacob 1977. algorithms achieve compression building maintaining data structure, called HISTORYBUFFER. encode process decode process both initialize this structure same known state, update identical fashion. encoder does this using input data receives compression, while decoder generates identical data stream output, which also uses update process. compression process consists examining incoming data stream identify sequences strings data bytes which already exist encoder history. identical such history available decoder, this matching string encoded output element COPYPOINTER, containing byte count history location. then possible decoder reproduce this string exactly, copying from given location history. COPYPOINTER encoded fewer bits information than required data string specifies, compression achieved.
incoming byte data does form part matching string, LITERAL, containing this embedded value, encoded then output explicitly represent this byte. decoder performs inverse operation first parsing compressed data stream into LITERALS COPYPOINTERS processing. ALDC lossless algorithm, insuring that decompressed data output exactly same uncompressed data input. QIC-154 Development Standard describes this industry standard algorithm detail.
PORT PORT CONFIGURATION
Port Port operate identically. They both 16-bit bidirectional data ports with parity checking generation. There three configuration registers associated with each port polarity register that determines polarity control signals that port. function control determined either xCNF0[13, bits Command register programmed peripheral access. polarity control signals controlled specific bits Polarity registers.
Table
Port Interface Signals SIGNAL NAME
ACIN ACOUT APCS
MASTER
SLAVE=0 DACKA DREQA deasserted deasserted APCS
SLAVE
SLAVE=1 DREQA DACKA APCS
APOL
DIRECTION
Table
Port Interface Signals SIGNAL NAME
BCIN BCOUT BPCS
MASTER
SLAVE=0 DACKB DREQB deasserted deasserted BPCS
SLAVE
SLAVE=1 DREQB DACKB BPCS
BPOL
DIRECTION
comtech corporation
SYSTEMS APPLICATIONS
typical application AHA3520 implementation data compression tape drive system. in-line architecture employed this system. in-line application inserts compression directly between host system data buffer. There direct connection between buffer host. compression, data flows from host, through controller into AHA3520. data then compressed ALDC engine flows into system buffer followed tape drive interface. This data flow usually controlled local microprocessor. decompression, flow reversed. in-line architecture compression chip operates data rate host interface controller. AHA3520 device supports sustained data transfer rate MBytes/sec. look-aside application, system buffer series with data flow. There direct connection between host buffer memory through port. compression, data flows from host, through interface peripheral controller into system buffer. Data then flows from system buffer into AHA3520 where compressed sent back system buffer. Finally, data transferred from system buffer interface. During decompression, this flow reversed.
ORDERING INFORMATION
PART NUMBER DESCRIPTION
MBytes/sec ALDC Data AHA3520A-040 PQC-G Compression Coprocessor
ABOUT
Comtech Corporation (AHA) develops markets superior integrated circuits, boards, intellectual property core technology communications systems architects worldwide. been setting standard Forward Error Correction Lossless Data Compression technology many years provides flexible, cost-effective solutions today's growing bandwidth reliability challenges. Comtech Corporation wholly owned subsidiary Comtech Telecommuncations Corp. (NASDAQ: CMTL). more information, visit www.aha.com.
EXAMPLE IN-LINE APPLICATION
BUFFER DRAM
INTERFACE
SCSI ATAPI CONTROLLER
AHA3520 DATA COMPRESSION CHIP
SYSTEM MEMORY CONTROLLER TAPE DRIVE INTERFACE
SYSTEM PROCESSOR
EXAMPLE LOOK-ASIDE APPLICATION
BUFFER DRAM
INTERFACE
SCSI ATAPI CONTROLLER
SYSTEM MEMORY CONTROLLER PERIPHERAL CONTROLLER
AHA3520 DATA COMPRESSION CHIP
comtech corporation
subsidiary Comtech Telecommunications Corporation
SYSTEM PROCESSOR DATA FLOW CONTROL
1126 Alturas Drive Moscow 83843-8331 tel: 208.892.5600 fax: 208.892.5601 e-mail: sales@aha.com www.aha.com
PB3520_1205
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