SiI100/101 Applications Note Schematic Design Suggestions Silicon

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SiI100/101 Applications Note Schematic Design Suggestions
Silicon Image, Inc.
October 1997 SiI/AN-0002-A
Silicon Image, Inc.
SiI/AN-0002-A
Copyright Notice This Application Note copyrighted Silicon Image, Inc. reproduce, transform other format, send/transmit part this documentation without express written permission Silicon Image, Inc. Trademark Acknowledgment PanelLinkis trademark Silicon Image, Inc. VESA® registered trademark Video Electronics Standards Association. other trademarks property their respective holders. Disclaimer This document provided technical information user. Silicon Image, Inc. reserves right modify information this document necessary, customer should make sure that they have most recent version. Silicon Image, Inc. holds responsibility errors which appear this document. Customers should take appropriate action ensure their products does infringe upon patents. Silicon Image, Inc. respects valid patent rights third parties does infringe upon assist others infringe upon such rights.
Revision SiI100/101 Application Note
Silicon Image, Inc.
SiI/AN-0002-A
TABLE CONTENTS
INTRODUCTION REFERENCE SCHEMATIC.4 POWER SUPPLY FILTERING ISOLATION Power supply pins SiI100/101.5 3.1.1 SiI100; Power supply pins.5 3.1.2 SiI101; Power supply pins:.6 Calculating filter capacitor values 3.2.1 Filter capacitors SiI100 3.2.2 Filter capacitors SiI101 Selecting ferrite beads HIGH SPEED DIFFERENTIAL INTERFACE SYSTEM INTERFACING.16 CONCLUSIONS.19
LIST FIGURES
Figure Basic reference schematic PanelLink Figure Power supply filter circuits SiI100 Figure Power supply filter circuits SiI101 Figure Extending filter response with parallel capacitors Figure Schematic differential interface.16 Figure Current limiting resistors outputs chip Figure Current limiting resistors outputs SiI101
LIST TABLES
Table Supply pins SiI100 Table Supply pins SiI101.6 Table Capacitance value ranges SiI100 Table Capacitance value ranges SiI101 Table Important characteristics ferrite beads Table Differential signal pins (SiI100).15 Table Differential signal pins (SiI101).15 Table Input pins SiI100.16 Table Output pins SiI101
Revision SiI100/101 Application Note
Silicon Image, Inc.
SiI/AN-0002-A
INTRODUCTION
SiI100 SiI101(PanelLinkTM) chip differential, high speed, serial transmitter-receiver pair designed high speed data transmission. SiI100 SiI101 easily transmit data speeds 650Mb/s channel. ideal interfacing controller with panel note book desktop computer display system. high quality, count, standardized display interface easily implemented with PanelLink. This application note presents basic schematic around SiI100/SiI101interface. Other variations this design also possible. intended reference schematic designing reliable, high quality interface using PanelLink. Good high speed layout techniques should observed during implementation. Careful consideration should given system level Electro-Magnetic Interference (EMI) signalintegrity optimization. This note organized into four sections: Reference schematic, Power supply filtering isolation, High speed differential interface System interfacing. This first part series design guidelines PanelLink. Part this note will present guidelines layout interface cable issues.
REFERENCE SCHEMATIC Figure shows basic schematic PanelLink interface. shows hookup four high speed differential pairs (TX0,1,2,C) power supply distribution scheme. this schematic, both SiI100 SiI101 share common power (VCC). simplicity, signals from controller shown; Outputs from SiI101 Panel Controller also depicted. These signals will discussed later later section.
IVCC PVCC AVCC
AVCC PVCC OVCC
SiI101
PGND AGND
AGND PGND OGND
Figure Basic reference schematic PanelLink
Revision SiI100/101 Application Note
Silicon Image, Inc.
SiI/AN-0002-A
Figure ferrite beads FB1-FB4 isolate analog supply pins (PVCC, AVCC) from main power VCC. Isolation serves functions: prevents system noise that exists line from contaminating PVCC AVCC supplies, prevents high frequency currents PVCC AVCC lines from being injected back into system line. Because their high frequency absorption properties, ferrite beads commonly used control power bus. Figures show details power distribution scheme Figure configuration Figure only high frequency current loop exists (Shared line only). This allows quicker system optimization. Other configurations such shared AVCC power line between SiI100 SiI101, well shared ground also possible.
POWER SUPPLY FILTERING ISOLATION
Power supply pins SiI100/101
SiI100/101 integrated circuits consist several functional blocks. Independent supply return lines dedicated each block. designer access these lines power supply pins package. Tables list these pins. description SiI100/101 block diagram level, refer data sheet user's guide.
3.1.1 SiI100; Power supply pins Table lists supply pins four functional blocks SiI100. IVCC SiI100 should tied same supply voltage level controller's panel interface voltage, which either 3.3V pins shared return pins both IVCC supply.
Table Supply pins SiI100 Name AVCC AGND PVCC PGND IVCC Function Number
Supply pins high speed (Analog) outputs Return pins high speed (Analog) circuits supply return Core logic supplies Core logic return lines interface supplies interface returns (Shared with core logic returns)
Revision SiI100/101 Application Note
Silicon Image, Inc.
SiI/AN-0002-A
3.1.2 SiI101; Power supply pins: Table lists different supply pins SiI101. OVCC pins tied same supply voltage level Panel Controller (either 3.3V 5V). current OVCC pins returns OGND pins. AVCC pins supply current analog block SiI101. current differential lines always flows through these pins.
Table Supply pins SiI101 Name AVCC AGND PVCC PGND OVCC OGND Function Number
Supply pins high speed (Analog) outputs Return pins high speed (Analog) circuits supply return Core logic supplies Core logic return lines Panel controller interface supplies Panel controller interface returns
Figure next page, shows power supply configuration SiI100. capacitor values generally determined testing iteration. Besides loading requirements each supply line, value will depend capacitor's resonance frequency other layout parasitics. Trace length trace inductance also influence filter capacitor selection. placement components affects design, since device parasitics proximity effects create "sneak" paths high frequency signals. Placement signal routing will discussed later application note. resistor shown dotted lines Figure used place ferrite bead PVCC line. ferrite bead suppresses noise currents 100MHz 300MHz range. contrast, resistor suppresses currents frequencies, therefore greater effect slowing down edges wave form. However, resistor also causes voltage drop power supply line. value suggested this resistor.
Revision SiI100/101 Application Note
Silicon Image, Inc.
SiI/AN-0002-A
IVCC Connected IVCC 3.3V 330pF
Bead 10µF 0.056uF*(2 560pF *(2)
0.022 AVCC 100pF *(2) AGND
Bead
PVCC
*(1)
0.022uF
100pF PGND
*(3)
Figure Power supply filter circuits SiI100
schematic figure shows suggested capacitor values. number pieces each capacitor shown asterisk mark. noted before, layout parasitics often cause circuit deviate from desired response. designer begin with design Figure then optimize performance fine tuning these values Table should used guideline selecting capacitors each supply. high frequency system, some amount trial error testing usually needed determine final, optimized value filter capacitors. Depending circuit parasitics particular application circuit, sometimes these optimized values beyond range values shown Table Table provides convenient starting point design. Table Capacitance value ranges SiI100 Name AVCC PVCC IVCC Storage None None 4.7uF-10uF; None Capacitor values Mid-band 0.01uF-0.1uF; 0.01uF-0.1uF; 0.01uF-0.1uF; None High freq. 100pF-1000pF; 100pF-1000pF; 100pF-1000pF; 100pF-1000pF; 1pc.
Revision SiI100/101 Application Note
Silicon Image, Inc.
SiI/AN-0002-A
There three pins SiI100 (Pins 39), each side package. minimize trace inductance, capacitors should placed close these pins. This sets capacitors recommended. Mid-band, High frequency) should connected other board space available, third also dedicated Figure shows filter configuration SiI101. This schematic used first pass design. After testing, designer should converge optimum component values carefully evaluating resonance effects layout parasitics mentioned previously. Table quick starting point filter capacitor values. need some trial error order optimize these capacitance values your specific design.
Connected OVCC 3.3V 1000pF*3
0.02uF*
OVCC
OGND
Bead 10µF 0.056uF*(2) 560pF *(2)
0.022 AVCC 100pF *(2) AGND
Bead
PVCC
*(1)
0.022uF
100pF PGND
Figure Power supply filter circuits SiI101
Table Capacitance value ranges SiI101 Name AVCC PVCC OVCC Capacitor values Mid-band 0.01uF-0.1uF; 0.01uF-0.1uF; 0.01uF-0.1uF; 0.01uF-0.1uF;
Storage None None 4.7uF-10uF; None
High freq. 100pF-1000pF; 100pF-1000pF; 100pF-1000pF; 100pF-1000pF; 3pc.
Revision SiI100/101 Application Note
Silicon Image, Inc.
SiI/AN-0002-A
least capacitors recommended each supply. example, both 0.022uF capacitor 100pF capacitors filter AVCC pin. 100pF capacitor intended supply fast charge analog block, while 0.022uF should sustain longer term loads. There three pins SiI101 (Pins 61). optimum arrangement place near second near third (Optional) placed, space permits, near capacitors (even surface mount devices) possess some lead inductance. This inductance usually specified manufacturer Equivalent Series Inductance (ESL). causes capacitor resonate characteristic (resonant) frequency. Larger capacitors possess greater lead inductance their size, they resonate lower frequencies. Similarly, smaller capacitors resonate relatively higher frequencies. Capacitor resonance lead host circuit problems. Minor annoyances such supply ripple circuit noise, well serious reflections often attributed filter capacitor resonance. Resonance power supply lines avoided paralleling capacitors different values. Figure
-20dB/decade
+20dB/decade
10dB Log(f)
Figure Extending filter response with parallel capacitors
Figure shows frequency response capacitors Capacitor larger than impedance drops with frequency until resonance reached frequency f01. Beyond f01, dominates impedance begins increase. increased impedance compensated adding smaller capacitor parallel with impedance continues decrease beyond frequency f01, until reaches resonance characteristic frequency f02. This technique extends filter's bandwidth should kept mind that trace easily introduce series inductance. Keeping traces short wide helps maintain series inductance path capacitors.
resonance frequency capacitor given 1/[2 (LC) Where capacitance capacitor. general rule, should times f01; This means that capacitor Figure should times value This condition ensures that impedance filter will vary more than 10dB over pass band. f02/f01 >10, filter's impedance will increase greater than 10dB band. designer should take special care region around where impedance curves intersect. vicinity capacitors their respective ESL's experience compound resonance effect. This effect observed probing supply lines. oscilloscope will detect increase noise voltage around this frequency. defeat this small resistance series with supply line. Revision SiI100/101 Application Note
Silicon Image, Inc.
SiI/AN-0002-A
designer should check values specified each capacitor. Manufacturers normally publish frequency response curves their capacitors. Tantalum, ceramic mica capacitors possess values, good choices high frequency filtering. Special inductance (Less than 1nH) capacitors available from some manufacturers. such capacitor chosen value selected significantly greater than Filter capacitors should never connected stub, matter thoroughly line been filtered. Rather, they should shunt supply line location between power supply supply pins smaller (high frequency) capacitors must placed closer pins. Stubs generate standing waves that seriously degrade signal quality cause problems. effect trace stubs will discussed detail application note layout using PanelLink.
Calculating filter capacitor values
example calculating filter capacitor values SiI100 SiI101's supplies given below. Assume typical high color, 18-bit resolution system. transmitted data three differential data pairs reach speeds 650Mb/sec (Bit period 1.5ns). differential clock transmitted 65MHz. supply ripple levels assumed this example arbitrary. designer should determine amount ripple that his/her particular design tolerate. This decision should made basis signal quality considerations. this example, peak current demand specified supply pins SiI100 SiI101 conservative values. designer these peak current values variation design presented below. 3.2.1 Filter capacitors SiI100 AVCC Pins: High frequency bypass capacitor:
Assume: Peak current demand acceptable ripple 100mV. estimate 20mA (Peak) analog supply conservative value. Rise time 500ps (ie., time). 20mA (0.5ns 100mV) 100pF Therefore, 100pF capacitor used each AVCC pins. Since AVCC supplies very fast currents, capacitor should selected. capacitor will hold supply ripple close original goal 100mV. Mid-band bypass capacitor: Referring general rule previous section, (100pF 100pF) 0.022uF
schematic Figure inductance, 0.022uF capacitor chosen. PVCC pin: Revision SiI100/101 Application Note
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SiI/AN-0002-A
PVCC supplies currents clock circuitry SiI100. clock operates times clock. Therefore, application frequency 162.5 MHz.
High frequency bypass capacitor:
Assume peak current demand 162.5 MHz, acceptable ripple 100mV clock period 1/162.5MHz 6.15ns Rise time (i.e. half-period). 10mA (1ns 100mV) 100pF
Mid-band bypass capacitor: According general rule, 0.01uF should sufficient. Since 0.022uF, capacitor already selected AVCC, same value used PVCC.
iii. IVCC pin: IVCC supplies current input interface SiI100. current demand this extremely low. maximum data rate input interface 65Mb/s. input clock frequency 65MHz. single, band bypass capacitor should provide sufficient filtering this pin.
High frequency bypass capacitor:
required.
Mid-band bypass capacitor: Assume peak current demand: MHz, acceptable ripple 10mV clock period 1/65MHz 15ns Assume 2.5ns (1/3 half period) (2.5ns 10mV) 240pF 330pF capacitor selected limit ripple 10mV
pins: pins supply power logic block SiI100. core logic draws largest portion current SiI100. core logic operates 3.3V, process bits data. Therefore, pins need heavier filtering compared other supply pins this chip. this reason, three pins dedicated lines both SiI100 SiI101.
Revision SiI100/101 Application Note
Silicon Image, Inc.
SiI/AN-0002-A
High frequency bypass capacitor:
Assume peak current demand: 10mA MHz, acceptable ripple 50mV clock period 65MHz 15ns Assume fast rise time currents 2.5ns (ie. half period) 10mA (2.5ns 50mV) 560pF
band bypass capacitor: 100X 0.056uF should sufficient.
Storage capacitor:
addition band high frequency bypass capacitors, storage capacitor should placed line. This capacitor will serve reservoir bulk charge that will slowly replenish bypass capacitors AVCC, PVCC IVCC lines. Although SiI100 typically draws around 50-60mA, good practice assume conservative value 100mA. Also assume 10mV ripple. Assume charge bulk capacitor replenished every 0.5us (Typical 200KHz dc/dc converter) 100mA (0.5us 10mV) 4.7uF 10uF capacitor selected. storage capacitor will isolate SiI100 from frequency noise originating from system, such dc/dc converter ripple other disturbances. 10uF selected schematic Figure
3.2.2 Filter capacitors SiI101 With exception IVCC (SiI100) OVCC (SiI101) pins, current draw corresponding pins both devices similar. example, current AVCC pins both SiI100 SiI101 similar. Therefore, similar filter configurations used. OVCC SiI101 supplies current output drivers (D0-D35, ODCLK, HSYNC, VSYNC DE). Figure shows filter schematics SiI101. AVCC Pins:
current analog block SiI101 similar that SiI100. Therefore, borrow design AVCC filter from SiI100 circuit.
High frequency bypass capacitor: 100pF capacitor used each AVCC pins.
Revision SiI100/101 Application Note
Silicon Image, Inc.
SiI/AN-0002-A
Mid-band bypass capacitor: ESL, 0.022uF capacitor selected.
PVCC pin: PVCC SiI101 supplies current clock circuitry. very similar characteristics SiI100. also operates times clock frequency. filter configuration, identical that SiI100's supply selected. High frequency bypass capacitor: 100pF Mid-band bypass capacitor: Since 0.022uF, capacitor selected PVCC line SiI100, same value used here.
iii. OVCC pins:
OVCC pins supply current output interface block SiI101. When clock (ODCLK) operating 65MHz (single pixel clock mode), maximum output data rate 65Mb/s. pixel clock mode clock data lines toggle half speed. large portion current OVCC pins drives output pins ODCLK, D0-35, HSYNC, VSYNC Filter capacitor selection therefore depends loading output pins. Current limiting resistors series with outputs highly recommended. Output current limiting will reduce ground bounce, which particularly nasty problem under Simultaneously Switching Outputs (SSO) conditions. will also significantly reduce arising from data clock lines. Series current limiting will discussed detail later section this note. outputs SiI101 swing either 3.3V commonly known that large voltage swings data generate emissions harmonics clock (i.e. 3rd, etc. harmonics). Bypass capacitors necessary provide short path harmonic currents. Assume that series resistance placed each output. Also assume 10pF trace capacitance circuit board. data sheet specifies that 3.3V supply, SiI101 drive 28mA output Peak current (Per output) (3.3V/270) 13mA mentioned previously, assume system; Total output current data lines, clock line, HSYNC, VSYNC 13mA 286mA
High frequency bypass capacitor:
Assuming rise time 2.5ns (1/3 half-clock period) Rise time harmonic 500ps maximum ripple 20mV, then Revision SiI100/101 Application Note
Silicon Image, Inc.
SiI/AN-0002-A
57.2mA 500ps/20mV 1500pF There three OVCC pins. Therefore 500pF capacitor chosen each
Mid-band bypass capacitor: Rise time 2.5ns Tolerable ripple 20mV 286mA 2.5ns/20mV 0.036uF There three OVCC pins. Therefore, three 0.022uF capacitors were chosen
pins: Power requirements core logic SiI101 similar those SiI100. Therefore, same filter design used. High frequency bypass capacitor: 560pF
Mid-band bypass capacitor: 0.056uF
Storage capacitor: 10uF
Selecting ferrite beads
Ferrite beads exhibit loss characteristics that depend frequency. losses ferrite bead megahertz usually negligible. loss increases significantly beyond depending material, peaks around MHz. Thus, ferrite beads popular choice isolating supply subcircuits that share common power bus. selection ferrite beads application fairly straight forward. filter schematics shown Figure Figure reasonable impedance value lies range. Table lists important characteristics that should considered when selecting ferrite bead.
Revision SiI100/101 Application Note
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SiI/AN-0002-A
Table Important characteristics ferrite beads Characteristic Impedance Frequency Response Current rating Size Units inch Comment High high frequencies, negligible Flat impedance response desirable Will saturate become ineffective under rated thru-hole
Ferrite beads with impedance higher generally exhibit high resistance. Such beads should used, since their resistance causes power loss voltage sag.
Although schematics Figures indicate ferrite beads AVCC PVCC lines, system level testing will establish they absolutely necessary. Ferrite beads effective suppressing high frequency noise currents. obvious reasons, noise suppression helps reduce EMI. However, obtain full benefits noise suppression, ferrite bead must properly designed system. This requires correct placement schematic; also involves serious consideration physical location bead printed circuit board. bead should placed close noise source used noise suppression. bead should placed close circuit being used protect sensitive circuit from noisy line. Besides schematic considerations location bead PCB, other factors consider are: Electrical ratings ferrite bead (Impedance, frequency response, current rating) Inductance/capacitance connecting traces/pads Proximity other "Susceptible" circuits, Stray capacitance/inductance chassis
Many factors influence performance system. Before design tested, designer accurately predict benefits placing ferrite bead design. first design iteration should include provisions bypassing ferrite beads that indicated schematic. Figures this achieved jumpers achieve inductance jumper connection, short wide traces preferred.
HIGH SPEED DIFFERENTIAL INTERFACE
transmission link between SiI100 SiI101consists high speed differential interface. Four differential pairs transmit data clock from transmitter receiver (See Tables Table Differential signal pins (SiI100) Table Differential signal pins (SiI101)
Revision SiI100/101 Application Note
Silicon Image, Inc.
SiI/AN-0002-A
Signal Name TXCTXC+ TX0TX0+ TX1TX1+ TX2TX2+
Pair
Pins
Signal Name RXCRXC+ RX0RX0+ RX1RX1+ RX2RX2+
Pair
Pins
connection differential lines between SiI100 SiI101 straightforward. pins SiI100 should connected directly through cable corresponding pins SiI101. This path, including cable, should treated transmission line, since transmission rate achieves speeds 650Mb/s. recommended differential impedance transmission line single-ended impedance).
SiI101 features on-chip termination four differential input pairs. designer adjust single-ended termination anywhere between match transmission line. termination value selected with external resistor termination range selected logic high logic (Z0CONT). Signal swing selected with resistor connected between SiI100 AVCC line. Figure shows typical values these resistors.
AVCC
EXT_SWING TXCTXC+ TX0TX0+
AVCC Cable Transmission line
RXCRXC+ RX0RX0+ RX1RX1+ RX2RX2+ EXT_RES
SiI100
TX1TX1+ TX2TX2+
SiI101
differential transmission line Figure Schematic differential interface
SYSTEM INTERFACING
Revision SiI100/101 Application Note
Silicon Image, Inc.
SiI/AN-0002-A
inputs SiI100 parallel, TTL/CMOS signals that originate from controller. outputs SiI101 parallel, TTL/CMOS signals that interface DSTN panel controller. designer must carefully consider design inputs outputs from system level point view. achieve best display quality possible, noise should minimized. optimized length cable that properly routed, well good power supply distribution scheme within system will unleash maximum performance from PanelLink interface. Such measures will also significantly reduce EMI. Input interface SiI100 Table lists input interface pins SiI100. Refer data sheet assignments.
Table Input pins SiI100 Signal Name D0-D23 IDCLK HSYNC VSYNC CLT0-3 Function Input data Input clock Data enable HSYNC input VSYNC input General inputs
IDCLK D0-D23 fastest signals inputs SiI100. 65MHz system, controller drive data lines speeds 65Mb/s, with voltage excursions 3.3-5V. resulting switching currents inject high levels noise into power ground planes. This important limit output drive currents controller. Figure Series damping resistors ferrite beads used current limiting. Trace inductance capacitance data lines cause ringing which degrade performance. Resistors preferred over ferrite beads because their termination capability. size damping resistor depends output current strength VGA. Normally, value resistor lies between 220. Most controllers designed drive capacitive loads, such loading presented long cable traditional parallel interface. most PanelLink interface systems, controller normally drives short path SiI100, high current drive necessary. 22-220
IDCK
SiI100
Figure Current limiting resistors outputs chip
Output interface SiI101
Table lists output interface pins SiI101. Refer data sheet assignments. SiI101's outputs interface either 3.3V supply. They also capable delivering 28mA drive Revision SiI100/101 Application Note
Silicon Image, Inc.
SiI/AN-0002-A
current. outputs SiI101 lightly loaded Panel Controller, series resistors help limit current from SiI101. Figure
Table Output pins SiI101 Signal Name D0-D35 ODCLK HSYNC VSYNC CLT0-3 Function Output data Output clock Data enable HSYNC output VSYNC output General outputs
Damping resistor values: Assume 3.3V XGA, single pixel clock, panel with 10pF trace capacitance line. From data sheet, 3.3V, SiI101 drives 28mA output data line. With 65MHz clock, 2.5ns rise time should acceptable. 10pF 3.3V 2.5ns 13.2mA Therefore, Rlimit 3.3V/13.2mA value selected output data clock lines. Placing SiI101 close Panel Controller will help reduce emissions from data lines. Layout guidelines optimum component placement will presented subsequent applications note.
SiI101
ODCK
Panel Controller
Figure Current limiting resistors outputs SiI101
Revision SiI100/101 Application Note
Silicon Image, Inc.
SiI/AN-0002-A
CONCLUSIONS
high speed transmission capabilities PanelLink possible implement high resolution, standardized, pin-count interface. With SiI100/101 transmitter/receiver chip set, system designer minimize peripheral circuitry necessary implement such interface. high speed interface designer usually objectives: maximization signal integrity minimization EMI. Unique features PanelLink such transition minimization, on-chip termination adjustable differential swing, help designer achieve both objectives with minimum effort. Transmission quality achievable with SiI100/101 chip-set extremely high. performance link generally does depend power supply configuration. With reasonably "clean" power source, many different power distribution schemes used implement highly reliable link notebook desk computer display system. However, well filtered, dedicated AVCC supply highly recommended. basic power distribution scheme been presented; variations this design derived with only minor modifications. designer flexibility implement supply scheme that best optimizes system level performance. Effective bypassing, supply isolation proper signal termination (Impedance matching) help achieve significant reductions EMI. Peripheral circuits (eg. outputs, Panel Controller circuitry their power supplies) should optimized minimum emissions. Most emissions problems occur when TTL/CMOS level data/clock lines inject high currents into ground supply planes. Ferrite beads useful isolating power lines from common power bus. important features ferrite beads a)impedance high frequencies, current carrying capacity. current rating ferrite bead must rated higher than maximum expected current. ferrite bead saturates when operated close maximum current capacity. When saturated, loses ability absorb high frequency currents. Bypass capacitors help localize high frequency current paths. When properly sized, bypass capacitors very effective control. strategically placed inductance bypass capacitor will shrink current loops high frequencies providing local source fast charge. Matching termination receiver chip (SiI101) cable's characteristic impedance allows complete absorption received signal. differential impedance single-ended) recommended transmission line (Trace, cable termination). However, designer free select impedance value between adjusting termination impedance SiI101. Note that single-ended standard impedance that allows compatibility between most panel/system boards. Emissions lower frequencies (e.g. Clock fundamental, etc.) often result activity outputs from controller. Most controllers designed drive high load currents TTL/CMOS levels. those outputs lightly loaded path between controller SiI100 short), reflection well ground power supply bounce occur. This disturbance contributes common mode radiation. Series resistors should used limit output currents VGA. outputs SiI101are capable driving high currents TTL/CMOS voltage levels. with controllers, significant reflection occur these lines lightly loaded. This also cause ground supply bounce. Series resistors output lines help reduce this effect. They will also help minimize common mode emissions.
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