AN99-13 APPLICATION NOTE SC1406G INTRODUCTION DESCRIPTION SC1406G

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AN99-13 APPLICATION NOTE SC1406G INTRODUCTION DESCRIPTION SC1406G

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GEYSERVILLE SOLUTION MOBILE CPUs
AN99-13
APPLICATION NOTE SC1406G INTRODUCTION DESCRIPTION SC1406G High Speed, High performance Hysteretic Mode controller. part chip solution, with SC1405 Smart Driver, providing power advanced microprocessors. uses Dynamic Point switching technique along with ultra-fast comparator provide control signal external high speed Mosfet driver. 5-bit sets output voltage, thus providing voltage resolution 25mV 50mV range output voltage from 0.925V 2.00V. SC1406G on-chip linear regulators which drive external transistors with output voltage settings 1.5V 2.5Vdc. linear regulator drivers have separate soft start. PWRGD level signal asserted when voltages within specifications. part features Battery Detect Undervoltage Lock-Out main Hysteretic controller assure V-DC within acceptable limits. Over-Current comparator disables main controller during overcurrent condition using externally programmable threshold. APPLICATIONS High Speed Hysteretic controller provides high efficiency over wide operating load range Inherently stable Complete power solution with drivers Programmable output voltage Pentium Processors FEATURES Laptop Notebook computers High performance Microprocessor based systems High efficiency distributed power supplies
BLOCK DIAGRAM
2000 SEMTECH CORP. MITCHELL ROAD NEWBURY PARK 91320
GEYSERVILLE SOLUTION MOBILE CPUs
AN99-13
DESCRIPTION
Name Function CLSET VCOUT VCIN VCBYP VID4 VID3 VID2 VID1 VID0 BASE25 FB25 BASE15 FB15 Core comparator hysteresis settling. Current limit setting pin. Voltage clamp output. Voltage clamp input. Voltage clamp bypass pin. Needs have 1500pF from this ground ensure proper operation. most significant main controller voltage programming input. input input input least significant main controller voltage programming input. 2.5V Linear regulator drive. 2.5V Linear regulator output feedback. 1.5V Linear regulator drive. 1.5V Linear regulator output feedback. Enable. SC1406A enabled when this signal High. This capable accepting 5.0V signal level. When used with SC1405 driver, this connected PWRDY SC1405 include UVLO feature (Intel Smart Driver's VCC). Power Good. When main converter output approaches stays within ±12% setting, both soft-start circuits periods main core controller linear regulator controllers have been terminated, this signal driven high level. During UVLO, this signal undefined. battery input. This used minimum voltage converter through external resistor divider. When input this less than 1.225V, typical, Tamky held Under-Voltage-Lock-Out mode regardless status Linear regulators soft start. During power-up with high UVLO, external soft start capacitor (1200pF, typ) charged internal current source ramp time linear regulator outputs, 1.5V 2.5V. This ramp time typically 2ms, max. This discharged through internal switch when BIASEN low, enter UVLO region. Enabling internal bias soft start requires voltage drop below threshold 150mV typical (200mV max). Linear regulator soft start current tolerance tracks core soft start current within 10%.
PWRGD
LBIN
SSLR
SSCORE Main controller CORE output soft start. During power-up with high UVLO, external soft start capacitor (1800pF, typ) charged internal current source ramp time main converter output. This ramp time typically 3ms, max. This discharged internal switch when BIASEN low, UVLO. Enabling internal bias soft start requires voltage drop below threshold 150mV typical (200mV max). Core soft start current tolerance tracks soft start current within 10%.
2000 SEMTECH CORP. MITCHELL ROAD NEWBURY PARK 91320
GEYSERVILLE SOLUTION MOBILE CPUs
AN99-13
DESCRIPTION (Cont.)
Name Function CORE Main CORE converter output feedback. Main controller digital analog output. Ground Comparator output. Main regulator controller output used drive input SC1405 driver Input power. Supply voltage input. This input capable accepting 3.3V 5.0V supply voltage. Core comparator input pin.
CMPREF Core comparator reference input pin. CLREF Current limit input pin. Current limit reference input pin.
2000 SEMTECH CORP. MITCHELL ROAD NEWBURY PARK 91320
GEYSERVILLE SOLUTION MOBILE CPUs
AN99-13
VDAC VOLTAGE
+VCC_CPU_CORE 2.00 1.95 1.90 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 CPU*
2000 SEMTECH CORP. MITCHELL ROAD NEWBURY PARK 91320
+3.3Vcc
36,75
2000 SEMTECH CORP.
+5Vcc
LL42
MMelf
SC1406G 2.55k CORE CLREF 2.55k 1.2k
160k
CLSET SC1405 OVPS Si4822 100p 240k
CLOH
+V_IN
25-30 C19,20 0.1u C17,18 56/25V "OS-CON,SP" D10x10.5
100kCLSET
ovps
+4.75
TYPICAL APPLICATION SCHEMATIC
VCOUT CMPREF
VCIN VCBYP
OFFSET
0.003
C23,24 ovps
+VccCPU_CORE
41-63
VID4 DSPSDR
VID3 SMOD PGND
1.2k
100k
+SENSE
Si4822 C21,22 1200/2.5V "OS-CON,SP" "D10x10.5" 5.1K
0.001 VID2 VID1 1.8n VID0 1.2n BASE25 3.9k 0.001 1.2k BASE15 PWRGD SSLR SSCORE CORE PRDY DELAYC
14.1A
MMBT4403LT1
1-23,31-34,37,40,65-70
SOT-23
FB25 LBIN
-SENSE
MJD127
DPAK
FB15
150/4V(POSCAP)
150/4V(POSCAP)
GEYSERVILLE SOLUTION MOBILE CPUs
1uF,10V+/_20%MLCC
V_GATE
VR_ON
71-73
2.5V@0.15Amax
1.5V@2.2/4.6Ap-k
AN99-13
MITCHELL ROAD NEWBURY PARK 91320
GEYSERVILLE SOLUTION MOBILE CPUs
AN99-13
TYPICAL APPLICATIONS (Cont.)
Component View
Bottom Component View
Connector View
2000 SEMTECH CORP. MITCHELL ROAD NEWBURY PARK 91320
GEYSERVILLE SOLUTION MOBILE CPUs
AN99-13
TYPICAL APPLICATIONS (Cont.)
Copper
Middle Copper
Bottom Copper
2000 SEMTECH CORP. MITCHELL ROAD NEWBURY PARK 91320
GEYSERVILLE SOLUTION MOBILE CPUs
AN99-13
FUNCTIONAL DESCRIPTION
SUPPLY chip optimized operate from 3.3V rail also designed work maximum supply voltage. 3.3V voltage range, quiescent current will increase somewhat slight degradation line regulation expected. UNDER VOLTAGE LOCK-OUT CIRCUIT under voltage lockout circuit consists comparators, battery (low supply voltage) comparators. output comparator gated with Enable signal turns internal bias, enables disables output, initiates resets soft start timers. POWER GOOD GENERATOR chip enabled UVLO condition, core voltage gets within +10% programmed value, then high level Power Good signal generated PWRGD trigger power sequence. chip either disabled enabled UVLO condition, then PWRGD stays low. This condition satisfied presence internal 200k pull-down resistor connected from PWRGD ground. During soft start, PWRGD stays independently from status Vcore voltage. During this time, PWRGD status "don't care". BAND REFERENCE better than precision band reference acts internal reference voltage standard chip, which critical biasing voltages currents derived from. references VREF equations follow will assume VREF 1.7V. CORE CONVERTER CONTROLLER Precision Reference 5-bit digital analog converter (DAC) serves programmable reference source core comparator. Programming accomplished CMOS logic level code applied inputs. code output shown Output Voltage Table. accuracy maintained same level band reference. There 10µA pull-up current each input while high.
Core Comparator This ultra-fast hysteretic comparator with typical propagation delay approximately 20ns 20mV overdrive. hysteresis determined resistance ratio external resistors, RHYS ROH, high accuracy internal reference voltage, VREF.
VHYS VREF
This chip used standard hysteretic mode controller configuration DSPS (Dynamic Point Switching) hysteretic controller scheme. standard hysteretic controller configuration, core comparator compares output voltage core converter, VCORE code programmed voltage, VDAC. VCORE(t) VDAC VHYST(t) core voltage ramps down between thresholds determined hysteresis comparator: VHCORE VDAC VHYST VLCORE VDAC VHYST DSPS hysteretic controller configuration, core comparator compares core voltage, VCORE, voltage, VDAC directly rather voltage less than voltage DSPS voltage, VDSPS. VCORE(t) VDAC VDSPS(t) VHYST(t) DSPS voltage function load current. generated from current sense voltage, developed across sense resistor, RCS, which inserted series with main buck inductor also used current sensing cycle-by-cycle current limiting. sense voltage scaled DSPS gain, ADSPS, which resistance ratio external resistors, RDAC RCORE.
VDSPS DSPS CORE CORE
2000 SEMTECH CORP. MITCHELL ROAD NEWBURY PARK 91320
GEYSERVILLE SOLUTION MOBILE CPUs
January 2000 DSPS hysteretic controller configuration (Cont'd) comparator reference voltage positioning such that increasing current sense voltage, VCS, i,e, elevating load current, causes reference voltage decrease, consequence, core output voltage also droops. load current, there droop while maximum load, droop likewise maximum. order core voltage positioned around nominal VDAC voltage symmetrically just downward from nominal value, DSPS offset voltage, VDSPSOFFS, introduced. offset voltage moves comparator reference voltage upward load. optimal offsetting, reference voltage above nominal level load currents less than half maximum load, below nominal value currents higher than that. maximum amount core voltage positioning determined from constrain which says output voltage load condition must still remain below upper threshold core voltage regulation window, maximum load, must above lower threshold. offset voltage generated across resistor, ROH, which also used create hysteresis voltage forcing unipolar DSPS offsetting current through offsetting current conveniently provided high value resistor, ROFFSET, connected from comparator ground.
DSPSOFFS IDSPS VCORE OFFSET OFFSET
AN99-13
Core Voltage Offsetting order core voltage positioned around nominal VDAC voltage symmetrically just always direction downward, core offset voltage, VOFFS introduced. offset voltage moves comparator reference voltage upwards. Using optimal offsetting, core comparator reference voltage will above programmed nominal voltage load currents less than half maximum load, below that higher current. maximum amount core voltage positioning determined from constraint that output voltage regulation window, maximum load, above lower threshold. positioning offset voltage generated across same resistor, also used create hysteresis voltage, forcing unipolar offsetting current through offsetting current conveniently provided high value resistor, ROFFS connected from comparator ground. Current Limit Comparator current limit comparator monitors core converter output current turns high side switch when current exceeds upper current limit threshold, VHCL re-enable only load current drops below lower current limit threshold, VLCL. current sensed monitoring voltage drop across current sense resistor, RCS, connected series with core converter main inductor (the same resistor used DSPS input signal generation). thresholds have following relationships:
VHCL VLCL VHYSCL CLOH CLSET CLOH CLSET
VCORE VCORE VDAC ,ROH ROFFSET
DSPS hysterestic controller configuration, comparator thresholds calculated from voltage, VDAC, DSPS offsetting voltage, VDSPSOFFS, DSPS voltage VDSPS, bipolar hysteresis voltage, VHYST summing them comparator inputs appropriate load current levels:
Vcore
CLOH CLSET
Vdac (Roffset Rcore Icore Roffset (Rcore Rdac Rcore Roffset Rdac
Vcore Vhys
Rcore (Roffset Rcore Roffset Rdac
Rcore (Roffset Rcore Roffset Rdac
2000 SEMTECH CORP. MITCHELL ROAD NEWBURY PARK 91320
GEYSERVILLE SOLUTION MOBILE CPUs
January 2000 Core Converter Soft Start Timer main purpose this block control rampup time core voltage order reduce initial inrush current core input voltage (battery) rail. soft start circuit consists internal current source, external soft start timing capacitor, internal switch across capacitor, comparator monitoring capacitor voltage. LINEAR REGULATOR CONTROLLER 1.5V Linear Regulator This block linear regulator controller, which drives external bipolar transistor pass element. linear regulator capable delivering 500mA steady state current should support transient current assuming output filtering capacitor properly selected provide enough charge duration load transient. 2.5V Linear Regulator This block drop-out (LDO) linear regulator controller, which drives external bipolar transistor pass element. linear regulator capable delivering 100mA steady current should support transient current 100mA, assuming output filtering capacitor properly selected provide enough charge duration load transient.
AN99-13
Linear Regulator Soft Start Timer soft start timer circuit linear regulators similar that core converter, used control ramp time linear regulator output voltages. maximum flexibility controlling start sequence, soft start function linear regulators separated from that core converter. VOLTAGE CLAMP level translator converts input voltage swing rail, into voltage swing rail depending where open drain output translator tied through external pull-up resistor. level translator track input phase, must able switch (typical) following input threshold intercept.
APPLICATION INFORMATION
Power on/off Sequence
2000 SEMTECH CORP. MITCHELL ROAD NEWBURY PARK 91320
GEYSERVILLE SOLUTION MOBILE CPUs
AN99-13
OUTLINE DRAWING TSSOP-28
2000 SEMTECH CORP. MITCHELL ROAD NEWBURY PARK 91320

AN99-13 APPLICATION NOTE SC1406G INTRODUCTION DESCRIPTION SC1406G

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