Order Number: MC88915T/D 08/2001 Skew CMOS Clock Drivers, 3-State

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Order Number: MC88915T/D 08/2001 Skew CMOS Clock Drivers, 3-State

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Order Number: MC88915T/D 08/2001
Skew CMOS Clock Drivers, 3-State
100, 160MHz Versions
MC88915T Clock Driver utilizes phase-locked loop technology lock skew outputs' frequency phase onto input reference clock. designed provide clock distribution high performance PC's workstations. 3.3V version, MC88LV915T data sheet. allows high current, skew outputs lock onto single SKEW CMOS clock input distribute with essentially zero delay multiple components board. also allows MC88915T multiply CLOCK DRIVER frequency input clock distribute locally higher (2X) system frequency. Multiple 88915's lock onto single reference clock, which ideal applications when central system clock must distributed synchronously multiple boards (see Figure Five outputs (Q0-Q4) provided with less than skew between their rising edges. output inverted (180° phase shift) from outputs. 2X_Q output runs twice output frequency, while runs frequency. designed optimally between 2X_Q Fmax specification. wiring diagrams Figure detail different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios outputs SYNC input 2:1, 1:1, 1:2. FREQ_SEL provides programmable divide-by feedback path PLL. selects between divide-by-1 divide-by-2 before signal reaches internal clock distribution section chip (see block diagram page most applications FREQ_SEL should held high (÷1). frequency reference clock input used, holding FREQ_SEL (÷2) will allow optimal range (>20MHz >40MHz TFN133 version). normal phase-locked operation PLL_EN held high. Pulling PLL_EN disables puts 88915 static "test mode". this mode there frequency limitation input clock, which necessary frequency board test environment. second SYNC input used test clock input further simplify board-level testing (see detailed description page 11). Pulling OE/RST puts clock outputs 2X_Q, Q0-Q4, into high impedance state (3-state). After OE/RST goes back high Q0-Q4, will reset state, with 2X_Q being inverse selected SYNC input. Assuming PLL_EN low, outputs will remain reset until 88915 sees SYNC input pulse. lock indicator output (LOCK) will high when loop steady-state phase frequency lock. LOCK output will phase-lock lost when PLL_EN low. LOCK output will high later than 10ms after 88915 sees SYNC signal full VCC.
MC88915TFN55 MC88915TFN70 MC88915TFN100 MC88915TFN133 MC88915TFN160
Features
Five Outputs (Q0-Q4) with Output-Output Skew each being phase frequency locked SYNC input phase variation from part-to-part between SYNC FEEDBACK inputs less than (derived from specification, which defines part-to-part skew) Input/Output phase-locked frequency ratios 1:2, 1:1, available Input frequency range from 5MHz 2X_Q FMAX spec. (10MHz 2X_Q FMAX TFN133 version) Additional outputs available system frequency. Also (180° phase shift) output available outputs have drive (equal high low) CMOS levels, drive either CMOS inputs. inputs TTL-level compatible. ±88mA IOL/IOH specifications guarantee transmission line switching incident edge Test Mode (PLL_EN) provided frequency testing. selectable CLOCK inputs test redundancy purposes. outputs into high impedance (3-state) board test purposes Lock Indicator (LOCK) accuracy indicates phase-locked state
Yield Surface Modeling trademarks Motorola, Inc.
Motorola, Inc. 2001
Pinout: 28-Lead PLCC (Top View)
OE/RST FEEDBACK REF_SEL SYNC[0] VCC(AN) GND(AN) SYNC[1] PLL_EN 2X_Q LOCK
FREQ_SEL
SUFFIX PLASTIC PLCC CASE 776-02
SUMMARY
Name Function
SYNC[0] SYNC[1] REF_SEL FREQ_SEL FEEDBACK Q(0-4) 2x_Q LOCK OE/RST PLL_EN VCC,GND
Input Input Input Input Input Input Output Output Output Output Output Input Input
Reference clock input Reference clock input Chooses reference between sync[0] Sync[1] Doubles Internal Frequency (low) Feedback input phase detector Input external network Clock output (locked sync) Inverse clock output clock output frequency (synchronous) Clock output(Q) frequency (synchronous) Indicates phase lock been achieved (high when locked) Output Enable/Asynchronous reset (active low) Disables phase-lock freq. testing Power ground pins (note pins analog" supply pins internal only)
LOCK FEEDBACK
SYNC
SYNC
PHASE/FREQ. DETECTOR
CHARGE PUMP/LOOP FILTER
VOLTAGE CONTROLLED OSCILLATOR
REF_SEL
EXTERNAL NETWORK (RC1 Pin)
PLL_EN
2x_Q
(÷1) DIVIDE (÷2) FREQ_SEL OE/RST
Figure MC88915T Block Diagram (All Versions) MOTOROLA
MC88915TFN55 MC88915TFN70
SYNC INPUT TIMING REQUIREMENTS
Minimum Symbol tRISE/FALL,SYNC Inputs tCYCLE, SYNC Inputs Duty Cycle SYNC Inputs Parameter Rise/Fall Time, SYNC Inputs From 2.0V Input Clock Period SYNC Inputs Input Duty Cycle SYNC Inputs TFN70 28.5 TFN55 36.0 ±25% Maximum Unit
These tCYCLE minimum values valid when output back connected FEEDBACK pin. This configuration shown Figure Information Table Note specification notes describe this specification limits depending what output back, FREQ_SEL high low.
ELECTRICAL CHARACTERISTICS
(Voltages Referenced GND) =-40° +85° 55MHz Version; +70° 70MHz Version; Symbol ICCT IOLD IOHD Maximum Quiescent Supply Current (per Package) Maximum 3-State Leakage Current Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current Test Conditions Vout Vout VOLD 1.0V VOHD 3.85V VIL;VO 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 5.25 5.25 5.25 5.25 5.25 5.25 Target Limit 4.01 4.51 0.44 0.44 ±1.0
Unit
12mA -12mA respectively LOCK output. PLL_EN input guaranteed meet this specification. Maximum test duration 2.0ms, output loaded time. Specification value preliminary, will finalized upon `MC' status.
CAPACITANCE POWER SPECIFICATIONS
Symbol Input Capacitance Power Dissipation Capacitance Power Dissipation 50MHz with Thevenin Termination Power Dissipation 50MHz with Parallel Termination Parameter Typical Values 23mW/Output 184mW/Device 57mW/Output 456mW/Device Unit Conditions 25°C
NOTE: mW/Output numbers output.
MC88915TFN55 MC88915TFN70 (continued)
FREQUENCY SPECIFICATIONS =-40° +85° ±5%)
Guaranteed Minimum Symbol fmax Parameter Maximum Operating Frequency (2X_Q Output) Maximum Operating Frequency (Q0-Q4,Q5 Output) TFN70 TFN55 27.5 Unit
Maximum Operating Frequency guaranteed with part phase-locked condition, outputs loaded with terminated VCC/2.
CHARACTERISTICS =-40° +85° 5.0V ±5%, Load Terminated VCC/2)
Symbol tRISE/FALL Outputs tRISE/FALL1 2X_Q Output tPULSE WIDTH1 (Q0-Q4, Q/2) tPULSE WIDTH1 (2X_Q Output) tPULSE WIDTH1 (2X_Q Output) SYNC Feedback Parameter Rise/Fall Time, Outputs (Between 0.2VCC 0.8VCC) Rise/Fall Time Into 20pF Load, With Termination Specified Note Output Pulse Width: VCC/2 Output Pulse Width: 2X_Q 1.5V Output Pulse Width: 2X_Q VCC/2 66MHz 50MHz 40MHz 50-65MHz 40-49MHz 66-70MHz 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE Unit Condition Into Load Terminated VCC/2 tRISE: 0.8V 2.0V tFALL: 2.0V 0.8V Into Load Terminated VCC/2 Must Termination Specified Note Into Load Terminated VCC/2 Note Figure Detailed lanation Explanation
SYNC Input Feedback Delay (Measured SYNC0 FEEDBACK Pins) Input
(With from VCC) -1.05 -0.40
(With from GND) +1.25 tSKEWr (Rising) Note tSKEWf (Falling) tSKEWall1,4 Output-to-Output Skew Between Outputs Q0-Q4, (Rising Edges Only) Output-to-Output Skew Between Outputs Q0-Q4 (Falling Edges Only) Output-to-Output Skew 2X_Q, Q/2, Q0-Q4 Rising, Falling Time Required Acquire Phase-Lock From Time SYNC Input Signal Received Output Enable Time OE/RST 2X_Q, Q0-Q4, Output Disable Time OE/RST 2X_Q, Q0-Q4, +3.25 Outputs Into Matched Load Terminated VCC/2 Outputs Into Matched Load Terminated VCC/2 Outputs Into Matched Load Terminated VCC/2 Also Time LOCK Indicator High Measured With PLL_EN Measured With PLL_EN
tLOCK5
tPZL6 tPHZ,tPLZ6
These specifications tested, they guaranteed statistcal characterization. specification Note TCYCLE this spec 1/Frequency which particular output running. specification's min/max values shift closer zero larger pullup resistor used. Under equally loaded conditions fixed temperature voltage. With fully powered-on, output properly connected FEEDBACK pin. tLOCK maximum with 0.1µF, tLOCK minimum with 0.01µF. tPZL, tPHZ, tPLZ minimum maximum specifications estimates, final guaranteed values will available when `MC' status reached.
MC88915TFN100
SYNC INPUT TIMING REQUIREMENTS
Symbol tRISE/FALL,SYNC Inputs tCYCLE, SYNC Inputs Duty Cycle SYNC Inputs Parameter Rise/Fall Time, SYNC Inputs From 2.0V Input Clock Period SYNC Inputs Input Duty Cycle SYNC Inputs Minimum 20.0 ±25% Maximum Unit
These tCYCLE minimum values valid when output back connected FEEDBACK pin. This configuration shown Figure Information Table Note specification notes describe this specification limits depending what output back, FREQ_SEL high low.
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND) =-40° +85°
Symbol ICCT IOLD IOHD Maximum Quiescent Supply Current (per Package) Maximum 3-State Leakage Current Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current Test Conditions Vout Vout VOLD 1.0V VOHD 3.85V VIL;VO 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 5.25 5.25 5.25 5.25 5.25 5.25 Target Limit 4.01 4.51 0.44 0.44 ±1.0
Unit
12mA -12mA respectively LOCK output. PLL_EN input guaranteed meet this specification. Maximum test duration 2.0ms, output loaded time. Specification value preliminary, will finalized upon `MC' status.
CAPACITANCE POWER SPECIFICATIONS
Symbol Input Capacitance Power Dissipation Capacitance Power Dissipation 50MHz with Thevenin Termination Power Dissipation 50MHz with Parallel Termination Parameter Typical Values 23mW/Output 184mW/Device 57mW/Output 456mW/Device Unit Conditions 25°C
NOTE: mW/Output numbers output.
FREQUENCY SPECIFICATIONS =-40° +85° ±5%)
Guaranteed Minimum Symbol fmax Parameter Maximum Operating Frequency (2X_Q Output) Maximum Operating Frequency (Q0-Q4,Q5 Output) TFN100 Unit
Maximum Operating Frequency guaranteed with part phase-locked condition, outputs loaded with terminated VCC/2.
MC88915TFN100 (continued)
CHARACTERISTICS =-40° +85° 5.0V ±5%, Load Terminated VCC/2)
Symbol tRISE/FALL Outputs tRISE/FALL1 2X_Q Output tPULSE WIDTH1 (Q0-Q4, Q/2) tPULSE WIDTH1 (2X_Q Output) tPULSE WIDTH1 (2X_Q Output) SYNC Feedback Parameter Rise/Fall Time, Outputs (Between 0.2VCC 0.8VCC) Rise/Fall Time Into 20pF Load, With Termination Specified Note Output Pulse Width: VCC/2 Output Pulse Width: 2X_Q 1.5V Output Pulse Width: 2X_Q VCC/2 40-49MHz 50-65MHz 66-100MHz 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE Unit Condition Into Load Terminated VCC/2 tRISE: 0.8V 2.0V tFALL: 2.0V 0.8V Into Load Terminated VCC/2 Must Termination Specified Note Into Load Terminated VCC/2 Note Figure Detailed lanation Explanation
SYNC Input Feedback Delay (Measured SYNC0 FEEDBACK Pins) Input
(With from VCC) -1.05 -0.30
(With from GND) +1.25 tSKEWr (Rising) Note tSKEWf (Falling) tSKEWall1,4
+3.25 Outputs Into Matched Load Terminated VCC/2 Outputs Into Matched Load Terminated VCC/2 Outputs Into Matched Load Terminated VCC/2 Also Time LOCK Indicator High Measured With PLL_EN Measured With PLL_EN
Output-to-Output Skew Between Outputs Q0-Q4, (Rising Edges Only) Output-to-Output Skew Between Outputs Q0-Q4 (Falling Edges Only) Output-to-Output Skew 2X_Q, Q/2, Q0-Q4 Rising, Falling Time Required Acquire Phase-Lock From Time SYNC Input Signal Received Output Enable Time OE/RST 2X_Q, Q0-Q4, Output Disable Time OE/RST 2X_Q, Q0-Q4,
tLOCK5
tPZL6 tPHZ,tPLZ6
These specifications tested, they guaranteed statistcal characterization. specification Note TCYCLE this spec 1/Frequency which particular output running. specification's min/max values shift closer zero larger pullup resistor used. Under equally loaded conditions fixed temperature voltage. With fully powered-on, output properly connected FEEDBACK pin. tLOCK maximum with 0.1µF, tLOCK minimum with 0.01µF. tPZL, tPHZ, tPLZ minimum maximum specifications estimates, final guaranteed values will available when `MC' status reached.
MC88915TFN133
SYNC INPUT TIMING REQUIREMENTS
Symbol tRISE/FALL,SYNC Inputs tCYCLE, SYNC Inputs Duty Cycle SYNC Inputs Parameter Rise/Fall Time, SYNC Inputs From 2.0V Input Clock Period SYNC Inputs Input Duty Cycle SYNC Inputs Minimum 15.0 ±25% Maximum Unit
These tCYCLE minimum values valid when output back connected FEEDBACK pin. This configuration shown Figure Information Table Note specification notes describe this specification limits depending what output back, FREQ_SEL high low.
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND) =-40° +85°
Symbol ICCT IOLD IOHD Maximum Quiescent Supply Current (per Package) Maximum 3-State Leakage Current Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current Test Conditions Vout Vout VOLD 1.0V VOHD 3.85V VIL;VO 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 5.25 5.25 5.25 5.25 5.25 5.25 Target Limit 4.01 4.51 0.44 0.44 ±1.0
Unit
12mA -12mA respectively LOCK output. PLL_EN input guaranteed meet this specification. Maximum test duration 2.0ms, output loaded time. Specification value preliminary, will finalized upon `MC' status.
CAPACITANCE POWER SPECIFICATIONS
Symbol Input Capacitance Power Dissipation Capacitance Power Dissipation 50MHz with Thevenin Termination Power Dissipation 50MHz with Parallel Termination Parameter Typical Values 23mW/Output 184mW/Device 57mW/Output 456mW/Device Unit Conditions 25°C
NOTE: mW/Output numbers output.
FREQUENCY SPECIFICATIONS =-40° +85° ±5%)
Guaranteed Minimum Symbol fmax Parameter Maximum Operating Frequency (2X_Q Output) Maximum Operating Frequency (Q0-Q4,Q5 Output) TFN133 Unit
Maximum Operating Frequency guaranteed with part phase-locked condition, outputs loaded with terminated VCC/2.
MC88915TFN133 (continued)
CHARACTERISTICS =-40° +85° 5.0V ±5%, Load Terminated VCC/2)
Symbol tRISE/FALL Outputs tRISE/FALL1 2X_Q Output tPULSE WIDTH1 (Q0-Q4, Q/2) tPULSE WIDTH1 (2X_Q Output) tPULSE WIDTH1 (2X_Q Output) SYNC Feedback Parameter Rise/Fall Time, Outputs (Between 0.2VCC 0.8VCC) Rise/Fall Time Into 20pF Load, With Termination Specified Note Output Pulse Width: VCC/2 Output Pulse Width: 2X_Q 1.5V Output Pulse Width: 2X_Q VCC/2 66-133MHz 40-65MHz 66-133MHz 40-65MHz 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE Unit Condition Into Load Terminated VCC/2 tRISE: 0.8V 2.0V tFALL: 2.0V 0.8V Into Load Terminated VCC/2 Must Termination Specified Note Into Load Terminated VCC/2 Note Figure Detailed lanation Explanation
SYNC Input Feedback Delay (Measured SYNC0 FEEDBACK Pins) Input
(With from VCC) -1.05 -0.25
(With from GND) +1.25 tSKEWr (Rising) Note tSKEWf (Falling) tSKEWall1,4
+3.25 Outputs Into Matched Load Terminated VCC/2 Outputs Into Matched Load Terminated VCC/2 Outputs Into Matched Load Terminated VCC/2 Also Time LOCK Indicator High Measured With PLL_EN Measured With PLL_EN
Output-to-Output Skew Between Outputs Q0-Q4, (Rising Edges Only) Output-to-Output Skew Between Outputs Q0-Q4 (Falling Edges Only) Output-to-Output Skew 2X_Q, Q/2, Q0-Q4 Rising, Falling Time Required Acquire Phase-Lock From Time SYNC Input Signal Received Output Enable Time OE/RST 2X_Q, Q0-Q4, Output Disable Time OE/RST 2X_Q, Q0-Q4,
tLOCK5
tPZL6 tPHZ,tPLZ6
These specifications tested, they guaranteed statistcal characterization. specification Note TCYCLE this spec 1/Frequency which particular output running. specification's min/max values shift closer zero larger pullup resistor used. Under equally loaded conditions fixed temperature voltage. With fully powered-on, output properly connected FEEDBACK pin. tLOCK maximum with 0.1µF, tLOCK minimum with 0.01µF. tPZL, tPHZ, tPLZ minimum maximum specifications estimates, final guaranteed values will available when `MC' status reached.
MC88915TFN160
SYNC INPUT TIMING REQUIREMENTS
Symbol tRISE/FALL,SYNC Inputs tCYCLE, SYNC Inputs Duty Cycle SYNC Inputs Parameter Rise/Fall Time, SYNC Inputs From 2.0V Input Clock Period SYNC Inputs Input Duty Cycle SYNC Inputs Minimum 12.5 ±25% Maximum Unit
These tCYCLE minimum values valid when output back connected FEEDBACK pin. This configuration shown Figure Information Table Note specification notes describe this specification limits depending what output back, FREQ_SEL high low.
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND) +70°
Symbol ICCT IOLD IOHD Maximum Quiescent Supply Current (per Package) Maximum 3-State Leakage Current Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current Test Conditions Vout Vout VOLD 1.0V VOHD 3.85V VIL;VO 4.75 5.25 4.75 5.25 4.75 5.25 4.75 5.25 5.25 5.25 5.25 5.25 5.25 5.25 Target Limit 4.01 4.51 0.44 0.44 ±1.0
Unit
12mA -12mA respectively LOCK output. PLL_EN input guaranteed meet this specification. Maximum test duration 2.0ms, output loaded time. Specification value preliminary, will finalized upon `MC' status.
CAPACITANCE POWER SPECIFICATIONS
Symbol Input Capacitance Power Dissipation Capacitance Power Dissipation 50MHz with Thevenin Termination Power Dissipation 50MHz with Parallel Termination Parameter Typical Values 15mW/Output 120mW/Device 57mW/Output 456mW/Device Unit Conditions 25°C
NOTE: mW/Output numbers output.
FREQUENCY SPECIFICATIONS +70° ±5%)
Guaranteed Minimum Symbol fmax
Parameter Maximum Operating Frequency (2X_Q Output) Maximum Operating Frequency (Q0-Q4,Q5 Output)
TFN160
Unit
Maximum Operating Frequency guaranteed with part phase-locked condition, outputs loaded with terminated VCC/2.
MC88915TFN160 (continued)
CHARACTERISTICS +70° 5.0V ±5%, Load Terminated VCC/2)
Symbol tRISE/FALL Outputs tRISE/FALL 2X_Q Output tPULSE WIDTH (Q0-Q4, Q/2) tPULSE WIDTH (2X_Q Output) Parameter Rise/Fall Time, Outputs (Between 0.2VCC 0.8VCC) Rise/Fall Time Output Pulse Width: VCC/2 Output Pulse Width: 2X_Q 80MHz 100MHz 133MHz 160MHz 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE 0.5tCYCLE Unit Condition Into Load Terminated VCC/2 tRISE: 0.8V 2.0V tFALL: 2.0V 0.8V Into Load Terminated VCC/2
tPD1 SYNC Feedback
SYNC Input Feedback Delay (Measured SYNC0 FEEDBACK Input Pins) 133MHz 160MHz
(With from VCC)
Note Figure Detailed Explanation
-1.05 -0.9 tCYCLE 300ps tCYCLE 300ps
-0.25 -0.10 tCYCLE 300ps tCYCLE 300ps Outputs Into Matched Load Terminated VCC/2 Outputs Into Matched Load Terminated VCC/2 Outputs Into Matched Load Terminated VCC/2 Also Time LOCK Indicator High Measured With PLL_EN Measured With PLL_EN
tCYCLE (2x_Q Output) tSKEWr3 (Rising) Note tSKEWf3 (Falling) tSKEWall3
Cycle-to-Cycle Variation
133MHz 160MHz
Output-to-Output Skew Between Outputs Q0-Q4, (Rising Edges Only) Output-to-Output Skew Between Outputs Q0-Q4 (Falling Edges Only) Output-to-Output Skew 2X_Q, Q/2, Q0-Q4 Rising, Falling Time Required Acquire Phase-Lock From Time SYNC Input Signal Received Output Enable Time OE/RST 2X_Q, Q0-Q4, Output Disable Time OE/RST 2X_Q, Q0-Q4,
tLOCK4
tPZL5 tPHZ,tPLZ5
TCYCLE this spec 1/Frequency which particular output running. specification's min/max values shift closer zero larger pullup resistor used. Under equally loaded conditions fixed temperature voltage. With fully powered-on, output properly connected FEEDBACK pin. tLOCK maximum with 0.1µF, tLOCK minimum with 0.01µF. tPZL, tPHZ, tPLZ minimum maximum specifications estimates, final guaranteed values will available when `MC' status reached.
Applications Information Versions
General Specification Notes Several specifications only measured when MC88915TFN55, phase-locked operation. possible have part phase-lock (automated test equipment). Statistical characterization techniques were used guarantee those specifications which cannot measured ATE. MC88915TFN55, units were fabricated with transistor properties intentionally varied create cell designed experimental matrix. performance characterized over range transistor properties (represented cells) excess expected process variation wafer fabrication area, performance limits testable specifications within those which guaranteed statistical characterization. this units passing test will meet exceed non-tested specifications limits.
These specs (tRlSE/FALL tPULSE Width 2X_Q output) guarantee that MC88915T meets 40MHz 33MHz MC68040 P-Clock input specification 80MHz 66MHz, respectively). these specs guaranteed Motorola, termination scheme shown below Figure must used. wiring Diagrams explanations Figure demonstrate input output frequency relationships three possible feedback configurations. allowable SYNC input range each case also indicated. There allowable SYNC frequency ranges, depending whether FREQ_SEL high low. Although shown, possible feed back output, thus creating 180° phase shift between SYNC input outputs. Table below summarizes allowable SYNC frequency range each possible configuration.
88915 2X_Q Output
(CLOCK TRACE)
68040 P-Clock Input
Figure MC68040 P-Clock Input Termination Scheme Table Allowable SYNC Input Frequency Ranges Different Feedback Configurations. FREQ_SEL Level HIGH HIGH HIGH HIGH Feedback Output (Q0-Q4) 2X_Q (Q0-Q4) 2X_Q Allowable SYNC Input Frequency Range (MHZ) (2X_Q FMAX Spec)/4 (2X_Q FMAX Spec)/2 (2X_Q FMAX Spec)/2 (2X_Q FMAX Spec) (2X_Q FMAX Spec)/8 (2X_Q FMAX Spec)/4 (2X_Q FMAX Spec)/4 (2X_Q FMAX Spec)/2 Corresponding Frequency Range (2X_Q FMAX Spec) (2X_Q FMAX Spec) (2X_Q FMAX Spec) (2X_Q FMAX Spec) (2X_Q FMAX Spec) (2X_Q FMAX Spec) (2X_Q FMAXSpec) (2X_Q FMAXSpec) Phase Relationships Outputs Rising SYNC Edge 180° 180°
resistor tied either Analog Analog shown Figure required ensure jitter present MC88915T outputs. This technique causes phase offset between SYNC input output connected FEEDBACK input, measured input pins. spec describes this offset varies with process, temperature, voltage. specs were arrived
measuring phase relationship lots described note while part phase-locked operation. actual measurements were made with 10MHz SYNC input (1.0ns edge rate from 0.8V 2.0V) with output back. phase measurements were made 1.5V. output terminated FEEDBACK input with ground.
EXTERNAL LOOP FILTER 0.1µF
REFERENCE RESISTOR ANALOG
ANALOG REFERENCE RESISTOR
ANALOG
0.1µF
With resistor tied this fashion, specification measured input pins 2.25ns 1.0ns
With resistor tied this fashion, specification measured input pins -0.775ns 0.275ns
SYNC INPUT 2.25ns OFFSET FEEDBACK OUTPUT
3.0V 5.0V
SYNC INPUT
-0.775ns OFFSET
3.0V
5.0V FEEDBACK OUTPUT
Figure Depiction Fixed SYNC Feedback Offset (tPD) Which Present When Resistor Tied Ground
tSKEWr specification guarantees that rising edges outputs Q/2, will always fall within 500ps window within part. However, relative position each output within this window specified, window must added each side specification limits calculate total part-to-part skew. this reason absolute
distribution these outputs provided table When taking skew data, used reference, measurements relative this output. information Table derived from measurements taken from process lots described Note over temperature voltage range.
Table Relative Positions Outputs Q/2, Q0-Q4, 2X_Q, Within 500ps tSKEWr Spec Window Output (ps) (ps) 2X_Q -274 -633
Calculation Total Output-to-Skew between multiple parts (Part-to-Part skew) combining specification information Note worst case output-to-output skew between multiple 88915's connected parallel calculated. This calculation assumes that parts have common SYNC input clock with equal delay that input signal each part. This skew value valid 88915 output pins only (equally loaded), does include trace delays varying loads. With resistor tied analog shown note spec. limits between SYNC output (connected FEEDBACK pin) -1.05ns -0.5ns. calculate skew given output between more parts, absolute value distribution that output given table must subtracted added lower upper spec limits respectively. output [276 (-44)] 320ps absolute value distribution. Therefore [-1.05ns 0.32ns] -1.37ns
lower limit, [-0.5ns 0.32ns] -0.18ns upper limit. Therefore worst case skew output between number parts |(-1.37) (-0.18)| 1.19ns. worst case skew distribution output, 1.2ns absolute worst case output-to-output skew between multiple parts.
Note explains that specification measured guaranteed configuration output connected FEEDBACK SYNC input running 10MHz. fixed offset (tPD) described above some dependence input frequency what frequency running. graphs Figure demonstrate this dependence. data presented Figure from devices representing process extremes, measurements were also taken voltage extremes (VCC 5.25V 4.75V). Therefore data Figure realistic representation variation tPD.
-0.50 -0.75 SYNC -1.00 FEEDBACK (ns) -1.25 -1.50
-0.5
-1.0 SYNC FEEDBACK (ns) -1.5
10.0 12.5 15.0 SYNC INPUT FREQUENCY (MHz)
17.5
-2.0
10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 SYNC INPUT FREQUENCY (MHz)
Figure versus Frequency Variation Output Back, Including Process Voltage Variation 25°C (With Resistor Tied Analog VCC)
SYNC FEEDBACK (ns) 10.0 12.5 15.0 SYNC INPUT FREQUENCY (MHz) 17.5
Figure versus Frequency Variation Output Back, Including Process Voltage Variation 25°C (With Resistor Tied Analog VCC)
SYNC FEEDBACK (ns) SYNC INPUT FREQUENCY (MHz)
Figure versus Frequency Variation Output Back, Including Process Voltage Variation 25°C (With Resistor Tied Analog GND) lock indicator (LOCK) will reliably indicate phase-locked condition SYNC input frequencies down 10MHz. frequencies below 10MHz, frequency correction pulses going into phase detector form SYNC FEEDBACK pins sufficient allow lock indicator circuitry accurately predict phase-locked conditition. MC88915T guaranteed
Figure versus Frequency Variation Output Back, Including Process Voltage Variation 25°C (With Resistor Tied Analog GND) provide stable phase-locked operation down appropriate minimum input frequency given Table even though LOCK frequencies below 10MHZ. exact minimum frequency where lock indicator functionality guaranteed will available when MC88915T reaches `MC' status.
SYNC INPUT (SYNC[1] SYNC[0]) tCYCLE SYNC INPUT
FEEDBACK INPUT
OUTPUT
tSKEWALL
tSKEWf
tSKEWr
tSKEWf
tSKEWR
OUTPUTS
tCYCLE OUTPUTS OUTPUT
2X_Q OUTPUT
Figure Output/Input Switching Waveforms Timing Diagrams (These waveforms represent hook-up configuration Figure page Timing Notes:
MC88915T aligns rising edges FEEDBACK input SYNC input, therefore SYNC input does
require duty cycle.
skew specs measured between VCC/2 crossing point appropriate output edges.All skews
specified `windows', deviation around center point.
output connected FEEDBACK input (this situation shown), output frequency
would match SYNC input frequency, 2X_Q output would twice SYNC frequency, output would half SYNC frequency.
25MHz FEEDBACK SIGNAL HIGH FEEDBACK REF_SEL
100MHz SIGNAL Input Output Frequency Relationship 2X_Q 50MHz CLOCK OUTPUTS this application, output connected FEEDBACK input. internal will line positive edges SYNC, thus frequency will equal SYNC frequency. outputs (Q0-Q4, will always frequency, 2X_Q output will frequency.
25MHz INPUT CRYSTAL OSCILLATOR EXTERNAL LOOP FILTER
SYNC[0] MC88915T ANALOG ANALOG FQ_SEL HIGH
Allowable Input Frequency Range: PLL_EN HIGH 5MHz (2X_Q FMAX Spec)/4 (for FREQ_SEL HIGH) 2.5MHz (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW)
Note: OE/RST input active, pull-up pull-down sistor isn't necessary FEEDBACK won't when back output goes into 3-state. Figure Wiring Diagram Frequency Relationships With Output Feed Back 100MHz SIGNAL 50MHz FEEDBACK SIGNAL HIGH FEEDBACK REF_SEL 2X_Q Input Output Frequency Relationship 25MHz SIGNAL this application, output connected FEEDBACK input. internal will line 50MHz positive edges SYNC, thus frequency (and rest outputs) will CLOCK equal SYNC frequency. output will OUTPUTS ways frequency, 2X_Q output will frequency. Allowable Input Frequency Range: 10MHz (2X_Q FMAX Spec)/2 (for FREQ_SEL HIGH) 5MHz (2X_Q FMAX Spec)/4 (for FREQ_SEL LOW)
CRYSTAL OSCILLATOR 50MHZ INPUT
EXTERNAL LOOP FILTER
SYNC[0] MC88915T ANALOG ANALOG FQ_SEL HIGH
PLL_EN HIGH
CRYSTAL OSCILLATOR
Figure Wiring Diagram Frequency Relationships With Output Feed Back 100MHz FEEDBACK SIGNAL HIGH Input Output Frequency Relationship 2X_Q this application, 2X_Q output connected 25MHz FEEDBACK input. internal will line FEEDBACK SIGNAL positive edges 2X_Q SYNC, thus REF_SEL 2X_Q frequency will equal SYNC frequency. 100MHz INPUT MC88915T SYNC[0] 50MHz output will always 2X_Q ANALOG quency, outputs will EXTERNAL CLOCK 2X_Q frequency. LOOP OUTPUTS FILTER ANALOG Allowable Input Frequency Range: FQ_SEL HIGH PLL_EN HIGH 20MHz (2X_Q FMAX Spec) (for FREQ_SEL HIGH) 10MHz (2X_Q FMAX Spec)/2 (for FREQ_SEL LOW)
Figure Wiring Diagram Frequency Relationships with 2X_Q Output Feed Back
BOARD 10µF FREQ BYPASS 0.1µF HIGH FREQ BYPASS 0.1µF (LOOP FILTER CAP) ANALOG ANALOG LOOP FILTER/VCO SECTION MC88915T 28-PIN PLCC PACKAGE (NOT DRAWN SCALE)
ANALOG
BOARD
SEPARATE ANALOG POWER SUPPLY NECESSARY SHOULD USED. FOLLOWING THESE PRESCRIBED GUIDELINES THAT NECESSARY MC88915T NORMAL DIGITAL ENVIRONMENT.
Figure Recommended Loop Filter Analog Isolation Scheme MC88915T Notes Concerning Loop Filter Board Layout Issues Figure shows loop filter analog isolation scheme which will effective most applications. following guidelines should followed ensure stable jitter-free operation: 1a.All loop filter analog isolation components should tied close package possible. Stray current passing through parasitics long traces cause undesirable voltage transients pin. 1b.The resistors, 10µF frequency bypass capacitor, 0.1µF high frequency bypass capacitor form wide bandwidth filter that will minimize 88915T's sensitivity voltage transients from system digital supply ground planes. This filter will typically ensure that 100mV step deviation digital supply will cause more than 100pS phase deviation 88915T outputs. 250mV step deviation using recommended filter values should cause more than 250pS phase deviation; 25µF bypass capacitor used (instead 10µF) 250mV step should cause more than 100pS phase deviation. good bypass techniques used board design near components which cause digital ground noise, above described step deviations should occur 88915T's digital supply. purpose bypass filtering scheme shown Figure give 88915T additional protection from power supply ground plane transients that occur high frequency, high speed digital system. 1c.There special requirements forth loop filter resistors 330). loop filter capacitor (0.1µF) ceramic chip capacitior, same standard bypass capacitor. 1d.The reference resistor injects current into internal charge pump PLL, causing fixed offset between outputs SYNC input. This also prevents excessive jitter caused inherent dead-band. (2X_Q output) running above 40MHz, resistor provides correct amount current injection into charge pump (2-3µA). TFN55, 100, running below 40MHz, 1.5M reference resistor should used (instead 1M). addition bypass capacitors used analog filter Figure there should 0.1µF bypass capacitor between each other (digital) four pins board ground plane. This will reduce output switching noise caused 88915T outputs, addition reducing potential noise `analog' section chip. These bypass capacitors should also tied close 88915T package possible.
MC88915T CLOCK
CMMU
CMMU CMMU
CARD
SYSTEM CLOCK SOURCE MC88915T DISTRIBUTE CLOCK
CMMU
CMMU
CMMU
CMMU CMMU
CARD
CMMU CLOCK POINT
CMMU
MC88915T MEMORY CONTROL
MEMORY CARDS
CLOCK POINT
Figure Representation Potential Multi-Processing Application Utilizing MC88915T Frequency Multiplication Board-to-Board Skew MC88915T System Level Testing Functionality 3-state functionality been added 100MHz version MC88915T ease system board testing. Bringing OE/RST will outputs (except LOCK) into high impedance state. long PLL_EN low, Q0-Q4, outputs will remain reset state after OE/RST until falling SYNC edge seen. 2X_Q output will inverse SYNC signal this mode. 3-state functionality will used, pull-up pull-down resistor must tied FEEDBACK input prevent from floating when fedback output goes into high impedance. With PLL_EN selected SYNC signal gated directly into internal clock distribution network, bypassing disabling VCO. this mode outputs directly driven SYNC input (per block diagram). This mode also used frequency board testing. Note: outputs into 3-state during normal operation, loop will broken phase-lock will lost. will take maximum 10mS (tLOCK spec) regain phase-lock after OE/RST goes back high.
OUTLINE DIMENSIONS
SUFFIX PLASTIC PACKAGE CASE 776-02 ISSUE
0.007 (0.180)
0.007 (0.180)
VIEW
0.010 (0.250)
0.007 (0.180) 0.007 (0.180)
0.007 (0.180)
0.010 (0.250)
0.004 (0.100)
VIEW
SEATING PLANE
VIEW 0.007 (0.180)
NOTES: DATUMS -L-, -M-, DETERMINED WHERE LEAD SHOULDER EXITS PLASTIC BODY MOLD PARTING LINE. DIMENSION TRUE POSITION MEASURED DATUM -T-, SEATING PLANE. DIMENSIONS INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH 0.010 (0.250) SIDE. DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: INCH. PACKAGE SMALLER THAN PACKAGE BOTTOM 0.012 (0.300). DIMENSIONS DETERMINED OUTERMOST EXTREMES PLASTIC BODY EXCLUSIVE MOLD FLASH, BURRS, GATE BURRS INTERLEAD FLASH, INCLUDING MISMATCH BETWEEN BOTTOM PLASTIC BODY. DIMENSION DOES INCLUDE DAMBAR PROTRUSION INTRUSION. DAMBAR PROTRUSION(S) SHALL CAUSE DIMENSION GREATER THAN 0.037 (0.940). DAMBAR INTRUSION(S) SHALL CAUSE DIMENSION SMALLER THAN 0.025 (0.635).
INCHES 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 0.026 0.032 0.020 -0.025 -0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 -0.020 0.410 0.430 0.040
MILLIMETERS 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 0.66 0.81 0.51 -0.64 -11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 -0.50 10.42 10.92 1.02
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided Motorola data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer. MOTOROLA Stylized Logo registered Patent Trademark Office. other product service names property their respective owners. Motorola, Inc. 2001. reach USA/EUROPE/Locations Listed: Motorola Literature Distribution; P.O. 5405, Denver, Colorado 80217. 1-303-675-2140 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, King Street, Industrial Estate, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE:
MC88915T/D

Order Number: MC88915T/D 08/2001 Skew CMOS Clock Drivers, 3-State

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