Pinout A236 Parallel Video Chip PQFP Rev. December 1998. download
|
|
|
Top Searches for this datasheet
Pinout A236 Parallel Video Chip
Pinout A236 Parallel Video Chip PQFP
Rev. December 1998. download. Note: Negations shown "#". Arrows indicate direction signal flow: input, output, bidirectional Name ->CPU_Clk ->Reset# ->Suspend# ->Test0 <>Serial_Clk Vdd5 <>Serial_Data ->Test1 <-Sync Vdd5 ->RS232_RxD <-RS232_TxD ->RS232_CTS# <-RS232_RTS# ->H_Port_En# <>H_Active# Vdd5 <>H_InRdy Type input power input passive input power passive input bidirectional power bidirectional passive input output power input output power input output power input bidirectional power bidirectional Style Comments
clock 50/50 duty cycle zero line line zero line line zero line line line zero line line zero line line zero line line zero line core core control core control output pads core control open drain wired-OR core serial port core control test output pads RS-232 data RS-232 data core RS-232 control RS-232 control output pads Host port control Host port control input pads open drain wired-OR
Pinout A236 Parallel Video Chip
<>H_Strobe ->H_Grt <>H_Req Vdd5 <>H_Data_Valid# <>Host15 <>Host14 <>Host13 <>Host12 <>Host11 <>Host10 <>Host9 Vdd5 <>Host8 <>Host7 <>Host6 <>Host5 Vdd5 <>Host4 <>Host3 <>Host2 <>Host1 <>Host0 Right0<> Right1<> Right2<> Right3<>
bidirectional power input bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional power bidirectional bidirectional power bidirectional bidirectional
clock Host port control zero line line zero line line zero line line zero line line zero line line zero line line zero line line zero line line zero line line zero line zero line line zero line line input pads Host port control Host port control core Host port control Host port data core Host port data Host port data output pads Host port data Host port data core Host port data Host port data output pads Host port data Host port data output pads Host port data Host port data core Host port data Host port data core Host port data Host port data output pads Host port data input pads Right port data Right port data core Right port data Right port data
Pinout A236 Parallel Video Chip
Right4<> Right5<> Vdd5 Right6<> Right7<> Right8<> Right9<> Right10<> Right11<> Vdd5 Right12<> Right13<> Right14<> Right15<> Vdd5 R_Data_Valid#<> R_FSync|Req<> R_LSync|Grt<Vdd5 R_Strobe<> R_VSync|InRdy<> R_Active#<> R_Port_En#<Vss Mem_DQ0<> Mem_DQ1<> Mem_DQ2<> Mem_DQ3<> Vdd3.3 Mem_DQ4<>
power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional power bidirectional input power bidirectional bidirectional power bidirectional input power bidirectional bidirectional power bidirectional bidirectional power bidirectional
zero line line zero line line zero line line zero line line zero line line zero line line zero line zero line line zero line zero line line zero line line zero line line zero line
output pads Right port data Right port data core Right port data Right port data core Right port data Right port data output pads Right port data Right port data output pads Right port data Right port data output pads Right port data Right port data core Right port control core Right port control Right port control input pads open drain wired-OR input pads Right port control Right port control output pads memory data memory data output pads memory data memory data memory output pads memory data
clock Right port control
Pinout A236 Parallel Video Chip
Mem_DQ5<> Mem_DQ6<> Mem_DQ7<> Vdd3.3 Mem_DQ8<> Mem_DQ9<> Vdd3.3 Mem_DQ10<> Mem_DQ11<> Mem_DQ12<> Mem_DQ13<> Mem_DQ14<> Mem_DQ15<> Mem_A0-> Mem_A1-> Vdd3.3 Mem_A2-> Mem_A3-> Vdd5 Mem_A4-> Mem_A5-> Mem_A6-> Mem_RAS#-> Vdd3.3 Mem_CAS#-> Mem_CS0#-> ->Mem_Clk
power bidirectional bidirectional power bidirectional power bidirectional bidirectional power power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional power output output power output output power power output output power output output power output output power input
zero line line zero line zero line line zero zero line line zero line line zero line line zero line line zero line line zero zero line line zero line line zero line line zero
input pads memory data memory data output pads memory data memory output pads memory data memory data core memory output pads memory data memory data output pads memory data memory data input pads memory data memory data output pads memory address memory address memory output pads memory address memory address core output pads memory address memory address core memory address memory control memory control core memory control memory control input pads
clock memory control
Pinout A236 Parallel Video Chip
Mem_CS1#-> Mem_WE#-> Mem_A7-> Mem_A8-> Vdd5 Mem_A9-> Mem_A10-> Mem_A11-> Mem_CS2#|A12-> Vdd3.3 Mem_CS3#|A13-> Mem_DQ16<> Mem_DQ17<> Mem_DQ18<> Mem_DQ19<> Mem_DQ20<> Mem_DQ21<> Mem_DQ22<> Vdd3.3 ->Test_En# <>Mem_DQ23 <>Mem_DQ24 Vdd3.3 <>Mem_DQ25 <>Mem_DQ26 <>Mem_DQ27 Vdd3.3
power output output power output output power output output power output output power output bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional power passive input power bidirectional bidirectional power bidirectional power bidirectional power bidirectional power
zero line line zero line line zero line line zero line line zero line line zero line line zero line line zero line line zero line zero line line zero line zero line zero line zero
output pads memory control memory control core memory address memory address core memory address memory address output pads memory address memory control/address memory output pads memory control/address memory data output pads memory data memory data input pads memory data memory data output pads memory data memory data memory output pads connect through resistor core memory data memory data memory output pads memory data output pads memory data input pads memory data memory output pads
Pinout A236 Parallel Video Chip
<>Mem_DQ28 <>Mem_DQ29 <>Mem_DQ30 <>Mem_DQ31 ->L_Port_En# <>L_Active# <>L_VSync|InRdy <>L_Strobe Vdd5 ->L_LSync|Grt <>L_FSync|Req <>L_Data_Valid# Vdd5 <>Left15 <>Left14 <>Left13 <>Left12 Vdd5 <>Left11 <>Left10 <>Left9 <>Left8 <>Left7 <>Left6 Vdd5 <>Left5 <>Left4 <>Left3 <>Left2
bidirectional bidirectional power bidirectional bidirectional power input bidirectional power bidirectional bidirectional power input bidirectional power bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional power bidirectional bidirectional
line line zero line line zero line line zero line zero line line zero line zero line line zero line line zero line line zero line line zero line line zero line line zero line line
memory data memory data output pads memory data memory data output pads Left port control Left port control input pads open drain wired-OR input pads Left port control Left port control core Left port control core Left port data Left port data output pads Left port data Left port data output pads Left port data Left port data output pads Left port data Left port data core Left port data Left port data core Left port data Left port data output pads Left port data Left port data
clock Left port control
Pinout A236 Parallel Video Chip
<>Left1 <>Left0
power bidirectional bidirectional power
zero line line zero
core Left port data Left port data input pads
Oxford Micro Devices, Inc.
Ax36 Parallel Video Digital Signal Processor Chips Lantern Ridge Office Park; Main Street, Bldg. Suite Monroe, 06468 tel. 203-445-0562; 203-445-0564; e-mail: info@omdi.com; Web: http://www.omdi.com/ Copyright 1995 1999. rights reserved. Patents pending. trademarks property their respective owners used product identification purposes only.
Other recent searches
SN74ALVC16901 - SN74ALVC16901 SN74ALVC16901 Datasheet
JW050R - JW050R JW050R Datasheet
JW075R - JW075R JW075R Datasheet
JW100R - JW100R JW100R Datasheet
JW150R - JW150R JW150R Datasheet
CXA3170N - CXA3170N CXA3170N Datasheet
CAT9532 - CAT9532 CAT9532 Datasheet
APT33GF120BR - APT33GF120BR APT33GF120BR Datasheet
AN1482 - AN1482 AN1482 Datasheet
74VCX16839 - 74VCX16839 74VCX16839 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
