CLC522 Advanced Operating Considerations Military Specifications

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CLC522 Advanced Operating Considerations Military Specifications

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CLC522 Advanced Operating Considerations Military Specifications
CLC522 Variable Gain Amplifier versatile circuit that used wide variety applications. basic operation specifications CLC522 described datasheet CLC522; however, many more demanding applications, information contained datasheet insufficient analyze expected performance. purpose this application note provide additional information needed analysis some these more demanding applications. application note companion datasheet, have copy datasheet, should requested obtain full benefit from this application note. Frequency Response Determining Elements CLC522 should thought four separate amplifier elements single package. These very wideband, closed loop, unity gain buffers, quadrant multiplier core with gain control linearization, wideband current feedback used transimpedance output stage. Both buffer bandwidths multiplier bandwidth typically excess output amp. therefore frequency response output stage that typically sets overall bandwidth CLC522. However, high values (low Avmax), input buffers peaking slightly. This allows increased bandlimit output amplifier compensation this input buffer peaking. Conversely, very Rg's (high Avmax), input buffers start become bandlimiting point. this case, decreased from nominal value peak output amplifier. This partially compensates increased rolloff input heavy loading buffer outputs. This discussion reflected plot showing suggested Avmax. This plot shows required most closely match Avmax typical frequency response when operating with 1.1V. addition, plot shows bandwidth reduction various Avmax settings) increased value. Increasing will allow increased, given desired Avmax, which will allow higher maximum differential (VAdmax) input signal applied. Very little change frequency response observed reduced below volt reducing CLC522 signal gain from Avmax. Since frequency response dominantly determined output amplifier, shunting signal away ground quadrant multiplier little effect shape either magnitude phase response (see plots 10). When CLC522
1994 National Semiconductor Corporation
Printed U.S.A.
actually being used attenuator, however, high frequency feedthrough will alter shape frequency response high frequencies (see plots Usable Gain Adjustment Range gain CLC522 always varied from Avmax varied from applications where maximum input voltage that always less than Vdmax applied, CLC522 used adjust output swing, this full attenuation range available. This application reflected plots through However, when CLC522 gain adjust used compensate very wide range input signals increasing gain inputs decreasing gain higher inputs, there very definite limits usable gain adjustment range. (This discussion usable gain adjustment range will neglect added setting gain). From maximum gain Avmax 1.85 Rf/Rg, CLC522 thought electrical attenuator gain control voltage reduced below situations where constant maximum output signal voltage desired, maximum gain will used minimum input while minimum gain will used when maximum input signal present. This that gain being adjusted hold constant output voltage swing. Rather, input signal varying over range voltages CLC522 gain being adjusted such that maximum input signal always being scaled desired maximum output voltage. Given resistor values selected along with current limit input stage (ITAIL), maximum attenuation from Avmax computed that satisfies requirement that maximum input voltage minimum gain) does cause more than ITAIL flow useful here discuss gain range terms also often useful consider input output sinusoidal voltage swings terms dBm. gain from differential input voltage output voltage terms given equation ((Vg+1) Avmax/2))
Converting sinusoidal voltage from peak peak swing into done using equation PdBm
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Strictly speaking, this power resistor referenced 1mW. However, purposes this discussion, peak-to-peak voltage swing across resistive load will computed equation Given maximum plus minus current available (±ITAIL), this current, times 1.85, maximum (when volt) that available feed through producing maximum available output voltage swing; Vopp(max) 1.85 ITAIL When CLC522 gain being adjusted hold output swing relatively constant, desired maximum Vopp must less than Vopp(max) shown above there gain adjust range. gain reduced from Avmax, available maximum current through also being attenuated same amount that gain been attenuated. gain therefore only reduced from Avmax until this attenuation gain times 1.85 ITAIL equals desired maximum Vopp. ratio maximum available swing, Vopp(max), desired maximum output voltage swing, Vopp, also ratio maximum gain minimum gain. Equation summarizes this discussion showing available gain range before input limiting occurs. Linear (V/V) gain adjustment range Vmax 1.85 ITAIL vmin Vopp terms, gain adjust range 1.85 ITAIL Vopp
ment range requirement leads maximum Vopp, 1.85 ITAIL/) that less than desired, fixed gain postamplifier should used. Gain Accuracy Considerations CLC522 intended provide exceptionally well controlled attenuation from Avmax where full gain adjust range ground referenced from volt. actually compared internal reference developed from negative supply voltage. Equation modifies equation 2(?) include effect minus supply. Vg/(0.2 (|VEE|))) Avmax/2
equation reduces equation effect variations expand contract full scale gain control range. variations will modulate output dependent upon input signal present. PSRR (plot therefore only positive supply voltage since variations minus supply will show output dependent input signal present. critically important, therefore, keep minus supply stable free high frequency noise. Controlling Offsets With input signal present, there will always residual voltage output. This offset arises from input stage mismatches, bias current 2-quadrant multiplier output, output error terms. Figure shows error model including these effects.
Note that this gain adjustment range independent hence Avmax. This will gain adjustment range available from maximum gain selected given desired maximum Vopp. form equation used plot ITAIL 1.8mA given range values swept over wide range desired maximum output voltage swings. CLC522 design done using these results. Given required gain adjustment range, select from plot consistent with desired bandwidth (with some assumption Avmax this point), then, entering plot y-axis desired gain adjustment range over intersection with selected line then extend downward read available fixed output swing. available Vopp less than equal desired level, using minimum input voltage coming maximum gain hence resolved (Some iterating this would required since plot parametric terms Avmax). required desired bandwidth along with gain adjust-
Ibcore
1.85 (Ib1R Vio1 Ib2R Vio2 (Ibcore Ib1) IbnRb
Figure Offset Model model Figure includes input bias currents offset voltages each input buffers well usual error terms output amp. also includes dependent current, Ibcore, that sums parallel with inverting input bias current output amplifier. This error current non-linear dependence
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gain adjust voltage, buffer input bias currents typically matched closer than 0.1mA while buffer input offset voltages matched typically less than 1mV. take advantage this excellent bias current match buffer inputs offset current), matched source impedances should provided buffer inputs. output offset voltage improved using adjustments shown Figure
0.1µF
Output Trim
Input Trim
1,13,14
CLC522
Vout
correct only errors introduced output amplifier, gain should first adjusted minimum -1). With contribution input error terms, Figure used current into inverting node output amplifier cancel just output amplifier error terms. This adjustment could alternatively used introduce fixed independent) offset into output voltage. With output amplifier's level determined while returning maximum expected value (gain) will allow input error terms cancelled. With maximum value that will used, Figure adjusted return output voltage value measured when minimum gain setting. This input adjustment actually introducing offset that cancelling effect both input buffer error terms effect Ibcore maximum gain setting. adjustment Figure could alternatively used cancel fixed component input signal. this application, input should connected adjusted move component desired level output. Adjusting input output stage offsets gain extremes will hold output error minimum these points gain range. non-linear error introduced multiplier core will cause residual, gain dependent, offset appear output gain swept from minimum maximum. Also, neither input output offset adjustments described here will improve temperature drift effects. Generally, will reduce gain error current terms inverting input output amplifier. Note that matching Figure bias current cancellation output will work current feedback amplifiers, and, case, should always good matching, actual errors introduced input buffers relatively minimal particularly with low, matched, source impedances (Rs1 Rs2). Although shown Figure each input
0.1µF
Power supply de-coupling shown
Figure Input Output Stage Offset Adjustments will possible completely null output offset gain adjusted since Ibcore term Figure will vary non-linearly over gain adjustment range. However, first order correction error terms Figure accomplished removing input signal (but retaining source impedance) making following adjustments.
3.2nV 1.6pA
4kTRS1
(noiseless)
4kTR'g
(14pA)Rg
optional
IgRMS Icore 30.5pA
4kTRf
VRS2 3.2nV 1.6pA 1.9nV
4kTRb
4kTRS2
Figure Full CLC522 Noise Model
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buffers introduce very well matched drop approximately 0.9V from their inputs output voltage across This common mode voltage level shift resistor consequence normal operation, should kept mind paths connected some reason pins Noise Model complete noise model part flexible CLC522 necessarily somewhat complex. That model, with external resistor noise sources included, shown Figure optional resistor coming into inverting output amplifier been included this model completeness. This would impedance looking back towards either offset adjust network separate signal source. Each noise voltages currents Figure spot noises (per Hz). arrive expression total output spot noise nV/Hz) each noise sources Figure must taken output gain then squared. total equivalent output noise then square root squared contributing elements. application note OA-12 general discussion computing amplifier noise. analysis equation steps through developing total output noise voltage from model Figure This analysis generates expression total output noise first developing noise voltages squared (powers) output amplifier noise, then contribution input stage noise terms, finally gain signal level dependent current noise term inverting input output amplifier, Icore, considered.
Total output spot noise power
Icore noise term merits additional description. This term actually modeling noise injected through gain adjustment input, either gain extreme, (for ±1V), this term zero. Icore noise current reaches maximum which would maximum gain setting. this Icore shows peak value that dependent current resistor. Noise path will modulate gain this input signal current. maximum gain, signal current being passed transimpedance stage Icore contribution zero. Similarly, with gain adjust channel shut -1V, signal current passed through multiplier core Icore again zero. maximum noise contribution through channel where exactly half signal current being diverted ground, effect this increasing Icore with reducing gain hold output noise through first attenuation from maximum gain. This recommended values, only perceptible relatively Avmax observed plot Avmax Avmax Computing Signal Noise Ratio applications where desired hold fixed output voltage swing (Vopp), most meaningful consider output. this application, worst case will generally occur maximum gain, Avmax. possible, lower Avmax settings, slight degradation first attenuation from maximum gain effect Icore discussed previous section. However, improved accuracy does justify complexity introduced including this term analysis. Therefore, good approximation that worst case output will
(1.9nV) (5pARb 4kTRb
4kTR Output amplifier noise terms 14pAR
(3.2nV) 1.6pARs1
(1.6pARs
1.85
Input stage noise terms Ig(RMS) 30.5pA 12.4pA 7.5pA
Fixed term Core current noise Ig(RMS) current (include Generally, most these terms negligible; with relatively 4kTR relative (30.5pAR
14pAR
Ig(RMS) (3.2nV) 1.85 30.5pA 12.4pA 7.5pA 1444444444 24444444444 Icore
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occur Avmax. This would when input minimum applications that using CLC522 move very widely varying input range more limited output range. While will improve gain reduced, harmonic distortion will getting worse input signal range increasing. Most distortion terms current which will maximum when gain minimum. Using some operating constraints imposed CLC522, possible significantly simplify equation into relatively simple expression worst case output Avmax. Continuing assumptions equation (that Rs1, Rs2, low, that present, that voltage noise output amplifier contribution resistor noise negligible), evaluating this expression Avmax, yields maximum output spot noise voltage.
14pAR
Solving substituting ITAIL
These three expressions constraining Avmax, substituted into equation yield
Vopp 14pA (3.2nV)2 30.5pA 2ITAIL 1.85 ITAIL
After some algebraic manipulation equation results Vopp 2ITAIL
(21.6pA)2 3.2nV
2ITAIL
Note that that
2ITAIL Vopp 2ITAIL 1.85
(3.2nV) 1.85 (30.5pA
situations where minimum input voltage (Vimin), maximum input voltage (Vimax), desired output voltage (Vopp) known, both will determined gain maximum differential input voltage constraints (see discussion usable gain adjust range). expression Eomax then simplified using these constraints assumption that this analysis will make that resistor values will such that ±ITAIL will flow when input maximum peak-to-peak swing. This will make full dynamic range CLC522. discussion input output voltage swings peak -to-peak, current limited peak sense. half peak peak input voltage therefore used computing peak current From equation expression found solving either gain adjust range,
This greatly simplified expression maximum output spot noise compared output signal voltage worst case SNR. This will done relative maximum Vopp. Recognize, however, that application output voltage gain setting will going below this Vopp. Dividing this maximum Vopp computed minimum will tell below Vopp signal discerned from noise output. this convert output spot noise integrated noise voltage multiplying equation square root Noise Power Bandwidth dividing this into output voltage ((Vopp/(2 sinusoids). Doing this yields: Minimum Vopp Vopp 2ITAIL 2ITAIL
1.85 ITAIL
Vopp
where linear gain adjust range
(21.6pA)2 3.2nV
Simplifying equation gives Minimum ITAIL
also assumed that minimum input will operate maximum gain (and neglecting simplicity that added setting Avmax) 1.85
input stage current will constrain follows
(21.6pA)2
3.2nV TAIL
2NPB
ITAIL (recalling that peak peak
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important note that value Vimax strongly influences minimum SNR. Vimax becomes relatively small, minimum become rapidly larger. Setting noise currents under radical equal solving Vimax will yield crossover point where effect Vimax starts dominate. Using ITAIL= 1.35mA, this yields Vimax .57Vpp. Vimax 0.57Vpp, this second term radical rapidly becomes negligible achievable minimum reaches floor 21.6pA term. Vimax 0.57Vpp, minimum will decrease steadily with decreasing Vimax also important note that output will improve from value computed equation gain reduced from Avmax. This follows from assumption that input signal increasing gain reduced below Avmax. Example Calculation Minimum Using results previous section, would instructive step through entire design. example, following design information: Vimax 1Vpp (gain adjustment range, implies Vimin 0.1Vpp) ITAIL 1.35mA 50MHz Then, using equation worst case RMS/RMS) Minimum 1.35mA
Checking whether ITAIL current limit satisfied Igmax (Vimax/2)/Rg (1Vpp/2)/370 1.35mA finally, checking plot CLC522 bandwidth that will result 2000 Avmax shows approximately 74MHz. Some means setting 50MHz after CLC520 will required above results. alternative design approach would control desired bandwidth using assumed Avmax plot only modification foregoing analysis that, with given along with gain adjust range Vimax, minimum expression unchanged achievable output voltage expression used earlier Solving
1.85 ITAIL
Vopp
Vopp
Vopp
1.85 ITAIL
Re-doing previous example while targeting 1000 yields same value Vopp goes Vopp 1000 1.85 1.35mA 1.85 1000
(21.6pA)
2(1.35mA 3.2nV 1Vpp
50MHz
imum gain dropped
This result states that when input signal ranging 0.1Vpp (and CLC522 maximum gain whatever needed desired Vopp) input signal range down 0.1Vpp/544 0.18mV have power CLC522 output equal noise power. very interesting note that although actual value desired Vopp will have impact minimum SNR, will, along with desired gain adjustment range ITAIL, determine required value Continuing this example determine values, targeting Vopp 1Vpp (which will Avmax 1Vpp output when Vipp 0.1Vpp).
Going plot Avmax shows 220MHz bandwidth. becomes necessary achieve particular bandwidth, take whatever Vopp that results, fixed gain post amplifier used adjust Vopp higher level desired. would very poor post amplifier that would degrade from that available output CLC522. summary, when CLC522 being used scale varying input range fixed output range, minimum output will occur maximum gain setting since this operating condition when input minimum. From equation this minimum depends only maximum current allowed (ITAIL), desired gain adjust range maximum anticipated input signal, noise power bandwidth, some constant noise terms associated with CLC522. This minimum independent desired Vopp. value feedback resistor (Rf) will simultaneously both Vopp, Avmax, CLC522 bandwidth. primary design then make correct tradeoff's getting value
1.85 ITAIL 1.85 1.35mA)
1.85 2002 1.85
Vopp
1Vpp
2002
(from
(recall that physical resistor must lower account buffer output impedances)
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Using Output Amplifier Separately Although output principally intended transimpedance stage signal current coming gain adjustment stage, also used inverting additional signals. non-inverting input this also available However, this should never used inject signal offsets. should always connected good ground plane through resistor. Figure shows example high frequency signal summed into output (with gain this case) independently output signal gain adjusted input
minimum distortion level that expected (see plots 32). output amplifier shows exceptional harmonic distortion harmonic term that increases rapidly with power frequency. input stage contributes harmonic distortion that depends only power level resistor relatively independent gain setting. fact input stage shows very good match order intercept model. (Some statement here harmonic distortion) Limits Range Overdrive Recovery Several factors limit input output voltage ranges. most cases, input stage will limit before output stage reached maximum voltage swing. maximum current available through simply 1.85 ITAIL. long 1.85 ITAIL Vomax, input stage will always limit ITAIL before output amplifier reach it's maximum voltage (i.e. Vomax). output amplifier limiting case, 1.85 ITAIL Vomax. With ITAIL 1.8mA Vomax volts, must >1.1k. Thus far, only maximum gain case been considered. This when full 1.85*ITAIL passed through multiplier core output transimpedance stage. gain reduced from Avmax, less maximum current available voltage swing limit will eventually return input stage even high values. This shown equating available maximum current through output amplifier's voltage limit shown equation 1.85 ITAIL
1,13,14
CLC522
Vout
Supply decoupling shown
Figure Using Output Amplifier Separate Signal circuit Figure with volt, ||Rt series output resistor into load, used illustrate output amplifier performance plots These plots show that output exceptional amplifier itself. output configured inverting amplifier offers small signal bandwidth excess 200MHz (for inverting gains harmonic distortion powers greater than 60dBm less than fundamental output signals 20MHz 2Vpp (10dBm) into 100W load, 2-tone order intercept 35dBm frequencies <20MHz (defined matched load). output should used inverting gains this inverting gain increased beyond this, order effects will start limit bandwidth signal current from gain adjust stage. addition, higher inverting gains will begin contribute significant errors from output amp's non-inverting input offset voltage noise. Predicting Harmonic Distortion (still development) total harmonic distortion present output will combination both input stage output amplifier effects. output amplifier's harmonic distortion sets
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Solving required have equal input output limit (note that this bipolar limit) 1.85 ITAIL
example, consider Avmax case with ITAIL 1.8mA Vomax Volts. Avmax, voltage swing limit will output stage Vomax since 1.1k. Solving equation this example shows that 0.11 Volt voltage limit will move input stage. Once swing limit moved input, right side equation what available output. Recall that this input limit simply differential input voltage that causes ITAIL flow This discussion provide another approach computing available attenuation from maximum gain fixed desired output voltage swing. Substituting desired Vopeak into equation place Vomax, (and recognizing that this peak swing actually available peak-to-peak swing since ITAIL bipolar), will yield minimum before input stage limiting occurs. this expression substituted into log((Vg+1)/2) (which form attenuation Vg), equation results
Vopeak available attentuation 1.85 ITAIL
Eq.14
This simply earlier expression gain adjust range, equation with Vopp/2 replaced Vopeak fraction flipped over give negative numbers maximum attenuation. Output limited overdrives recover much more quickly than input limited overdrives. This seen typical overdrive recovery waveforms plots important additional limit operation input. input voltages beyond control input range risk saturating internal nodes which will severely degrade apparent gain control channel bandwidth brought back into range. This gain control channel saturation change loop dynamics continuous feedback adjustable gain circuits. this slowing down gain control response problematic, limit +1.2V should observed avoid internal saturation gain adjust channel. Specifications Several dynamic range characteristics unique amplifier descriptions. specifications that applied CLC522 include noise figure, 2-tone, order intercept, -1dB compression. While noise figure input referred specification, (with some assumption source impedance), intercept compression specifications commonly reference output power matched load. these specifications, then, will assumed that series resistor load present output. gain that been previously discussed voltage gain from input output will this matched load instead. Hence, input output gain will half decreased 6dB. Also, these specifications assuming purely sinusoidal inputs. further reference, application note OA-11 defines each these specifications describes apply them type amplifiers. addition, spreadsheet that will calculate noise figure 2-tone spurious levels over wide range operating conditions available from Comlinear applications department. Noise Figure noise figure device measure degradation Signal-to-Noise ratio going from input output. input noise taken noise power delivered source resistor input impedance amplifier circuit. Figure shows this definition CLC522.
Power supplies shown
CLC522
Input signal power Noise power
Noise Figure
delivered
Output signal power Output Noise power
Figure Noise Figure Definition Every term this noise figure equation power which considered this case voltage^2. After some manipulation, setting noise figure easily written terms total noise voltage output voltage gain from input output pins follows: where
total output noise voltage voltage gain from pin3 21(at 290°k
This expression noise figure then equation more complete expression output noise) compute noise figure particular gain resistor values. noise figure discussed here bandwidth (i.e. spot noise figure). Plot shows this spot noise figure (for each input terminated ground 50s) using equation complete expression total output noise. 2-tone, Order, Intermodulation Intercept simple model amplifier will typically project that order intermodulation spurious powers will increase 3dBm every 1dBm increase signal powers closely spaced frequencies. average frequency high power signals taken with equal spacing around this center frequency, order spurious terms will fall Assuming equal powers (Po) desired signals, equal order spurious powers (Ps) will also result. particular frequency, equation shows intercept (IM3) defined from single measurement (where powers matched load).
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utility this estimate intercept that given equal tone output signal power levels, spurious power intermodulation frequencies predicted shown equation
effect log(Rg/50) expression Given these contributions order spurious power, equation combines these into typical combined spurious power.
terms below desired signals spurious are, (IM3-Po)
general, input stage spurious will dominate contribution output order spurious power. input generated spurious will greater than output stage spurious long condition shown equation satisfied. output stage will dominate only high GdB. IM3o plot appropriate This plot would also apply additional signals brought into inverting input output amplifier. value IM3o other values should adjusted subtracting (Rf/1k) from value determined from plot operating frequency interest. This will approximately account change loop gain output amplifier different values This model predicting order spurious powers only holds operation linear region CLC522. principal limit operating region directed exceeding ITAIL input peak value input 2-tone sinusoidal waveform. equal powers (Po) matched load, equation computes peak through gain setting resistor, 0.002 2000
National application notes OA-11 OA-22 treat considerable detail this intercept model predicting 2tone intermodulation distortion levels. 2-tone intermodulation spurious powers output CLC522 combination order distortion mechanisms both input stage output amplifier. most cases, order distortion current will dominate setting intermodulation distortion output. Since this case cascaded amplifier intermodulation distortion, single number total amplifier applicable. However, separate values input stage output amplifier will allow calculation spurious power levels output. Using intercepts plot total output spurious level estimated. Since distortion coming points CLC522, (for single pair desired signal frequencies), distortion introduced input will have fixed (but unknown) phase relationship distortion introduced output stage. reasonable estimate would assume that these sources distortion quadrature will together square root summed squared voltages. Given desired tone power level matched load (Po), gain from input output, contributions spurious power output (Ps) will 2IM3o Output amplifier term IM3i Input stage term taken output IM3o IM3i taken from plot frequency interest. Note that gain from input output pins (equation term expression accounts loss going from output matched load. Since input stage distortion really depends current resistor, input power must converted power This
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peak
Test data CLC522 indicates that this model output 2-tone spurious power holds well IRg(peak) 2.2mA. example, consider calculating order 2-tone spurious power levels following conditions Avmax 20V/V (26dB) output pin: 20dB matched load 2.5k yield enough gain ITAIL 4Vpp satisfy 1.85 Rf/Rg (physical 229) Atten operating gain load (14dB) 4dBm (1Vpp each tone, 2Vpp 2-tone envelope) 20MHz (Test frequencies 20MHz ±100kHz) From this, various limits operation should checked. Total output voltage swing Peak output current Peak slew rate output Peak current into 2/100 20mA 20MHz)= 251V/msec (2/5)/231 1.73mA
these within operating range CLC522. output order spurious calculated using expressions developed previously.
IM3o 40dBm 10log(2500/1000) 36dBm (from plot adjusted 2.5k) IM3i 16dBm (from plot 20MHz) 2*36 -60dBm output amplifier term (equation 6.6) -63.2dBm input amplifier term (equation log(10^(-60/10) 10^(-63.2/10)) -58.3dBm combination input output spurious contributions (equation this case, output amplifier setting 2-tone spurious level. delta from 4dBm single tone power level spurious power (-58.3) 62.3dBc. Note also that 2.5k feedback resistor will drop bandwidth 49MHz (from plot -1dB Compression This performance measure, like 2-tone intercept, defined power matched load. plot input output -1dB compression (plot therefore power that across resistor ground with additional series resistor from output CLC522 this load resistor. -1dB compression power tested sweeping input power, fixed frequency, observing where output power 1dBm less than what power gain would predict. This measurement then repeated over range frequencies. reported -1dB compression power this actual measured power plus been compressed. Again, there both input output limit that determine -1dB compression. output amplifier's voltage swing limit will -1dB compression point when available signal current through multiplier core times will exceed swing limit output amplifier. output limited case, ITAIL (Vg+1)/2 Vomax. Hence, output limiting occur principally higher Rf's maximum gain settings. maximum gain case plot output limited compression obtained 1.4k while input limited operation obtained 900. When swing limit been reached lower frequencies, either output voltage input current limit, output waveform approaches square wave sinusoidal input. these frequencies (<40MHz) gain setting, -1dB compression power matched load will minimum 16.8dBm (due output amplifier voltage swing limits) 13.1dBm log(1.85 ITAIL (Vg+1)/4) (input limited)
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interesting note that, once been reduced cause input limit output -1dB compression, output compression will decrease directly with signal gain. Figure shows this clearly where output -1dB compression over frequency shifts directly with gain setting when input limit setting available output power.
-1dB Compression Gain Adjust
-1dB Compression (2dBm/div)
Input Limited Maximum Gain
Attenuation 12dB Attenuation
Frequency (MHz)
Figure -11dB Compression Gain Adjust Although preceding discussion gives good predictor -1dB compression, this number does provide good predictor 2-tone order intercept. simplified assumption that intercept 10dBm above -1db compression does hold CLC522. full model developed previous section should used predict order intermodulation spurious levels. Advanced Applications Each following applications circuits exploit several unique feature CLC522. Please contact Comlinear applications group additional information these applications. Differential Amplifier buffers input CLC522 provide high input impedance, matched frequency response path, implementing differential amplifier (see Figure differential signal impressed across transformed into single ended current signal through This provides exceptional differential single ended conversion right input stage. With added flexibility being adjustable gain part, CLC522 used implement very wideband differential amplifier. Application note OA-16 discusses this application both CLC522 CLC520. Differential Line Equalizing Receiver Extending idea differential amplifier line receiver, recognizing that gain setting element used shape frequency response, equalizing receiver easily implemented shown Figure gain setting network shown figure implements series zero/pole pairs that placed compensate rolloff typically seen long coax cables. frequencies, gain starts only Rgo.
resistor capacitor values such that short sequentially smoothly increasing gain placing decreasing impedance parallel with Rgo. Additional pairs added improve approximation. this circuit, maximum high frequency current gain setting network will Rg1||Rgo. important check that ITAIL exceeded when high frequency input differential signal placed across this Rg1||Rgo minimum impedance.
Supply decoupling shown
This circuit actually implements very wideband multiplying function. Instead scaling current internal DAC, this circuit uses CLC522's input scale current that goes CLC522's transimpedance stage. important note that output zero does output polarity invert goes This then multiplying sense that used compress gain from codes output voltage swing. This approach provides exceptionally impedance load with compliance voltage problems output DAC. +0.9V reference buffer inputs compensates 0.9V drop from buffer inputs their outputs allows currents sources drive into volt impedance load. resistors +Vcc supply provide bias compensate part internal 1.8mA ITAIL. This increases maximum value allowed output current before non-linear internal limiting will occur CLC522. should relatively high value plays role setting signal gain this case. Using CLC522 Feedback Element Another approach extending gain adjustment range CLC522 imbed adjustable gain stage feedback element either voltage current feedback amp. Figure shows this topology along with some example component values using CLC404 current feedback amp.
CLC522
Figure Wideband, Equalizing, Differential Cable Receiver with Adjustable Gain Transimpedance Interface Most high speed DAC's complementary current output devices where output actually sinking current into DAC. From fixed maximum current available, digital codes acts steer this total current split between outputs. pulling these currents directly CLC522 buffer outputs (pins CLC522 easily used perform adjustable gain complementary current single ended voltage conversion. example this shown Figure
CLC404
Power supplies decoupling shown
CLC522
CLC522
0.925
Vout
Figure Using CLC522 Feed Element This circuit offers several advantages disadvantages (over simply using CLC522 adjustable gain stage) applications where desired hold constant peak peak output swing. principal advantage this circuit that peak input swing into CLC522 constant. This eliminates gain adjust range limitations discussed earlier. Equation shows overall transfer function ignoring bandwidth limitations CLC522.
Vref
+0.9V
Full output swing
±0.925
Figure Differential Transimpedance Interface
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signal gain 1.85 1.85 Z(s) loop gain Z(s) Open loop transimpedance gain forward path current feedback
This circuit applies signal input both gain adjust non-inverting input pin. wideband dual amplifier, CLC412, used both signal correction factor -VEE supply inverting summing stage invert signal again correct polarity driving input CLC522. Stepping through algebra Vo/Vi yields signal gain including dependence negative supply Vo/Vii 1.85 (Rf/Rg) Vg/(.2 VEE)) Substituting from Figure 1.85 0.2VEE 1.85 (0.2)
This transfer function shows that forward gain depends inverse gain through CLC522. Hence, high forward gain, CLC522 needs operating attenuator. Some this attenuation provided resistor divider from output forward amp. linear gain adjust characteristic CLC522 been transformed type transfer gain. were adjusted shutting CLC522 off, forward path will open loop have gain equal Z(s)/Rc. Equation also shows that loop gain equation become purely voltage feedback type characteristic showing gain-bandwidth product even when using current feedback amp. current feedback forward stage preferred, however, provide superior large signal swing allow easy frequency response compensation through adjusting value input referred noise been increased since becomes output noise CLC522. However, input peak peak signal decreases, gain increased decreasing CLC522 gain. This will have effect decreasing input referred noise input signal level decreases. Voltage Squaring Circuit Figure shows using CLC522 square input signal voltage. specific values used this example will scale output multiple Vi^2.
+Vcc
This circuit will square input voltage will yield output Quadrant Multiplier CLC522 principally intended 2-quadrant multiplier. Although bipolar inputs either buffer inputs will pass output bipolar signals, inputs into input only compress gain signal channel inputs. other words, with fixed signal channel input, bipolar inputs channel generate bipolar output signals. However, summing non-inverting input buffer signal directly into inverting input output amplifier parallel with internal gain adjusted signal), quadrant multiplier emulated. Figure shows this application along with design equations Supply decoupling shown
-CLC412
CLC522
-Vee 3.75k source 53.6 Power supply decoupling shown
CLC522 3.24k
-CLC412 1.5k
bias current cancellation
2(0. 2)Vee
-Vee
1.85 1.85 1.85
(1.85 multipllier
scale factor
with
Figure High Speed Voltage Squaring Circuit
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Figure High-Speed Voltage Squaring
This circuit particularly suitable lower frequencies 5MHz). frequency increases, unequal delays between internal external signal paths reduce effectiveness. mixer application, this translates into decreased suppression higher frequencies. Wide Dynamic Range Wave Rectifier bipolar signal applied signal inputs CLC522 that same signal used toggle comparator that switches gain control channel from maximum gain full attenuation, simple effective wave rectifier implemented. Figure shows example this application.
Power supplies decoupling shown
Voltage feedback
A(s)
gain +1.1V CLC501 0.1µF 61.9 -1.1V 1.6k
||R2
Cutoff frequency
Figure Tuneable Single Pole Pass Filter This circuit implements inverting gain stage with gain -R2/R1. Varying effect raising lowering open loop forward gain which been given pure integrator shape input voltage feedback amp. Shifting open loop gain down will vary closed loop bandwidth when feedback gain fixed specific example this circuit shown Figure
3.2k
CLC522
Figure Wave Rectifier Most diode based rectifier circuits suffer from signal level dependent frequency response. circuit Figure relies upon polarity current into inverting input high speed current feedback clipping amplifier (the CLC501) switch CLC522's gain control input from full full off. this case, negative cycle sinusoidal signal cause CLC501 drive positive clamp passing those negative cycles CLC522 output. Since input been connected inverting buffer side, these negative cycles passed output CLC522 positive cycles. signal amplitude range that will produce good rectified outputs depends only good comparator driving gain adjust input. circuit Figure full open loop gain CLC501 available respond switch polarity current into inverting node. alternative high speed voltage controlled comparator could also used. speed operation primarily limited fast comparator respond change polarity input. Adjustable Cutoff, Single Pole, Pass Filter putting adjustable gain CLC522 inside loop integrator stage, variable cutoff pass filter implemented. Figure shows generalized analysis this technique.
1.6k 100pF
CLC420
1.5k
1.07k
CLC522
Vopp
Power supplies decoupling shown
Figure Adjustable Bandwidth Amplifier This particular configuration provides gain with 10MHz cutoff when CLC522 maximum gain gain decreased bandwidth will decrease directly. fixed output voltage swing, Vopp, decreasing bandwidth dropping CLC522 gain will increase voltage swing input CLC522. Given this desired Vopp, available range bandwidth reduction, before input range CLC522 exceeded, will ITAIL Rf/Vopp BWmax/BWmin (Please discussion usable gain adjust range).
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CLC522 Typical Performance
Freq Response Gain 2V/V)
Gain (5dB/div)
(TA=25°C, Vcc=±5V, v=+10V/V, Rf=100 Vg=1.1, unless noted)
Freq Response Gain =10V/V)
Gain (5dB/div)
Freq Response Gain =100V/V)
Fixed 0.25mV .125 -.368 -.644 -.800 -.888
.125 -.368
-.644
-.800
Fixed
Gain (5dB/div)
.125 -.368
-.644
-.800
Fixed
-.937
-.888 -.937 -.964 -.980
Frequency (25MHz/div) 250MHz
-.888 -.937 -.964 -.980
Frequency (10MHz/div) 100MHz
feedthrough -.980 -.964
500MHz
Frequency (50MHz/div)
PSRR CMRR (Input Referred)
CMRR
Feedback Resistor Bandwidth
100V/V 50V/V 20V/V 10V/V -3dB Frequency (MHz)
0.5V 1.1V/V
Magnitude (0.1dB/div)
Gain Flatness Linear Phase Deviation
Gain
2Vpp 1.1V
Deviation from Linear Phase(0.1°/div)
Feedback Resistor
2V/V 5V/V
PSRR/CMRR (dB)
PSRR
Phase
Phase normalized using 2.8nsec time delay
Frequency (Hz)
3MHz/div
30MHz
Phase Deviation from Constant Delay (degrees)
Phase Gain Adjustment
Magnitude (1dB/div, normalized)
Large Signal Frequency Response
10V/V
Magnitude 5Vpp 1.1V
Large Small Signal Pulse Response
=1.0V
Phase (deg)
0.5V
+.75 +.50 +.25 -.25 -.50
Large signal
5V/V
Phase
Small signal
-135 -180 -225
Traces have been skewed clarity 5ns/div
2.5V/V 0.75 1.25V/V
Phase normalized using 2.3nsec time delay
Frequency (20MHz/div)
+100 Frequency (25MHz/div)
-.75
Gain Control Settling Time Delay
Vout 0.25V
Gain Control Channel Feedthrough
Settling Error
-.05 -.15
Short Term Settling Time
output step 1.0V
Input
Vout (0.5V/div.)
1.0V
100mV/div
Output
1.0V 5ns/div
Time (5ns/div)
10ns/div
100ns
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CLC522 Typical Performance
(TA=25°C, Vcc=±5V, v=+10V/V, Rf=100 Vg=1.1, unless noted)
Long Term Settling Time
Settling Error
Settling Time Capacitive Load
Settling Time, (ns), 0.1%
Differential Gain Phase
(ohms)
Phase, 0.0V 4.43 Positive Sync
-.05 -.10 -.15 -.20
1.0V
Differential Gain
output step 1.0V
DifferentialPhase (degrees)
1000
Phase, 1.0V Gain, 1.0V Gain, 0.0V Number Loads
Time (sec)
Load Capacitance, (pF)
Differential Gain Phase
Gain Negative Sync Phase Negative Sync 4.43 1.0V
Settling Time Gain
1000
Output Voltage Noise Gain
Output Voltage Noise (nV/Hz)
vmax
Settling Time 0.1% (ns)
10V/V 5V/V
10V/V
DifferentialPhase (degrees)
Differential Gain
Phase Positive Sync Gain Positive Sync
2.5V/V
Number Loads
1.25V/V 0.625V/V
Attenuation From Maximum Gain (dB)
Frequency (Hz)
Harmonic Distortion
Harmonic Distortion
1.1V
-1dB Compression Maximum Gain
50MHz 20MHz 10MHz 5MHz
1.1V
Distortion Level (dBc)
50MHz
-1dB Compression (dBm)
Distortion Level (dBc)
Output Limited 1.4k
20MHz 10MHz 5MHz
Input Limited
Output Power (Pout, dBm)
Output Power (Pout, dBm)
Frequency (MHz)
Output Amplifier Harmonic
Distortion Level (dBc)
Output Amplifier Harmonic
-1.1V
Output Limited Overdrive Recovery
Input (1V/div)
3.83k 1.1V 10V/V
-1.1V1k
Distortion Level (dBc)
50MHz
Overdrive
50MHz 20MHz 10MHz 5MHz
20MHz
10MHz 5MHz Output Power dBm)
Output (1V/div)
Time (20ns/div)
Output Power dBm)
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CLC522 Electrical Characteristics
PARAMETER Ambient Temperature Ambient Temperature
FREQUENCY RESPONSE small signal bandwidth
(±Vcc=±5V, RL=100, Rf=1k1, Rg=1821, Avmax =+10V/V, Vg=+1.1V)
CONDITIONS CLC522AJ/AI CLC522A8
0.25 2000 -132 0.04 -0.0 1500 -2.2 990-0 -975-0 -4.0
1400 -129 -0.5 1.26 -1.2 -3.6
RATINGS
0.25 1400 -130 +0.5,-1.0 1.37 -1.4 -3.5 0.25 1400 -130 --0.5 -2.0 1.37 -1.2 -3.7 1400 -129 -0.5 1.15 -1.2 -3.7
UNITS SYMBOL
Vout 0.5Vpp Vout 5.0Vpp gain control bandwidth (Vin=0.2V) Vout,Vg 0.5Vpp gain flatness Vout 0.5Vpp peaking DC-30MHz rolloff DC-30MHz 0.05 peaking DC-200MHz rolloff DC-60MHz linear phase deviation DC-60MHz feedthrough max. attenuation) 30MHz 0.5V step 5.0V step 2.0V step 0.5V step step
V/µsec dBm1Hz nV/Hz mV/V
SSBW LSBW GFPL GFPH
TIME DOMAIN RESPONSE rise fall time settling time -0.1% overshoot slew rate
DISTORTION NOISE PERFORMANCE harmonic distortion 2Vpp, 20MHz harmonic distortion 2Vpp, 20MHz equivalent output noise (see noise model) noise floor 1-200MHz spot noise 1-200MHz STATIC PERFORMANCE integral signal nonlinearity Vout=-2Vpp gain control nonlinearity (40dB gain adjustment) input bias current average temperature coefficient input bias current gain error AVmax 10V/V output offset voltage average temperature coefficient input bias current average temperature coefficient input offset current average temperature coefficient power supply sensitivity output referred common mode rejection ratio input referred supply current load MISCELLANEOUS PERFORMANCE signal inputs resistance capacitance buffer tail current (ITAIL max. current) common mode voltage range control input resistance capacitance control voltage tolerance 10V/V 0V/V output impedance output voltage range load output current
DIBI
CMRR
Min/max ratings based product characterization simulation. Individual parameters tested Noted. Outgoing quality levels determined from tested parameters.
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CLC522 Advanced Operating Considerations Military Specifications

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