NSBMC096 Memory Controller i960CA User Application Guide TABLE CO
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NSBMC096 Memory Controller i960CA
NSBMC096 Memory Controller i960CA User Application Guide
TABLE CONTENTS DISTINCTIVE FEATURES Impact System Design i960CA Protocol Support Memory Interface Support Buffer Strategies PROCESSOR PROTOCOL SUPPORT Basic Access Burst Access Interleaved Burst Read Write Operation Burst Write Disabled Compare Mode Overview Miss Non-Interleave Operation Extended Cycle Mode MEMORY INTERFACE Address Multiplexing Memory Refresh Memory Performance Requirements Pre-Charge Time Access Time from Pre-Charge Time Access Time from Write Cycle Restrictions TIMER FUNCTIONS Interrupt Timer Operations Watch Timer SYSTEM INTERCONNECT Signal Description Processor Interface Memory Interface Buffer Control Signals Control Signal Interpretation Control Signal Interpretation Control Signal Interpretation Control Signal Interpretation
National Semiconductor Application Note 1993
Buffer Interconnect Strategies Nibble Wide Memories with ``543`` Buffers SIMM Modules with ``543'' Buffers Buffers with Direction Control Unbuffered Data Expanding Memory Size SOFTWARE DESIGN General Considerations i960CA Configuration Software Configuration NSBMC096 CONFIGURATION REGISTER SUMMARY APPENDIX LIST SORTED SIGNAL NAME APPENDIX DESIGN EXAMPLE DISTINCTIVE FEATURES NSBMC096 memory controller designed specifically i960CA based systems specific nature such systems precludes NSBMC096 from being general purpose device However within constraints targeted applications imposes architectural restrictions Every effort been made preserve application flexibility while still achieving principal design objective providing cost high performance glueless memory systems i960CA Systems Impact System Design supporting both i960CA interface fast page mode memory protocols NSBMC096 enables system designer incorporate very large memory sub-systems into high speed processing systems fact that little performance penalty incurred feature many application areas such intelligent peripheral controllers high speed communication controllers test instrumentation high performance work-stations large memory code data storage only desirable indispensable Given cost dynamic RAMs total system cost maintained levels approaching those currently popular systems that offer performance rates lower factor five more Cost performance ratios this magnitude possible lower density static memories substituted alternate implementations using power space consumptive discrete devices used i960CA Protocol Support NSBMC096 implements protocol described ``i960CA User's Manual'' Both basic burst access methods supported APPENDIX
User Application Guide
Mode Mode Mode Mode
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NSBMC096 functionally equivalent V96BMC NSBMC096is trademark National Semiconductor Corporation i960 registered trademark Intel Corporation C1995 National Semiconductor Corporation
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RRD-B30M75 Printed
interconnect processor's interface direct processor naming convention been used designating pins related this interface order connect NSBMC096 i960CA simply connects like named signal pins together eliminating requirement intermediate control logic NSBMC096 memory solution avoids problems associated with general purpose memory controllers namely performance larger board space requirement higher heat dissipation decreased reliability Memory Interface Support NSBMC096 supports DRAMs using fast page mode protocol taking advantage fast page feature DRAMs comparison logic NSBMC096 able achieve static performance from cost high density DRAMs outputs memory array have been designed with high current drive order avoid necessity external drivers addition care been taken during design minimize problems associated with ground bounce Simultaneously Switching Outputs Buffer Strategies Although NSBMC096 does provide data buffering ``on-chip'' does generate required control signals buffer components multi-mode buffer control signals provides designer with flexibility select buffer components which optimized desired cost performance criteria PROCESSOR PROTOCOL SUPPORT three memory peripheral access methods specified i960CA interface protocol Basic Access Pipelined Burst NSBMC096 supports both Basic Burst access Pipelined access i960CA unaffected external READY input processor Consequently pipelined
operation cannot supported DRAM systems which must dynamically insert wait states insure that back back DRAM access doesn't violate precharge time (for example) Wait states dynamically inserted processor begins access when refresh progress Basic Access Basic Access method conventional processor memory interface with synchronous handshake Using Figure reference basic access begins when address strobe (ADS) asserted with address range NSBMC096 (PCLK access begin either even memory bank (Bank bank (Bank sufficient precharge time elapsed will asserted appropriate bank immediately following cycle (following PCLK same cycle processor will assert BLAST signal indicate that access burst Consequently NSBMC096 will begin strobe opposing bank Either cycle following assertion column address driven onto address lines selected bank time which address switches from Column programmable configuration register After column address settled strobes asserted appropriate bytes memory (controlled Byte enable outputs i960CA) READY signal asserted PCLK indicate processor that data ready current cycle complete access request immediately follows cycle which been active additional wait states will inserted guarantee de-assertion minimum clocks This ensures that pre-charge time violated Consequently second access Figure additional wait state inserted since strobe doesn't begin early otherwise could (Cycle Time) configuration register used control overall access time allotted access operation depicted Figure assumes
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FIGURE Basic Access (Minimum Cycle Mode)
cleared resulting 3-cycle data time cycle data time When additional clock cycle inserted into slower memory higher clock speed this option considered with consequence introducing more wait states Section describes this option greater detail Burst Access burst access method i960CA protocol crucial achieving near theoretical performance NSBMC096 fully supports slave device specification this access method both Read Write access Although i960CA restricts bursts words NSBMC096 allows bursts (512 words) High speed peripherals which have master capability could benefit from longer bursts While NSBMC096 allows bursts begin word boundary i960CA always begins burst even word boundary
Interleaved Burst Read Write Operation burst access begins identical manner basic access when Address strobe asserted with valid address Following cycle (PCLK Figure first bank asserted (always RASA i960CA) Unlike basic access BLAST signal remains de-asserted PCLK resulting assertion opposing Bank Once burst established READY line remains asserted resulting zero wait states remaining data With additional cycle inserted when cycle time (20) bursts proceed with effectively wait state (Section burst read cycle always unused cycle (CASA following PCLK This consequence fact that BLAST guaranteed valid time stop assertion Obviously data from this strobe used
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FIGURE Burst Read Followed Burst Write Access
Burst Write Disabled Burst write should disabled higher speed systems using non-latching buffers purpose disabling burst writes under these circumstances force processor hold data long enough meet hold time requirements DRAM optimal performance burst write should enabled latches should used hold data (refer Section
When burst write disabled (configuration NSBMC096 will return BTERM with READY response burst request (BLAST asserted) This forces i960 re-issue signal continue sequential access depicted Figure below word burst write burst write begins with PCLK With absence BLAST PCLK RASB would normally asserted However basic access performed until PCLK which time BTERM asserted This forces processor issue second address sequence basic access begins Bank
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FIGURE Burst Write Access with Burst Write Disabled
Compare Mode achieve maximum performance comparison feature NSBMC096 should enabled comparison minimizes time memory system uses strobe addresses into DRAM performing strobe only changes from that preceding access Consequently there delay caused RAS-precharge time back-to-back accesses within performance benefits realized particularly noticeable code which repetitively references memory within size this section timing various access modes will explained they operate with compare enabled
de-asserted access NSBMC096 controlled memory will initiate access cycles strobing appropriate signals With compare enabled signals remain asserted access cycle strobes will remain asserted until refresh request detected access requested access begins same NSBMC096 simply cycles between ``Access Cycles'' state ``Row Hold'' state case that compare mode enabled exclusively Instruction Data NSBMC096 will directly ``Idle'' state ``Row Hold'' state depending access type decoded from signal example instruction compare enabled data compare disabled then NSBMC096 will directly ``Idle'' state following data access instruction access however will result expected branch ``Row Hold'' state timing diagram Figure provides more detailed explanation NSBMC096 when ``Row Hit'' access performed Prior PCLK controller ``Idle'' Following PCLK controller asserts RASA requested access Since compare enabled RASB asserted PCLK spite fact that access Bank required compare enabled access NSBMC096 always strobes both banks memory that they will synchronized future access When burst access begins PCLK controller issues first strobe that cycle Consequently first datum ready PCLK (one wait state first access) compare enabled both signals would de-asserted PCLK However only access refresh request will cause them de-assert
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FIGURE NSBMC096 Simplified State Diagram Overview When compare enabled Instruction Data NSBMC096 exist modes operation indicated above state diagram controller initially begins idle state wherein Memory control signals
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FIGURE NSBMC096 with Compare Enabled ``Hit''
Miss When access begins controller will first return idle mode before beginning remains idle state PCLK cycles that precharge time required DRAMs will inserted Consequently miss results additional wait states Figure contrasts that illustrating miss con-
dition second access basic access PCLK proceeds Figure However address (PCLK state changes ``Idle'' before proceeding with access cycles With place DRAMs ready access within PCLK (``Row Hold'' state)
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FIGURE NSBMC096 with Compare Enabled ``Miss'' Non-Interleave Operation NSBMC096 restrict access single bank DRAM achieve non-interleave operation configuration register ``1'' supporting non-interleave memory system integrator assemble processor card with only memory devices That same card then upgraded higher performance interleaved system simply adding additional memory devices provide dual banks Some restrictions apply non-interleave operation Only single block bank populated since there advantage expanding memory depth without going interleaved operation Burst sizes words supported whereas interleave mode supports word bursts compare should enabled when non-interleave mode active Figure indicates non-interleave mode uses Bank side only Consequently Bank signals should connected Note also that read write cycles identical with exception Write Enable (WE) DRAM interleave mode READY signal asserted beginning write cycles read cycles)
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FIGURE Non-Interleave Read Write Access
Extended Cycle Mode until this point timing diagrams have depicted minimum cycle mode operation (Configuration However when Column access delay becomes critical (with slower DRAMs higher clock rates) then additional wait state inserted extend
cycle diagram below documents case basic access burst read write (row compare disabled) results when compare enabled similar those Section except that strobes cycles wide opposed cycles
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FIGURE Basic Burst Read Access Extended Cycle Mode MEMORY INTERFACE this chapter NSBMC096 memory interface explained More specifically processor address translated into memory address This section also provides calculations required determine DRAM speed requirements given memory configuration based NSBMC096 controller access speed required system DRAM function processor clock speed processor data setup hold times buffer delays NSBMC096 delays operating mode Address Multiplexing Processor address translated into Column address listed Table During phase access memory address lines (MA11 derived from addresses under ``Row'' heading from ``Col'' section table during column phase After initial access burst memory address automatically incremented column Table contains address mapping normal interleave operation Tables reveal that mapping changes according memory block size configured when non-interleave operation selected TABLE Interleave Mode (Any DRAM Size) Memory Address MA11 MA10
TABLE Non-Interleave Block (DRAM Size Memory Address MA11 MA10
TABLE Non-Interleave Block (DRAM Size Memory Address MA11 MA10
TABLE Non-Interleave Block (DRAM Size Memory Address MA11 MA10
TABLE Non-Interleave Block (DRAM Size Memory Address MA11 MA10
Memory Refresh only refresh cycle performed rate determined internal refresh counter When counter decrements terminal count value NSBMC096 will start refresh memory cycle soon idle period available refresh counter however does pause refresh memory cycle completion operates continuously independently guarantee overall device refresh rate refresh address generator always maintains full 12-bit refresh address refresh address automatically incremented between refresh cycles outstanding refresh request priority over initiation access refresh period derived from system clock value programmed into configuration bits (Programmed Value row) PCLK Frequency (MHz) valid range programmed value from value used refresh cycle execution will disabled Memory Performance Requirements When selecting memory with NSBMC096 important that performance devices examined with regard rate which system operate NSBMC096 only supports page mode devices However since these most prevalent types devices market this constraint Particular attention must paid page mode behavior memory devices Most DRAM manufacturers offer fast page feature memories megabit greater characteristics fast page mode devices generally those required reliable operation speeds above following sections present some critical performance requirements memory devices function system operating frequency Pre-Charge Time minimum PCLK cycles provided between successive cycles Therefore required pre-charge time given 2(tPC) tRHL tRLH Where DRAM Pre-Charge Time PCLK Cycle Time tRHL High Delay tRLH High Delay Because tRHL tRLH always this requirement reduces 2(tPC) Access Time from possible control required access time DRAM memory using NSBMC096 Configuration register (Bit basic access time calculated Where tRAC tRHL tBUF tRAC tRHL tBUF DRAM Access Time PCLK Cycle Time High Delay Buffer Delay i960CA Data Setup Time
When configuration additional PCLK cycle inserted into cycle tRAC increased additional period Pre-Charge Time pre-charge time during page mode access factors that determines page mode cycle time maximum permissible value given tPCH tCHL tCLH DRAM Pre-Charge Time tPCH PCLK High Time (tPC Approx tCHL High Delay tCLH High Delay Because tCHL tCLH times this requirement reduces tPCH Where Access Time from required access time given Where tCAC tCHL tBUF tCAC DRAM Page Mode Access Time PCLK Cycle Time tCHL High Delay tBUF Buffer Delay i960CA Data Setup Time
Write Cycle Restrictions During burst write cycle data hold time DRAM must considered Typically DRAM requires nonzero data hold time following assertion strobe early write cycle alternatives exist meeting hold time specification Configure NSBMC096 burst write disable registers latches data into DRAM method chosen will depend desired cost performance ratio given application These methods further described Section sub-sections through TIMER FUNCTIONS addition memory support NSBMC096 also contains several features which further enhance potential maximize system integration first these additional features 24-Bit programmable interval timer designed divide system clock (PCLK) programmable division factor This functionality usually required most microprocessor applications would otherwise require additional components Watch Timer also integrated into NSBMC096 necessary avoid ``freezing'' when access initiated region address space which doesn't reach READY condition Interrupt Timer Operations interrupt timer function NSBMC096 consists 24-bit down counter that automatically re-loads itself terminal count with count value contained configuration register bits Consequently timer output signal (TINT) pulsed constant frequency primarily
intended clock interrupt generator Both edge level sensitive interrupt modes supported When enabled edge sensitive interrupt TINT pulses PCLK cycle level sensitive operation desired then output will asserted until explicitly acknowledged Acknowledgement accomplished ``Special Operation'' (Appendix During system boot initialization 24-bit count value should loaded into counter register counter enabled using ``Special Operation'' functions dedicated that purpose (refer Appendix special operation codes) interrupt rate changed time simply storing value into ``Timer Count Value''(TCV) field configuration register Since configuration register accessed Byte quantities 24-bit must updated steps When value placed most significant byte immediately loaded into counter rate then takes effect Consequently should modified first updating lower Bytes that they will place when counter re-load forced counter disabled period time then will reload that when next enabled first interrupt will seen after full count period Watch Timer ``Freezing'' condition wherein processor initiates data access expects READY reply although none generated This situation occur with i960CA external READY enabled some region memory that decoded peripheral memory controller NSBMC096 generates READY status memory access that controls also asserts READY when it's configuration registers accessed However access address range NSBMC096's jurisdiction problematic there un-implemented ``Holes'' address space 5-bit Watch Timer detect freeze condition force READY interrupt monitoring processors (data enable) output When processor initiates access asserts signal rescinds only when access completed absence internal external READY condition will remain asserted indefinitely When asserted Watch Timer begins count down from it's initialized value reaches terminal count then READY interrupt (via BERR output) will generated After rescinded counter re-loaded prepared next access BERR signal used level edge sensitive interrupt depending state configuration (Appendix SYSTEM INTERCONNECT This section describes connection NSBMC096 both host i960CA processor DRAM memory devices describes some possible buffer strategies interconnecting i960CA data memory array inputs outputs
Signal Description NSBMC096 signals subdivided into distinct categories processor interface memory interface buffer control signals complete listing these signals device pin-outs presented NSBMC096 data sheet addition Appendices this document What follows brief functional description major signal groups Processor Interface signals this group assigned same names their counterparts i960CA They designed connected directly i960CA multiple NSBMC096s system fully supported outputs reply signals (READY BTERM) have been designed that they simply wire ``OR''ed together connected directly processor interface outputs tristate open collector require only nominal pull-up approximately
Note Devices that generate READY BTERM from totem pole output require logic gate such 74F08 combine multiple sources together
Memory Interface memory block controlled NSBMC096 organized banks bits each Parity directly supported controller since data connected NSBMC096 However parity checker generator buffers used this purpose memory interface outputs support high current drivers that will drive loads bank Given nominal input load device trace capacitance memory devices bank (byte parity included) easily supported These outputs however must externally matched input impedance DRAM memory array passive serial parallel terminating network that required practice series resistor between optimal most applications Buffer Control Signals transfer Instructions Data from memory subsystem processor data facilitated buffers controlled NSBMC096 signals provided this purpose operate multiple modes according Buffer Mode Field configuration register these signals provide true transparent latch enable controls during data transfers from i960CA memory They designed operate with 74FCT543 style transparent latches provide additional data hold time during write operations high PCLK speeds with slow memories lower speeds functions performed remaining signals change according programmed mode signal names they appear logic symbol reflect functions performed operational mode Table shows control signals their assigned names various operating modes
TABLE Mode Dependent Buffer Control Signals Mode (Default) Mode Mode BankB Mode BankB
Modes primarily designed with wide memories Since these memories have output enables separate buffers each bank required multiplex between banks Modes designed take advantage output enables nibble wide memories Modes used with buffers which have chip enable direction control direction controls connected memory write enables chip enables connected appropriate chip enable signal When devices with select direction controls used care should taken connect ports that true write enables signals MWeA data transfer direction from proces-
into memories 74F245's connect port memories) modes NSBMC096 generates signal called BANKB high level this signal indicates that BANK must enabled starting next rising edge PCLK Conversely level indicates that BANK must enabled starting next rising edge PCLK order memory chip enables each bank operate with correct timing memory output enable (derived from BANKB delay from PCLK must kept minimum Section provides more details BANKB signal
Figure provides composite view buffer controls displayed each modes
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FIGURE Buffer Control Timing Buffer Control Modes
Control Signal Interpretation
Mode
This mode designed used with wide memories buffers which have separate output enables each direction 74FCT543) transmit enable controls each bank asserted read operations from memory while memory bank write enables MWeA asserted write operations Control Signal Interpretation Mode When configured this mode NSBMC096 asserts separate data chip enable controls each bank during both read write operations signals MWeA asserted only during write operations determine direction data transfers This configuration mode appropriate direct control 74F245 style devices that have single enable direction control Control Signal Interpretation Mode This configuration supports nibble wide memories 74F543 style buffers that have output enable controls NSBMC096 generates single transmit enable data access transmit enables asserted read operations either bank memory bank write enables MWeA asserted write operations either bank used Mode BANKB signal used select which bank next accessed read operations Control Signal Interpretation Mode this mode selected single chip enable generated data access both banks asserted both
read write operations either bank BANKB signal used select which bank read Both memory bank write enables asserted write operations either bank Buffer Interconnect Strategies size cost memory system design function types DRAM chosen desired system performance sections following expand some possible configurations illustrate them with appropriate diagrams these configurations will work higher clock rates modes Therefore care should taken select memory buffer components match speed requirements Appendix elaborates some necessary calculations Nibble Wide Memories with ``543'' Buffers nibble wide DRAM devices used conjunction with 74FCT543 octal buffers possible design cost system with minimal component count 256k 4-bit Mbit) devices used memory size results Since NSBMC096 accommodates devices (16M 4-Bit) size system memory size easily expanded using larger devices
Figure shows connection NSBMC096 control signals data buffers memory NSBMC096 should configured buffer mode output enables DRAM driven signals derived from BANKB signal write enable strobes from NSBMC096 used disable output enable during write cycles
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FIGURE Circuit Nibble Wide DRAM Using ``543'' Buffers Mode Controls
SIMM Modules with ``543'' Style Buffers Unfortunately standard configurations SIMM modules lack output enable signal rely instead signal gate output buffers previous example DRAM output enables were used provide multiplexing between banks memory data read cycles However when using SIMMs wide DRAMs necessary individually buffer each memory banks provide multiplexing function illustration this seen Figure NSBMC096 must configured buffer mode order generate required signals important configure signals distribute them properly depending type memories used When using 8-bit SIMMs wide DRAMs ``DRAM
Size'' field (bits configuration register should through (depending memory size) This insures that signals bank operate unison This allows signal drive each Byte DRAMs component loads) that load distributed 32-bit SIMMs used then signal module used DRAM size code should between additional signals then used expand memory size disadvantage this buffer configuration that larger number buffers required than previous example benefit using SIMM modules that memory expansion accomplished simply replacing modules with higher density ones Using 32-bit modules only required interleave operation
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FIGURE Data Buffering SIMM Wide DRAM Using ``543'' Latches Buffers with Direction Control Many popular buffers such ubiquitous ``245'' have common enable signal direction control These buffers easily used place ``543'' components last sections However Figure buffer mode should used with enable ``245'' driven from signal direction controlled write enables same replacement made Figure with driving enables respective sets ``245s'' Since ``245'' devices provide latching necessary disable burst write operation Consequently ``543'' option preferred Unbuffered Data most efficient board real estate realized directly connecting DRAM data processor However data loading should considered example single block nibble wide DRAMs results only DRAM data loads processor data signal However fully expanded system with blocks DRAM places loads data Only nibble wide DRAMs used they equipped with output enable multiplexing between banks interleave memory output enables driven depicted Figure explained previously probably necessary disable burst write since data latched improve hold time Expanding Memory Size When using nibble wide memories possible populate single NSBMC096 with blocks memory devices Expansion this manner accomplished using pair signals each block memory depicted Figure Using megabit (256k devices base memory size (only block installed) (configure ``DRAM size'' field required then additional memory devices installed
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FIGURE Employing Multiple Outputs Memory Expansion SOFTWARE DESIGN ease with which NSBMC096 integrated into circuit design been illustrated foregoing sections There restrictions placed software architecture that imposed NSBMC096 with exception requirement proper initialization General Considerations performance optimized single external data access should minimized where possible favor data bursts order this call tree analysis subroutine flow tracing should performed with view maximizing data locality reference While optimizing compiler long maximizing local variable placement array access loop constructs responsibility global external data placement province programmer supporting burst access data memory NSBMC096 promotes locality reference augmented register ``spill fill'' means enhancing program performance i960CA Configuration order NSBMC096 interact correctly with i960CA imperative that processors ``Memory Region Configuration'' properly initialized region which NSBMC096 resides following parameters should used Burst External Ready Pipe-Lining NRAD NRDD NWAD NWDD NXDA Width Enabled Enabled Disabled 32-Bit
Software Configuration NSBMC096 Configuration NSBMC096 occurs when supervisor write cycles initiated within address range FF0F0000 FF0FFFFF Each byte configuration register mapped into region processors address space lower bits address (bits used ``data'' configuration register address required load configuration byte built following manner
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Where NSBMC096 code placed pins NSBMC096 Conf Byte Select bytes 64-bit configuration word Configuration Data data written into selected byte configuration following program could used configure NSBMC096 Register Usage Initialize Constants FF0F0000H call call cfgword loop shlo extract shlo shlo cmpinci loop Configuration Word Calculate base configuration byte Extract required field Convert byte address word address Calc byte select portion address Base Address configuration data Configure byte Increment Loop Count Branch until bytes complete 00055500 D907A120 cfgword 1000H cfgword systemboot Base Address NSBMC096 order Configuration Word High order Configuration Word Temp Register Count Value Configuration Store Address
Base Address NSBMC096 order Configuration Word High order Configuration Word Configure first bits
Base address config bytes Configure second bits proceed with system boot Configure bytes NSBMC096 Count Value
APPENDIX
CONFIGURATION REGISTER SUMMARY
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Bits Special Operations Access other Configuration Bits Instruction Access Compare Disable (Default) Instruction Access Compare Enable Data Access Compare Disable (Default) Data Access Compare Enable Acknowledge Timer Interrupt Enable Timer Output Level Sense Interrupt Disable Timer Interrupts (Default) Enable Timer Output Edge Sense Interrupt
Bits Buffer Mode Mode Bits Signal Signal BankB BankB Signal Signal
Interleave Mode Interleave Operation Non-Interleave Operation Column Multiplex PCLK Cycle Hold PCLK Cycle Hold Burst Write Disable Burst Write Enable Burst Write Disable Cycle Time Minimum Maximum Bits Timer Count Value TINT Output Rate PCLK (Timer Count Value) Bits Time Number PCLK cycles error BERR Mode Edge Sense Interrupt Level Sense Interrupt BERR Enable Disable Enable READY Enable READY asserted error READY asserted when error occurs
Bits Refresh Rate Refresh Rate (PCLK Frequency) Bits DRAM Size Memory Size Code Memory Block Size 128M 128M Banks
Programmed Val-
Memory Types 256K 256K
APPENDIX Name
LIST SORTED SIGNAL NAME Name AA10 AA11 AB10 AB11 BERR BLAST BTERM CASA0 CASA1 CASA2 CASA3 CASB0 CASB1 CASB2 CASB3 MWEA MWEB PCLK Name RASA0 RASA1 RASA2 RASA3 RASB0 RASB1 RASB2 RASB3 READY Reserved RESET TINT
APPENDIX
DESIGN EXAMPLE
purpose this Appendix demonstrate configure NSBMC096 specific application verify timing requirements purposes this example following assumptions will made System Clock Memory Size Memory Configuration Timer Output 74FCT543 Prop Delay 74F32 Prop Delay DRAM Access Time tRAC Access Time tRAC Precharge Time Precharge Time Address Hold tRAH Column Address Setup tASC Data Hold Time using 16k-256k DRAMs expandable using DRAMs Minimum Cycle Time Burst Write Capabilities 2-Way Interleave Refresh cycles Edge Sensitive Interrupt Minimum Minimum
DATA HOLD TIME (Burst Write) latches used data tDH(DRAM) tPCL tCHL(NSBMC096) (Worst Case) Obviously more hold time required Using circuit Figure provide latching latch enable signals track timing with very skew Consequently latch enable signals instruct latches ``Hold'' just being asserted This guarantees minimum hold time (less some possible clock skew) tDH(DRAM) tP(min) (F32) tP(min) (IDT74FCT543) Clock Skew (Worst Case) This sufficient DRAM Pre-Charge Time From 2(tPC) (Worst Case) Sufficient DRAM Access Time from From tRAC tRHL(max) (NSBMC096) tSU(i960CA) Minimum Cycle Mode (Worst Case) Sufficient DRAM Simply Maximum Cycle mode resulting
Pre-Charge Time From tPCH This sufficient both DRAM Access Time from From tCAS tCHL(max) tBUF(max) (IDT74FCT543) (i960CA) This compatible with both DRAMs Address Hold Time Time config tRAH Time config tRAH Both modes compatible with DRAMs Column Address Setup Time Time config tRAH tCHL tCAV Time config tRAH tPCH tCHL tCAV Both modes compatible with DRAMs Chose config Refresh Rate Rows Refresh every Refresh Configuration Constant Timer Count Value Timer interrupt 500000 07A120 Watch Timer Time Asserted longer than Time cycles
Configuration each fields configuration register following values have been derived this example Rate DRAM size Buffer Mode Interleave Mode Time Burst Write Disable Cycle Time Block Address Timer Count Value 07A120 BERR mode BERR Enable BERR READY enable resulting 64-bit configuration follows 0xD907A12000055500
NSBMC096 Memory Controller i960CA User Application Guide
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